arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/uaccess.h>
  26 #include <asm/kvm_arm.h>
  27 #include <asm/kvm_host.h>
  28 #include <asm/kvm_emulate.h>
  29 #include <asm/kvm_coproc.h>
  30 #include <asm/kvm_mmu.h>
  31 #include <asm/cacheflush.h>
  32 #include <asm/cputype.h>
  33 #include <asm/debug-monitors.h>
  34 #include <trace/events/kvm.h>
  35
  36 #include "sys_regs.h"
  37
  38 /*
  39  * All of this file is extremly similar to the ARM coproc.c, but the
  40  * types are different. My gut feeling is that it should be pretty
  41  * easy to merge, but that would be an ABI breakage -- again. VFP
  42  * would also need to be abstracted.
  43  *
  44  * For AArch32, we only take care of what is being trapped. Anything
  45  * that has to do with init and userspace access has to go via the
  46  * 64bit interface.
  47  */
  48
  49 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  50 static u32 cache_levels;
  51
  52 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  53 #define CSSELR_MAX 12
  54
  55 /* Which cache CCSIDR represents depends on CSSELR value. */
  56 static u32 get_ccsidr(u32 csselr)
  57 {
  58         u32 ccsidr;
  59
  60         /* Make sure noone else changes CSSELR during this! */
  61         local_irq_disable();
  62         /* Put value into CSSELR */
  63         asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
  64         isb();
  65         /* Read result out of CCSIDR */
  66         asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
  67         local_irq_enable();
  68
  69         return ccsidr;
  70 }
  71
  72 static void do_dc_cisw(u32 val)
  73 {
  74         asm volatile("dc cisw, %x0" : : "r" (val));
  75         dsb(ish);
  76 }
  77
  78 static void do_dc_csw(u32 val)
  79 {
  80         asm volatile("dc csw, %x0" : : "r" (val));
  81         dsb(ish);
  82 }
  83
  84 /* See note at ARM ARM B1.14.4 */
  85 static bool access_dcsw(struct kvm_vcpu *vcpu,
  86                         const struct sys_reg_params *p,
  87                         const struct sys_reg_desc *r)
  88 {
  89         unsigned long val;
  90         int cpu;
  91
  92         if (!p->is_write)
  93                 return read_from_write_only(vcpu, p);
  94
  95         cpu = get_cpu();
  96
  97         cpumask_setall(&vcpu->arch.require_dcache_flush);
  98         cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
  99
 100         /* If we were already preempted, take the long way around */
 101         if (cpu != vcpu->arch.last_pcpu) {
 102                 flush_cache_all();
 103                 goto done;
 104         }
 105
 106         val = *vcpu_reg(vcpu, p->Rt);
 107
 108         switch (p->CRm) {
 109         case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
 110         case 14:                /* DCCISW */
 111                 do_dc_cisw(val);
 112                 break;
 113
 114         case 10:                /* DCCSW */
 115                 do_dc_csw(val);
 116                 break;
 117         }
 118
 119 done:
 120         put_cpu();
 121
 122         return true;
 123 }
 124
 125 /*
 126  * Generic accessor for VM registers. Only called as long as HCR_TVM
 127  * is set.
 128  */
 129 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 130                           const struct sys_reg_params *p,
 131                           const struct sys_reg_desc *r)
 132 {
 133         unsigned long val;
 134
 135         BUG_ON(!p->is_write);
 136
 137         val = *vcpu_reg(vcpu, p->Rt);
 138         if (!p->is_aarch32) {
 139                 vcpu_sys_reg(vcpu, r->reg) = val;
 140         } else {
 141                 if (!p->is_32bit)
 142                         vcpu_cp15_64_high(vcpu, r->reg) = val >> 32;
 143                 vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;
 144         }
 145
 146         return true;
 147 }
 148
 149 /*
 150  * SCTLR_EL1 accessor. Only called as long as HCR_TVM is set.  If the
 151  * guest enables the MMU, we stop trapping the VM sys_regs and leave
 152  * it in complete control of the caches.
 153  */
 154 static bool access_sctlr(struct kvm_vcpu *vcpu,
 155                          const struct sys_reg_params *p,
 156                          const struct sys_reg_desc *r)
 157 {
 158         access_vm_reg(vcpu, p, r);
 159
 160         if (vcpu_has_cache_enabled(vcpu)) {     /* MMU+Caches enabled? */
 161                 vcpu->arch.hcr_el2 &= ~HCR_TVM;
 162                 stage2_flush_vm(vcpu->kvm);
 163         }
 164
 165         return true;
 166 }
 167
 168 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 169                         const struct sys_reg_params *p,
 170                         const struct sys_reg_desc *r)
 171 {
 172         if (p->is_write)
 173                 return ignore_write(vcpu, p);
 174         else
 175                 return read_zero(vcpu, p);
 176 }
 177
 178 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 179                            const struct sys_reg_params *p,
 180                            const struct sys_reg_desc *r)
 181 {
 182         if (p->is_write) {
 183                 return ignore_write(vcpu, p);
 184         } else {
 185                 *vcpu_reg(vcpu, p->Rt) = (1 << 3);
 186                 return true;
 187         }
 188 }
 189
 190 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 191                                    const struct sys_reg_params *p,
 192                                    const struct sys_reg_desc *r)
 193 {
 194         if (p->is_write) {
 195                 return ignore_write(vcpu, p);
 196         } else {
 197                 u32 val;
 198                 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
 199                 *vcpu_reg(vcpu, p->Rt) = val;
 200                 return true;
 201         }
 202 }
 203
 204 /*
 205  * We want to avoid world-switching all the DBG registers all the
 206  * time:
 207  *
 208  * - If we've touched any debug register, it is likely that we're
 209  *   going to touch more of them. It then makes sense to disable the
 210  *   traps and start doing the save/restore dance
 211  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 212  *   then mandatory to save/restore the registers, as the guest
 213  *   depends on them.
 214  *
 215  * For this, we use a DIRTY bit, indicating the guest has modified the
 216  * debug registers, used as follow:
 217  *
 218  * On guest entry:
 219  * - If the dirty bit is set (because we're coming back from trapping),
 220  *   disable the traps, save host registers, restore guest registers.
 221  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 222  *   set the dirty bit, disable the traps, save host registers,
 223  *   restore guest registers.
 224  * - Otherwise, enable the traps
 225  *
 226  * On guest exit:
 227  * - If the dirty bit is set, save guest registers, restore host
 228  *   registers and clear the dirty bit. This ensure that the host can
 229  *   now use the debug registers.
 230  */
 231 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 232                             const struct sys_reg_params *p,
 233                             const struct sys_reg_desc *r)
 234 {
 235         if (p->is_write) {
 236                 vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
 237                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 238         } else {
 239                 *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
 240         }
 241
 242         return true;
 243 }
 244
 245 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 246 {
 247         u64 amair;
 248
 249         asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
 250         vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
 251 }
 252
 253 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 254 {
 255         /*
 256          * Simply map the vcpu_id into the Aff0 field of the MPIDR.
 257          */
 258         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
 259 }
 260
 261 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 262 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 263         /* DBGBVRn_EL1 */                                               \
 264         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100),     \
 265           trap_debug_regs, reset_val, (DBGBVR0_EL1 + (n)), 0 },         \
 266         /* DBGBCRn_EL1 */                                               \
 267         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101),     \
 268           trap_debug_regs, reset_val, (DBGBCR0_EL1 + (n)), 0 },         \
 269         /* DBGWVRn_EL1 */                                               \
 270         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110),     \
 271           trap_debug_regs, reset_val, (DBGWVR0_EL1 + (n)), 0 },         \
 272         /* DBGWCRn_EL1 */                                               \
 273         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),     \
 274           trap_debug_regs, reset_val, (DBGWCR0_EL1 + (n)), 0 }
 275
 276 /*
 277  * Architected system registers.
 278  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 279  *
 280  * We could trap ID_DFR0 and tell the guest we don't support performance
 281  * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 282  * NAKed, so it will read the PMCR anyway.
 283  *
 284  * Therefore we tell the guest we have 0 counters.  Unfortunately, we
 285  * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 286  * all PM registers, which doesn't crash the guest kernel at least.
 287  *
 288  * Debug handling: We do trap most, if not all debug related system
 289  * registers. The implementation is good enough to ensure that a guest
 290  * can use these with minimal performance degradation. The drawback is
 291  * that we don't implement any of the external debug, none of the
 292  * OSlock protocol. This should be revisited if we ever encounter a
 293  * more demanding guest...
 294  */
 295 static const struct sys_reg_desc sys_reg_descs[] = {
 296         /* DC ISW */
 297         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 298           access_dcsw },
 299         /* DC CSW */
 300         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 301           access_dcsw },
 302         /* DC CISW */
 303         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 304           access_dcsw },
 305
 306         DBG_BCR_BVR_WCR_WVR_EL1(0),
 307         DBG_BCR_BVR_WCR_WVR_EL1(1),
 308         /* MDCCINT_EL1 */
 309         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 310           trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 311         /* MDSCR_EL1 */
 312         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 313           trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 314         DBG_BCR_BVR_WCR_WVR_EL1(2),
 315         DBG_BCR_BVR_WCR_WVR_EL1(3),
 316         DBG_BCR_BVR_WCR_WVR_EL1(4),
 317         DBG_BCR_BVR_WCR_WVR_EL1(5),
 318         DBG_BCR_BVR_WCR_WVR_EL1(6),
 319         DBG_BCR_BVR_WCR_WVR_EL1(7),
 320         DBG_BCR_BVR_WCR_WVR_EL1(8),
 321         DBG_BCR_BVR_WCR_WVR_EL1(9),
 322         DBG_BCR_BVR_WCR_WVR_EL1(10),
 323         DBG_BCR_BVR_WCR_WVR_EL1(11),
 324         DBG_BCR_BVR_WCR_WVR_EL1(12),
 325         DBG_BCR_BVR_WCR_WVR_EL1(13),
 326         DBG_BCR_BVR_WCR_WVR_EL1(14),
 327         DBG_BCR_BVR_WCR_WVR_EL1(15),
 328
 329         /* MDRAR_EL1 */
 330         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 331           trap_raz_wi },
 332         /* OSLAR_EL1 */
 333         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
 334           trap_raz_wi },
 335         /* OSLSR_EL1 */
 336         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
 337           trap_oslsr_el1 },
 338         /* OSDLR_EL1 */
 339         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
 340           trap_raz_wi },
 341         /* DBGPRCR_EL1 */
 342         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
 343           trap_raz_wi },
 344         /* DBGCLAIMSET_EL1 */
 345         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
 346           trap_raz_wi },
 347         /* DBGCLAIMCLR_EL1 */
 348         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
 349           trap_raz_wi },
 350         /* DBGAUTHSTATUS_EL1 */
 351         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
 352           trap_dbgauthstatus_el1 },
 353
 354         /* TEECR32_EL1 */
 355         { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 356           NULL, reset_val, TEECR32_EL1, 0 },
 357         /* TEEHBR32_EL1 */
 358         { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
 359           NULL, reset_val, TEEHBR32_EL1, 0 },
 360
 361         /* MDCCSR_EL1 */
 362         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
 363           trap_raz_wi },
 364         /* DBGDTR_EL0 */
 365         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
 366           trap_raz_wi },
 367         /* DBGDTR[TR]X_EL0 */
 368         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
 369           trap_raz_wi },
 370
 371         /* DBGVCR32_EL2 */
 372         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
 373           NULL, reset_val, DBGVCR32_EL2, 0 },
 374
 375         /* MPIDR_EL1 */
 376         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 377           NULL, reset_mpidr, MPIDR_EL1 },
 378         /* SCTLR_EL1 */
 379         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 380           access_sctlr, reset_val, SCTLR_EL1, 0x00C50078 },
 381         /* CPACR_EL1 */
 382         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 383           NULL, reset_val, CPACR_EL1, 0 },
 384         /* TTBR0_EL1 */
 385         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 386           access_vm_reg, reset_unknown, TTBR0_EL1 },
 387         /* TTBR1_EL1 */
 388         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 389           access_vm_reg, reset_unknown, TTBR1_EL1 },
 390         /* TCR_EL1 */
 391         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 392           access_vm_reg, reset_val, TCR_EL1, 0 },
 393
 394         /* AFSR0_EL1 */
 395         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 396           access_vm_reg, reset_unknown, AFSR0_EL1 },
 397         /* AFSR1_EL1 */
 398         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 399           access_vm_reg, reset_unknown, AFSR1_EL1 },
 400         /* ESR_EL1 */
 401         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 402           access_vm_reg, reset_unknown, ESR_EL1 },
 403         /* FAR_EL1 */
 404         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 405           access_vm_reg, reset_unknown, FAR_EL1 },
 406         /* PAR_EL1 */
 407         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 408           NULL, reset_unknown, PAR_EL1 },
 409
 410         /* PMINTENSET_EL1 */
 411         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
 412           trap_raz_wi },
 413         /* PMINTENCLR_EL1 */
 414         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
 415           trap_raz_wi },
 416
 417         /* MAIR_EL1 */
 418         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 419           access_vm_reg, reset_unknown, MAIR_EL1 },
 420         /* AMAIR_EL1 */
 421         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 422           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 423
 424         /* VBAR_EL1 */
 425         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 426           NULL, reset_val, VBAR_EL1, 0 },
 427
 428         /* ICC_SRE_EL1 */
 429         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
 430           trap_raz_wi },
 431
 432         /* CONTEXTIDR_EL1 */
 433         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 434           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 435         /* TPIDR_EL1 */
 436         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 437           NULL, reset_unknown, TPIDR_EL1 },
 438
 439         /* CNTKCTL_EL1 */
 440         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 441           NULL, reset_val, CNTKCTL_EL1, 0},
 442
 443         /* CSSELR_EL1 */
 444         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 445           NULL, reset_unknown, CSSELR_EL1 },
 446
 447         /* PMCR_EL0 */
 448         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
 449           trap_raz_wi },
 450         /* PMCNTENSET_EL0 */
 451         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
 452           trap_raz_wi },
 453         /* PMCNTENCLR_EL0 */
 454         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
 455           trap_raz_wi },
 456         /* PMOVSCLR_EL0 */
 457         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
 458           trap_raz_wi },
 459         /* PMSWINC_EL0 */
 460         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
 461           trap_raz_wi },
 462         /* PMSELR_EL0 */
 463         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
 464           trap_raz_wi },
 465         /* PMCEID0_EL0 */
 466         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 467           trap_raz_wi },
 468         /* PMCEID1_EL0 */
 469         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
 470           trap_raz_wi },
 471         /* PMCCNTR_EL0 */
 472         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
 473           trap_raz_wi },
 474         /* PMXEVTYPER_EL0 */
 475         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
 476           trap_raz_wi },
 477         /* PMXEVCNTR_EL0 */
 478         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
 479           trap_raz_wi },
 480         /* PMUSERENR_EL0 */
 481         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
 482           trap_raz_wi },
 483         /* PMOVSSET_EL0 */
 484         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
 485           trap_raz_wi },
 486
 487         /* TPIDR_EL0 */
 488         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
 489           NULL, reset_unknown, TPIDR_EL0 },
 490         /* TPIDRRO_EL0 */
 491         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
 492           NULL, reset_unknown, TPIDRRO_EL0 },
 493
 494         /* DACR32_EL2 */
 495         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
 496           NULL, reset_unknown, DACR32_EL2 },
 497         /* IFSR32_EL2 */
 498         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
 499           NULL, reset_unknown, IFSR32_EL2 },
 500         /* FPEXC32_EL2 */
 501         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
 502           NULL, reset_val, FPEXC32_EL2, 0x70 },
 503 };
 504
 505 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
 506                         const struct sys_reg_params *p,
 507                         const struct sys_reg_desc *r)
 508 {
 509         if (p->is_write) {
 510                 return ignore_write(vcpu, p);
 511         } else {
 512                 u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
 513                 u64 pfr = read_cpuid(ID_AA64PFR0_EL1);
 514                 u32 el3 = !!((pfr >> 12) & 0xf);
 515
 516                 *vcpu_reg(vcpu, p->Rt) = ((((dfr >> 20) & 0xf) << 28) |
 517                                           (((dfr >> 12) & 0xf) << 24) |
 518                                           (((dfr >> 28) & 0xf) << 20) |
 519                                           (6 << 16) | (el3 << 14) | (el3 << 12));
 520                 return true;
 521         }
 522 }
 523
 524 static bool trap_debug32(struct kvm_vcpu *vcpu,
 525                          const struct sys_reg_params *p,
 526                          const struct sys_reg_desc *r)
 527 {
 528         if (p->is_write) {
 529                 vcpu_cp14(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
 530                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 531         } else {
 532                 *vcpu_reg(vcpu, p->Rt) = vcpu_cp14(vcpu, r->reg);
 533         }
 534
 535         return true;
 536 }
 537
 538 #define DBG_BCR_BVR_WCR_WVR(n)                                  \
 539         /* DBGBVRn */                                           \
 540         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_debug32,    \
 541           NULL, (cp14_DBGBVR0 + (n) * 2) },                     \
 542         /* DBGBCRn */                                           \
 543         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_debug32,    \
 544           NULL, (cp14_DBGBCR0 + (n) * 2) },                     \
 545         /* DBGWVRn */                                           \
 546         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_debug32,    \
 547           NULL, (cp14_DBGWVR0 + (n) * 2) },                     \
 548         /* DBGWCRn */                                           \
 549         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_debug32,    \
 550           NULL, (cp14_DBGWCR0 + (n) * 2) }
 551
 552 #define DBGBXVR(n)                                              \
 553         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_debug32,    \
 554           NULL, cp14_DBGBXVR0 + n * 2 }
 555
 556 /*
 557  * Trapped cp14 registers. We generally ignore most of the external
 558  * debug, on the principle that they don't really make sense to a
 559  * guest. Revisit this one day, whould this principle change.
 560  */
 561 static const struct sys_reg_desc cp14_regs[] = {
 562         /* DBGIDR */
 563         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
 564         /* DBGDTRRXext */
 565         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
 566
 567         DBG_BCR_BVR_WCR_WVR(0),
 568         /* DBGDSCRint */
 569         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
 570         DBG_BCR_BVR_WCR_WVR(1),
 571         /* DBGDCCINT */
 572         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
 573         /* DBGDSCRext */
 574         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
 575         DBG_BCR_BVR_WCR_WVR(2),
 576         /* DBGDTR[RT]Xint */
 577         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
 578         /* DBGDTR[RT]Xext */
 579         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
 580         DBG_BCR_BVR_WCR_WVR(3),
 581         DBG_BCR_BVR_WCR_WVR(4),
 582         DBG_BCR_BVR_WCR_WVR(5),
 583         /* DBGWFAR */
 584         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
 585         /* DBGOSECCR */
 586         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
 587         DBG_BCR_BVR_WCR_WVR(6),
 588         /* DBGVCR */
 589         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
 590         DBG_BCR_BVR_WCR_WVR(7),
 591         DBG_BCR_BVR_WCR_WVR(8),
 592         DBG_BCR_BVR_WCR_WVR(9),
 593         DBG_BCR_BVR_WCR_WVR(10),
 594         DBG_BCR_BVR_WCR_WVR(11),
 595         DBG_BCR_BVR_WCR_WVR(12),
 596         DBG_BCR_BVR_WCR_WVR(13),
 597         DBG_BCR_BVR_WCR_WVR(14),
 598         DBG_BCR_BVR_WCR_WVR(15),
 599
 600         /* DBGDRAR (32bit) */
 601         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
 602
 603         DBGBXVR(0),
 604         /* DBGOSLAR */
 605         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
 606         DBGBXVR(1),
 607         /* DBGOSLSR */
 608         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
 609         DBGBXVR(2),
 610         DBGBXVR(3),
 611         /* DBGOSDLR */
 612         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
 613         DBGBXVR(4),
 614         /* DBGPRCR */
 615         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
 616         DBGBXVR(5),
 617         DBGBXVR(6),
 618         DBGBXVR(7),
 619         DBGBXVR(8),
 620         DBGBXVR(9),
 621         DBGBXVR(10),
 622         DBGBXVR(11),
 623         DBGBXVR(12),
 624         DBGBXVR(13),
 625         DBGBXVR(14),
 626         DBGBXVR(15),
 627
 628         /* DBGDSAR (32bit) */
 629         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
 630
 631         /* DBGDEVID2 */
 632         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
 633         /* DBGDEVID1 */
 634         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
 635         /* DBGDEVID */
 636         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
 637         /* DBGCLAIMSET */
 638         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
 639         /* DBGCLAIMCLR */
 640         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
 641         /* DBGAUTHSTATUS */
 642         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
 643 };
 644
 645 /* Trapped cp14 64bit registers */
 646 static const struct sys_reg_desc cp14_64_regs[] = {
 647         /* DBGDRAR (64bit) */
 648         { Op1( 0), CRm( 1), .access = trap_raz_wi },
 649
 650         /* DBGDSAR (64bit) */
 651         { Op1( 0), CRm( 2), .access = trap_raz_wi },
 652 };
 653
 654 /*
 655  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
 656  * depending on the way they are accessed (as a 32bit or a 64bit
 657  * register).
 658  */
 659 static const struct sys_reg_desc cp15_regs[] = {
 660         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },
 661         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 662         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
 663         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
 664         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
 665         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
 666         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
 667         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
 668         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
 669         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
 670         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
 671
 672         /*
 673          * DC{C,I,CI}SW operations:
 674          */
 675         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
 676         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
 677         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
 678
 679         /* PMU */
 680         { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
 681         { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 682         { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 683         { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
 684         { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
 685         { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 686         { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 687         { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
 688         { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
 689         { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
 690         { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
 691         { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
 692         { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
 693
 694         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
 695         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
 696         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
 697         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
 698
 699         /* ICC_SRE */
 700         { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
 701
 702         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
 703 };
 704
 705 static const struct sys_reg_desc cp15_64_regs[] = {
 706         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 707         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
 708 };
 709
 710 /* Target specific emulation tables */
 711 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
 712
 713 void kvm_register_target_sys_reg_table(unsigned int target,
 714                                        struct kvm_sys_reg_target_table *table)
 715 {
 716         target_tables[target] = table;
 717 }
 718
 719 /* Get specific register table for this target. */
 720 static const struct sys_reg_desc *get_target_table(unsigned target,
 721                                                    bool mode_is_64,
 722                                                    size_t *num)
 723 {
 724         struct kvm_sys_reg_target_table *table;
 725
 726         table = target_tables[target];
 727         if (mode_is_64) {
 728                 *num = table->table64.num;
 729                 return table->table64.table;
 730         } else {
 731                 *num = table->table32.num;
 732                 return table->table32.table;
 733         }
 734 }
 735
 736 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
 737                                          const struct sys_reg_desc table[],
 738                                          unsigned int num)
 739 {
 740         unsigned int i;
 741
 742         for (i = 0; i < num; i++) {
 743                 const struct sys_reg_desc *r = &table[i];
 744
 745                 if (params->Op0 != r->Op0)
 746                         continue;
 747                 if (params->Op1 != r->Op1)
 748                         continue;
 749                 if (params->CRn != r->CRn)
 750                         continue;
 751                 if (params->CRm != r->CRm)
 752                         continue;
 753                 if (params->Op2 != r->Op2)
 754                         continue;
 755
 756                 return r;
 757         }
 758         return NULL;
 759 }
 760
 761 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
 762 {
 763         kvm_inject_undefined(vcpu);
 764         return 1;
 765 }
 766
 767 /*
 768  * emulate_cp --  tries to match a sys_reg access in a handling table, and
 769  *                call the corresponding trap handler.
 770  *
 771  * @params: pointer to the descriptor of the access
 772  * @table: array of trap descriptors
 773  * @num: size of the trap descriptor array
 774  *
 775  * Return 0 if the access has been handled, and -1 if not.
 776  */
 777 static int emulate_cp(struct kvm_vcpu *vcpu,
 778                       const struct sys_reg_params *params,
 779                       const struct sys_reg_desc *table,
 780                       size_t num)
 781 {
 782         const struct sys_reg_desc *r;
 783
 784         if (!table)
 785                 return -1;      /* Not handled */
 786
 787         r = find_reg(params, table, num);
 788
 789         if (r) {
 790                 /*
 791                  * Not having an accessor means that we have
 792                  * configured a trap that we don't know how to
 793                  * handle. This certainly qualifies as a gross bug
 794                  * that should be fixed right away.
 795                  */
 796                 BUG_ON(!r->access);
 797
 798                 if (likely(r->access(vcpu, params, r))) {
 799                         /* Skip instruction, since it was emulated */
 800                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 801                 }
 802
 803                 /* Handled */
 804                 return 0;
 805         }
 806
 807         /* Not handled */
 808         return -1;
 809 }
 810
 811 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
 812                                 struct sys_reg_params *params)
 813 {
 814         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
 815         int cp;
 816
 817         switch(hsr_ec) {
 818         case ESR_EL2_EC_CP15_32:
 819         case ESR_EL2_EC_CP15_64:
 820                 cp = 15;
 821                 break;
 822         case ESR_EL2_EC_CP14_MR:
 823         case ESR_EL2_EC_CP14_64:
 824                 cp = 14;
 825                 break;
 826         default:
 827                 WARN_ON((cp = -1));
 828         }
 829
 830         kvm_err("Unsupported guest CP%d access at: %08lx\n",
 831                 cp, *vcpu_pc(vcpu));
 832         print_sys_reg_instr(params);
 833         kvm_inject_undefined(vcpu);
 834 }
 835
 836 /**
 837  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP15 access
 838  * @vcpu: The VCPU pointer
 839  * @run:  The kvm_run struct
 840  */
 841 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
 842                             const struct sys_reg_desc *global,
 843                             size_t nr_global,
 844                             const struct sys_reg_desc *target_specific,
 845                             size_t nr_specific)
 846 {
 847         struct sys_reg_params params;
 848         u32 hsr = kvm_vcpu_get_hsr(vcpu);
 849         int Rt2 = (hsr >> 10) & 0xf;
 850
 851         params.is_aarch32 = true;
 852         params.is_32bit = false;
 853         params.CRm = (hsr >> 1) & 0xf;
 854         params.Rt = (hsr >> 5) & 0xf;
 855         params.is_write = ((hsr & 1) == 0);
 856
 857         params.Op0 = 0;
 858         params.Op1 = (hsr >> 16) & 0xf;
 859         params.Op2 = 0;
 860         params.CRn = 0;
 861
 862         /*
 863          * Massive hack here. Store Rt2 in the top 32bits so we only
 864          * have one register to deal with. As we use the same trap
 865          * backends between AArch32 and AArch64, we get away with it.
 866          */
 867         if (params.is_write) {
 868                 u64 val = *vcpu_reg(vcpu, params.Rt);
 869                 val &= 0xffffffff;
 870                 val |= *vcpu_reg(vcpu, Rt2) << 32;
 871                 *vcpu_reg(vcpu, params.Rt) = val;
 872         }
 873
 874         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
 875                 goto out;
 876         if (!emulate_cp(vcpu, &params, global, nr_global))
 877                 goto out;
 878
 879         unhandled_cp_access(vcpu, &params);
 880
 881 out:
 882         /* Do the opposite hack for the read side */
 883         if (!params.is_write) {
 884                 u64 val = *vcpu_reg(vcpu, params.Rt);
 885                 val >>= 32;
 886                 *vcpu_reg(vcpu, Rt2) = val;
 887         }
 888
 889         return 1;
 890 }
 891
 892 /**
 893  * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
 894  * @vcpu: The VCPU pointer
 895  * @run:  The kvm_run struct
 896  */
 897 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
 898                             const struct sys_reg_desc *global,
 899                             size_t nr_global,
 900                             const struct sys_reg_desc *target_specific,
 901                             size_t nr_specific)
 902 {
 903         struct sys_reg_params params;
 904         u32 hsr = kvm_vcpu_get_hsr(vcpu);
 905
 906         params.is_aarch32 = true;
 907         params.is_32bit = true;
 908         params.CRm = (hsr >> 1) & 0xf;
 909         params.Rt  = (hsr >> 5) & 0xf;
 910         params.is_write = ((hsr & 1) == 0);
 911         params.CRn = (hsr >> 10) & 0xf;
 912         params.Op0 = 0;
 913         params.Op1 = (hsr >> 14) & 0x7;
 914         params.Op2 = (hsr >> 17) & 0x7;
 915
 916         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
 917                 return 1;
 918         if (!emulate_cp(vcpu, &params, global, nr_global))
 919                 return 1;
 920
 921         unhandled_cp_access(vcpu, &params);
 922         return 1;
 923 }
 924
 925 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 926 {
 927         const struct sys_reg_desc *target_specific;
 928         size_t num;
 929
 930         target_specific = get_target_table(vcpu->arch.target, false, &num);
 931         return kvm_handle_cp_64(vcpu,
 932                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
 933                                 target_specific, num);
 934 }
 935
 936 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 937 {
 938         const struct sys_reg_desc *target_specific;
 939         size_t num;
 940
 941         target_specific = get_target_table(vcpu->arch.target, false, &num);
 942         return kvm_handle_cp_32(vcpu,
 943                                 cp15_regs, ARRAY_SIZE(cp15_regs),
 944                                 target_specific, num);
 945 }
 946
 947 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 948 {
 949         return kvm_handle_cp_64(vcpu,
 950                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
 951                                 NULL, 0);
 952 }
 953
 954 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 955 {
 956         return kvm_handle_cp_32(vcpu,
 957                                 cp14_regs, ARRAY_SIZE(cp14_regs),
 958                                 NULL, 0);
 959 }
 960
 961 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
 962                            const struct sys_reg_params *params)
 963 {
 964         size_t num;
 965         const struct sys_reg_desc *table, *r;
 966
 967         table = get_target_table(vcpu->arch.target, true, &num);
 968
 969         /* Search target-specific then generic table. */
 970         r = find_reg(params, table, num);
 971         if (!r)
 972                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
 973
 974         if (likely(r)) {
 975                 /*
 976                  * Not having an accessor means that we have
 977                  * configured a trap that we don't know how to
 978                  * handle. This certainly qualifies as a gross bug
 979                  * that should be fixed right away.
 980                  */
 981                 BUG_ON(!r->access);
 982
 983                 if (likely(r->access(vcpu, params, r))) {
 984                         /* Skip instruction, since it was emulated */
 985                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 986                         return 1;
 987                 }
 988                 /* If access function fails, it should complain. */
 989         } else {
 990                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
 991                         *vcpu_pc(vcpu));
 992                 print_sys_reg_instr(params);
 993         }
 994         kvm_inject_undefined(vcpu);
 995         return 1;
 996 }
 997
 998 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
 999                               const struct sys_reg_desc *table, size_t num)
1000 {
1001         unsigned long i;
1002
1003         for (i = 0; i < num; i++)
1004                 if (table[i].reset)
1005                         table[i].reset(vcpu, &table[i]);
1006 }
1007
1008 /**
1009  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1010  * @vcpu: The VCPU pointer
1011  * @run:  The kvm_run struct
1012  */
1013 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1014 {
1015         struct sys_reg_params params;
1016         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1017
1018         params.is_aarch32 = false;
1019         params.is_32bit = false;
1020         params.Op0 = (esr >> 20) & 3;
1021         params.Op1 = (esr >> 14) & 0x7;
1022         params.CRn = (esr >> 10) & 0xf;
1023         params.CRm = (esr >> 1) & 0xf;
1024         params.Op2 = (esr >> 17) & 0x7;
1025         params.Rt = (esr >> 5) & 0x1f;
1026         params.is_write = !(esr & 1);
1027
1028         return emulate_sys_reg(vcpu, &params);
1029 }
1030
1031 /******************************************************************************
1032  * Userspace API
1033  *****************************************************************************/
1034
1035 static bool index_to_params(u64 id, struct sys_reg_params *params)
1036 {
1037         switch (id & KVM_REG_SIZE_MASK) {
1038         case KVM_REG_SIZE_U64:
1039                 /* Any unused index bits means it's not valid. */
1040                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1041                               | KVM_REG_ARM_COPROC_MASK
1042                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1043                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1044                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1045                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1046                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1047                         return false;
1048                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1049                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1050                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1051                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1052                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1053                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1054                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1055                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1056                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1057                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1058                 return true;
1059         default:
1060                 return false;
1061         }
1062 }
1063
1064 /* Decode an index value, and find the sys_reg_desc entry. */
1065 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1066                                                     u64 id)
1067 {
1068         size_t num;
1069         const struct sys_reg_desc *table, *r;
1070         struct sys_reg_params params;
1071
1072         /* We only do sys_reg for now. */
1073         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1074                 return NULL;
1075
1076         if (!index_to_params(id, &params))
1077                 return NULL;
1078
1079         table = get_target_table(vcpu->arch.target, true, &num);
1080         r = find_reg(&params, table, num);
1081         if (!r)
1082                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1083
1084         /* Not saved in the sys_reg array? */
1085         if (r && !r->reg)
1086                 r = NULL;
1087
1088         return r;
1089 }
1090
1091 /*
1092  * These are the invariant sys_reg registers: we let the guest see the
1093  * host versions of these, so they're part of the guest state.
1094  *
1095  * A future CPU may provide a mechanism to present different values to
1096  * the guest, or a future kvm may trap them.
1097  */
1098
1099 #define FUNCTION_INVARIANT(reg)                                         \
1100         static void get_##reg(struct kvm_vcpu *v,                       \
1101                               const struct sys_reg_desc *r)             \
1102         {                                                               \
1103                 u64 val;                                                \
1104                                                                         \
1105                 asm volatile("mrs %0, " __stringify(reg) "\n"           \
1106                              : "=r" (val));                             \
1107                 ((struct sys_reg_desc *)r)->val = val;                  \
1108         }
1109
1110 FUNCTION_INVARIANT(midr_el1)
1111 FUNCTION_INVARIANT(ctr_el0)
1112 FUNCTION_INVARIANT(revidr_el1)
1113 FUNCTION_INVARIANT(id_pfr0_el1)
1114 FUNCTION_INVARIANT(id_pfr1_el1)
1115 FUNCTION_INVARIANT(id_dfr0_el1)
1116 FUNCTION_INVARIANT(id_afr0_el1)
1117 FUNCTION_INVARIANT(id_mmfr0_el1)
1118 FUNCTION_INVARIANT(id_mmfr1_el1)
1119 FUNCTION_INVARIANT(id_mmfr2_el1)
1120 FUNCTION_INVARIANT(id_mmfr3_el1)
1121 FUNCTION_INVARIANT(id_isar0_el1)
1122 FUNCTION_INVARIANT(id_isar1_el1)
1123 FUNCTION_INVARIANT(id_isar2_el1)
1124 FUNCTION_INVARIANT(id_isar3_el1)
1125 FUNCTION_INVARIANT(id_isar4_el1)
1126 FUNCTION_INVARIANT(id_isar5_el1)
1127 FUNCTION_INVARIANT(clidr_el1)
1128 FUNCTION_INVARIANT(aidr_el1)
1129
1130 /* ->val is filled in by kvm_sys_reg_table_init() */
1131 static struct sys_reg_desc invariant_sys_regs[] = {
1132         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1133           NULL, get_midr_el1 },
1134         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1135           NULL, get_revidr_el1 },
1136         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1137           NULL, get_id_pfr0_el1 },
1138         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1139           NULL, get_id_pfr1_el1 },
1140         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1141           NULL, get_id_dfr0_el1 },
1142         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1143           NULL, get_id_afr0_el1 },
1144         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1145           NULL, get_id_mmfr0_el1 },
1146         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1147           NULL, get_id_mmfr1_el1 },
1148         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1149           NULL, get_id_mmfr2_el1 },
1150         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1151           NULL, get_id_mmfr3_el1 },
1152         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1153           NULL, get_id_isar0_el1 },
1154         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1155           NULL, get_id_isar1_el1 },
1156         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1157           NULL, get_id_isar2_el1 },
1158         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1159           NULL, get_id_isar3_el1 },
1160         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1161           NULL, get_id_isar4_el1 },
1162         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1163           NULL, get_id_isar5_el1 },
1164         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1165           NULL, get_clidr_el1 },
1166         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1167           NULL, get_aidr_el1 },
1168         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1169           NULL, get_ctr_el0 },
1170 };
1171
1172 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1173 {
1174         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1175                 return -EFAULT;
1176         return 0;
1177 }
1178
1179 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1180 {
1181         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1182                 return -EFAULT;
1183         return 0;
1184 }
1185
1186 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1187 {
1188         struct sys_reg_params params;
1189         const struct sys_reg_desc *r;
1190
1191         if (!index_to_params(id, &params))
1192                 return -ENOENT;
1193
1194         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1195         if (!r)
1196                 return -ENOENT;
1197
1198         return reg_to_user(uaddr, &r->val, id);
1199 }
1200
1201 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1202 {
1203         struct sys_reg_params params;
1204         const struct sys_reg_desc *r;
1205         int err;
1206         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1207
1208         if (!index_to_params(id, &params))
1209                 return -ENOENT;
1210         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1211         if (!r)
1212                 return -ENOENT;
1213
1214         err = reg_from_user(&val, uaddr, id);
1215         if (err)
1216                 return err;
1217
1218         /* This is what we mean by invariant: you can't change it. */
1219         if (r->val != val)
1220                 return -EINVAL;
1221
1222         return 0;
1223 }
1224
1225 static bool is_valid_cache(u32 val)
1226 {
1227         u32 level, ctype;
1228
1229         if (val >= CSSELR_MAX)
1230                 return false;
1231
1232         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1233         level = (val >> 1);
1234         ctype = (cache_levels >> (level * 3)) & 7;
1235
1236         switch (ctype) {
1237         case 0: /* No cache */
1238                 return false;
1239         case 1: /* Instruction cache only */
1240                 return (val & 1);
1241         case 2: /* Data cache only */
1242         case 4: /* Unified cache */
1243                 return !(val & 1);
1244         case 3: /* Separate instruction and data caches */
1245                 return true;
1246         default: /* Reserved: we can't know instruction or data. */
1247                 return false;
1248         }
1249 }
1250
1251 static int demux_c15_get(u64 id, void __user *uaddr)
1252 {
1253         u32 val;
1254         u32 __user *uval = uaddr;
1255
1256         /* Fail if we have unknown bits set. */
1257         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1258                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1259                 return -ENOENT;
1260
1261         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1262         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1263                 if (KVM_REG_SIZE(id) != 4)
1264                         return -ENOENT;
1265                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1266                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1267                 if (!is_valid_cache(val))
1268                         return -ENOENT;
1269
1270                 return put_user(get_ccsidr(val), uval);
1271         default:
1272                 return -ENOENT;
1273         }
1274 }
1275
1276 static int demux_c15_set(u64 id, void __user *uaddr)
1277 {
1278         u32 val, newval;
1279         u32 __user *uval = uaddr;
1280
1281         /* Fail if we have unknown bits set. */
1282         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1283                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1284                 return -ENOENT;
1285
1286         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1287         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1288                 if (KVM_REG_SIZE(id) != 4)
1289                         return -ENOENT;
1290                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1291                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1292                 if (!is_valid_cache(val))
1293                         return -ENOENT;
1294
1295                 if (get_user(newval, uval))
1296                         return -EFAULT;
1297
1298                 /* This is also invariant: you can't change it. */
1299                 if (newval != get_ccsidr(val))
1300                         return -EINVAL;
1301                 return 0;
1302         default:
1303                 return -ENOENT;
1304         }
1305 }
1306
1307 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1308 {
1309         const struct sys_reg_desc *r;
1310         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1311
1312         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1313                 return demux_c15_get(reg->id, uaddr);
1314
1315         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1316                 return -ENOENT;
1317
1318         r = index_to_sys_reg_desc(vcpu, reg->id);
1319         if (!r)
1320                 return get_invariant_sys_reg(reg->id, uaddr);
1321
1322         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
1323 }
1324
1325 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1326 {
1327         const struct sys_reg_desc *r;
1328         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1329
1330         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1331                 return demux_c15_set(reg->id, uaddr);
1332
1333         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1334                 return -ENOENT;
1335
1336         r = index_to_sys_reg_desc(vcpu, reg->id);
1337         if (!r)
1338                 return set_invariant_sys_reg(reg->id, uaddr);
1339
1340         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
1341 }
1342
1343 static unsigned int num_demux_regs(void)
1344 {
1345         unsigned int i, count = 0;
1346
1347         for (i = 0; i < CSSELR_MAX; i++)
1348                 if (is_valid_cache(i))
1349                         count++;
1350
1351         return count;
1352 }
1353
1354 static int write_demux_regids(u64 __user *uindices)
1355 {
1356         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1357         unsigned int i;
1358
1359         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1360         for (i = 0; i < CSSELR_MAX; i++) {
1361                 if (!is_valid_cache(i))
1362                         continue;
1363                 if (put_user(val | i, uindices))
1364                         return -EFAULT;
1365                 uindices++;
1366         }
1367         return 0;
1368 }
1369
1370 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
1371 {
1372         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
1373                 KVM_REG_ARM64_SYSREG |
1374                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
1375                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
1376                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
1377                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
1378                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
1379 }
1380
1381 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
1382 {
1383         if (!*uind)
1384                 return true;
1385
1386         if (put_user(sys_reg_to_index(reg), *uind))
1387                 return false;
1388
1389         (*uind)++;
1390         return true;
1391 }
1392
1393 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
1394 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
1395 {
1396         const struct sys_reg_desc *i1, *i2, *end1, *end2;
1397         unsigned int total = 0;
1398         size_t num;
1399
1400         /* We check for duplicates here, to allow arch-specific overrides. */
1401         i1 = get_target_table(vcpu->arch.target, true, &num);
1402         end1 = i1 + num;
1403         i2 = sys_reg_descs;
1404         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
1405
1406         BUG_ON(i1 == end1 || i2 == end2);
1407
1408         /* Walk carefully, as both tables may refer to the same register. */
1409         while (i1 || i2) {
1410                 int cmp = cmp_sys_reg(i1, i2);
1411                 /* target-specific overrides generic entry. */
1412                 if (cmp <= 0) {
1413                         /* Ignore registers we trap but don't save. */
1414                         if (i1->reg) {
1415                                 if (!copy_reg_to_user(i1, &uind))
1416                                         return -EFAULT;
1417                                 total++;
1418                         }
1419                 } else {
1420                         /* Ignore registers we trap but don't save. */
1421                         if (i2->reg) {
1422                                 if (!copy_reg_to_user(i2, &uind))
1423                                         return -EFAULT;
1424                                 total++;
1425                         }
1426                 }
1427
1428                 if (cmp <= 0 && ++i1 == end1)
1429                         i1 = NULL;
1430                 if (cmp >= 0 && ++i2 == end2)
1431                         i2 = NULL;
1432         }
1433         return total;
1434 }
1435
1436 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
1437 {
1438         return ARRAY_SIZE(invariant_sys_regs)
1439                 + num_demux_regs()
1440                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
1441 }
1442
1443 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1444 {
1445         unsigned int i;
1446         int err;
1447
1448         /* Then give them all the invariant registers' indices. */
1449         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
1450                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
1451                         return -EFAULT;
1452                 uindices++;
1453         }
1454
1455         err = walk_sys_regs(vcpu, uindices);
1456         if (err < 0)
1457                 return err;
1458         uindices += err;
1459
1460         return write_demux_regids(uindices);
1461 }
1462
1463 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
1464 {
1465         unsigned int i;
1466
1467         for (i = 1; i < n; i++) {
1468                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
1469                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
1470                         return 1;
1471                 }
1472         }
1473
1474         return 0;
1475 }
1476
1477 void kvm_sys_reg_table_init(void)
1478 {
1479         unsigned int i;
1480         struct sys_reg_desc clidr;
1481
1482         /* Make sure tables are unique and in order. */
1483         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
1484         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
1485         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
1486         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1487         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
1488         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
1489
1490         /* We abuse the reset function to overwrite the table itself. */
1491         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
1492                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
1493
1494         /*
1495          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
1496          *
1497          *   If software reads the Cache Type fields from Ctype1
1498          *   upwards, once it has seen a value of 0b000, no caches
1499          *   exist at further-out levels of the hierarchy. So, for
1500          *   example, if Ctype3 is the first Cache Type field with a
1501          *   value of 0b000, the values of Ctype4 to Ctype7 must be
1502          *   ignored.
1503          */
1504         get_clidr_el1(NULL, &clidr); /* Ugly... */
1505         cache_levels = clidr.val;
1506         for (i = 0; i < 7; i++)
1507                 if (((cache_levels >> (i*3)) & 7) == 0)
1508                         break;
1509         /* Clear all higher bits. */
1510         cache_levels &= (1 << (i*3))-1;
1511 }
1512
1513 /**
1514  * kvm_reset_sys_regs - sets system registers to reset value
1515  * @vcpu: The VCPU pointer
1516  *
1517  * This function finds the right table above and sets the registers on the
1518  * virtual CPU struct to their architecturally defined reset values.
1519  */
1520 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
1521 {
1522         size_t num;
1523         const struct sys_reg_desc *table;
1524
1525         /* Catch someone adding a register without putting in reset entry. */
1526         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
1527
1528         /* Generic chip reset first (so target could override). */
1529         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1530
1531         table = get_target_table(vcpu->arch.target, true, &num);
1532         reset_sys_reg_descs(vcpu, table, num);
1533
1534         for (num = 1; num < NR_SYS_REGS; num++)
1535                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
1536                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
1537 }