arch/mips/include/asm/cpu.h

   1 /*
   2  * cpu.h: Values of the PRId register used to match up
   3  *        various MIPS cpu types.
   4  *
   5  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   6  * Copyright (C) 2004, 2013  Maciej W. Rozycki
   7  */
   8 #ifndef _ASM_CPU_H
   9 #define _ASM_CPU_H
  10
  11 /*
  12    As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
  13    register 15, select 0) is defined in this (backwards compatible) way:
  14
  15   +----------------+----------------+----------------+----------------+
  16   | Company Options| Company ID     | Processor ID   | Revision       |
  17   +----------------+----------------+----------------+----------------+
  18    31            24 23            16 15             8 7
  19
  20    I don't have docs for all the previous processors, but my impression is
  21    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
  22    spec.
  23 */
  24
  25 #define PRID_OPT_MASK           0xff000000
  26
  27 /*
  28  * Assigned Company values for bits 23:16 of the PRId register.
  29  */
  30
  31 #define PRID_COMP_MASK          0xff0000
  32
  33 #define PRID_COMP_LEGACY        0x000000
  34 #define PRID_COMP_MIPS          0x010000
  35 #define PRID_COMP_BROADCOM      0x020000
  36 #define PRID_COMP_ALCHEMY       0x030000
  37 #define PRID_COMP_SIBYTE        0x040000
  38 #define PRID_COMP_SANDCRAFT     0x050000
  39 #define PRID_COMP_NXP           0x060000
  40 #define PRID_COMP_TOSHIBA       0x070000
  41 #define PRID_COMP_LSI           0x080000
  42 #define PRID_COMP_LEXRA         0x0b0000
  43 #define PRID_COMP_NETLOGIC      0x0c0000
  44 #define PRID_COMP_CAVIUM        0x0d0000
  45 #define PRID_COMP_INGENIC       0xd00000
  46
  47 /*
  48  * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
  49  * register.  In order to detect a certain CPU type exactly eventually
  50  * additional registers may need to be examined.
  51  */
  52
  53 #define PRID_IMP_MASK           0xff00
  54
  55 /*
  56  * These are valid when 23:16 == PRID_COMP_LEGACY
  57  */
  58
  59 #define PRID_IMP_R2000          0x0100
  60 #define PRID_IMP_AU1_REV1       0x0100
  61 #define PRID_IMP_AU1_REV2       0x0200
  62 #define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
  63 #define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
  64 #define PRID_IMP_R4000          0x0400
  65 #define PRID_IMP_R6000A         0x0600
  66 #define PRID_IMP_R10000         0x0900
  67 #define PRID_IMP_R4300          0x0b00
  68 #define PRID_IMP_VR41XX         0x0c00
  69 #define PRID_IMP_R12000         0x0e00
  70 #define PRID_IMP_R14000         0x0f00
  71 #define PRID_IMP_R8000          0x1000
  72 #define PRID_IMP_PR4450         0x1200
  73 #define PRID_IMP_R4600          0x2000
  74 #define PRID_IMP_R4700          0x2100
  75 #define PRID_IMP_TX39           0x2200
  76 #define PRID_IMP_R4640          0x2200
  77 #define PRID_IMP_R4650          0x2200          /* Same as R4640 */
  78 #define PRID_IMP_R5000          0x2300
  79 #define PRID_IMP_TX49           0x2d00
  80 #define PRID_IMP_SONIC          0x2400
  81 #define PRID_IMP_MAGIC          0x2500
  82 #define PRID_IMP_RM7000         0x2700
  83 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
  84 #define PRID_IMP_RM9000         0x3400
  85 #define PRID_IMP_LOONGSON1      0x4200
  86 #define PRID_IMP_R5432          0x5400
  87 #define PRID_IMP_R5500          0x5500
  88 #define PRID_IMP_LOONGSON2      0x6300
  89
  90 #define PRID_IMP_UNKNOWN        0xff00
  91
  92 /*
  93  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
  94  */
  95
  96 #define PRID_IMP_4KC            0x8000
  97 #define PRID_IMP_5KC            0x8100
  98 #define PRID_IMP_20KC           0x8200
  99 #define PRID_IMP_4KEC           0x8400
 100 #define PRID_IMP_4KSC           0x8600
 101 #define PRID_IMP_25KF           0x8800
 102 #define PRID_IMP_5KE            0x8900
 103 #define PRID_IMP_4KECR2         0x9000
 104 #define PRID_IMP_4KEMPR2        0x9100
 105 #define PRID_IMP_4KSD           0x9200
 106 #define PRID_IMP_24K            0x9300
 107 #define PRID_IMP_34K            0x9500
 108 #define PRID_IMP_24KE           0x9600
 109 #define PRID_IMP_74K            0x9700
 110 #define PRID_IMP_1004K          0x9900
 111 #define PRID_IMP_1074K          0x9a00
 112 #define PRID_IMP_M14KC          0x9c00
 113 #define PRID_IMP_M14KEC         0x9e00
 114
 115 /*
 116  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 117  */
 118
 119 #define PRID_IMP_SB1            0x0100
 120 #define PRID_IMP_SB1A           0x1100
 121
 122 /*
 123  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
 124  */
 125
 126 #define PRID_IMP_SR71000        0x0400
 127
 128 /*
 129  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
 130  */
 131
 132 #define PRID_IMP_BMIPS32_REV4   0x4000
 133 #define PRID_IMP_BMIPS32_REV8   0x8000
 134 #define PRID_IMP_BMIPS3300      0x9000
 135 #define PRID_IMP_BMIPS3300_ALT  0x9100
 136 #define PRID_IMP_BMIPS3300_BUG  0x0000
 137 #define PRID_IMP_BMIPS43XX      0xa000
 138 #define PRID_IMP_BMIPS5000      0x5a00
 139
 140 #define PRID_REV_BMIPS4380_LO   0x0040
 141 #define PRID_REV_BMIPS4380_HI   0x006f
 142
 143 /*
 144  * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
 145  */
 146
 147 #define PRID_IMP_CAVIUM_CN38XX 0x0000
 148 #define PRID_IMP_CAVIUM_CN31XX 0x0100
 149 #define PRID_IMP_CAVIUM_CN30XX 0x0200
 150 #define PRID_IMP_CAVIUM_CN58XX 0x0300
 151 #define PRID_IMP_CAVIUM_CN56XX 0x0400
 152 #define PRID_IMP_CAVIUM_CN50XX 0x0600
 153 #define PRID_IMP_CAVIUM_CN52XX 0x0700
 154 #define PRID_IMP_CAVIUM_CN63XX 0x9000
 155 #define PRID_IMP_CAVIUM_CN68XX 0x9100
 156 #define PRID_IMP_CAVIUM_CN66XX 0x9200
 157 #define PRID_IMP_CAVIUM_CN61XX 0x9300
 158 #define PRID_IMP_CAVIUM_CNF71XX 0x9400
 159 #define PRID_IMP_CAVIUM_CN78XX 0x9500
 160 #define PRID_IMP_CAVIUM_CN70XX 0x9600
 161
 162 /*
 163  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
 164  */
 165
 166 #define PRID_IMP_JZRISC        0x0200
 167
 168 /*
 169  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
 170  */
 171 #define PRID_IMP_NETLOGIC_XLR732        0x0000
 172 #define PRID_IMP_NETLOGIC_XLR716        0x0200
 173 #define PRID_IMP_NETLOGIC_XLR532        0x0900
 174 #define PRID_IMP_NETLOGIC_XLR308        0x0600
 175 #define PRID_IMP_NETLOGIC_XLR532C       0x0800
 176 #define PRID_IMP_NETLOGIC_XLR516C       0x0a00
 177 #define PRID_IMP_NETLOGIC_XLR508C       0x0b00
 178 #define PRID_IMP_NETLOGIC_XLR308C       0x0f00
 179 #define PRID_IMP_NETLOGIC_XLS608        0x8000
 180 #define PRID_IMP_NETLOGIC_XLS408        0x8800
 181 #define PRID_IMP_NETLOGIC_XLS404        0x8c00
 182 #define PRID_IMP_NETLOGIC_XLS208        0x8e00
 183 #define PRID_IMP_NETLOGIC_XLS204        0x8f00
 184 #define PRID_IMP_NETLOGIC_XLS108        0xce00
 185 #define PRID_IMP_NETLOGIC_XLS104        0xcf00
 186 #define PRID_IMP_NETLOGIC_XLS616B       0x4000
 187 #define PRID_IMP_NETLOGIC_XLS608B       0x4a00
 188 #define PRID_IMP_NETLOGIC_XLS416B       0x4400
 189 #define PRID_IMP_NETLOGIC_XLS412B       0x4c00
 190 #define PRID_IMP_NETLOGIC_XLS408B       0x4e00
 191 #define PRID_IMP_NETLOGIC_XLS404B       0x4f00
 192 #define PRID_IMP_NETLOGIC_AU13XX        0x8000
 193
 194 #define PRID_IMP_NETLOGIC_XLP8XX        0x1000
 195 #define PRID_IMP_NETLOGIC_XLP3XX        0x1100
 196 #define PRID_IMP_NETLOGIC_XLP2XX        0x1200
 197
 198 /*
 199  * Particular Revision values for bits 7:0 of the PRId register.
 200  */
 201
 202 #define PRID_REV_MASK           0x00ff
 203
 204 /*
 205  * Definitions for 7:0 on legacy processors
 206  */
 207
 208 #define PRID_REV_TX4927         0x0022
 209 #define PRID_REV_TX4937         0x0030
 210 #define PRID_REV_R4400          0x0040
 211 #define PRID_REV_R3000A         0x0030
 212 #define PRID_REV_R3000          0x0020
 213 #define PRID_REV_R2000A         0x0010
 214 #define PRID_REV_TX3912         0x0010
 215 #define PRID_REV_TX3922         0x0030
 216 #define PRID_REV_TX3927         0x0040
 217 #define PRID_REV_VR4111         0x0050
 218 #define PRID_REV_VR4181         0x0050  /* Same as VR4111 */
 219 #define PRID_REV_VR4121         0x0060
 220 #define PRID_REV_VR4122         0x0070
 221 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 222 #define PRID_REV_VR4130         0x0080
 223 #define PRID_REV_34K_V1_0_2     0x0022
 224 #define PRID_REV_LOONGSON1B     0x0020
 225 #define PRID_REV_LOONGSON2E     0x0002
 226 #define PRID_REV_LOONGSON2F     0x0003
 227
 228 /*
 229  * Older processors used to encode processor version and revision in two
 230  * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
 231  * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
 232  * the patch number.  *ARGH*
 233  */
 234 #define PRID_REV_ENCODE_44(ver, rev)                                    \
 235         ((ver) << 4 | (rev))
 236 #define PRID_REV_ENCODE_332(ver, rev, patch)                            \
 237         ((ver) << 5 | (rev) << 2 | (patch))
 238
 239 /*
 240  * FPU implementation/revision register (CP1 control register 0).
 241  *
 242  * +---------------------------------+----------------+----------------+
 243  * | 0                               | Implementation | Revision       |
 244  * +---------------------------------+----------------+----------------+
 245  *  31                             16 15             8 7              0
 246  */
 247
 248 #define FPIR_IMP_MASK           0xff00
 249
 250 #define FPIR_IMP_NONE           0x0000
 251
 252 enum cpu_type_enum {
 253         CPU_UNKNOWN,
 254
 255         /*
 256          * R2000 class processors
 257          */
 258         CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
 259         CPU_R3081, CPU_R3081E,
 260
 261         /*
 262          * R6000 class processors
 263          */
 264         CPU_R6000, CPU_R6000A,
 265
 266         /*
 267          * R4000 class processors
 268          */
 269         CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
 270         CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
 271         CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
 272         CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
 273         CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
 274         CPU_SR71000, CPU_RM9000, CPU_TX49XX,
 275
 276         /*
 277          * R8000 class processors
 278          */
 279         CPU_R8000,
 280
 281         /*
 282          * TX3900 class processors
 283          */
 284         CPU_TX3912, CPU_TX3922, CPU_TX3927,
 285
 286         /*
 287          * MIPS32 class processors
 288          */
 289         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
 290         CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
 291         CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
 292         CPU_M14KEC,
 293
 294         /*
 295          * MIPS64 class processors
 296          */
 297         CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
 298         CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
 299         CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
 300
 301         CPU_LAST
 302 };
 303
 304
 305 /*
 306  * ISA Level encodings
 307  *
 308  */
 309 #define MIPS_CPU_ISA_II         0x00000001
 310 #define MIPS_CPU_ISA_III        0x00000002
 311 #define MIPS_CPU_ISA_IV         0x00000004
 312 #define MIPS_CPU_ISA_V          0x00000008
 313 #define MIPS_CPU_ISA_M32R1      0x00000010
 314 #define MIPS_CPU_ISA_M32R2      0x00000020
 315 #define MIPS_CPU_ISA_M64R1      0x00000040
 316 #define MIPS_CPU_ISA_M64R2      0x00000080
 317
 318 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
 319         MIPS_CPU_ISA_M32R2)
 320 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
 321         MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
 322
 323 /*
 324  * CPU Option encodings
 325  */
 326 #define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
 327 #define MIPS_CPU_4KEX           0x00000002 /* "R4K" exception model */
 328 #define MIPS_CPU_3K_CACHE       0x00000004 /* R3000-style caches */
 329 #define MIPS_CPU_4K_CACHE       0x00000008 /* R4000-style caches */
 330 #define MIPS_CPU_TX39_CACHE     0x00000010 /* TX3900-style caches */
 331 #define MIPS_CPU_FPU            0x00000020 /* CPU has FPU */
 332 #define MIPS_CPU_32FPR          0x00000040 /* 32 dbl. prec. FP registers */
 333 #define MIPS_CPU_COUNTER        0x00000080 /* Cycle count/compare */
 334 #define MIPS_CPU_WATCH          0x00000100 /* watchpoint registers */
 335 #define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
 336 #define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
 337 #define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
 338 #define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
 339 #define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
 340 #define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
 341 #define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
 342 #define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
 343 #define MIPS_CPU_INCLUSIVE_CACHES       0x00020000 /* P-cache subset enforced */
 344 #define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
 345 #define MIPS_CPU_VINT           0x00080000 /* CPU supports MIPSR2 vectored interrupts */
 346 #define MIPS_CPU_VEIC           0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
 347 #define MIPS_CPU_ULRI           0x00200000 /* CPU has ULRI feature */
 348 #define MIPS_CPU_PCI            0x00400000 /* CPU has Perf Ctr Int indicator */
 349 #define MIPS_CPU_RIXI           0x00800000 /* CPU has TLB Read/eXec Inhibit */
 350 #define MIPS_CPU_MICROMIPS      0x01000000 /* CPU has microMIPS capability */
 351
 352 /*
 353  * CPU ASE encodings
 354  */
 355 #define MIPS_ASE_MIPS16         0x00000001 /* code compression */
 356 #define MIPS_ASE_MDMX           0x00000002 /* MIPS digital media extension */
 357 #define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
 358 #define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
 359 #define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
 360 #define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
 361 #define MIPS_ASE_DSP2P          0x00000040 /* Signal Processing ASE Rev 2 */
 362 #define MIPS_ASE_VZ             0x00000080 /* Virtualization ASE */
 363
 364 #endif /* _ASM_CPU_H */