arch/powerpc/include/asm/opal.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_H
  13 #define __OPAL_H
  14
  15 /****** Takeover interface ********/
  16
  17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
  18  * it from within pHyp (tech preview only).
  19  *
  20  * This is exclusively used in prom_init.c
  21  */
  22
  23 #ifndef __ASSEMBLY__
  24
  25 struct opal_takeover_args {
  26         u64     k_image;                /* r4 */
  27         u64     k_size;                 /* r5 */
  28         u64     k_entry;                /* r6 */
  29         u64     k_entry2;               /* r7 */
  30         u64     hal_addr;               /* r8 */
  31         u64     rd_image;               /* r9 */
  32         u64     rd_size;                /* r10 */
  33         u64     rd_loc;                 /* r11 */
  34 };
  35
  36 /*
  37  * SG entry
  38  *
  39  * WARNING: The current implementation requires each entry
  40  * to represent a block that is 4k aligned *and* each block
  41  * size except the last one in the list to be as well.
  42  */
  43 struct opal_sg_entry {
  44         __be64 data;
  45         __be64 length;
  46 };
  47
  48 /* SG list */
  49 struct opal_sg_list {
  50         __be64 length;
  51         __be64 next;
  52         struct opal_sg_entry entry[];
  53 };
  54
  55 /* We calculate number of sg entries based on PAGE_SIZE */
  56 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
  57
  58 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
  59
  60 extern long opal_do_takeover(struct opal_takeover_args *args);
  61
  62 struct rtas_args;
  63 extern int opal_enter_rtas(struct rtas_args *args,
  64                            unsigned long data,
  65                            unsigned long entry);
  66
  67 #endif /* __ASSEMBLY__ */
  68
  69 /****** OPAL APIs ******/
  70
  71 /* Return codes */
  72 #define OPAL_SUCCESS            0
  73 #define OPAL_PARAMETER          -1
  74 #define OPAL_BUSY               -2
  75 #define OPAL_PARTIAL            -3
  76 #define OPAL_CONSTRAINED        -4
  77 #define OPAL_CLOSED             -5
  78 #define OPAL_HARDWARE           -6
  79 #define OPAL_UNSUPPORTED        -7
  80 #define OPAL_PERMISSION         -8
  81 #define OPAL_NO_MEM             -9
  82 #define OPAL_RESOURCE           -10
  83 #define OPAL_INTERNAL_ERROR     -11
  84 #define OPAL_BUSY_EVENT         -12
  85 #define OPAL_HARDWARE_FROZEN    -13
  86 #define OPAL_WRONG_STATE        -14
  87 #define OPAL_ASYNC_COMPLETION   -15
  88
  89 /* API Tokens (in r0) */
  90 #define OPAL_INVALID_CALL                       -1
  91 #define OPAL_CONSOLE_WRITE                      1
  92 #define OPAL_CONSOLE_READ                       2
  93 #define OPAL_RTC_READ                           3
  94 #define OPAL_RTC_WRITE                          4
  95 #define OPAL_CEC_POWER_DOWN                     5
  96 #define OPAL_CEC_REBOOT                         6
  97 #define OPAL_READ_NVRAM                         7
  98 #define OPAL_WRITE_NVRAM                        8
  99 #define OPAL_HANDLE_INTERRUPT                   9
 100 #define OPAL_POLL_EVENTS                        10
 101 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
 102 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
 103 #define OPAL_PCI_CONFIG_READ_BYTE               13
 104 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
 105 #define OPAL_PCI_CONFIG_READ_WORD               15
 106 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
 107 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
 108 #define OPAL_PCI_CONFIG_WRITE_WORD              18
 109 #define OPAL_SET_XIVE                           19
 110 #define OPAL_GET_XIVE                           20
 111 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
 112 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
 113 #define OPAL_PCI_EEH_FREEZE_STATUS              23
 114 #define OPAL_PCI_SHPC                           24
 115 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
 116 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
 117 #define OPAL_PCI_PHB_MMIO_ENABLE                27
 118 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
 119 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
 120 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
 121 #define OPAL_PCI_SET_PE                         31
 122 #define OPAL_PCI_SET_PELTV                      32
 123 #define OPAL_PCI_SET_MVE                        33
 124 #define OPAL_PCI_SET_MVE_ENABLE                 34
 125 #define OPAL_PCI_GET_XIVE_REISSUE               35
 126 #define OPAL_PCI_SET_XIVE_REISSUE               36
 127 #define OPAL_PCI_SET_XIVE_PE                    37
 128 #define OPAL_GET_XIVE_SOURCE                    38
 129 #define OPAL_GET_MSI_32                         39
 130 #define OPAL_GET_MSI_64                         40
 131 #define OPAL_START_CPU                          41
 132 #define OPAL_QUERY_CPU_STATUS                   42
 133 #define OPAL_WRITE_OPPANEL                      43
 134 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 135 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 136 #define OPAL_PCI_RESET                          49
 137 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
 138 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
 139 #define OPAL_PCI_FENCE_PHB                      52
 140 #define OPAL_PCI_REINIT                         53
 141 #define OPAL_PCI_MASK_PE_ERROR                  54
 142 #define OPAL_SET_SLOT_LED_STATUS                55
 143 #define OPAL_GET_EPOW_STATUS                    56
 144 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 145 #define OPAL_RESERVED1                          58
 146 #define OPAL_RESERVED2                          59
 147 #define OPAL_PCI_NEXT_ERROR                     60
 148 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 149 #define OPAL_PCI_POLL                           62
 150 #define OPAL_PCI_MSI_EOI                        63
 151 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 152 #define OPAL_XSCOM_READ                         65
 153 #define OPAL_XSCOM_WRITE                        66
 154 #define OPAL_LPC_READ                           67
 155 #define OPAL_LPC_WRITE                          68
 156 #define OPAL_RETURN_CPU                         69
 157 #define OPAL_REINIT_CPUS                        70
 158 #define OPAL_ELOG_READ                          71
 159 #define OPAL_ELOG_WRITE                         72
 160 #define OPAL_ELOG_ACK                           73
 161 #define OPAL_ELOG_RESEND                        74
 162 #define OPAL_ELOG_SIZE                          75
 163 #define OPAL_FLASH_VALIDATE                     76
 164 #define OPAL_FLASH_MANAGE                       77
 165 #define OPAL_FLASH_UPDATE                       78
 166 #define OPAL_RESYNC_TIMEBASE                    79
 167 #define OPAL_DUMP_INIT                          81
 168 #define OPAL_DUMP_INFO                          82
 169 #define OPAL_DUMP_READ                          83
 170 #define OPAL_DUMP_ACK                           84
 171 #define OPAL_GET_MSG                            85
 172 #define OPAL_CHECK_ASYNC_COMPLETION             86
 173 #define OPAL_SYNC_HOST_REBOOT                   87
 174 #define OPAL_SENSOR_READ                        88
 175 #define OPAL_GET_PARAM                          89
 176 #define OPAL_SET_PARAM                          90
 177 #define OPAL_DUMP_RESEND                        91
 178 #define OPAL_DUMP_INFO2                         94
 179
 180 #ifndef __ASSEMBLY__
 181
 182 #include <linux/notifier.h>
 183
 184 /* Other enums */
 185 enum OpalVendorApiTokens {
 186         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 187 };
 188
 189 enum OpalFreezeState {
 190         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 191         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 192         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 193         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 194         OPAL_EEH_STOPPED_RESET = 4,
 195         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 196         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 197 };
 198
 199 enum OpalEehFreezeActionToken {
 200         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 201         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 202         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
 203 };
 204
 205 enum OpalPciStatusToken {
 206         OPAL_EEH_NO_ERROR       = 0,
 207         OPAL_EEH_IOC_ERROR      = 1,
 208         OPAL_EEH_PHB_ERROR      = 2,
 209         OPAL_EEH_PE_ERROR       = 3,
 210         OPAL_EEH_PE_MMIO_ERROR  = 4,
 211         OPAL_EEH_PE_DMA_ERROR   = 5
 212 };
 213
 214 enum OpalPciErrorSeverity {
 215         OPAL_EEH_SEV_NO_ERROR   = 0,
 216         OPAL_EEH_SEV_IOC_DEAD   = 1,
 217         OPAL_EEH_SEV_PHB_DEAD   = 2,
 218         OPAL_EEH_SEV_PHB_FENCED = 3,
 219         OPAL_EEH_SEV_PE_ER      = 4,
 220         OPAL_EEH_SEV_INF        = 5
 221 };
 222
 223 enum OpalShpcAction {
 224         OPAL_SHPC_GET_LINK_STATE = 0,
 225         OPAL_SHPC_GET_SLOT_STATE = 1
 226 };
 227
 228 enum OpalShpcLinkState {
 229         OPAL_SHPC_LINK_DOWN = 0,
 230         OPAL_SHPC_LINK_UP = 1
 231 };
 232
 233 enum OpalMmioWindowType {
 234         OPAL_M32_WINDOW_TYPE = 1,
 235         OPAL_M64_WINDOW_TYPE = 2,
 236         OPAL_IO_WINDOW_TYPE = 3
 237 };
 238
 239 enum OpalShpcSlotState {
 240         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 241         OPAL_SHPC_DEV_PRESENT = 1
 242 };
 243
 244 enum OpalExceptionHandler {
 245         OPAL_MACHINE_CHECK_HANDLER = 1,
 246         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 247         OPAL_SOFTPATCH_HANDLER = 3
 248 };
 249
 250 enum OpalPendingState {
 251         OPAL_EVENT_OPAL_INTERNAL        = 0x1,
 252         OPAL_EVENT_NVRAM                = 0x2,
 253         OPAL_EVENT_RTC                  = 0x4,
 254         OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
 255         OPAL_EVENT_CONSOLE_INPUT        = 0x10,
 256         OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
 257         OPAL_EVENT_ERROR_LOG            = 0x40,
 258         OPAL_EVENT_EPOW                 = 0x80,
 259         OPAL_EVENT_LED_STATUS           = 0x100,
 260         OPAL_EVENT_PCI_ERROR            = 0x200,
 261         OPAL_EVENT_DUMP_AVAIL           = 0x400,
 262         OPAL_EVENT_MSG_PENDING          = 0x800,
 263 };
 264
 265 enum OpalMessageType {
 266         OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
 267                                          * additional params function-specific
 268                                          */
 269         OPAL_MSG_MEM_ERR,
 270         OPAL_MSG_EPOW,
 271         OPAL_MSG_SHUTDOWN,
 272         OPAL_MSG_TYPE_MAX,
 273 };
 274
 275 /* Machine check related definitions */
 276 enum OpalMCE_Version {
 277         OpalMCE_V1 = 1,
 278 };
 279
 280 enum OpalMCE_Severity {
 281         OpalMCE_SEV_NO_ERROR = 0,
 282         OpalMCE_SEV_WARNING = 1,
 283         OpalMCE_SEV_ERROR_SYNC = 2,
 284         OpalMCE_SEV_FATAL = 3,
 285 };
 286
 287 enum OpalMCE_Disposition {
 288         OpalMCE_DISPOSITION_RECOVERED = 0,
 289         OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
 290 };
 291
 292 enum OpalMCE_Initiator {
 293         OpalMCE_INITIATOR_UNKNOWN = 0,
 294         OpalMCE_INITIATOR_CPU = 1,
 295 };
 296
 297 enum OpalMCE_ErrorType {
 298         OpalMCE_ERROR_TYPE_UNKNOWN = 0,
 299         OpalMCE_ERROR_TYPE_UE = 1,
 300         OpalMCE_ERROR_TYPE_SLB = 2,
 301         OpalMCE_ERROR_TYPE_ERAT = 3,
 302         OpalMCE_ERROR_TYPE_TLB = 4,
 303 };
 304
 305 enum OpalMCE_UeErrorType {
 306         OpalMCE_UE_ERROR_INDETERMINATE = 0,
 307         OpalMCE_UE_ERROR_IFETCH = 1,
 308         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
 309         OpalMCE_UE_ERROR_LOAD_STORE = 3,
 310         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
 311 };
 312
 313 enum OpalMCE_SlbErrorType {
 314         OpalMCE_SLB_ERROR_INDETERMINATE = 0,
 315         OpalMCE_SLB_ERROR_PARITY = 1,
 316         OpalMCE_SLB_ERROR_MULTIHIT = 2,
 317 };
 318
 319 enum OpalMCE_EratErrorType {
 320         OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
 321         OpalMCE_ERAT_ERROR_PARITY = 1,
 322         OpalMCE_ERAT_ERROR_MULTIHIT = 2,
 323 };
 324
 325 enum OpalMCE_TlbErrorType {
 326         OpalMCE_TLB_ERROR_INDETERMINATE = 0,
 327         OpalMCE_TLB_ERROR_PARITY = 1,
 328         OpalMCE_TLB_ERROR_MULTIHIT = 2,
 329 };
 330
 331 enum OpalThreadStatus {
 332         OPAL_THREAD_INACTIVE = 0x0,
 333         OPAL_THREAD_STARTED = 0x1,
 334         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 335 };
 336
 337 enum OpalPciBusCompare {
 338         OpalPciBusAny   = 0,    /* Any bus number match */
 339         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 340         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 341         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 342         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 343         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 344         OpalPciBusAll   = 7,    /* Match bus number exactly */
 345 };
 346
 347 enum OpalDeviceCompare {
 348         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 349         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 350 };
 351
 352 enum OpalFuncCompare {
 353         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 354         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 355 };
 356
 357 enum OpalPeAction {
 358         OPAL_UNMAP_PE = 0,
 359         OPAL_MAP_PE = 1
 360 };
 361
 362 enum OpalPeltvAction {
 363         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 364         OPAL_ADD_PE_TO_DOMAIN = 1
 365 };
 366
 367 enum OpalMveEnableAction {
 368         OPAL_DISABLE_MVE = 0,
 369         OPAL_ENABLE_MVE = 1
 370 };
 371
 372 enum OpalPciResetScope {
 373         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
 374         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
 375         OPAL_PCI_IODA_TABLE_RESET = 6,
 376 };
 377
 378 enum OpalPciReinitScope {
 379         OPAL_REINIT_PCI_DEV = 1000
 380 };
 381
 382 enum OpalPciResetState {
 383         OPAL_DEASSERT_RESET = 0,
 384         OPAL_ASSERT_RESET = 1
 385 };
 386
 387 enum OpalPciMaskAction {
 388         OPAL_UNMASK_ERROR_TYPE = 0,
 389         OPAL_MASK_ERROR_TYPE = 1
 390 };
 391
 392 enum OpalSlotLedType {
 393         OPAL_SLOT_LED_ID_TYPE = 0,
 394         OPAL_SLOT_LED_FAULT_TYPE = 1
 395 };
 396
 397 enum OpalLedAction {
 398         OPAL_TURN_OFF_LED = 0,
 399         OPAL_TURN_ON_LED = 1,
 400         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 401 };
 402
 403 enum OpalEpowStatus {
 404         OPAL_EPOW_NONE = 0,
 405         OPAL_EPOW_UPS = 1,
 406         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 407         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 408 };
 409
 410 /*
 411  * Address cycle types for LPC accesses. These also correspond
 412  * to the content of the first cell of the "reg" property for
 413  * device nodes on the LPC bus
 414  */
 415 enum OpalLPCAddressType {
 416         OPAL_LPC_MEM    = 0,
 417         OPAL_LPC_IO     = 1,
 418         OPAL_LPC_FW     = 2,
 419 };
 420
 421 /* System parameter permission */
 422 enum OpalSysparamPerm {
 423         OPAL_SYSPARAM_READ      = 0x1,
 424         OPAL_SYSPARAM_WRITE     = 0x2,
 425         OPAL_SYSPARAM_RW        = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 426 };
 427
 428 struct opal_msg {
 429         __be32 msg_type;
 430         __be32 reserved;
 431         __be64 params[8];
 432 };
 433
 434 struct opal_machine_check_event {
 435         enum OpalMCE_Version    version:8;      /* 0x00 */
 436         uint8_t                 in_use;         /* 0x01 */
 437         enum OpalMCE_Severity   severity:8;     /* 0x02 */
 438         enum OpalMCE_Initiator  initiator:8;    /* 0x03 */
 439         enum OpalMCE_ErrorType  error_type:8;   /* 0x04 */
 440         enum OpalMCE_Disposition disposition:8; /* 0x05 */
 441         uint8_t                 reserved_1[2];  /* 0x06 */
 442         uint64_t                gpr3;           /* 0x08 */
 443         uint64_t                srr0;           /* 0x10 */
 444         uint64_t                srr1;           /* 0x18 */
 445         union {                                 /* 0x20 */
 446                 struct {
 447                         enum OpalMCE_UeErrorType ue_error_type:8;
 448                         uint8_t         effective_address_provided;
 449                         uint8_t         physical_address_provided;
 450                         uint8_t         reserved_1[5];
 451                         uint64_t        effective_address;
 452                         uint64_t        physical_address;
 453                         uint8_t         reserved_2[8];
 454                 } ue_error;
 455
 456                 struct {
 457                         enum OpalMCE_SlbErrorType slb_error_type:8;
 458                         uint8_t         effective_address_provided;
 459                         uint8_t         reserved_1[6];
 460                         uint64_t        effective_address;
 461                         uint8_t         reserved_2[16];
 462                 } slb_error;
 463
 464                 struct {
 465                         enum OpalMCE_EratErrorType erat_error_type:8;
 466                         uint8_t         effective_address_provided;
 467                         uint8_t         reserved_1[6];
 468                         uint64_t        effective_address;
 469                         uint8_t         reserved_2[16];
 470                 } erat_error;
 471
 472                 struct {
 473                         enum OpalMCE_TlbErrorType tlb_error_type:8;
 474                         uint8_t         effective_address_provided;
 475                         uint8_t         reserved_1[6];
 476                         uint64_t        effective_address;
 477                         uint8_t         reserved_2[16];
 478                 } tlb_error;
 479         } u;
 480 };
 481
 482 /* FSP memory errors handling */
 483 enum OpalMemErr_Version {
 484         OpalMemErr_V1 = 1,
 485 };
 486
 487 enum OpalMemErrType {
 488         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 489         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 490         OPAL_MEM_ERR_TYPE_SCRUB,
 491 };
 492
 493 /* Memory Reilience error type */
 494 enum OpalMemErr_ResilErrType {
 495         OPAL_MEM_RESILIENCE_CE          = 0,
 496         OPAL_MEM_RESILIENCE_UE,
 497         OPAL_MEM_RESILIENCE_UE_SCRUB,
 498 };
 499
 500 /* Dynamic Memory Deallocation type */
 501 enum OpalMemErr_DynErrType {
 502         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 503 };
 504
 505 /* OpalMemoryErrorData->flags */
 506 #define OPAL_MEM_CORRECTED_ERROR        0x0001
 507 #define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
 508 #define OPAL_MEM_ACK_REQUIRED           0x8000
 509
 510 struct OpalMemoryErrorData {
 511         enum OpalMemErr_Version version:8;      /* 0x00 */
 512         enum OpalMemErrType     type:8;         /* 0x01 */
 513         __be16                  flags;          /* 0x02 */
 514         uint8_t                 reserved_1[4];  /* 0x04 */
 515
 516         union {
 517                 /* Memory Resilience corrected/uncorrected error info */
 518                 struct {
 519                         enum OpalMemErr_ResilErrType resil_err_type:8;
 520                         uint8_t         reserved_1[7];
 521                         __be64          physical_address_start;
 522                         __be64          physical_address_end;
 523                 } resilience;
 524                 /* Dynamic memory deallocation error info */
 525                 struct {
 526                         enum OpalMemErr_DynErrType dyn_err_type:8;
 527                         uint8_t         reserved_1[7];
 528                         __be64          physical_address_start;
 529                         __be64          physical_address_end;
 530                 } dyn_dealloc;
 531         } u;
 532 };
 533
 534 enum {
 535         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 536         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 537         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 538         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 539         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 540         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 541         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 542 };
 543
 544 struct OpalIoP7IOCErrorData {
 545         uint16_t type;
 546
 547         /* GEM */
 548         uint64_t gemXfir;
 549         uint64_t gemRfir;
 550         uint64_t gemRirqfir;
 551         uint64_t gemMask;
 552         uint64_t gemRwof;
 553
 554         /* LEM */
 555         uint64_t lemFir;
 556         uint64_t lemErrMask;
 557         uint64_t lemAction0;
 558         uint64_t lemAction1;
 559         uint64_t lemWof;
 560
 561         union {
 562                 struct OpalIoP7IOCRgcErrorData {
 563                         uint64_t rgcStatus;             /* 3E1C10 */
 564                         uint64_t rgcLdcp;               /* 3E1C18 */
 565                 }rgc;
 566                 struct OpalIoP7IOCBiErrorData {
 567                         uint64_t biLdcp0;               /* 3C0100, 3C0118 */
 568                         uint64_t biLdcp1;               /* 3C0108, 3C0120 */
 569                         uint64_t biLdcp2;               /* 3C0110, 3C0128 */
 570                         uint64_t biFenceStatus;         /* 3C0130, 3C0130 */
 571
 572                         uint8_t  biDownbound;           /* BI Downbound or Upbound */
 573                 }bi;
 574                 struct OpalIoP7IOCCiErrorData {
 575                         uint64_t ciPortStatus;          /* 3Dn008 */
 576                         uint64_t ciPortLdcp;            /* 3Dn010 */
 577
 578                         uint8_t  ciPort;                /* Index of CI port: 0/1 */
 579                 }ci;
 580         };
 581 };
 582
 583 /**
 584  * This structure defines the overlay which will be used to store PHB error
 585  * data upon request.
 586  */
 587 enum {
 588         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 589 };
 590
 591 enum {
 592         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 593         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 594 };
 595
 596 enum {
 597         OPAL_P7IOC_NUM_PEST_REGS = 128,
 598         OPAL_PHB3_NUM_PEST_REGS = 256
 599 };
 600
 601 struct OpalIoPhbErrorCommon {
 602         __be32 version;
 603         __be32 ioType;
 604         __be32 len;
 605 };
 606
 607 struct OpalIoP7IOCPhbErrorData {
 608         struct OpalIoPhbErrorCommon common;
 609
 610         uint32_t brdgCtl;
 611
 612         // P7IOC utl regs
 613         uint32_t portStatusReg;
 614         uint32_t rootCmplxStatus;
 615         uint32_t busAgentStatus;
 616
 617         // P7IOC cfg regs
 618         uint32_t deviceStatus;
 619         uint32_t slotStatus;
 620         uint32_t linkStatus;
 621         uint32_t devCmdStatus;
 622         uint32_t devSecStatus;
 623
 624         // cfg AER regs
 625         uint32_t rootErrorStatus;
 626         uint32_t uncorrErrorStatus;
 627         uint32_t corrErrorStatus;
 628         uint32_t tlpHdr1;
 629         uint32_t tlpHdr2;
 630         uint32_t tlpHdr3;
 631         uint32_t tlpHdr4;
 632         uint32_t sourceId;
 633
 634         uint32_t rsv3;
 635
 636         // Record data about the call to allocate a buffer.
 637         uint64_t errorClass;
 638         uint64_t correlator;
 639
 640         //P7IOC MMIO Error Regs
 641         uint64_t p7iocPlssr;                // n120
 642         uint64_t p7iocCsr;                  // n110
 643         uint64_t lemFir;                    // nC00
 644         uint64_t lemErrorMask;              // nC18
 645         uint64_t lemWOF;                    // nC40
 646         uint64_t phbErrorStatus;            // nC80
 647         uint64_t phbFirstErrorStatus;       // nC88
 648         uint64_t phbErrorLog0;              // nCC0
 649         uint64_t phbErrorLog1;              // nCC8
 650         uint64_t mmioErrorStatus;           // nD00
 651         uint64_t mmioFirstErrorStatus;      // nD08
 652         uint64_t mmioErrorLog0;             // nD40
 653         uint64_t mmioErrorLog1;             // nD48
 654         uint64_t dma0ErrorStatus;           // nD80
 655         uint64_t dma0FirstErrorStatus;      // nD88
 656         uint64_t dma0ErrorLog0;             // nDC0
 657         uint64_t dma0ErrorLog1;             // nDC8
 658         uint64_t dma1ErrorStatus;           // nE00
 659         uint64_t dma1FirstErrorStatus;      // nE08
 660         uint64_t dma1ErrorLog0;             // nE40
 661         uint64_t dma1ErrorLog1;             // nE48
 662         uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
 663         uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
 664 };
 665
 666 struct OpalIoPhb3ErrorData {
 667         struct OpalIoPhbErrorCommon common;
 668
 669         __be32 brdgCtl;
 670
 671         /* PHB3 UTL regs */
 672         __be32 portStatusReg;
 673         __be32 rootCmplxStatus;
 674         __be32 busAgentStatus;
 675
 676         /* PHB3 cfg regs */
 677         __be32 deviceStatus;
 678         __be32 slotStatus;
 679         __be32 linkStatus;
 680         __be32 devCmdStatus;
 681         __be32 devSecStatus;
 682
 683         /* cfg AER regs */
 684         __be32 rootErrorStatus;
 685         __be32 uncorrErrorStatus;
 686         __be32 corrErrorStatus;
 687         __be32 tlpHdr1;
 688         __be32 tlpHdr2;
 689         __be32 tlpHdr3;
 690         __be32 tlpHdr4;
 691         __be32 sourceId;
 692
 693         __be32 rsv3;
 694
 695         /* Record data about the call to allocate a buffer */
 696         __be64 errorClass;
 697         __be64 correlator;
 698
 699         __be64 nFir;                    /* 000 */
 700         __be64 nFirMask;                /* 003 */
 701         __be64 nFirWOF;         /* 008 */
 702
 703         /* PHB3 MMIO Error Regs */
 704         __be64 phbPlssr;                /* 120 */
 705         __be64 phbCsr;          /* 110 */
 706         __be64 lemFir;          /* C00 */
 707         __be64 lemErrorMask;            /* C18 */
 708         __be64 lemWOF;          /* C40 */
 709         __be64 phbErrorStatus;  /* C80 */
 710         __be64 phbFirstErrorStatus;     /* C88 */
 711         __be64 phbErrorLog0;            /* CC0 */
 712         __be64 phbErrorLog1;            /* CC8 */
 713         __be64 mmioErrorStatus; /* D00 */
 714         __be64 mmioFirstErrorStatus;    /* D08 */
 715         __be64 mmioErrorLog0;           /* D40 */
 716         __be64 mmioErrorLog1;           /* D48 */
 717         __be64 dma0ErrorStatus; /* D80 */
 718         __be64 dma0FirstErrorStatus;    /* D88 */
 719         __be64 dma0ErrorLog0;           /* DC0 */
 720         __be64 dma0ErrorLog1;           /* DC8 */
 721         __be64 dma1ErrorStatus; /* E00 */
 722         __be64 dma1FirstErrorStatus;    /* E08 */
 723         __be64 dma1ErrorLog0;           /* E40 */
 724         __be64 dma1ErrorLog1;           /* E48 */
 725         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 726         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 727 };
 728
 729 enum {
 730         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 731         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 732 };
 733
 734 typedef struct oppanel_line {
 735         const char *    line;
 736         uint64_t        line_len;
 737 } oppanel_line_t;
 738
 739 /* /sys/firmware/opal */
 740 extern struct kobject *opal_kobj;
 741
 742 /* /ibm,opal */
 743 extern struct device_node *opal_node;
 744
 745 /* API functions */
 746 int64_t opal_invalid_call(void);
 747 int64_t opal_console_write(int64_t term_number, __be64 *length,
 748                            const uint8_t *buffer);
 749 int64_t opal_console_read(int64_t term_number, __be64 *length,
 750                           uint8_t *buffer);
 751 int64_t opal_console_write_buffer_space(int64_t term_number,
 752                                         __be64 *length);
 753 int64_t opal_rtc_read(__be32 *year_month_day,
 754                       __be64 *hour_minute_second_millisecond);
 755 int64_t opal_rtc_write(uint32_t year_month_day,
 756                        uint64_t hour_minute_second_millisecond);
 757 int64_t opal_cec_power_down(uint64_t request);
 758 int64_t opal_cec_reboot(void);
 759 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 760 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 761 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
 762 int64_t opal_poll_events(__be64 *outstanding_event_mask);
 763 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 764                                     uint64_t tce_mem_size);
 765 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 766                                     uint64_t tce_mem_size);
 767 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 768                                   uint64_t offset, uint8_t *data);
 769 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 770                                        uint64_t offset, __be16 *data);
 771 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 772                                   uint64_t offset, __be32 *data);
 773 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 774                                    uint64_t offset, uint8_t data);
 775 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 776                                         uint64_t offset, uint16_t data);
 777 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 778                                    uint64_t offset, uint32_t data);
 779 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 780 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
 781 int64_t opal_register_exception_handler(uint64_t opal_exception,
 782                                         uint64_t handler_address,
 783                                         uint64_t glue_cache_line);
 784 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 785                                    uint8_t *freeze_state,
 786                                    __be16 *pci_error_type,
 787                                    __be64 *phb_status);
 788 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 789                                   uint64_t eeh_action_token);
 790 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 791
 792
 793
 794 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 795                                  uint16_t window_num, uint16_t enable);
 796 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 797                                     uint16_t window_num,
 798                                     uint64_t starting_real_address,
 799                                     uint64_t starting_pci_address,
 800                                     uint16_t segment_size);
 801 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 802                                     uint16_t window_type, uint16_t window_num,
 803                                     uint16_t segment_num);
 804 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 805                                       uint64_t ivt_addr, uint64_t ivt_len,
 806                                       uint64_t reject_array_addr,
 807                                       uint64_t peltv_addr);
 808 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 809                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 810                         uint8_t pe_action);
 811 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 812                            uint8_t state);
 813 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 814 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 815                                 uint32_t state);
 816 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 817                                   uint8_t *p_bit, uint8_t *q_bit);
 818 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 819                                   uint8_t p_bit, uint8_t q_bit);
 820 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 821 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 822                              uint32_t xive_num);
 823 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 824                              __be32 *interrupt_source_number);
 825 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 826                         uint8_t msi_range, __be32 *msi_address,
 827                         __be32 *message_data);
 828 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 829                         uint32_t xive_num, uint8_t msi_range,
 830                         __be64 *msi_address, __be32 *message_data);
 831 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 832 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 833 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 834 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 835                                    uint16_t tce_levels, uint64_t tce_table_addr,
 836                                    uint64_t tce_table_size, uint64_t tce_page_size);
 837 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 838                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 839                                         uint64_t pci_mem_size);
 840 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 841
 842 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
 843                                    uint64_t diag_buffer_len);
 844 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
 845                                    uint64_t diag_buffer_len);
 846 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
 847                                     uint64_t diag_buffer_len);
 848 int64_t opal_pci_fence_phb(uint64_t phb_id);
 849 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
 850 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 851 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 852 int64_t opal_get_epow_status(__be64 *status);
 853 int64_t opal_set_system_attention_led(uint8_t led_action);
 854 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
 855                             __be16 *pci_error_type, __be16 *severity);
 856 int64_t opal_pci_poll(uint64_t phb_id);
 857 int64_t opal_return_cpu(void);
 858 int64_t opal_reinit_cpus(uint64_t flags);
 859
 860 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
 861 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
 862
 863 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 864                        uint32_t addr, uint32_t data, uint32_t sz);
 865 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
 866                       uint32_t addr, __be32 *data, uint32_t sz);
 867
 868 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
 869 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
 870 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
 871 int64_t opal_send_ack_elog(uint64_t log_id);
 872 void opal_resend_pending_logs(void);
 873
 874 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
 875 int64_t opal_manage_flash(uint8_t op);
 876 int64_t opal_update_flash(uint64_t blk_list);
 877 int64_t opal_dump_init(uint8_t dump_type);
 878 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
 879 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
 880 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
 881 int64_t opal_dump_ack(uint32_t dump_id);
 882 int64_t opal_dump_resend_notification(void);
 883
 884 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
 885 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
 886 int64_t opal_sync_host_reboot(void);
 887 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 888                 uint64_t length);
 889 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 890                 uint64_t length);
 891 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 892
 893 /* Internal functions */
 894 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 895                                    int depth, void *data);
 896 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
 897                                  const char *uname, int depth, void *data);
 898
 899 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 900 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 901
 902 extern void hvc_opal_init_early(void);
 903
 904 extern int opal_notifier_register(struct notifier_block *nb);
 905 extern int opal_notifier_unregister(struct notifier_block *nb);
 906
 907 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
 908                                                 struct notifier_block *nb);
 909 extern void opal_notifier_enable(void);
 910 extern void opal_notifier_disable(void);
 911 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
 912
 913 extern int __opal_async_get_token(void);
 914 extern int opal_async_get_token_interruptible(void);
 915 extern int __opal_async_release_token(int token);
 916 extern int opal_async_release_token(int token);
 917 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
 918 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
 919
 920 struct rtc_time;
 921 extern int opal_set_rtc_time(struct rtc_time *tm);
 922 extern void opal_get_rtc_time(struct rtc_time *tm);
 923 extern unsigned long opal_get_boot_time(void);
 924 extern void opal_nvram_init(void);
 925 extern void opal_flash_init(void);
 926 extern void opal_flash_term_callback(void);
 927 extern int opal_elog_init(void);
 928 extern void opal_platform_dump_init(void);
 929 extern void opal_sys_param_init(void);
 930 extern void opal_msglog_init(void);
 931
 932 extern int opal_machine_check(struct pt_regs *regs);
 933 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
 934
 935 extern void opal_shutdown(void);
 936 extern int opal_resync_timebase(void);
 937
 938 extern void opal_lpc_init(void);
 939
 940 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
 941                                              unsigned long vmalloc_size);
 942 void opal_free_sg_list(struct opal_sg_list *sg);
 943
 944 #endif /* __ASSEMBLY__ */
 945
 946 #endif /* __OPAL_H */