2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #include <linux/config.h>
27 #include <linux/threads.h>
31 #include <asm/systemcfg.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
35 #include <asm/cputable.h>
36 #include <asm/setup.h>
37 #include <asm/hvcall.h>
38 #include <asm/iSeries/LparMap.h>
40 #ifdef CONFIG_PPC_ISERIES
41 #define DO_SOFT_DISABLE
45 * We layout physical memory as follows:
46 * 0x0000 - 0x00ff : Secondary processor spin code
47 * 0x0100 - 0x2fff : pSeries Interrupt prologs
48 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
49 * 0x6000 - 0x6fff : Initial (CPU0) segment table
50 * 0x7000 - 0x7fff : FWNMI data area
51 * 0x8000 - : Early init and support code
59 * SPRG0 reserved for hypervisor
60 * SPRG1 temp - used to save gpr
61 * SPRG2 temp - used to save gpr
62 * SPRG3 virt addr of paca
66 * Entering into this code we make the following assumptions:
68 * 1. The MMU is off & open firmware is running in real mode.
69 * 2. The kernel is entered at __start
72 * 1. The MMU is on (as it always is for iSeries)
73 * 2. The kernel is entered at system_reset_iSeries
79 #ifdef CONFIG_PPC_MULTIPLATFORM
81 /* NOP this out unconditionally */
83 b .__start_initialization_multiplatform
85 #endif /* CONFIG_PPC_MULTIPLATFORM */
87 /* Catch branch to 0 in real mode */
90 #ifdef CONFIG_PPC_ISERIES
92 * At offset 0x20, there is a pointer to iSeries LPAR data.
93 * This is required by the hypervisor
96 .llong hvReleaseData-KERNELBASE
99 * At offset 0x28 and 0x30 are offsets to the mschunks_map
100 * array (used by the iSeries LPAR debugger to do translation
101 * between physical addresses and absolute addresses) and
102 * to the pidhash table (also used by the debugger)
104 .llong mschunks_map-KERNELBASE
105 .llong 0 /* pidhash-KERNELBASE SFRXXX */
107 /* Offset 0x38 - Pointer to start of embedded System.map */
108 .globl embedded_sysmap_start
109 embedded_sysmap_start:
111 /* Offset 0x40 - Pointer to end of embedded System.map */
112 .globl embedded_sysmap_end
116 #endif /* CONFIG_PPC_ISERIES */
118 /* Secondary processors spin on this value until it goes to 1. */
119 .globl __secondary_hold_spinloop
120 __secondary_hold_spinloop:
123 /* Secondary processors write this value with their cpu # */
124 /* after they enter the spin loop immediately below. */
125 .globl __secondary_hold_acknowledge
126 __secondary_hold_acknowledge:
131 * The following code is used on pSeries to hold secondary processors
132 * in a spin loop after they have been freed from OpenFirmware, but
133 * before the bulk of the kernel has been relocated. This code
134 * is relocated to physical address 0x60 before prom_init is run.
135 * All of it must fit below the first exception vector at 0x100.
137 _GLOBAL(__secondary_hold)
140 mtmsrd r24 /* RI on */
142 /* Grab our linux cpu number */
145 /* Tell the master cpu we're here */
146 /* Relocation is off & we are located at an address less */
147 /* than 0x100, so only need to grab low order offset. */
148 std r24,__secondary_hold_acknowledge@l(0)
151 /* All secondary cpus wait here until told to start. */
152 100: ld r4,__secondary_hold_spinloop@l(0)
161 b .pSeries_secondary_smp_init
167 /* This value is used to mark exception frames on the stack. */
170 .tc ID_72656773_68657265[TC],0x7265677368657265
174 * The following macros define the code that appears as
175 * the prologue to each of the exception handlers. They
176 * are split into two parts to allow a single kernel binary
177 * to be used for pSeries and iSeries.
178 * LOL. One day... - paulus
182 * We make as much of the exception code common between native
183 * exception handlers (including pSeries LPAR) and iSeries LPAR
184 * implementations as possible.
188 * This is the start of the interrupt handlers for pSeries
189 * This code runs with relocation off.
197 #define EX_R3 40 /* SLB miss saves R3, but not SRR0 */
199 #define EX_LR 48 /* SLB miss saves LR, but not DAR */
203 #define EXCEPTION_PROLOG_PSERIES(area, label) \
204 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
205 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
206 std r10,area+EX_R10(r13); \
207 std r11,area+EX_R11(r13); \
208 std r12,area+EX_R12(r13); \
209 mfspr r9,SPRN_SPRG1; \
210 std r9,area+EX_R13(r13); \
212 clrrdi r12,r13,32; /* get high part of &label */ \
214 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
215 ori r12,r12,(label)@l; /* virt addr of handler */ \
216 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
217 mtspr SPRN_SRR0,r12; \
218 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
219 mtspr SPRN_SRR1,r10; \
221 b . /* prevent speculative execution */
224 * This is the start of the interrupt handlers for iSeries
225 * This code runs with relocation on.
227 #define EXCEPTION_PROLOG_ISERIES_1(area) \
228 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
229 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
230 std r10,area+EX_R10(r13); \
231 std r11,area+EX_R11(r13); \
232 std r12,area+EX_R12(r13); \
233 mfspr r9,SPRN_SPRG1; \
234 std r9,area+EX_R13(r13); \
237 #define EXCEPTION_PROLOG_ISERIES_2 \
239 ld r11,PACALPPACA+LPPACASRR0(r13); \
240 ld r12,PACALPPACA+LPPACASRR1(r13); \
241 ori r10,r10,MSR_RI; \
245 * The common exception prolog is used for all except a few exceptions
246 * such as a segment miss on a kernel address. We have to be prepared
247 * to take another exception from the point where we first touch the
248 * kernel stack onwards.
250 * On entry r13 points to the paca, r9-r13 are saved in the paca,
251 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
252 * SRR1, and relocation is on.
254 #define EXCEPTION_PROLOG_COMMON(n, area) \
255 andi. r10,r12,MSR_PR; /* See if coming from user */ \
256 mr r10,r1; /* Save r1 */ \
257 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
259 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
260 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
261 bge- cr1,bad_stack; /* abort if it is */ \
262 std r9,_CCR(r1); /* save CR in stackframe */ \
263 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
264 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
265 std r10,0(r1); /* make stack chain pointer */ \
266 std r0,GPR0(r1); /* save r0 in stackframe */ \
267 std r10,GPR1(r1); /* save r1 in stackframe */ \
268 std r2,GPR2(r1); /* save r2 in stackframe */ \
269 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
270 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
271 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
272 ld r10,area+EX_R10(r13); \
275 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
276 ld r10,area+EX_R12(r13); \
277 ld r11,area+EX_R13(r13); \
281 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
282 mflr r9; /* save LR in stackframe */ \
284 mfctr r10; /* save CTR in stackframe */ \
286 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
289 std r9,_TRAP(r1); /* set trap number */ \
291 ld r11,exception_marker@toc(r2); \
292 std r10,RESULT(r1); /* clear regs->result */ \
293 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
298 #define STD_EXCEPTION_PSERIES(n, label) \
300 .globl label##_pSeries; \
303 mtspr SPRN_SPRG1,r13; /* save r13 */ \
305 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
307 #define STD_EXCEPTION_ISERIES(n, label, area) \
308 .globl label##_iSeries; \
311 mtspr SPRN_SPRG1,r13; /* save r13 */ \
313 EXCEPTION_PROLOG_ISERIES_1(area); \
314 EXCEPTION_PROLOG_ISERIES_2; \
317 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
318 .globl label##_iSeries; \
321 mtspr SPRN_SPRG1,r13; /* save r13 */ \
323 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
324 lbz r10,PACAPROCENABLED(r13); \
326 beq- label##_iSeries_masked; \
327 EXCEPTION_PROLOG_ISERIES_2; \
330 #ifdef DO_SOFT_DISABLE
331 #define DISABLE_INTS \
332 lbz r10,PACAPROCENABLED(r13); \
336 stb r11,PACAPROCENABLED(r13); \
337 ori r10,r10,MSR_EE; \
340 #define ENABLE_INTS \
341 lbz r10,PACAPROCENABLED(r13); \
344 ori r11,r11,MSR_EE; \
347 #else /* hard enable/disable interrupts */
350 #define ENABLE_INTS \
353 rlwimi r11,r12,0,MSR_EE; \
358 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
360 .globl label##_common; \
362 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
365 addi r3,r1,STACK_FRAME_OVERHEAD; \
369 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
371 .globl label##_common; \
373 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
375 addi r3,r1,STACK_FRAME_OVERHEAD; \
377 b .ret_from_except_lite
380 * Start of pSeries system interrupt routines
383 .globl __start_interrupts
386 STD_EXCEPTION_PSERIES(0x100, system_reset)
389 _machine_check_pSeries:
391 mtspr SPRN_SPRG1,r13 /* save r13 */
393 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
396 .globl data_access_pSeries
405 rlwimi r13,r12,16,0x20
408 beq .do_stab_bolted_pSeries
411 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
412 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
415 .globl data_access_slb_pSeries
416 data_access_slb_pSeries:
420 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
421 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
422 std r10,PACA_EXSLB+EX_R10(r13)
423 std r11,PACA_EXSLB+EX_R11(r13)
424 std r12,PACA_EXSLB+EX_R12(r13)
425 std r3,PACA_EXSLB+EX_R3(r13)
427 std r9,PACA_EXSLB+EX_R13(r13)
429 mfspr r12,SPRN_SRR1 /* and SRR1 */
431 b .do_slb_miss /* Rel. branch works in real mode */
433 STD_EXCEPTION_PSERIES(0x400, instruction_access)
436 .globl instruction_access_slb_pSeries
437 instruction_access_slb_pSeries:
441 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
442 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
443 std r10,PACA_EXSLB+EX_R10(r13)
444 std r11,PACA_EXSLB+EX_R11(r13)
445 std r12,PACA_EXSLB+EX_R12(r13)
446 std r3,PACA_EXSLB+EX_R3(r13)
448 std r9,PACA_EXSLB+EX_R13(r13)
450 mfspr r12,SPRN_SRR1 /* and SRR1 */
451 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
452 b .do_slb_miss /* Rel. branch works in real mode */
454 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
455 STD_EXCEPTION_PSERIES(0x600, alignment)
456 STD_EXCEPTION_PSERIES(0x700, program_check)
457 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
458 STD_EXCEPTION_PSERIES(0x900, decrementer)
459 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
460 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
463 .globl system_call_pSeries
472 oris r12,r12,system_call_common@h
473 ori r12,r12,system_call_common@l
475 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
479 b . /* prevent speculative execution */
481 STD_EXCEPTION_PSERIES(0xd00, single_step)
482 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
484 /* We need to deal with the Altivec unavailable exception
485 * here which is at 0xf20, thus in the middle of the
486 * prolog code of the PerformanceMonitor one. A little
487 * trickery is thus necessary
490 b performance_monitor_pSeries
492 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
494 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
495 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
499 /*** pSeries interrupt support ***/
501 /* moved from 0xf00 */
502 STD_EXCEPTION_PSERIES(., performance_monitor)
505 _GLOBAL(do_stab_bolted_pSeries)
508 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
511 * Vectors for the FWNMI option. Share common code.
513 .globl system_reset_fwnmi
516 mtspr SPRN_SPRG1,r13 /* save r13 */
518 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
520 .globl machine_check_fwnmi
523 mtspr SPRN_SPRG1,r13 /* save r13 */
525 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
527 #ifdef CONFIG_PPC_ISERIES
528 /*** ISeries-LPAR interrupt handlers ***/
530 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
532 .globl data_access_iSeries
540 rlwimi r13,r12,16,0x20
543 beq .do_stab_bolted_iSeries
546 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
547 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
548 EXCEPTION_PROLOG_ISERIES_2
551 .do_stab_bolted_iSeries:
554 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
555 EXCEPTION_PROLOG_ISERIES_2
558 .globl data_access_slb_iSeries
559 data_access_slb_iSeries:
560 mtspr SPRN_SPRG1,r13 /* save r13 */
561 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
562 std r3,PACA_EXSLB+EX_R3(r13)
563 ld r12,PACALPPACA+LPPACASRR1(r13)
567 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
569 .globl instruction_access_slb_iSeries
570 instruction_access_slb_iSeries:
571 mtspr SPRN_SPRG1,r13 /* save r13 */
572 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
573 std r3,PACA_EXSLB+EX_R3(r13)
574 ld r12,PACALPPACA+LPPACASRR1(r13)
575 ld r3,PACALPPACA+LPPACASRR0(r13)
578 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
579 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
580 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
581 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
582 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
583 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
584 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
586 .globl system_call_iSeries
590 EXCEPTION_PROLOG_ISERIES_2
593 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
594 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
595 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
597 .globl system_reset_iSeries
598 system_reset_iSeries:
599 mfspr r13,SPRN_SPRG3 /* Get paca address */
602 mtmsrd r24 /* RI on */
603 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
604 cmpwi 0,r24,0 /* Are we processor 0? */
605 beq .__start_initialization_iSeries /* Start up the first processor */
607 li r5,CTRL_RUNLATCH /* Turn off the run light */
614 lbz r23,PACAPROCSTART(r13) /* Test if this processor
617 LOADADDR(r3,current_set)
618 sldi r28,r24,3 /* get current_set[cpu#] */
620 addi r1,r3,THREAD_SIZE
621 subi r1,r1,STACK_FRAME_OVERHEAD
624 beq iSeries_secondary_smp_loop /* Loop until told to go */
625 bne .__secondary_start /* Loop until told to go */
626 iSeries_secondary_smp_loop:
627 /* Let the Hypervisor know we are alive */
628 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
630 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
631 #else /* CONFIG_SMP */
632 /* Yield the processor. This is required for non-SMP kernels
633 which are running on multi-threaded machines. */
635 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
636 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
637 li r4,0 /* "yield timed" */
638 li r5,-1 /* "yield forever" */
639 #endif /* CONFIG_SMP */
640 li r0,-1 /* r0=-1 indicates a Hypervisor call */
641 sc /* Invoke the hypervisor via a system call */
642 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
643 b 1b /* If SMP not configured, secondaries
646 .globl decrementer_iSeries_masked
647 decrementer_iSeries_masked:
649 stb r11,PACALPPACA+LPPACADECRINT(r13)
650 lwz r12,PACADEFAULTDECR(r13)
654 .globl hardware_interrupt_iSeries_masked
655 hardware_interrupt_iSeries_masked:
656 mtcrf 0x80,r9 /* Restore regs */
657 ld r11,PACALPPACA+LPPACASRR0(r13)
658 ld r12,PACALPPACA+LPPACASRR1(r13)
661 ld r9,PACA_EXGEN+EX_R9(r13)
662 ld r10,PACA_EXGEN+EX_R10(r13)
663 ld r11,PACA_EXGEN+EX_R11(r13)
664 ld r12,PACA_EXGEN+EX_R12(r13)
665 ld r13,PACA_EXGEN+EX_R13(r13)
667 b . /* prevent speculative execution */
668 #endif /* CONFIG_PPC_ISERIES */
670 /*** Common interrupt handlers ***/
672 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
675 * Machine check is different because we use a different
676 * save area: PACA_EXMC instead of PACA_EXGEN.
679 .globl machine_check_common
680 machine_check_common:
681 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
684 addi r3,r1,STACK_FRAME_OVERHEAD
685 bl .machine_check_exception
688 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
689 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
690 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
691 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
692 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
693 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
694 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
695 #ifdef CONFIG_ALTIVEC
696 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
698 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
702 * Here we have detected that the kernel stack pointer is bad.
703 * R9 contains the saved CR, r13 points to the paca,
704 * r10 contains the (bad) kernel stack pointer,
705 * r11 and r12 contain the saved SRR0 and SRR1.
706 * We switch to using an emergency stack, save the registers there,
707 * and call kernel_bad_stack(), which panics.
710 ld r1,PACAEMERGSP(r13)
711 subi r1,r1,64+INT_FRAME_SIZE
732 addi r11,r1,INT_FRAME_SIZE
737 1: addi r3,r1,STACK_FRAME_OVERHEAD
742 * Return from an exception with minimal checks.
743 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
744 * If interrupts have been enabled, or anything has been
745 * done that might have changed the scheduling status of
746 * any task or sent any task a signal, you should use
747 * ret_from_except or ret_from_except_lite instead of this.
749 fast_exception_return:
752 andi. r3,r12,MSR_RI /* check if RI is set */
766 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
774 b . /* prevent speculative execution */
778 1: addi r3,r1,STACK_FRAME_OVERHEAD
779 bl .unrecoverable_exception
783 * Here r13 points to the paca, r9 contains the saved CR,
784 * SRR0 and SRR1 are saved in r11 and r12,
785 * r9 - r13 are saved in paca->exgen.
788 .globl data_access_common
790 RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */
792 std r10,PACA_EXGEN+EX_DAR(r13)
794 stw r10,PACA_EXGEN+EX_DSISR(r13)
795 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
796 ld r3,PACA_EXGEN+EX_DAR(r13)
797 lwz r4,PACA_EXGEN+EX_DSISR(r13)
799 b .do_hash_page /* Try to handle as hpte fault */
802 .globl instruction_access_common
803 instruction_access_common:
804 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
808 b .do_hash_page /* Try to handle as hpte fault */
811 .globl hardware_interrupt_common
812 .globl hardware_interrupt_entry
813 hardware_interrupt_common:
814 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
815 hardware_interrupt_entry:
817 addi r3,r1,STACK_FRAME_OVERHEAD
819 b .ret_from_except_lite
822 .globl alignment_common
825 std r10,PACA_EXGEN+EX_DAR(r13)
827 stw r10,PACA_EXGEN+EX_DSISR(r13)
828 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
829 ld r3,PACA_EXGEN+EX_DAR(r13)
830 lwz r4,PACA_EXGEN+EX_DSISR(r13)
834 addi r3,r1,STACK_FRAME_OVERHEAD
836 bl .alignment_exception
840 .globl program_check_common
841 program_check_common:
842 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
844 addi r3,r1,STACK_FRAME_OVERHEAD
846 bl .program_check_exception
850 .globl fp_unavailable_common
851 fp_unavailable_common:
852 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
853 bne .load_up_fpu /* if from user, just load it up */
855 addi r3,r1,STACK_FRAME_OVERHEAD
857 bl .kernel_fp_unavailable_exception
861 .globl altivec_unavailable_common
862 altivec_unavailable_common:
863 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
864 #ifdef CONFIG_ALTIVEC
866 bne .load_up_altivec /* if from user, just load it up */
867 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
870 addi r3,r1,STACK_FRAME_OVERHEAD
872 bl .altivec_unavailable_exception
875 #ifdef CONFIG_ALTIVEC
877 * load_up_altivec(unused, unused, tsk)
878 * Disable VMX for the task which had it previously,
879 * and save its vector registers in its thread_struct.
880 * Enables the VMX for use in the kernel on return.
881 * On SMP we know the VMX is free, since we give it up every
882 * switch (ie, no lazy save of the vector registers).
883 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
885 _STATIC(load_up_altivec)
886 mfmsr r5 /* grab the current MSR */
888 mtmsrd r5 /* enable use of VMX now */
892 * For SMP, we don't do lazy VMX switching because it just gets too
893 * horrendously complex, especially when a task switches from one CPU
894 * to another. Instead we call giveup_altvec in switch_to.
895 * VRSAVE isn't dealt with here, that is done in the normal context
896 * switch code. Note that we could rely on vrsave value to eventually
897 * avoid saving all of the VREGs here...
900 ld r3,last_task_used_altivec@got(r2)
904 /* Save VMX state to last_task_used_altivec's THREAD struct */
910 /* Disable VMX for last_task_used_altivec */
912 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
915 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
917 #endif /* CONFIG_SMP */
918 /* Hack: if we get an altivec unavailable trap with VRSAVE
919 * set to all zeros, we assume this is a broken application
920 * that fails to set it properly, and thus we switch it to
929 /* enable use of VMX after return */
930 ld r4,PACACURRENT(r13)
931 addi r5,r4,THREAD /* Get THREAD */
932 oris r12,r12,MSR_VEC@h
936 stw r4,THREAD_USED_VR(r5)
941 /* Update last_task_used_math to 'current' */
942 subi r4,r5,THREAD /* Back to 'current' */
944 #endif /* CONFIG_SMP */
945 /* restore registers and return */
946 b fast_exception_return
947 #endif /* CONFIG_ALTIVEC */
953 _GLOBAL(do_hash_page)
957 andis. r0,r4,0xa450 /* weird error? */
958 bne- .handle_page_fault /* if not, try to insert a HPTE */
960 andis. r0,r4,0x0020 /* Is it a segment table fault? */
961 bne- .do_ste_alloc /* If so handle it */
962 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
965 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
966 * accessing a userspace segment (even from the kernel). We assume
967 * kernel addresses always have the high bit set.
969 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
970 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
971 orc r0,r12,r0 /* MSR_PR | ~high_bit */
972 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
973 ori r4,r4,1 /* add _PAGE_PRESENT */
974 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
977 * On iSeries, we soft-disable interrupts here, then
978 * hard-enable interrupts so that the hash_page code can spin on
979 * the hash_table_lock without problems on a shared processor.
984 * r3 contains the faulting address
985 * r4 contains the required access permissions
986 * r5 contains the trap number
988 * at return r3 = 0 for success
990 bl .hash_page /* build HPTE if possible */
991 cmpdi r3,0 /* see if hash_page succeeded */
993 #ifdef DO_SOFT_DISABLE
995 * If we had interrupts soft-enabled at the point where the
996 * DSI/ISI occurred, and an interrupt came in during hash_page,
998 * We jump to ret_from_except_lite rather than fast_exception_return
999 * because ret_from_except_lite will check for and handle pending
1000 * interrupts if necessary.
1002 beq .ret_from_except_lite
1003 /* For a hash failure, we don't bother re-enabling interrupts */
1007 * hash_page couldn't handle it, set soft interrupt enable back
1008 * to what it was before the trap. Note that .local_irq_restore
1009 * handles any interrupts pending at this point.
1012 bl .local_irq_restore
1015 beq fast_exception_return /* Return from exception on success */
1016 ble- 12f /* Failure return from hash_page */
1021 /* Here we have a page fault that hash_page can't handle. */
1022 _GLOBAL(handle_page_fault)
1026 addi r3,r1,STACK_FRAME_OVERHEAD
1029 beq+ .ret_from_except_lite
1032 addi r3,r1,STACK_FRAME_OVERHEAD
1037 /* We have a page fault that hash_page could handle but HV refused
1041 addi r3,r1,STACK_FRAME_OVERHEAD
1046 /* here we have a segment miss */
1047 _GLOBAL(do_ste_alloc)
1048 bl .ste_allocate /* try to insert stab entry */
1050 beq+ fast_exception_return
1051 b .handle_page_fault
1054 * r13 points to the PACA, r9 contains the saved CR,
1055 * r11 and r12 contain the saved SRR0 and SRR1.
1056 * r9 - r13 are saved in paca->exslb.
1057 * We assume we aren't going to take any exceptions during this procedure.
1058 * We assume (DAR >> 60) == 0xc.
1061 _GLOBAL(do_stab_bolted)
1062 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1063 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1065 /* Hash to the primary group */
1066 ld r10,PACASTABVIRT(r13)
1069 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1071 /* Calculate VSID */
1072 /* This is a kernel address, so protovsid = ESID */
1073 ASM_VSID_SCRAMBLE(r11, r9)
1074 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1076 /* Search the primary group for a free entry */
1077 1: ld r11,0(r10) /* Test valid bit of the current ste */
1084 /* Stick for only searching the primary group for now. */
1085 /* At least for now, we use a very simple random castout scheme */
1086 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1088 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1091 /* r10 currently points to an ste one past the group of interest */
1092 /* make it point to the randomly selected entry */
1094 or r10,r10,r11 /* r10 is the entry to invalidate */
1096 isync /* mark the entry invalid */
1098 rldicl r11,r11,56,1 /* clear the valid bit */
1103 clrrdi r11,r11,28 /* Get the esid part of the ste */
1106 2: std r9,8(r10) /* Store the vsid part of the ste */
1109 mfspr r11,SPRN_DAR /* Get the new esid */
1110 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1111 ori r11,r11,0x90 /* Turn on valid and kp */
1112 std r11,0(r10) /* Put new entry back into the stab */
1116 /* All done -- return from exception. */
1117 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1118 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1120 andi. r10,r12,MSR_RI
1123 mtcrf 0x80,r9 /* restore CR */
1131 ld r9,PACA_EXSLB+EX_R9(r13)
1132 ld r10,PACA_EXSLB+EX_R10(r13)
1133 ld r11,PACA_EXSLB+EX_R11(r13)
1134 ld r12,PACA_EXSLB+EX_R12(r13)
1135 ld r13,PACA_EXSLB+EX_R13(r13)
1137 b . /* prevent speculative execution */
1140 * r13 points to the PACA, r9 contains the saved CR,
1141 * r11 and r12 contain the saved SRR0 and SRR1.
1142 * r3 has the faulting address
1143 * r9 - r13 are saved in paca->exslb.
1144 * r3 is saved in paca->slb_r3
1145 * We assume we aren't going to take any exceptions during this procedure.
1147 _GLOBAL(do_slb_miss)
1150 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1151 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1153 bl .slb_allocate /* handle it */
1155 /* All done -- return from exception. */
1157 ld r10,PACA_EXSLB+EX_LR(r13)
1158 ld r3,PACA_EXSLB+EX_R3(r13)
1159 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1160 #ifdef CONFIG_PPC_ISERIES
1161 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
1162 #endif /* CONFIG_PPC_ISERIES */
1166 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1172 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1175 #ifdef CONFIG_PPC_ISERIES
1178 #endif /* CONFIG_PPC_ISERIES */
1179 ld r9,PACA_EXSLB+EX_R9(r13)
1180 ld r10,PACA_EXSLB+EX_R10(r13)
1181 ld r11,PACA_EXSLB+EX_R11(r13)
1182 ld r12,PACA_EXSLB+EX_R12(r13)
1183 ld r13,PACA_EXSLB+EX_R13(r13)
1185 b . /* prevent speculative execution */
1188 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1191 1: addi r3,r1,STACK_FRAME_OVERHEAD
1192 bl .unrecoverable_exception
1196 * Space for CPU0's segment table.
1198 * On iSeries, the hypervisor must fill in at least one entry before
1199 * we get control (with relocate on). The address is give to the hv
1200 * as a page number (see xLparMap in lpardata.c), so this must be at a
1201 * fixed address (the linker can't compute (u64)&initial_stab >>
1204 . = STAB0_PHYS_ADDR /* 0x6000 */
1210 * Data area reserved for FWNMI option.
1211 * This address (0x7000) is fixed by the RPA.
1214 .globl fwnmi_data_area
1217 /* iSeries does not use the FWNMI stuff, so it is safe to put
1218 * this here, even if we later allow kernels that will boot on
1219 * both pSeries and iSeries */
1220 #ifdef CONFIG_PPC_ISERIES
1222 #include "lparmap.s"
1224 * This ".text" is here for old compilers that generate a trailing
1225 * .note section when compiling .c files to .s
1228 #endif /* CONFIG_PPC_ISERIES */
1233 * On pSeries, secondary processors spin in the following code.
1234 * At entry, r3 = this processor's number (physical cpu id)
1236 _GLOBAL(pSeries_secondary_smp_init)
1239 /* turn on 64-bit mode */
1243 /* Copy some CPU settings from CPU 0 */
1244 bl .__restore_cpu_setup
1246 /* Set up a paca value for this processor. Since we have the
1247 * physical cpu id in r24, we need to search the pacas to find
1248 * which logical id maps to our physical one.
1250 LOADADDR(r13, paca) /* Get base vaddr of paca array */
1251 li r5,0 /* logical cpu id */
1252 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1253 cmpw r6,r24 /* Compare to our id */
1255 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1260 mr r3,r24 /* not found, copy phys to r3 */
1261 b .kexec_wait /* next kernel might do better */
1263 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1264 /* From now on, r24 is expected to be logical cpuid */
1267 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1271 /* Create a temp kernel stack for use before relocation is on. */
1272 ld r1,PACAEMERGSP(r13)
1273 subi r1,r1,STACK_FRAME_OVERHEAD
1277 bne .__secondary_start
1279 b 3b /* Loop until told to go */
1281 #ifdef CONFIG_PPC_ISERIES
1282 _STATIC(__start_initialization_iSeries)
1283 /* Clear out the BSS */
1284 LOADADDR(r11,__bss_stop)
1285 LOADADDR(r8,__bss_start)
1286 sub r11,r11,r8 /* bss size */
1287 addi r11,r11,7 /* round up to an even double word */
1288 rldicl. r11,r11,61,3 /* shift right by 3 */
1292 mtctr r11 /* zero this many doublewords */
1296 LOADADDR(r1,init_thread_union)
1297 addi r1,r1,THREAD_SIZE
1299 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1301 LOADADDR(r3,cpu_specs)
1302 LOADADDR(r4,cur_cpu_spec)
1306 LOADADDR(r2,__toc_start)
1310 bl .iSeries_early_setup
1313 /* relocation is on at this point */
1315 b .start_here_common
1316 #endif /* CONFIG_PPC_ISERIES */
1318 #ifdef CONFIG_PPC_MULTIPLATFORM
1322 andi. r0,r3,MSR_IR|MSR_DR
1329 b . /* prevent speculative execution */
1333 * Here is our main kernel entry point. We support currently 2 kind of entries
1334 * depending on the value of r5.
1336 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1339 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1340 * DT block, r4 is a physical pointer to the kernel itself
1343 _GLOBAL(__start_initialization_multiplatform)
1345 * Are we booted from a PROM Of-type client-interface ?
1348 bne .__boot_from_prom /* yes -> prom */
1350 /* Save parameters */
1354 /* Make sure we are running in 64 bits mode */
1357 /* Setup some critical 970 SPRs before switching MMU off */
1358 bl .__970_cpu_preinit
1363 /* Switch off MMU if not already */
1364 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1367 b .__after_prom_start
1369 _STATIC(__boot_from_prom)
1370 /* Save parameters */
1377 /* Make sure we are running in 64 bits mode */
1380 /* put a relocation offset into r3 */
1383 LOADADDR(r2,__toc_start)
1387 /* Relocate the TOC from a virt addr to a real addr */
1390 /* Restore parameters */
1397 /* Do all of the interaction with OF client interface */
1399 /* We never return */
1403 * At this point, r3 contains the physical address we are running at,
1404 * returned by prom_init()
1406 _STATIC(__after_prom_start)
1409 * We need to run with __start at physical address 0.
1410 * This will leave some code in the first 256B of
1411 * real memory, which are reserved for software use.
1412 * The remainder of the first page is loaded with the fixed
1413 * interrupt vectors. The next two pages are filled with
1414 * unknown exception placeholders.
1416 * Note: This process overwrites the OF exception vectors.
1417 * r26 == relocation offset
1422 SET_REG_TO_CONST(r27,KERNELBASE)
1424 li r3,0 /* target addr */
1426 // XXX FIXME: Use phys returned by OF (r30)
1427 sub r4,r27,r26 /* source addr */
1428 /* current address of _start */
1429 /* i.e. where we are running */
1430 /* the source addr */
1432 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1435 li r6,0x100 /* Start offset, the first 0x100 */
1436 /* bytes were copied earlier. */
1438 bl .copy_and_flush /* copy the first n bytes */
1439 /* this includes the code being */
1440 /* executed here. */
1442 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1443 mtctr r0 /* that we just made/relocated */
1446 4: LOADADDR(r5,klimit)
1448 ld r5,0(r5) /* get the value of klimit */
1450 bl .copy_and_flush /* copy the rest */
1451 b .start_here_multiplatform
1453 #endif /* CONFIG_PPC_MULTIPLATFORM */
1456 * Copy routine used to copy the kernel to start at physical address 0
1457 * and flush and invalidate the caches as needed.
1458 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1459 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1461 * Note: this routine *only* clobbers r0, r6 and lr
1463 _GLOBAL(copy_and_flush)
1466 4: li r0,16 /* Use the least common */
1467 /* denominator cache line */
1468 /* size. This results in */
1469 /* extra cache line flushes */
1470 /* but operation is correct. */
1471 /* Can't get cache line size */
1472 /* from NACA as it is being */
1475 mtctr r0 /* put # words/line in ctr */
1476 3: addi r6,r6,8 /* copy a cache line */
1480 dcbst r6,r3 /* write it to memory */
1482 icbi r6,r3 /* flush the icache line */
1494 #ifdef CONFIG_PPC_PMAC
1496 * On PowerMac, secondary processors starts from the reset vector, which
1497 * is temporarily turned into a call to one of the functions below.
1502 .globl pmac_secondary_start_1
1503 pmac_secondary_start_1:
1505 b .pmac_secondary_start
1507 .globl pmac_secondary_start_2
1508 pmac_secondary_start_2:
1510 b .pmac_secondary_start
1512 .globl pmac_secondary_start_3
1513 pmac_secondary_start_3:
1515 b .pmac_secondary_start
1517 _GLOBAL(pmac_secondary_start)
1518 /* turn on 64-bit mode */
1522 /* Copy some CPU settings from CPU 0 */
1523 bl .__restore_cpu_setup
1525 /* pSeries do that early though I don't think we really need it */
1528 mtmsrd r3 /* RI on */
1530 /* Set up a paca value for this processor. */
1531 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1532 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1533 add r13,r13,r4 /* for this processor. */
1534 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1536 /* Create a temp kernel stack for use before relocation is on. */
1537 ld r1,PACAEMERGSP(r13)
1538 subi r1,r1,STACK_FRAME_OVERHEAD
1540 b .__secondary_start
1542 #endif /* CONFIG_PPC_PMAC */
1545 * This function is called after the master CPU has released the
1546 * secondary processors. The execution environment is relocation off.
1547 * The paca for this processor has the following fields initialized at
1549 * 1. Processor number
1550 * 2. Segment table pointer (virtual address)
1551 * On entry the following are set:
1552 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1553 * r24 = cpu# (in Linux terms)
1554 * r13 = paca virtual address
1555 * SPRG3 = paca virtual address
1557 _GLOBAL(__secondary_start)
1559 HMT_MEDIUM /* Set thread priority to MEDIUM */
1563 stb r6,PACAPROCENABLED(r13)
1565 #ifndef CONFIG_PPC_ISERIES
1566 /* Initialize the page table pointer register. */
1568 ld r6,0(r6) /* get the value of _SDR1 */
1569 mtspr SPRN_SDR1,r6 /* set the htab location */
1571 /* Initialize the first segment table (or SLB) entry */
1572 ld r3,PACASTABVIRT(r13) /* get addr of segment table */
1575 /* Initialize the kernel stack. Just a repeat for iSeries. */
1576 LOADADDR(r3,current_set)
1577 sldi r28,r24,3 /* get current_set[cpu#] */
1579 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1580 std r1,PACAKSAVE(r13)
1582 ld r3,PACASTABREAL(r13) /* get raddr of segment table */
1583 ori r4,r3,1 /* turn on valid bit */
1585 #ifdef CONFIG_PPC_ISERIES
1586 li r0,-1 /* hypervisor call */
1588 sldi r3,r3,63 /* 0x8000000000000000 */
1589 ori r3,r3,4 /* 0x8000000000000004 */
1590 sc /* HvCall_setASR */
1593 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1595 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1596 andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
1597 beq 98f /* branch if result is 0 */
1600 cmpwi r3,0x37 /* SStar */
1602 cmpwi r3,0x36 /* IStar */
1604 cmpwi r3,0x34 /* Pulsar */
1606 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1607 HVSC /* Invoking hcall */
1609 98: /* !(rpa hypervisor) || !(star) */
1610 mtasr r4 /* set the stab location */
1616 /* enable MMU and jump to start_secondary */
1617 LOADADDR(r3,.start_secondary_prolog)
1618 SET_REG_TO_CONST(r4, MSR_KERNEL)
1619 #ifdef DO_SOFT_DISABLE
1625 b . /* prevent speculative execution */
1628 * Running with relocation on at this point. All we want to do is
1629 * zero the stack back-chain pointer before going into C code.
1631 _GLOBAL(start_secondary_prolog)
1633 std r3,0(r1) /* Zero the stack frame pointer */
1638 * This subroutine clobbers r11 and r12
1640 _GLOBAL(enable_64b_mode)
1641 mfmsr r11 /* grab the current MSR */
1643 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1646 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1652 #ifdef CONFIG_PPC_MULTIPLATFORM
1654 * This is where the main kernel code starts.
1656 _STATIC(start_here_multiplatform)
1657 /* get a new offset, now that the kernel has moved. */
1661 /* Clear out the BSS. It may have been done in prom_init,
1662 * already but that's irrelevant since prom_init will soon
1663 * be detached from the kernel completely. Besides, we need
1664 * to clear it now for kexec-style entry.
1666 LOADADDR(r11,__bss_stop)
1667 LOADADDR(r8,__bss_start)
1668 sub r11,r11,r8 /* bss size */
1669 addi r11,r11,7 /* round up to an even double word */
1670 rldicl. r11,r11,61,3 /* shift right by 3 */
1674 mtctr r11 /* zero this many doublewords */
1681 mtmsrd r6 /* RI on */
1684 /* Start up the second thread on cpu 0 */
1687 cmpwi r3,0x34 /* Pulsar */
1689 cmpwi r3,0x36 /* Icestar */
1691 cmpwi r3,0x37 /* SStar */
1693 b 91f /* HMT not supported */
1695 bl .hmt_start_secondary
1699 /* The following gets the stack and TOC set up with the regs */
1700 /* pointing to the real addr of the kernel stack. This is */
1701 /* all done to support the C function call below which sets */
1702 /* up the htab. This is done because we have relocated the */
1703 /* kernel but are still running in real mode. */
1705 LOADADDR(r3,init_thread_union)
1708 /* set up a stack pointer (physical address) */
1709 addi r1,r3,THREAD_SIZE
1711 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1713 /* set up the TOC (physical address) */
1714 LOADADDR(r2,__toc_start)
1719 LOADADDR(r3,cpu_specs)
1721 LOADADDR(r4,cur_cpu_spec)
1726 /* Save some low level config HIDs of CPU0 to be copied to
1727 * other CPUs later on, or used for suspend/resume
1729 bl .__save_cpu_setup
1732 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1733 * note that boot_cpuid can always be 0 nowadays since there is
1734 * nowhere it can be initialized differently before we reach this
1737 LOADADDR(r27, boot_cpuid)
1741 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1742 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1743 add r13,r13,r24 /* for this processor. */
1744 sub r13,r13,r26 /* convert to physical addr */
1745 mtspr SPRN_SPRG3,r13 /* PPPBBB: Temp... -Peter */
1747 /* Do very early kernel initializations, including initial hash table,
1748 * stab and slb setup before we turn on relocation. */
1750 /* Restore parameters passed from prom_init/kexec */
1755 ld r3,PACASTABREAL(r13)
1756 ori r4,r3,1 /* turn on valid bit */
1757 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1759 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1760 andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
1761 beq 98f /* branch if result is 0 */
1764 cmpwi r3,0x37 /* SStar */
1766 cmpwi r3,0x36 /* IStar */
1768 cmpwi r3,0x34 /* Pulsar */
1770 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1771 HVSC /* Invoking hcall */
1773 98: /* !(rpa hypervisor) || !(star) */
1774 mtasr r4 /* set the stab location */
1776 /* Set SDR1 (hash table pointer) */
1777 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1779 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1780 /* Test if bit 0 is set (LPAR bit) */
1781 andi. r3,r3,PLATFORM_LPAR
1782 bne 98f /* branch if result is !0 */
1783 LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
1785 ld r6,0(r6) /* get the value of _SDR1 */
1786 mtspr SPRN_SDR1,r6 /* set the htab location */
1788 LOADADDR(r3,.start_here_common)
1789 SET_REG_TO_CONST(r4, MSR_KERNEL)
1793 b . /* prevent speculative execution */
1794 #endif /* CONFIG_PPC_MULTIPLATFORM */
1796 /* This is where all platforms converge execution */
1797 _STATIC(start_here_common)
1798 /* relocation is on at this point */
1800 /* The following code sets up the SP and TOC now that we are */
1801 /* running with translation enabled. */
1803 LOADADDR(r3,init_thread_union)
1805 /* set up the stack */
1806 addi r1,r3,THREAD_SIZE
1808 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1810 /* Apply the CPUs-specific fixups (nop out sections not relevant
1814 bl .do_cpu_ftr_fixups
1816 LOADADDR(r26, boot_cpuid)
1819 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1820 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1821 add r13,r13,r24 /* for this processor. */
1822 mtspr SPRN_SPRG3,r13
1824 /* ptr to current */
1825 LOADADDR(r4,init_task)
1826 std r4,PACACURRENT(r13)
1830 std r1,PACAKSAVE(r13)
1834 /* Load up the kernel context */
1836 #ifdef DO_SOFT_DISABLE
1838 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1840 ori r5,r5,MSR_EE /* Hard Enabled */
1848 LOADADDR(r5, hmt_thread_data)
1851 cmpwi r7,0x34 /* Pulsar */
1853 cmpwi r7,0x36 /* Icestar */
1855 cmpwi r7,0x37 /* SStar */
1858 90: mfspr r6,SPRN_PIR
1861 91: mfspr r6,SPRN_PIR
1865 bl .hmt_start_secondary
1868 __hmt_secondary_hold:
1869 LOADADDR(r5, hmt_thread_data)
1879 93: andi. r6,r6,0x3f
1893 b .pSeries_secondary_smp_init
1896 _GLOBAL(hmt_start_secondary)
1897 LOADADDR(r4,__hmt_secondary_hold)
1899 mtspr SPRN_NIADORM, r4
1900 mfspr r4, SPRN_MSRDORM
1903 mtspr SPRN_MSRDORM, r4
1912 mfspr r4, SPRN_CTRLF
1914 mtspr SPRN_CTRLT, r4
1918 #if defined(CONFIG_KEXEC) || defined(CONFIG_SMP)
1919 _GLOBAL(smp_release_cpus)
1920 /* All secondary cpus are spinning on a common
1921 * spinloop, release them all now so they can start
1922 * to spin on their individual paca spinloops.
1923 * For non SMP kernels, the secondary cpus never
1924 * get out of the common spinloop.
1925 * XXX This does nothing useful on iSeries, secondaries are
1926 * already waiting on their paca.
1929 LOADADDR(r5,__secondary_hold_spinloop)
1933 #endif /* CONFIG_SMP */
1937 * We put a few things here that have to be page-aligned.
1938 * This stuff goes at the beginning of the bss, which is page-aligned.
1944 .globl empty_zero_page
1948 .globl swapper_pg_dir
1953 * This space gets a copy of optional info passed to us by the bootstrap
1954 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1958 .space COMMAND_LINE_SIZE