arch/powerpc/platforms/cell/interrupt.c

   1 /*
   2  * Cell Internal Interrupt Controller
   3  *
   4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *
   6  * Author: Arnd Bergmann <arndb@de.ibm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/config.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/module.h>
  27 #include <linux/percpu.h>
  28 #include <linux/types.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/prom.h>
  33 #include <asm/ptrace.h>
  34
  35 #include "interrupt.h"
  36 #include "cbe_regs.h"
  37
  38 struct iic {
  39         struct cbe_iic_thread_regs __iomem *regs;
  40         u8 target_id;
  41 };
  42
  43 static DEFINE_PER_CPU(struct iic, iic);
  44
  45 void iic_local_enable(void)
  46 {
  47         struct iic *iic = &__get_cpu_var(iic);
  48         u64 tmp;
  49
  50         /*
  51          * There seems to be a bug that is present in DD2.x CPUs
  52          * and still only partially fixed in DD3.1.
  53          * This bug causes a value written to the priority register
  54          * not to make it there, resulting in a system hang unless we
  55          * write it again.
  56          * Masking with 0xf0 is done because the Cell BE does not
  57          * implement the lower four bits of the interrupt priority,
  58          * they always read back as zeroes, although future CPUs
  59          * might implement different bits.
  60          */
  61         do {
  62                 out_be64(&iic->regs->prio, 0xff);
  63                 tmp = in_be64(&iic->regs->prio);
  64         } while ((tmp & 0xf0) != 0xf0);
  65 }
  66
  67 void iic_local_disable(void)
  68 {
  69         out_be64(&__get_cpu_var(iic).regs->prio, 0x0);
  70 }
  71
  72 static unsigned int iic_startup(unsigned int irq)
  73 {
  74         return 0;
  75 }
  76
  77 static void iic_enable(unsigned int irq)
  78 {
  79         iic_local_enable();
  80 }
  81
  82 static void iic_disable(unsigned int irq)
  83 {
  84 }
  85
  86 static void iic_end(unsigned int irq)
  87 {
  88         iic_local_enable();
  89 }
  90
  91 static struct hw_interrupt_type iic_pic = {
  92         .typename = " CELL-IIC ",
  93         .startup = iic_startup,
  94         .enable = iic_enable,
  95         .disable = iic_disable,
  96         .end = iic_end,
  97 };
  98
  99 static int iic_external_get_irq(struct cbe_iic_pending_bits pending)
 100 {
 101         int irq;
 102         unsigned char node, unit;
 103
 104         node = pending.source >> 4;
 105         unit = pending.source & 0xf;
 106         irq = -1;
 107
 108         /*
 109          * This mapping is specific to the Cell Broadband
 110          * Engine. We might need to get the numbers
 111          * from the device tree to support future CPUs.
 112          */
 113         switch (unit) {
 114         case 0x00:
 115         case 0x0b:
 116                 /*
 117                  * One of these units can be connected
 118                  * to an external interrupt controller.
 119                  */
 120                 if (pending.class != 2)
 121                         break;
 122                 irq = IIC_EXT_OFFSET
 123                         + spider_get_irq(node)
 124                         + node * IIC_NODE_STRIDE;
 125                 break;
 126         case 0x01 ... 0x04:
 127         case 0x07 ... 0x0a:
 128                 /*
 129                  * These units are connected to the SPEs
 130                  */
 131                 if (pending.class > 2)
 132                         break;
 133                 irq = IIC_SPE_OFFSET
 134                         + pending.class * IIC_CLASS_STRIDE
 135                         + node * IIC_NODE_STRIDE
 136                         + unit;
 137                 break;
 138         }
 139         if (irq == -1)
 140                 printk(KERN_WARNING "Unexpected interrupt class %02x, "
 141                         "source %02x, prio %02x, cpu %02x\n", pending.class,
 142                         pending.source, pending.prio, smp_processor_id());
 143         return irq;
 144 }
 145
 146 /* Get an IRQ number from the pending state register of the IIC */
 147 int iic_get_irq(struct pt_regs *regs)
 148 {
 149         struct iic *iic;
 150         int irq;
 151         struct cbe_iic_pending_bits pending;
 152
 153         iic = &__get_cpu_var(iic);
 154         *(unsigned long *) &pending =
 155                 in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
 156
 157         irq = -1;
 158         if (pending.flags & CBE_IIC_IRQ_VALID) {
 159                 if (pending.flags & CBE_IIC_IRQ_IPI) {
 160                         irq = IIC_IPI_OFFSET + (pending.prio >> 4);
 161 /*
 162                         if (irq > 0x80)
 163                                 printk(KERN_WARNING "Unexpected IPI prio %02x"
 164                                         "on CPU %02x\n", pending.prio,
 165                                                         smp_processor_id());
 166 */
 167                 } else {
 168                         irq = iic_external_get_irq(pending);
 169                 }
 170         }
 171         return irq;
 172 }
 173
 174 /* hardcoded part to be compatible with older firmware */
 175
 176 static int setup_iic_hardcoded(void)
 177 {
 178         struct device_node *np;
 179         int nodeid, cpu;
 180         unsigned long regs;
 181         struct iic *iic;
 182
 183         for_each_possible_cpu(cpu) {
 184                 iic = &per_cpu(iic, cpu);
 185                 nodeid = cpu/2;
 186
 187                 for (np = of_find_node_by_type(NULL, "cpu");
 188                      np;
 189                      np = of_find_node_by_type(np, "cpu")) {
 190                         if (nodeid == *(int *)get_property(np, "node-id", NULL))
 191                                 break;
 192                         }
 193
 194                 if (!np) {
 195                         printk(KERN_WARNING "IIC: CPU %d not found\n", cpu);
 196                         iic->regs = NULL;
 197                         iic->target_id = 0xff;
 198                         return -ENODEV;
 199                         }
 200
 201                 regs = *(long *)get_property(np, "iic", NULL);
 202
 203                 /* hack until we have decided on the devtree info */
 204                 regs += 0x400;
 205                 if (cpu & 1)
 206                         regs += 0x20;
 207
 208                 printk(KERN_INFO "IIC for CPU %d at %lx\n", cpu, regs);
 209                 iic->regs = ioremap(regs, sizeof(struct cbe_iic_thread_regs));
 210                 iic->target_id = (nodeid << 4) + ((cpu & 1) ? 0xf : 0xe);
 211         }
 212
 213         return 0;
 214 }
 215
 216 static int setup_iic(void)
 217 {
 218         struct device_node *dn;
 219         unsigned long *regs;
 220         char *compatible;
 221         unsigned *np, found = 0;
 222         struct iic *iic = NULL;
 223
 224         for (dn = NULL; (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
 225                 compatible = (char *)get_property(dn, "compatible", NULL);
 226
 227                 if (!compatible) {
 228                         printk(KERN_WARNING "no compatible property found !\n");
 229                         continue;
 230                 }
 231
 232                 if (strstr(compatible, "IBM,CBEA-Internal-Interrupt-Controller"))
 233                         regs = (unsigned long *)get_property(dn,"reg", NULL);
 234                 else
 235                         continue;
 236
 237                 if (!regs)
 238                         printk(KERN_WARNING "IIC: no reg property\n");
 239
 240                 np = (unsigned int *)get_property(dn, "ibm,interrupt-server-ranges", NULL);
 241
 242                 if (!np) {
 243                         printk(KERN_WARNING "IIC: CPU association not found\n");
 244                         iic->regs = NULL;
 245                         iic->target_id = 0xff;
 246                         return -ENODEV;
 247                 }
 248
 249                 iic = &per_cpu(iic, np[0]);
 250                 iic->regs = ioremap(regs[0], sizeof(struct cbe_iic_thread_regs));
 251                 iic->target_id = ((np[0] & 2) << 3) + ((np[0] & 1) ? 0xf : 0xe);
 252                 printk("IIC for CPU %d at %lx mapped to %p\n", np[0], regs[0], iic->regs);
 253
 254                 iic = &per_cpu(iic, np[1]);
 255                 iic->regs = ioremap(regs[2], sizeof(struct cbe_iic_thread_regs));
 256                 iic->target_id = ((np[1] & 2) << 3) + ((np[1] & 1) ? 0xf : 0xe);
 257                 printk("IIC for CPU %d at %lx mapped to %p\n", np[1], regs[2], iic->regs);
 258
 259                 found++;
 260         }
 261
 262         if (found)
 263                 return 0;
 264         else
 265                 return -ENODEV;
 266 }
 267
 268 #ifdef CONFIG_SMP
 269
 270 /* Use the highest interrupt priorities for IPI */
 271 static inline int iic_ipi_to_irq(int ipi)
 272 {
 273         return IIC_IPI_OFFSET + IIC_NUM_IPIS - 1 - ipi;
 274 }
 275
 276 static inline int iic_irq_to_ipi(int irq)
 277 {
 278         return IIC_NUM_IPIS - 1 - (irq - IIC_IPI_OFFSET);
 279 }
 280
 281 void iic_setup_cpu(void)
 282 {
 283         out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
 284 }
 285
 286 void iic_cause_IPI(int cpu, int mesg)
 287 {
 288         out_be64(&per_cpu(iic, cpu).regs->generate, (IIC_NUM_IPIS - 1 - mesg) << 4);
 289 }
 290
 291 u8 iic_get_target_id(int cpu)
 292 {
 293         return per_cpu(iic, cpu).target_id;
 294 }
 295 EXPORT_SYMBOL_GPL(iic_get_target_id);
 296
 297 static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
 298 {
 299         smp_message_recv(iic_irq_to_ipi(irq), regs);
 300         return IRQ_HANDLED;
 301 }
 302
 303 static void iic_request_ipi(int ipi, const char *name)
 304 {
 305         int irq;
 306
 307         irq = iic_ipi_to_irq(ipi);
 308         /* IPIs are marked SA_INTERRUPT as they must run with irqs
 309          * disabled */
 310         get_irq_desc(irq)->handler = &iic_pic;
 311         get_irq_desc(irq)->status |= IRQ_PER_CPU;
 312         request_irq(irq, iic_ipi_action, SA_INTERRUPT, name, NULL);
 313 }
 314
 315 void iic_request_IPIs(void)
 316 {
 317         iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
 318         iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
 319 #ifdef CONFIG_DEBUGGER
 320         iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
 321 #endif /* CONFIG_DEBUGGER */
 322 }
 323 #endif /* CONFIG_SMP */
 324
 325 static void iic_setup_spe_handlers(void)
 326 {
 327         int be, isrc;
 328
 329         /* Assume two threads per BE are present */
 330         for (be=0; be < num_present_cpus() / 2; be++) {
 331                 for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) {
 332                         int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
 333                         get_irq_desc(irq)->handler = &iic_pic;
 334                 }
 335         }
 336 }
 337
 338 void iic_init_IRQ(void)
 339 {
 340         int cpu, irq_offset;
 341         struct iic *iic;
 342
 343         if (setup_iic() < 0)
 344                 setup_iic_hardcoded();
 345
 346         irq_offset = 0;
 347         for_each_possible_cpu(cpu) {
 348                 iic = &per_cpu(iic, cpu);
 349                 if (iic->regs)
 350                         out_be64(&iic->regs->prio, 0xff);
 351         }
 352         iic_setup_spe_handlers();
 353 }