arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/msi.h>
  24
  25 #include <asm/sections.h>
  26 #include <asm/io.h>
  27 #include <asm/prom.h>
  28 #include <asm/pci-bridge.h>
  29 #include <asm/machdep.h>
  30 #include <asm/msi_bitmap.h>
  31 #include <asm/ppc-pci.h>
  32 #include <asm/opal.h>
  33 #include <asm/iommu.h>
  34 #include <asm/tce.h>
  35 #include <asm/xics.h>
  36 #include <asm/debug.h>
  37
  38 #include "powernv.h"
  39 #include "pci.h"
  40
  41 #define define_pe_printk_level(func, kern_level)                \
  42 static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...)     \
  43 {                                                               \
  44         struct va_format vaf;                                   \
  45         va_list args;                                           \
  46         char pfix[32];                                          \
  47         int r;                                                  \
  48                                                                 \
  49         va_start(args, fmt);                                    \
  50                                                                 \
  51         vaf.fmt = fmt;                                          \
  52         vaf.va = &args;                                         \
  53                                                                 \
  54         if (pe->pdev)                                           \
  55                 strlcpy(pfix, dev_name(&pe->pdev->dev),         \
  56                         sizeof(pfix));                          \
  57         else                                                    \
  58                 sprintf(pfix, "%04x:%02x     ",                 \
  59                         pci_domain_nr(pe->pbus),                \
  60                         pe->pbus->number);                      \
  61         r = printk(kern_level "pci %s: [PE# %.3d] %pV",         \
  62                    pfix, pe->pe_number, &vaf);                  \
  63                                                                 \
  64         va_end(args);                                           \
  65                                                                 \
  66         return r;                                               \
  67 }                                                               \
  68
  69 define_pe_printk_level(pe_err, KERN_ERR);
  70 define_pe_printk_level(pe_warn, KERN_WARNING);
  71 define_pe_printk_level(pe_info, KERN_INFO);
  72
  73 /*
  74  * stdcix is only supposed to be used in hypervisor real mode as per
  75  * the architecture spec
  76  */
  77 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
  78 {
  79         __asm__ __volatile__("stdcix %0,0,%1"
  80                 : : "r" (val), "r" (paddr) : "memory");
  81 }
  82
  83 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
  84 {
  85         unsigned long pe;
  86
  87         do {
  88                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
  89                                         phb->ioda.total_pe, 0);
  90                 if (pe >= phb->ioda.total_pe)
  91                         return IODA_INVALID_PE;
  92         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
  93
  94         phb->ioda.pe_array[pe].phb = phb;
  95         phb->ioda.pe_array[pe].pe_number = pe;
  96         return pe;
  97 }
  98
  99 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
 100 {
 101         WARN_ON(phb->ioda.pe_array[pe].pdev);
 102
 103         memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
 104         clear_bit(pe, phb->ioda.pe_alloc);
 105 }
 106
 107 /* Currently those 2 are only used when MSIs are enabled, this will change
 108  * but in the meantime, we need to protect them to avoid warnings
 109  */
 110 #ifdef CONFIG_PCI_MSI
 111 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 112 {
 113         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 114         struct pnv_phb *phb = hose->private_data;
 115         struct pci_dn *pdn = pci_get_pdn(dev);
 116
 117         if (!pdn)
 118                 return NULL;
 119         if (pdn->pe_number == IODA_INVALID_PE)
 120                 return NULL;
 121         return &phb->ioda.pe_array[pdn->pe_number];
 122 }
 123 #endif /* CONFIG_PCI_MSI */
 124
 125 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 126 {
 127         struct pci_dev *parent;
 128         uint8_t bcomp, dcomp, fcomp;
 129         long rc, rid_end, rid;
 130
 131         /* Bus validation ? */
 132         if (pe->pbus) {
 133                 int count;
 134
 135                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 136                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 137                 parent = pe->pbus->self;
 138                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 139                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 140                 else
 141                         count = 1;
 142
 143                 switch(count) {
 144                 case  1: bcomp = OpalPciBusAll;         break;
 145                 case  2: bcomp = OpalPciBus7Bits;       break;
 146                 case  4: bcomp = OpalPciBus6Bits;       break;
 147                 case  8: bcomp = OpalPciBus5Bits;       break;
 148                 case 16: bcomp = OpalPciBus4Bits;       break;
 149                 case 32: bcomp = OpalPciBus3Bits;       break;
 150                 default:
 151                         pr_err("%s: Number of subordinate busses %d"
 152                                " unsupported\n",
 153                                pci_name(pe->pbus->self), count);
 154                         /* Do an exact match only */
 155                         bcomp = OpalPciBusAll;
 156                 }
 157                 rid_end = pe->rid + (count << 8);
 158         } else {
 159                 parent = pe->pdev->bus->self;
 160                 bcomp = OpalPciBusAll;
 161                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 162                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 163                 rid_end = pe->rid + 1;
 164         }
 165
 166         /* Associate PE in PELT */
 167         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 168                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 169         if (rc) {
 170                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 171                 return -ENXIO;
 172         }
 173         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 174                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 175
 176         /* Add to all parents PELT-V */
 177         while (parent) {
 178                 struct pci_dn *pdn = pci_get_pdn(parent);
 179                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 180                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 181                                                 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
 182                         /* XXX What to do in case of error ? */
 183                 }
 184                 parent = parent->bus->self;
 185         }
 186         /* Setup reverse map */
 187         for (rid = pe->rid; rid < rid_end; rid++)
 188                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 189
 190         /* Setup one MVTs on IODA1 */
 191         if (phb->type == PNV_PHB_IODA1) {
 192                 pe->mve_number = pe->pe_number;
 193                 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number,
 194                                       pe->pe_number);
 195                 if (rc) {
 196                         pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 197                                rc, pe->mve_number);
 198                         pe->mve_number = -1;
 199                 } else {
 200                         rc = opal_pci_set_mve_enable(phb->opal_id,
 201                                                      pe->mve_number, OPAL_ENABLE_MVE);
 202                         if (rc) {
 203                                 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 204                                        rc, pe->mve_number);
 205                                 pe->mve_number = -1;
 206                         }
 207                 }
 208         } else if (phb->type == PNV_PHB_IODA2)
 209                 pe->mve_number = 0;
 210
 211         return 0;
 212 }
 213
 214 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 215                                        struct pnv_ioda_pe *pe)
 216 {
 217         struct pnv_ioda_pe *lpe;
 218
 219         list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
 220                 if (lpe->dma_weight < pe->dma_weight) {
 221                         list_add_tail(&pe->dma_link, &lpe->dma_link);
 222                         return;
 223                 }
 224         }
 225         list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 226 }
 227
 228 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
 229 {
 230         /* This is quite simplistic. The "base" weight of a device
 231          * is 10. 0 means no DMA is to be accounted for it.
 232          */
 233
 234         /* If it's a bridge, no DMA */
 235         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
 236                 return 0;
 237
 238         /* Reduce the weight of slow USB controllers */
 239         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
 240             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
 241             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
 242                 return 3;
 243
 244         /* Increase the weight of RAID (includes Obsidian) */
 245         if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
 246                 return 15;
 247
 248         /* Default */
 249         return 10;
 250 }
 251
 252 #if 0
 253 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 254 {
 255         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 256         struct pnv_phb *phb = hose->private_data;
 257         struct pci_dn *pdn = pci_get_pdn(dev);
 258         struct pnv_ioda_pe *pe;
 259         int pe_num;
 260
 261         if (!pdn) {
 262                 pr_err("%s: Device tree node not associated properly\n",
 263                            pci_name(dev));
 264                 return NULL;
 265         }
 266         if (pdn->pe_number != IODA_INVALID_PE)
 267                 return NULL;
 268
 269         /* PE#0 has been pre-set */
 270         if (dev->bus->number == 0)
 271                 pe_num = 0;
 272         else
 273                 pe_num = pnv_ioda_alloc_pe(phb);
 274         if (pe_num == IODA_INVALID_PE) {
 275                 pr_warning("%s: Not enough PE# available, disabling device\n",
 276                            pci_name(dev));
 277                 return NULL;
 278         }
 279
 280         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 281          * pointer in the PE data structure, both should be destroyed at the
 282          * same time. However, this needs to be looked at more closely again
 283          * once we actually start removing things (Hotplug, SR-IOV, ...)
 284          *
 285          * At some point we want to remove the PDN completely anyways
 286          */
 287         pe = &phb->ioda.pe_array[pe_num];
 288         pci_dev_get(dev);
 289         pdn->pcidev = dev;
 290         pdn->pe_number = pe_num;
 291         pe->pdev = dev;
 292         pe->pbus = NULL;
 293         pe->tce32_seg = -1;
 294         pe->mve_number = -1;
 295         pe->rid = dev->bus->number << 8 | pdn->devfn;
 296
 297         pe_info(pe, "Associated device to PE\n");
 298
 299         if (pnv_ioda_configure_pe(phb, pe)) {
 300                 /* XXX What do we do here ? */
 301                 if (pe_num)
 302                         pnv_ioda_free_pe(phb, pe_num);
 303                 pdn->pe_number = IODA_INVALID_PE;
 304                 pe->pdev = NULL;
 305                 pci_dev_put(dev);
 306                 return NULL;
 307         }
 308
 309         /* Assign a DMA weight to the device */
 310         pe->dma_weight = pnv_ioda_dma_weight(dev);
 311         if (pe->dma_weight != 0) {
 312                 phb->ioda.dma_weight += pe->dma_weight;
 313                 phb->ioda.dma_pe_count++;
 314         }
 315
 316         /* Link the PE */
 317         pnv_ioda_link_pe_by_weight(phb, pe);
 318
 319         return pe;
 320 }
 321 #endif /* Useful for SRIOV case */
 322
 323 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
 324 {
 325         struct pci_dev *dev;
 326
 327         list_for_each_entry(dev, &bus->devices, bus_list) {
 328                 struct pci_dn *pdn = pci_get_pdn(dev);
 329
 330                 if (pdn == NULL) {
 331                         pr_warn("%s: No device node associated with device !\n",
 332                                 pci_name(dev));
 333                         continue;
 334                 }
 335                 pci_dev_get(dev);
 336                 pdn->pcidev = dev;
 337                 pdn->pe_number = pe->pe_number;
 338                 pe->dma_weight += pnv_ioda_dma_weight(dev);
 339                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
 340                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
 341         }
 342 }
 343
 344 /*
 345  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
 346  * single PCI bus. Another one that contains the primary PCI bus and its
 347  * subordinate PCI devices and buses. The second type of PE is normally
 348  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
 349  */
 350 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
 351 {
 352         struct pci_controller *hose = pci_bus_to_host(bus);
 353         struct pnv_phb *phb = hose->private_data;
 354         struct pnv_ioda_pe *pe;
 355         int pe_num;
 356
 357         pe_num = pnv_ioda_alloc_pe(phb);
 358         if (pe_num == IODA_INVALID_PE) {
 359                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
 360                         __func__, pci_domain_nr(bus), bus->number);
 361                 return;
 362         }
 363
 364         pe = &phb->ioda.pe_array[pe_num];
 365         pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
 366         pe->pbus = bus;
 367         pe->pdev = NULL;
 368         pe->tce32_seg = -1;
 369         pe->mve_number = -1;
 370         pe->rid = bus->busn_res.start << 8;
 371         pe->dma_weight = 0;
 372
 373         if (all)
 374                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
 375                         bus->busn_res.start, bus->busn_res.end, pe_num);
 376         else
 377                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
 378                         bus->busn_res.start, pe_num);
 379
 380         if (pnv_ioda_configure_pe(phb, pe)) {
 381                 /* XXX What do we do here ? */
 382                 if (pe_num)
 383                         pnv_ioda_free_pe(phb, pe_num);
 384                 pe->pbus = NULL;
 385                 return;
 386         }
 387
 388         /* Associate it with all child devices */
 389         pnv_ioda_setup_same_PE(bus, pe);
 390
 391         /* Put PE to the list */
 392         list_add_tail(&pe->list, &phb->ioda.pe_list);
 393
 394         /* Account for one DMA PE if at least one DMA capable device exist
 395          * below the bridge
 396          */
 397         if (pe->dma_weight != 0) {
 398                 phb->ioda.dma_weight += pe->dma_weight;
 399                 phb->ioda.dma_pe_count++;
 400         }
 401
 402         /* Link the PE */
 403         pnv_ioda_link_pe_by_weight(phb, pe);
 404 }
 405
 406 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
 407 {
 408         struct pci_dev *dev;
 409
 410         pnv_ioda_setup_bus_PE(bus, 0);
 411
 412         list_for_each_entry(dev, &bus->devices, bus_list) {
 413                 if (dev->subordinate) {
 414                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
 415                                 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
 416                         else
 417                                 pnv_ioda_setup_PEs(dev->subordinate);
 418                 }
 419         }
 420 }
 421
 422 /*
 423  * Configure PEs so that the downstream PCI buses and devices
 424  * could have their associated PE#. Unfortunately, we didn't
 425  * figure out the way to identify the PLX bridge yet. So we
 426  * simply put the PCI bus and the subordinate behind the root
 427  * port to PE# here. The game rule here is expected to be changed
 428  * as soon as we can detected PLX bridge correctly.
 429  */
 430 static void pnv_pci_ioda_setup_PEs(void)
 431 {
 432         struct pci_controller *hose, *tmp;
 433
 434         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 435                 pnv_ioda_setup_PEs(hose->bus);
 436         }
 437 }
 438
 439 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
 440 {
 441         struct pci_dn *pdn = pci_get_pdn(pdev);
 442         struct pnv_ioda_pe *pe;
 443
 444         /*
 445          * The function can be called while the PE#
 446          * hasn't been assigned. Do nothing for the
 447          * case.
 448          */
 449         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
 450                 return;
 451
 452         pe = &phb->ioda.pe_array[pdn->pe_number];
 453         set_iommu_table_base(&pdev->dev, &pe->tce32_table);
 454 }
 455
 456 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
 457 {
 458         struct pci_dev *dev;
 459
 460         list_for_each_entry(dev, &bus->devices, bus_list) {
 461                 set_iommu_table_base(&dev->dev, &pe->tce32_table);
 462                 if (dev->subordinate)
 463                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
 464         }
 465 }
 466
 467 static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe,
 468                                          struct iommu_table *tbl,
 469                                          __be64 *startp, __be64 *endp, bool rm)
 470 {
 471         __be64 __iomem *invalidate = rm ?
 472                 (__be64 __iomem *)pe->tce_inval_reg_phys :
 473                 (__be64 __iomem *)tbl->it_index;
 474         unsigned long start, end, inc;
 475
 476         start = __pa(startp);
 477         end = __pa(endp);
 478
 479         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
 480         if (tbl->it_busno) {
 481                 start <<= 12;
 482                 end <<= 12;
 483                 inc = 128 << 12;
 484                 start |= tbl->it_busno;
 485                 end |= tbl->it_busno;
 486         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
 487                 /* p7ioc-style invalidation, 2 TCEs per write */
 488                 start |= (1ull << 63);
 489                 end |= (1ull << 63);
 490                 inc = 16;
 491         } else {
 492                 /* Default (older HW) */
 493                 inc = 128;
 494         }
 495
 496         end |= inc - 1; /* round up end to be different than start */
 497
 498         mb(); /* Ensure above stores are visible */
 499         while (start <= end) {
 500                 if (rm)
 501                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
 502                 else
 503                         __raw_writeq(cpu_to_be64(start), invalidate);
 504                 start += inc;
 505         }
 506
 507         /*
 508          * The iommu layer will do another mb() for us on build()
 509          * and we don't care on free()
 510          */
 511 }
 512
 513 static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
 514                                          struct iommu_table *tbl,
 515                                          __be64 *startp, __be64 *endp, bool rm)
 516 {
 517         unsigned long start, end, inc;
 518         __be64 __iomem *invalidate = rm ?
 519                 (__be64 __iomem *)pe->tce_inval_reg_phys :
 520                 (__be64 __iomem *)tbl->it_index;
 521
 522         /* We'll invalidate DMA address in PE scope */
 523         start = 0x2ul << 60;
 524         start |= (pe->pe_number & 0xFF);
 525         end = start;
 526
 527         /* Figure out the start, end and step */
 528         inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64));
 529         start |= (inc << 12);
 530         inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64));
 531         end |= (inc << 12);
 532         inc = (0x1ul << 12);
 533         mb();
 534
 535         while (start <= end) {
 536                 if (rm)
 537                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
 538                 else
 539                         __raw_writeq(cpu_to_be64(start), invalidate);
 540                 start += inc;
 541         }
 542 }
 543
 544 void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
 545                                  __be64 *startp, __be64 *endp, bool rm)
 546 {
 547         struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
 548                                               tce32_table);
 549         struct pnv_phb *phb = pe->phb;
 550
 551         if (phb->type == PNV_PHB_IODA1)
 552                 pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm);
 553         else
 554                 pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm);
 555 }
 556
 557 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
 558                                       struct pnv_ioda_pe *pe, unsigned int base,
 559                                       unsigned int segs)
 560 {
 561
 562         struct page *tce_mem = NULL;
 563         const __be64 *swinvp;
 564         struct iommu_table *tbl;
 565         unsigned int i;
 566         int64_t rc;
 567         void *addr;
 568
 569         /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
 570 #define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
 571
 572         /* XXX FIXME: Handle 64-bit only DMA devices */
 573         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
 574         /* XXX FIXME: Allocate multi-level tables on PHB3 */
 575
 576         /* We shouldn't already have a 32-bit DMA associated */
 577         if (WARN_ON(pe->tce32_seg >= 0))
 578                 return;
 579
 580         /* Grab a 32-bit TCE table */
 581         pe->tce32_seg = base;
 582         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
 583                 (base << 28), ((base + segs) << 28) - 1);
 584
 585         /* XXX Currently, we allocate one big contiguous table for the
 586          * TCEs. We only really need one chunk per 256M of TCE space
 587          * (ie per segment) but that's an optimization for later, it
 588          * requires some added smarts with our get/put_tce implementation
 589          */
 590         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
 591                                    get_order(TCE32_TABLE_SIZE * segs));
 592         if (!tce_mem) {
 593                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
 594                 goto fail;
 595         }
 596         addr = page_address(tce_mem);
 597         memset(addr, 0, TCE32_TABLE_SIZE * segs);
 598
 599         /* Configure HW */
 600         for (i = 0; i < segs; i++) {
 601                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
 602                                               pe->pe_number,
 603                                               base + i, 1,
 604                                               __pa(addr) + TCE32_TABLE_SIZE * i,
 605                                               TCE32_TABLE_SIZE, 0x1000);
 606                 if (rc) {
 607                         pe_err(pe, " Failed to configure 32-bit TCE table,"
 608                                " err %ld\n", rc);
 609                         goto fail;
 610                 }
 611         }
 612
 613         /* Setup linux iommu table */
 614         tbl = &pe->tce32_table;
 615         pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
 616                                   base << 28);
 617
 618         /* OPAL variant of P7IOC SW invalidated TCEs */
 619         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
 620         if (swinvp) {
 621                 /* We need a couple more fields -- an address and a data
 622                  * to or.  Since the bus is only printed out on table free
 623                  * errors, and on the first pass the data will be a relative
 624                  * bus number, print that out instead.
 625                  */
 626                 tbl->it_busno = 0;
 627                 pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
 628                 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
 629                                 8);
 630                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE |
 631                                TCE_PCI_SWINV_PAIR;
 632         }
 633         iommu_init_table(tbl, phb->hose->node);
 634         iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number);
 635
 636         if (pe->pdev)
 637                 set_iommu_table_base(&pe->pdev->dev, tbl);
 638         else
 639                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
 640
 641         return;
 642  fail:
 643         /* XXX Failure: Try to fallback to 64-bit only ? */
 644         if (pe->tce32_seg >= 0)
 645                 pe->tce32_seg = -1;
 646         if (tce_mem)
 647                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
 648 }
 649
 650 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
 651                                        struct pnv_ioda_pe *pe)
 652 {
 653         struct page *tce_mem = NULL;
 654         void *addr;
 655         const __be64 *swinvp;
 656         struct iommu_table *tbl;
 657         unsigned int tce_table_size, end;
 658         int64_t rc;
 659
 660         /* We shouldn't already have a 32-bit DMA associated */
 661         if (WARN_ON(pe->tce32_seg >= 0))
 662                 return;
 663
 664         /* The PE will reserve all possible 32-bits space */
 665         pe->tce32_seg = 0;
 666         end = (1 << ilog2(phb->ioda.m32_pci_base));
 667         tce_table_size = (end / 0x1000) * 8;
 668         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
 669                 end);
 670
 671         /* Allocate TCE table */
 672         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
 673                                    get_order(tce_table_size));
 674         if (!tce_mem) {
 675                 pe_err(pe, "Failed to allocate a 32-bit TCE memory\n");
 676                 goto fail;
 677         }
 678         addr = page_address(tce_mem);
 679         memset(addr, 0, tce_table_size);
 680
 681         /*
 682          * Map TCE table through TVT. The TVE index is the PE number
 683          * shifted by 1 bit for 32-bits DMA space.
 684          */
 685         rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
 686                                         pe->pe_number << 1, 1, __pa(addr),
 687                                         tce_table_size, 0x1000);
 688         if (rc) {
 689                 pe_err(pe, "Failed to configure 32-bit TCE table,"
 690                        " err %ld\n", rc);
 691                 goto fail;
 692         }
 693
 694         /* Setup linux iommu table */
 695         tbl = &pe->tce32_table;
 696         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0);
 697
 698         /* OPAL variant of PHB3 invalidated TCEs */
 699         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
 700         if (swinvp) {
 701                 /* We need a couple more fields -- an address and a data
 702                  * to or.  Since the bus is only printed out on table free
 703                  * errors, and on the first pass the data will be a relative
 704                  * bus number, print that out instead.
 705                  */
 706                 tbl->it_busno = 0;
 707                 pe->tce_inval_reg_phys = be64_to_cpup(swinvp);
 708                 tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys,
 709                                 8);
 710                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 711         }
 712         iommu_init_table(tbl, phb->hose->node);
 713
 714         if (pe->pdev)
 715                 set_iommu_table_base(&pe->pdev->dev, tbl);
 716         else
 717                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
 718
 719         return;
 720 fail:
 721         if (pe->tce32_seg >= 0)
 722                 pe->tce32_seg = -1;
 723         if (tce_mem)
 724                 __free_pages(tce_mem, get_order(tce_table_size));
 725 }
 726
 727 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
 728 {
 729         struct pci_controller *hose = phb->hose;
 730         unsigned int residual, remaining, segs, tw, base;
 731         struct pnv_ioda_pe *pe;
 732
 733         /* If we have more PE# than segments available, hand out one
 734          * per PE until we run out and let the rest fail. If not,
 735          * then we assign at least one segment per PE, plus more based
 736          * on the amount of devices under that PE
 737          */
 738         if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
 739                 residual = 0;
 740         else
 741                 residual = phb->ioda.tce32_count -
 742                         phb->ioda.dma_pe_count;
 743
 744         pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
 745                 hose->global_number, phb->ioda.tce32_count);
 746         pr_info("PCI: %d PE# for a total weight of %d\n",
 747                 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
 748
 749         /* Walk our PE list and configure their DMA segments, hand them
 750          * out one base segment plus any residual segments based on
 751          * weight
 752          */
 753         remaining = phb->ioda.tce32_count;
 754         tw = phb->ioda.dma_weight;
 755         base = 0;
 756         list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
 757                 if (!pe->dma_weight)
 758                         continue;
 759                 if (!remaining) {
 760                         pe_warn(pe, "No DMA32 resources available\n");
 761                         continue;
 762                 }
 763                 segs = 1;
 764                 if (residual) {
 765                         segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
 766                         if (segs > remaining)
 767                                 segs = remaining;
 768                 }
 769
 770                 /*
 771                  * For IODA2 compliant PHB3, we needn't care about the weight.
 772                  * The all available 32-bits DMA space will be assigned to
 773                  * the specific PE.
 774                  */
 775                 if (phb->type == PNV_PHB_IODA1) {
 776                         pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
 777                                 pe->dma_weight, segs);
 778                         pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
 779                 } else {
 780                         pe_info(pe, "Assign DMA32 space\n");
 781                         segs = 0;
 782                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
 783                 }
 784
 785                 remaining -= segs;
 786                 base += segs;
 787         }
 788 }
 789
 790 #ifdef CONFIG_PCI_MSI
 791 static void pnv_ioda2_msi_eoi(struct irq_data *d)
 792 {
 793         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 794         struct irq_chip *chip = irq_data_get_irq_chip(d);
 795         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
 796                                            ioda.irq_chip);
 797         int64_t rc;
 798
 799         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
 800         WARN_ON_ONCE(rc);
 801
 802         icp_native_eoi(d);
 803 }
 804
 805 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
 806                                   unsigned int hwirq, unsigned int virq,
 807                                   unsigned int is_64, struct msi_msg *msg)
 808 {
 809         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
 810         struct pci_dn *pdn = pci_get_pdn(dev);
 811         struct irq_data *idata;
 812         struct irq_chip *ichip;
 813         unsigned int xive_num = hwirq - phb->msi_base;
 814         __be32 data;
 815         int rc;
 816
 817         /* No PE assigned ? bail out ... no MSI for you ! */
 818         if (pe == NULL)
 819                 return -ENXIO;
 820
 821         /* Check if we have an MVE */
 822         if (pe->mve_number < 0)
 823                 return -ENXIO;
 824
 825         /* Force 32-bit MSI on some broken devices */
 826         if (pdn && pdn->force_32bit_msi)
 827                 is_64 = 0;
 828
 829         /* Assign XIVE to PE */
 830         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
 831         if (rc) {
 832                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
 833                         pci_name(dev), rc, xive_num);
 834                 return -EIO;
 835         }
 836
 837         if (is_64) {
 838                 __be64 addr64;
 839
 840                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
 841                                      &addr64, &data);
 842                 if (rc) {
 843                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
 844                                 pci_name(dev), rc);
 845                         return -EIO;
 846                 }
 847                 msg->address_hi = be64_to_cpu(addr64) >> 32;
 848                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
 849         } else {
 850                 __be32 addr32;
 851
 852                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
 853                                      &addr32, &data);
 854                 if (rc) {
 855                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
 856                                 pci_name(dev), rc);
 857                         return -EIO;
 858                 }
 859                 msg->address_hi = 0;
 860                 msg->address_lo = be32_to_cpu(addr32);
 861         }
 862         msg->data = be32_to_cpu(data);
 863
 864         /*
 865          * Change the IRQ chip for the MSI interrupts on PHB3.
 866          * The corresponding IRQ chip should be populated for
 867          * the first time.
 868          */
 869         if (phb->type == PNV_PHB_IODA2) {
 870                 if (!phb->ioda.irq_chip_init) {
 871                         idata = irq_get_irq_data(virq);
 872                         ichip = irq_data_get_irq_chip(idata);
 873                         phb->ioda.irq_chip_init = 1;
 874                         phb->ioda.irq_chip = *ichip;
 875                         phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
 876                 }
 877
 878                 irq_set_chip(virq, &phb->ioda.irq_chip);
 879         }
 880
 881         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
 882                  " address=%x_%08x data=%x PE# %d\n",
 883                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
 884                  msg->address_hi, msg->address_lo, data, pe->pe_number);
 885
 886         return 0;
 887 }
 888
 889 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
 890 {
 891         unsigned int count;
 892         const __be32 *prop = of_get_property(phb->hose->dn,
 893                                              "ibm,opal-msi-ranges", NULL);
 894         if (!prop) {
 895                 /* BML Fallback */
 896                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
 897         }
 898         if (!prop)
 899                 return;
 900
 901         phb->msi_base = be32_to_cpup(prop);
 902         count = be32_to_cpup(prop + 1);
 903         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
 904                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
 905                        phb->hose->global_number);
 906                 return;
 907         }
 908
 909         phb->msi_setup = pnv_pci_ioda_msi_setup;
 910         phb->msi32_support = 1;
 911         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
 912                 count, phb->msi_base);
 913 }
 914 #else
 915 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
 916 #endif /* CONFIG_PCI_MSI */
 917
 918 /*
 919  * This function is supposed to be called on basis of PE from top
 920  * to bottom style. So the the I/O or MMIO segment assigned to
 921  * parent PE could be overrided by its child PEs if necessary.
 922  */
 923 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
 924                                   struct pnv_ioda_pe *pe)
 925 {
 926         struct pnv_phb *phb = hose->private_data;
 927         struct pci_bus_region region;
 928         struct resource *res;
 929         int i, index;
 930         int rc;
 931
 932         /*
 933          * NOTE: We only care PCI bus based PE for now. For PCI
 934          * device based PE, for example SRIOV sensitive VF should
 935          * be figured out later.
 936          */
 937         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
 938
 939         pci_bus_for_each_resource(pe->pbus, res, i) {
 940                 if (!res || !res->flags ||
 941                     res->start > res->end)
 942                         continue;
 943
 944                 if (res->flags & IORESOURCE_IO) {
 945                         region.start = res->start - phb->ioda.io_pci_base;
 946                         region.end   = res->end - phb->ioda.io_pci_base;
 947                         index = region.start / phb->ioda.io_segsize;
 948
 949                         while (index < phb->ioda.total_pe &&
 950                                region.start <= region.end) {
 951                                 phb->ioda.io_segmap[index] = pe->pe_number;
 952                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 953                                         pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
 954                                 if (rc != OPAL_SUCCESS) {
 955                                         pr_err("%s: OPAL error %d when mapping IO "
 956                                                "segment #%d to PE#%d\n",
 957                                                __func__, rc, index, pe->pe_number);
 958                                         break;
 959                                 }
 960
 961                                 region.start += phb->ioda.io_segsize;
 962                                 index++;
 963                         }
 964                 } else if (res->flags & IORESOURCE_MEM) {
 965                         /* WARNING: Assumes M32 is mem region 0 in PHB. We need to
 966                          * harden that algorithm when we start supporting M64
 967                          */
 968                         region.start = res->start -
 969                                        hose->mem_offset[0] -
 970                                        phb->ioda.m32_pci_base;
 971                         region.end   = res->end -
 972                                        hose->mem_offset[0] -
 973                                        phb->ioda.m32_pci_base;
 974                         index = region.start / phb->ioda.m32_segsize;
 975
 976                         while (index < phb->ioda.total_pe &&
 977                                region.start <= region.end) {
 978                                 phb->ioda.m32_segmap[index] = pe->pe_number;
 979                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 980                                         pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
 981                                 if (rc != OPAL_SUCCESS) {
 982                                         pr_err("%s: OPAL error %d when mapping M32 "
 983                                                "segment#%d to PE#%d",
 984                                                __func__, rc, index, pe->pe_number);
 985                                         break;
 986                                 }
 987
 988                                 region.start += phb->ioda.m32_segsize;
 989                                 index++;
 990                         }
 991                 }
 992         }
 993 }
 994
 995 static void pnv_pci_ioda_setup_seg(void)
 996 {
 997         struct pci_controller *tmp, *hose;
 998         struct pnv_phb *phb;
 999         struct pnv_ioda_pe *pe;
1000
1001         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1002                 phb = hose->private_data;
1003                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
1004                         pnv_ioda_setup_pe_seg(hose, pe);
1005                 }
1006         }
1007 }
1008
1009 static void pnv_pci_ioda_setup_DMA(void)
1010 {
1011         struct pci_controller *hose, *tmp;
1012         struct pnv_phb *phb;
1013
1014         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1015                 pnv_ioda_setup_dma(hose->private_data);
1016
1017                 /* Mark the PHB initialization done */
1018                 phb = hose->private_data;
1019                 phb->initialized = 1;
1020         }
1021 }
1022
1023 static void pnv_pci_ioda_create_dbgfs(void)
1024 {
1025 #ifdef CONFIG_DEBUG_FS
1026         struct pci_controller *hose, *tmp;
1027         struct pnv_phb *phb;
1028         char name[16];
1029
1030         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1031                 phb = hose->private_data;
1032
1033                 sprintf(name, "PCI%04x", hose->global_number);
1034                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
1035                 if (!phb->dbgfs)
1036                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
1037                                 __func__, hose->global_number);
1038         }
1039 #endif /* CONFIG_DEBUG_FS */
1040 }
1041
1042 static void pnv_pci_ioda_fixup(void)
1043 {
1044         pnv_pci_ioda_setup_PEs();
1045         pnv_pci_ioda_setup_seg();
1046         pnv_pci_ioda_setup_DMA();
1047
1048         pnv_pci_ioda_create_dbgfs();
1049
1050 #ifdef CONFIG_EEH
1051         eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
1052         eeh_addr_cache_build();
1053         eeh_init();
1054 #endif
1055 }
1056
1057 /*
1058  * Returns the alignment for I/O or memory windows for P2P
1059  * bridges. That actually depends on how PEs are segmented.
1060  * For now, we return I/O or M32 segment size for PE sensitive
1061  * P2P bridges. Otherwise, the default values (4KiB for I/O,
1062  * 1MiB for memory) will be returned.
1063  *
1064  * The current PCI bus might be put into one PE, which was
1065  * create against the parent PCI bridge. For that case, we
1066  * needn't enlarge the alignment so that we can save some
1067  * resources.
1068  */
1069 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
1070                                                 unsigned long type)
1071 {
1072         struct pci_dev *bridge;
1073         struct pci_controller *hose = pci_bus_to_host(bus);
1074         struct pnv_phb *phb = hose->private_data;
1075         int num_pci_bridges = 0;
1076
1077         bridge = bus->self;
1078         while (bridge) {
1079                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
1080                         num_pci_bridges++;
1081                         if (num_pci_bridges >= 2)
1082                                 return 1;
1083                 }
1084
1085                 bridge = bridge->bus->self;
1086         }
1087
1088         /* We need support prefetchable memory window later */
1089         if (type & IORESOURCE_MEM)
1090                 return phb->ioda.m32_segsize;
1091
1092         return phb->ioda.io_segsize;
1093 }
1094
1095 /* Prevent enabling devices for which we couldn't properly
1096  * assign a PE
1097  */
1098 static int pnv_pci_enable_device_hook(struct pci_dev *dev)
1099 {
1100         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1101         struct pnv_phb *phb = hose->private_data;
1102         struct pci_dn *pdn;
1103
1104         /* The function is probably called while the PEs have
1105          * not be created yet. For example, resource reassignment
1106          * during PCI probe period. We just skip the check if
1107          * PEs isn't ready.
1108          */
1109         if (!phb->initialized)
1110                 return 0;
1111
1112         pdn = pci_get_pdn(dev);
1113         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1114                 return -EINVAL;
1115
1116         return 0;
1117 }
1118
1119 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
1120                                u32 devfn)
1121 {
1122         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
1123 }
1124
1125 static void pnv_pci_ioda_shutdown(struct pnv_phb *phb)
1126 {
1127         opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET,
1128                        OPAL_ASSERT_RESET);
1129 }
1130
1131 void __init pnv_pci_init_ioda_phb(struct device_node *np,
1132                                   u64 hub_id, int ioda_type)
1133 {
1134         struct pci_controller *hose;
1135         struct pnv_phb *phb;
1136         unsigned long size, m32map_off, iomap_off, pemap_off;
1137         const __be64 *prop64;
1138         const __be32 *prop32;
1139         int len;
1140         u64 phb_id;
1141         void *aux;
1142         long rc;
1143
1144         pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
1145
1146         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
1147         if (!prop64) {
1148                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
1149                 return;
1150         }
1151         phb_id = be64_to_cpup(prop64);
1152         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
1153
1154         phb = alloc_bootmem(sizeof(struct pnv_phb));
1155         if (!phb) {
1156                 pr_err("  Out of memory !\n");
1157                 return;
1158         }
1159
1160         /* Allocate PCI controller */
1161         memset(phb, 0, sizeof(struct pnv_phb));
1162         phb->hose = hose = pcibios_alloc_controller(np);
1163         if (!phb->hose) {
1164                 pr_err("  Can't allocate PCI controller for %s\n",
1165                        np->full_name);
1166                 free_bootmem((unsigned long)phb, sizeof(struct pnv_phb));
1167                 return;
1168         }
1169
1170         spin_lock_init(&phb->lock);
1171         prop32 = of_get_property(np, "bus-range", &len);
1172         if (prop32 && len == 8) {
1173                 hose->first_busno = be32_to_cpu(prop32[0]);
1174                 hose->last_busno = be32_to_cpu(prop32[1]);
1175         } else {
1176                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
1177                 hose->first_busno = 0;
1178                 hose->last_busno = 0xff;
1179         }
1180         hose->private_data = phb;
1181         phb->hub_id = hub_id;
1182         phb->opal_id = phb_id;
1183         phb->type = ioda_type;
1184
1185         /* Detect specific models for error handling */
1186         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
1187                 phb->model = PNV_PHB_MODEL_P7IOC;
1188         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
1189                 phb->model = PNV_PHB_MODEL_PHB3;
1190         else
1191                 phb->model = PNV_PHB_MODEL_UNKNOWN;
1192
1193         /* Parse 32-bit and IO ranges (if any) */
1194         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
1195
1196         /* Get registers */
1197         phb->regs = of_iomap(np, 0);
1198         if (phb->regs == NULL)
1199                 pr_err("  Failed to map registers !\n");
1200
1201         /* Initialize more IODA stuff */
1202         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
1203         if (!prop32)
1204                 phb->ioda.total_pe = 1;
1205         else
1206                 phb->ioda.total_pe = be32_to_cpup(prop32);
1207
1208         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
1209         /* FW Has already off top 64k of M32 space (MSI space) */
1210         phb->ioda.m32_size += 0x10000;
1211
1212         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
1213         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
1214         phb->ioda.io_size = hose->pci_io_size;
1215         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
1216         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
1217
1218         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
1219         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
1220         m32map_off = size;
1221         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
1222         iomap_off = size;
1223         if (phb->type == PNV_PHB_IODA1) {
1224                 iomap_off = size;
1225                 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
1226         }
1227         pemap_off = size;
1228         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
1229         aux = alloc_bootmem(size);
1230         memset(aux, 0, size);
1231         phb->ioda.pe_alloc = aux;
1232         phb->ioda.m32_segmap = aux + m32map_off;
1233         if (phb->type == PNV_PHB_IODA1)
1234                 phb->ioda.io_segmap = aux + iomap_off;
1235         phb->ioda.pe_array = aux + pemap_off;
1236         set_bit(0, phb->ioda.pe_alloc);
1237
1238         INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
1239         INIT_LIST_HEAD(&phb->ioda.pe_list);
1240
1241         /* Calculate how many 32-bit TCE segments we have */
1242         phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
1243
1244         /* Clear unusable m64 */
1245         hose->mem_resources[1].flags = 0;
1246         hose->mem_resources[1].start = 0;
1247         hose->mem_resources[1].end = 0;
1248         hose->mem_resources[2].flags = 0;
1249         hose->mem_resources[2].start = 0;
1250         hose->mem_resources[2].end = 0;
1251
1252 #if 0 /* We should really do that ... */
1253         rc = opal_pci_set_phb_mem_window(opal->phb_id,
1254                                          window_type,
1255                                          window_num,
1256                                          starting_real_address,
1257                                          starting_pci_address,
1258                                          segment_size);
1259 #endif
1260
1261         pr_info("  %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n",
1262                 phb->ioda.total_pe,
1263                 phb->ioda.m32_size, phb->ioda.m32_segsize,
1264                 phb->ioda.io_size, phb->ioda.io_segsize);
1265
1266         phb->hose->ops = &pnv_pci_ops;
1267 #ifdef CONFIG_EEH
1268         phb->eeh_ops = &ioda_eeh_ops;
1269 #endif
1270
1271         /* Setup RID -> PE mapping function */
1272         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
1273
1274         /* Setup TCEs */
1275         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
1276
1277         /* Setup shutdown function for kexec */
1278         phb->shutdown = pnv_pci_ioda_shutdown;
1279
1280         /* Setup MSI support */
1281         pnv_pci_init_ioda_msis(phb);
1282
1283         /*
1284          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
1285          * to let the PCI core do resource assignment. It's supposed
1286          * that the PCI core will do correct I/O and MMIO alignment
1287          * for the P2P bridge bars so that each PCI bus (excluding
1288          * the child P2P bridges) can form individual PE.
1289          */
1290         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
1291         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
1292         ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
1293         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1294
1295         /* Reset IODA tables to a clean state */
1296         rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
1297         if (rc)
1298                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
1299
1300         /*
1301          * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset
1302          * has cleared the RTT which has the same effect
1303          */
1304         if (ioda_type == PNV_PHB_IODA1)
1305                 opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
1306 }
1307
1308 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
1309 {
1310         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
1311 }
1312
1313 void __init pnv_pci_init_ioda_hub(struct device_node *np)
1314 {
1315         struct device_node *phbn;
1316         const __be64 *prop64;
1317         u64 hub_id;
1318
1319         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
1320
1321         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
1322         if (!prop64) {
1323                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
1324                 return;
1325         }
1326         hub_id = be64_to_cpup(prop64);
1327         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
1328
1329         /* Count child PHBs */
1330         for_each_child_of_node(np, phbn) {
1331                 /* Look for IODA1 PHBs */
1332                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
1333                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
1334         }
1335 }