arch/powerpc/sysdev/mpic.c

   1 /*
   2  *  arch/powerpc/kernel/mpic.c
   3  *
   4  *  Driver for interrupt controllers following the OpenPIC standard, the
   5  *  common implementation beeing IBM's MPIC. This driver also can deal
   6  *  with various broken implementations of this HW.
   7  *
   8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9  *  Copyright 2010-2011 Freescale Semiconductor, Inc.
  10  *
  11  *  This file is subject to the terms and conditions of the GNU General Public
  12  *  License.  See the file COPYING in the main directory of this archive
  13  *  for more details.
  14  */
  15
  16 #undef DEBUG
  17 #undef DEBUG_IPI
  18 #undef DEBUG_IRQ
  19 #undef DEBUG_LOW
  20
  21 #include <linux/types.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/irq.h>
  25 #include <linux/smp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/bootmem.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/pci.h>
  30 #include <linux/slab.h>
  31 #include <linux/syscore_ops.h>
  32 #include <linux/ratelimit.h>
  33
  34 #include <asm/ptrace.h>
  35 #include <asm/signal.h>
  36 #include <asm/io.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/irq.h>
  39 #include <asm/machdep.h>
  40 #include <asm/mpic.h>
  41 #include <asm/smp.h>
  42
  43 #include "mpic.h"
  44
  45 #ifdef DEBUG
  46 #define DBG(fmt...) printk(fmt)
  47 #else
  48 #define DBG(fmt...)
  49 #endif
  50
  51 static struct mpic *mpics;
  52 static struct mpic *mpic_primary;
  53 static DEFINE_RAW_SPINLOCK(mpic_lock);
  54
  55 #ifdef CONFIG_PPC32     /* XXX for now */
  56 #ifdef CONFIG_IRQ_ALL_CPUS
  57 #define distribute_irqs (1)
  58 #else
  59 #define distribute_irqs (0)
  60 #endif
  61 #endif
  62
  63 #ifdef CONFIG_MPIC_WEIRD
  64 static u32 mpic_infos[][MPIC_IDX_END] = {
  65         [0] = { /* Original OpenPIC compatible MPIC */
  66                 MPIC_GREG_BASE,
  67                 MPIC_GREG_FEATURE_0,
  68                 MPIC_GREG_GLOBAL_CONF_0,
  69                 MPIC_GREG_VENDOR_ID,
  70                 MPIC_GREG_IPI_VECTOR_PRI_0,
  71                 MPIC_GREG_IPI_STRIDE,
  72                 MPIC_GREG_SPURIOUS,
  73                 MPIC_GREG_TIMER_FREQ,
  74
  75                 MPIC_TIMER_BASE,
  76                 MPIC_TIMER_STRIDE,
  77                 MPIC_TIMER_CURRENT_CNT,
  78                 MPIC_TIMER_BASE_CNT,
  79                 MPIC_TIMER_VECTOR_PRI,
  80                 MPIC_TIMER_DESTINATION,
  81
  82                 MPIC_CPU_BASE,
  83                 MPIC_CPU_STRIDE,
  84                 MPIC_CPU_IPI_DISPATCH_0,
  85                 MPIC_CPU_IPI_DISPATCH_STRIDE,
  86                 MPIC_CPU_CURRENT_TASK_PRI,
  87                 MPIC_CPU_WHOAMI,
  88                 MPIC_CPU_INTACK,
  89                 MPIC_CPU_EOI,
  90                 MPIC_CPU_MCACK,
  91
  92                 MPIC_IRQ_BASE,
  93                 MPIC_IRQ_STRIDE,
  94                 MPIC_IRQ_VECTOR_PRI,
  95                 MPIC_VECPRI_VECTOR_MASK,
  96                 MPIC_VECPRI_POLARITY_POSITIVE,
  97                 MPIC_VECPRI_POLARITY_NEGATIVE,
  98                 MPIC_VECPRI_SENSE_LEVEL,
  99                 MPIC_VECPRI_SENSE_EDGE,
 100                 MPIC_VECPRI_POLARITY_MASK,
 101                 MPIC_VECPRI_SENSE_MASK,
 102                 MPIC_IRQ_DESTINATION
 103         },
 104         [1] = { /* Tsi108/109 PIC */
 105                 TSI108_GREG_BASE,
 106                 TSI108_GREG_FEATURE_0,
 107                 TSI108_GREG_GLOBAL_CONF_0,
 108                 TSI108_GREG_VENDOR_ID,
 109                 TSI108_GREG_IPI_VECTOR_PRI_0,
 110                 TSI108_GREG_IPI_STRIDE,
 111                 TSI108_GREG_SPURIOUS,
 112                 TSI108_GREG_TIMER_FREQ,
 113
 114                 TSI108_TIMER_BASE,
 115                 TSI108_TIMER_STRIDE,
 116                 TSI108_TIMER_CURRENT_CNT,
 117                 TSI108_TIMER_BASE_CNT,
 118                 TSI108_TIMER_VECTOR_PRI,
 119                 TSI108_TIMER_DESTINATION,
 120
 121                 TSI108_CPU_BASE,
 122                 TSI108_CPU_STRIDE,
 123                 TSI108_CPU_IPI_DISPATCH_0,
 124                 TSI108_CPU_IPI_DISPATCH_STRIDE,
 125                 TSI108_CPU_CURRENT_TASK_PRI,
 126                 TSI108_CPU_WHOAMI,
 127                 TSI108_CPU_INTACK,
 128                 TSI108_CPU_EOI,
 129                 TSI108_CPU_MCACK,
 130
 131                 TSI108_IRQ_BASE,
 132                 TSI108_IRQ_STRIDE,
 133                 TSI108_IRQ_VECTOR_PRI,
 134                 TSI108_VECPRI_VECTOR_MASK,
 135                 TSI108_VECPRI_POLARITY_POSITIVE,
 136                 TSI108_VECPRI_POLARITY_NEGATIVE,
 137                 TSI108_VECPRI_SENSE_LEVEL,
 138                 TSI108_VECPRI_SENSE_EDGE,
 139                 TSI108_VECPRI_POLARITY_MASK,
 140                 TSI108_VECPRI_SENSE_MASK,
 141                 TSI108_IRQ_DESTINATION
 142         },
 143 };
 144
 145 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 146
 147 #else /* CONFIG_MPIC_WEIRD */
 148
 149 #define MPIC_INFO(name) MPIC_##name
 150
 151 #endif /* CONFIG_MPIC_WEIRD */
 152
 153 static inline unsigned int mpic_processor_id(struct mpic *mpic)
 154 {
 155         unsigned int cpu = 0;
 156
 157         if (!(mpic->flags & MPIC_SECONDARY))
 158                 cpu = hard_smp_processor_id();
 159
 160         return cpu;
 161 }
 162
 163 /*
 164  * Register accessor functions
 165  */
 166
 167
 168 static inline u32 _mpic_read(enum mpic_reg_type type,
 169                              struct mpic_reg_bank *rb,
 170                              unsigned int reg)
 171 {
 172         switch(type) {
 173 #ifdef CONFIG_PPC_DCR
 174         case mpic_access_dcr:
 175                 return dcr_read(rb->dhost, reg);
 176 #endif
 177         case mpic_access_mmio_be:
 178                 return in_be32(rb->base + (reg >> 2));
 179         case mpic_access_mmio_le:
 180         default:
 181                 return in_le32(rb->base + (reg >> 2));
 182         }
 183 }
 184
 185 static inline void _mpic_write(enum mpic_reg_type type,
 186                                struct mpic_reg_bank *rb,
 187                                unsigned int reg, u32 value)
 188 {
 189         switch(type) {
 190 #ifdef CONFIG_PPC_DCR
 191         case mpic_access_dcr:
 192                 dcr_write(rb->dhost, reg, value);
 193                 break;
 194 #endif
 195         case mpic_access_mmio_be:
 196                 out_be32(rb->base + (reg >> 2), value);
 197                 break;
 198         case mpic_access_mmio_le:
 199         default:
 200                 out_le32(rb->base + (reg >> 2), value);
 201                 break;
 202         }
 203 }
 204
 205 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 206 {
 207         enum mpic_reg_type type = mpic->reg_type;
 208         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 209                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 210
 211         if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 212                 type = mpic_access_mmio_be;
 213         return _mpic_read(type, &mpic->gregs, offset);
 214 }
 215
 216 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 217 {
 218         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 219                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 220
 221         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 222 }
 223
 224 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
 225 {
 226         unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
 227                               ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
 228
 229         if (tm >= 4)
 230                 offset += 0x1000 / 4;
 231
 232         return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
 233 }
 234
 235 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
 236 {
 237         unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
 238                               ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
 239
 240         if (tm >= 4)
 241                 offset += 0x1000 / 4;
 242
 243         _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
 244 }
 245
 246 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 247 {
 248         unsigned int cpu = mpic_processor_id(mpic);
 249
 250         return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 251 }
 252
 253 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 254 {
 255         unsigned int cpu = mpic_processor_id(mpic);
 256
 257         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 258 }
 259
 260 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 261 {
 262         unsigned int    isu = src_no >> mpic->isu_shift;
 263         unsigned int    idx = src_no & mpic->isu_mask;
 264         unsigned int    val;
 265
 266         val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
 267                          reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 268 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 269         if (reg == 0)
 270                 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
 271                         mpic->isu_reg0_shadow[src_no];
 272 #endif
 273         return val;
 274 }
 275
 276 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 277                                    unsigned int reg, u32 value)
 278 {
 279         unsigned int    isu = src_no >> mpic->isu_shift;
 280         unsigned int    idx = src_no & mpic->isu_mask;
 281
 282         _mpic_write(mpic->reg_type, &mpic->isus[isu],
 283                     reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 284
 285 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 286         if (reg == 0)
 287                 mpic->isu_reg0_shadow[src_no] =
 288                         value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 289 #endif
 290 }
 291
 292 #define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
 293 #define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
 294 #define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
 295 #define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
 296 #define mpic_tm_read(i)         _mpic_tm_read(mpic,(i))
 297 #define mpic_tm_write(i,v)      _mpic_tm_write(mpic,(i),(v))
 298 #define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
 299 #define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
 300 #define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
 301 #define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
 302
 303
 304 /*
 305  * Low level utility functions
 306  */
 307
 308
 309 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 310                            struct mpic_reg_bank *rb, unsigned int offset,
 311                            unsigned int size)
 312 {
 313         rb->base = ioremap(phys_addr + offset, size);
 314         BUG_ON(rb->base == NULL);
 315 }
 316
 317 #ifdef CONFIG_PPC_DCR
 318 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
 319                           unsigned int offset, unsigned int size)
 320 {
 321         phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
 322         rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
 323         BUG_ON(!DCR_MAP_OK(rb->dhost));
 324 }
 325
 326 static inline void mpic_map(struct mpic *mpic,
 327                             phys_addr_t phys_addr, struct mpic_reg_bank *rb,
 328                             unsigned int offset, unsigned int size)
 329 {
 330         if (mpic->flags & MPIC_USES_DCR)
 331                 _mpic_map_dcr(mpic, rb, offset, size);
 332         else
 333                 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 334 }
 335 #else /* CONFIG_PPC_DCR */
 336 #define mpic_map(m,p,b,o,s)     _mpic_map_mmio(m,p,b,o,s)
 337 #endif /* !CONFIG_PPC_DCR */
 338
 339
 340
 341 /* Check if we have one of those nice broken MPICs with a flipped endian on
 342  * reads from IPI registers
 343  */
 344 static void __init mpic_test_broken_ipi(struct mpic *mpic)
 345 {
 346         u32 r;
 347
 348         mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 349         r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 350
 351         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 352                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 353                 mpic->flags |= MPIC_BROKEN_IPI;
 354         }
 355 }
 356
 357 #ifdef CONFIG_MPIC_U3_HT_IRQS
 358
 359 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 360  * to force the edge setting on the MPIC and do the ack workaround.
 361  */
 362 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 363 {
 364         if (source >= 128 || !mpic->fixups)
 365                 return 0;
 366         return mpic->fixups[source].base != NULL;
 367 }
 368
 369
 370 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 371 {
 372         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 373
 374         if (fixup->applebase) {
 375                 unsigned int soff = (fixup->index >> 3) & ~3;
 376                 unsigned int mask = 1U << (fixup->index & 0x1f);
 377                 writel(mask, fixup->applebase + soff);
 378         } else {
 379                 raw_spin_lock(&mpic->fixup_lock);
 380                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 381                 writel(fixup->data, fixup->base + 4);
 382                 raw_spin_unlock(&mpic->fixup_lock);
 383         }
 384 }
 385
 386 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 387                                       bool level)
 388 {
 389         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 390         unsigned long flags;
 391         u32 tmp;
 392
 393         if (fixup->base == NULL)
 394                 return;
 395
 396         DBG("startup_ht_interrupt(0x%x) index: %d\n",
 397             source, fixup->index);
 398         raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 399         /* Enable and configure */
 400         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 401         tmp = readl(fixup->base + 4);
 402         tmp &= ~(0x23U);
 403         if (level)
 404                 tmp |= 0x22;
 405         writel(tmp, fixup->base + 4);
 406         raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 407
 408 #ifdef CONFIG_PM
 409         /* use the lowest bit inverted to the actual HW,
 410          * set if this fixup was enabled, clear otherwise */
 411         mpic->save_data[source].fixup_data = tmp | 1;
 412 #endif
 413 }
 414
 415 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
 416 {
 417         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 418         unsigned long flags;
 419         u32 tmp;
 420
 421         if (fixup->base == NULL)
 422                 return;
 423
 424         DBG("shutdown_ht_interrupt(0x%x)\n", source);
 425
 426         /* Disable */
 427         raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 428         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 429         tmp = readl(fixup->base + 4);
 430         tmp |= 1;
 431         writel(tmp, fixup->base + 4);
 432         raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 433
 434 #ifdef CONFIG_PM
 435         /* use the lowest bit inverted to the actual HW,
 436          * set if this fixup was enabled, clear otherwise */
 437         mpic->save_data[source].fixup_data = tmp & ~1;
 438 #endif
 439 }
 440
 441 #ifdef CONFIG_PCI_MSI
 442 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 443                                     unsigned int devfn)
 444 {
 445         u8 __iomem *base;
 446         u8 pos, flags;
 447         u64 addr = 0;
 448
 449         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 450              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 451                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 452                 if (id == PCI_CAP_ID_HT) {
 453                         id = readb(devbase + pos + 3);
 454                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 455                                 break;
 456                 }
 457         }
 458
 459         if (pos == 0)
 460                 return;
 461
 462         base = devbase + pos;
 463
 464         flags = readb(base + HT_MSI_FLAGS);
 465         if (!(flags & HT_MSI_FLAGS_FIXED)) {
 466                 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 467                 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 468         }
 469
 470         printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
 471                 PCI_SLOT(devfn), PCI_FUNC(devfn),
 472                 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 473
 474         if (!(flags & HT_MSI_FLAGS_ENABLE))
 475                 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 476 }
 477 #else
 478 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 479                                     unsigned int devfn)
 480 {
 481         return;
 482 }
 483 #endif
 484
 485 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 486                                     unsigned int devfn, u32 vdid)
 487 {
 488         int i, irq, n;
 489         u8 __iomem *base;
 490         u32 tmp;
 491         u8 pos;
 492
 493         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 494              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 495                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 496                 if (id == PCI_CAP_ID_HT) {
 497                         id = readb(devbase + pos + 3);
 498                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 499                                 break;
 500                 }
 501         }
 502         if (pos == 0)
 503                 return;
 504
 505         base = devbase + pos;
 506         writeb(0x01, base + 2);
 507         n = (readl(base + 4) >> 16) & 0xff;
 508
 509         printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 510                " has %d irqs\n",
 511                devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 512
 513         for (i = 0; i <= n; i++) {
 514                 writeb(0x10 + 2 * i, base + 2);
 515                 tmp = readl(base + 4);
 516                 irq = (tmp >> 16) & 0xff;
 517                 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 518                 /* mask it , will be unmasked later */
 519                 tmp |= 0x1;
 520                 writel(tmp, base + 4);
 521                 mpic->fixups[irq].index = i;
 522                 mpic->fixups[irq].base = base;
 523                 /* Apple HT PIC has a non-standard way of doing EOIs */
 524                 if ((vdid & 0xffff) == 0x106b)
 525                         mpic->fixups[irq].applebase = devbase + 0x60;
 526                 else
 527                         mpic->fixups[irq].applebase = NULL;
 528                 writeb(0x11 + 2 * i, base + 2);
 529                 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 530         }
 531 }
 532
 533
 534 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 535 {
 536         unsigned int devfn;
 537         u8 __iomem *cfgspace;
 538
 539         printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 540
 541         /* Allocate fixups array */
 542         mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
 543         BUG_ON(mpic->fixups == NULL);
 544
 545         /* Init spinlock */
 546         raw_spin_lock_init(&mpic->fixup_lock);
 547
 548         /* Map U3 config space. We assume all IO-APICs are on the primary bus
 549          * so we only need to map 64kB.
 550          */
 551         cfgspace = ioremap(0xf2000000, 0x10000);
 552         BUG_ON(cfgspace == NULL);
 553
 554         /* Now we scan all slots. We do a very quick scan, we read the header
 555          * type, vendor ID and device ID only, that's plenty enough
 556          */
 557         for (devfn = 0; devfn < 0x100; devfn++) {
 558                 u8 __iomem *devbase = cfgspace + (devfn << 8);
 559                 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 560                 u32 l = readl(devbase + PCI_VENDOR_ID);
 561                 u16 s;
 562
 563                 DBG("devfn %x, l: %x\n", devfn, l);
 564
 565                 /* If no device, skip */
 566                 if (l == 0xffffffff || l == 0x00000000 ||
 567                     l == 0x0000ffff || l == 0xffff0000)
 568                         goto next;
 569                 /* Check if is supports capability lists */
 570                 s = readw(devbase + PCI_STATUS);
 571                 if (!(s & PCI_STATUS_CAP_LIST))
 572                         goto next;
 573
 574                 mpic_scan_ht_pic(mpic, devbase, devfn, l);
 575                 mpic_scan_ht_msi(mpic, devbase, devfn);
 576
 577         next:
 578                 /* next device, if function 0 */
 579                 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 580                         devfn += 7;
 581         }
 582 }
 583
 584 #else /* CONFIG_MPIC_U3_HT_IRQS */
 585
 586 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 587 {
 588         return 0;
 589 }
 590
 591 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 592 {
 593 }
 594
 595 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 596
 597 /* Find an mpic associated with a given linux interrupt */
 598 static struct mpic *mpic_find(unsigned int irq)
 599 {
 600         if (irq < NUM_ISA_INTERRUPTS)
 601                 return NULL;
 602
 603         return irq_get_chip_data(irq);
 604 }
 605
 606 /* Determine if the linux irq is an IPI */
 607 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
 608 {
 609         unsigned int src = virq_to_hw(irq);
 610
 611         return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 612 }
 613
 614 /* Determine if the linux irq is a timer */
 615 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
 616 {
 617         unsigned int src = virq_to_hw(irq);
 618
 619         return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 620 }
 621
 622 /* Convert a cpu mask from logical to physical cpu numbers. */
 623 static inline u32 mpic_physmask(u32 cpumask)
 624 {
 625         int i;
 626         u32 mask = 0;
 627
 628         for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
 629                 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 630         return mask;
 631 }
 632
 633 #ifdef CONFIG_SMP
 634 /* Get the mpic structure from the IPI number */
 635 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
 636 {
 637         return irq_data_get_irq_chip_data(d);
 638 }
 639 #endif
 640
 641 /* Get the mpic structure from the irq number */
 642 static inline struct mpic * mpic_from_irq(unsigned int irq)
 643 {
 644         return irq_get_chip_data(irq);
 645 }
 646
 647 /* Get the mpic structure from the irq data */
 648 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
 649 {
 650         return irq_data_get_irq_chip_data(d);
 651 }
 652
 653 /* Send an EOI */
 654 static inline void mpic_eoi(struct mpic *mpic)
 655 {
 656         mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 657         (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 658 }
 659
 660 /*
 661  * Linux descriptor level callbacks
 662  */
 663
 664
 665 void mpic_unmask_irq(struct irq_data *d)
 666 {
 667         unsigned int loops = 100000;
 668         struct mpic *mpic = mpic_from_irq_data(d);
 669         unsigned int src = irqd_to_hwirq(d);
 670
 671         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
 672
 673         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 674                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 675                        ~MPIC_VECPRI_MASK);
 676         /* make sure mask gets to controller before we return to user */
 677         do {
 678                 if (!loops--) {
 679                         printk(KERN_ERR "%s: timeout on hwirq %u\n",
 680                                __func__, src);
 681                         break;
 682                 }
 683         } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 684 }
 685
 686 void mpic_mask_irq(struct irq_data *d)
 687 {
 688         unsigned int loops = 100000;
 689         struct mpic *mpic = mpic_from_irq_data(d);
 690         unsigned int src = irqd_to_hwirq(d);
 691
 692         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
 693
 694         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 695                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 696                        MPIC_VECPRI_MASK);
 697
 698         /* make sure mask gets to controller before we return to user */
 699         do {
 700                 if (!loops--) {
 701                         printk(KERN_ERR "%s: timeout on hwirq %u\n",
 702                                __func__, src);
 703                         break;
 704                 }
 705         } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 706 }
 707
 708 void mpic_end_irq(struct irq_data *d)
 709 {
 710         struct mpic *mpic = mpic_from_irq_data(d);
 711
 712 #ifdef DEBUG_IRQ
 713         DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 714 #endif
 715         /* We always EOI on end_irq() even for edge interrupts since that
 716          * should only lower the priority, the MPIC should have properly
 717          * latched another edge interrupt coming in anyway
 718          */
 719
 720         mpic_eoi(mpic);
 721 }
 722
 723 #ifdef CONFIG_MPIC_U3_HT_IRQS
 724
 725 static void mpic_unmask_ht_irq(struct irq_data *d)
 726 {
 727         struct mpic *mpic = mpic_from_irq_data(d);
 728         unsigned int src = irqd_to_hwirq(d);
 729
 730         mpic_unmask_irq(d);
 731
 732         if (irqd_is_level_type(d))
 733                 mpic_ht_end_irq(mpic, src);
 734 }
 735
 736 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
 737 {
 738         struct mpic *mpic = mpic_from_irq_data(d);
 739         unsigned int src = irqd_to_hwirq(d);
 740
 741         mpic_unmask_irq(d);
 742         mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
 743
 744         return 0;
 745 }
 746
 747 static void mpic_shutdown_ht_irq(struct irq_data *d)
 748 {
 749         struct mpic *mpic = mpic_from_irq_data(d);
 750         unsigned int src = irqd_to_hwirq(d);
 751
 752         mpic_shutdown_ht_interrupt(mpic, src);
 753         mpic_mask_irq(d);
 754 }
 755
 756 static void mpic_end_ht_irq(struct irq_data *d)
 757 {
 758         struct mpic *mpic = mpic_from_irq_data(d);
 759         unsigned int src = irqd_to_hwirq(d);
 760
 761 #ifdef DEBUG_IRQ
 762         DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 763 #endif
 764         /* We always EOI on end_irq() even for edge interrupts since that
 765          * should only lower the priority, the MPIC should have properly
 766          * latched another edge interrupt coming in anyway
 767          */
 768
 769         if (irqd_is_level_type(d))
 770                 mpic_ht_end_irq(mpic, src);
 771         mpic_eoi(mpic);
 772 }
 773 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
 774
 775 #ifdef CONFIG_SMP
 776
 777 static void mpic_unmask_ipi(struct irq_data *d)
 778 {
 779         struct mpic *mpic = mpic_from_ipi(d);
 780         unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
 781
 782         DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
 783         mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 784 }
 785
 786 static void mpic_mask_ipi(struct irq_data *d)
 787 {
 788         /* NEVER disable an IPI... that's just plain wrong! */
 789 }
 790
 791 static void mpic_end_ipi(struct irq_data *d)
 792 {
 793         struct mpic *mpic = mpic_from_ipi(d);
 794
 795         /*
 796          * IPIs are marked IRQ_PER_CPU. This has the side effect of
 797          * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 798          * applying to them. We EOI them late to avoid re-entering.
 799          */
 800         mpic_eoi(mpic);
 801 }
 802
 803 #endif /* CONFIG_SMP */
 804
 805 static void mpic_unmask_tm(struct irq_data *d)
 806 {
 807         struct mpic *mpic = mpic_from_irq_data(d);
 808         unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 809
 810         DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
 811         mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
 812         mpic_tm_read(src);
 813 }
 814
 815 static void mpic_mask_tm(struct irq_data *d)
 816 {
 817         struct mpic *mpic = mpic_from_irq_data(d);
 818         unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 819
 820         mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
 821         mpic_tm_read(src);
 822 }
 823
 824 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 825                       bool force)
 826 {
 827         struct mpic *mpic = mpic_from_irq_data(d);
 828         unsigned int src = irqd_to_hwirq(d);
 829
 830         if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
 831                 int cpuid = irq_choose_cpu(cpumask);
 832
 833                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 834         } else {
 835                 u32 mask = cpumask_bits(cpumask)[0];
 836
 837                 mask &= cpumask_bits(cpu_online_mask)[0];
 838
 839                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 840                                mpic_physmask(mask));
 841         }
 842
 843         return 0;
 844 }
 845
 846 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 847 {
 848         /* Now convert sense value */
 849         switch(type & IRQ_TYPE_SENSE_MASK) {
 850         case IRQ_TYPE_EDGE_RISING:
 851                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 852                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 853         case IRQ_TYPE_EDGE_FALLING:
 854         case IRQ_TYPE_EDGE_BOTH:
 855                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 856                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 857         case IRQ_TYPE_LEVEL_HIGH:
 858                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 859                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 860         case IRQ_TYPE_LEVEL_LOW:
 861         default:
 862                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 863                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 864         }
 865 }
 866
 867 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 868 {
 869         struct mpic *mpic = mpic_from_irq_data(d);
 870         unsigned int src = irqd_to_hwirq(d);
 871         unsigned int vecpri, vold, vnew;
 872
 873         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 874             mpic, d->irq, src, flow_type);
 875
 876         if (src >= mpic->irq_count)
 877                 return -EINVAL;
 878
 879         if (flow_type == IRQ_TYPE_NONE)
 880                 if (mpic->senses && src < mpic->senses_count)
 881                         flow_type = mpic->senses[src];
 882         if (flow_type == IRQ_TYPE_NONE)
 883                 flow_type = IRQ_TYPE_LEVEL_LOW;
 884
 885         irqd_set_trigger_type(d, flow_type);
 886
 887         if (mpic_is_ht_interrupt(mpic, src))
 888                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 889                         MPIC_VECPRI_SENSE_EDGE;
 890         else
 891                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
 892
 893         vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 894         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 895                         MPIC_INFO(VECPRI_SENSE_MASK));
 896         vnew |= vecpri;
 897         if (vold != vnew)
 898                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 899
 900         return IRQ_SET_MASK_OK_NOCOPY;
 901 }
 902
 903 void mpic_set_vector(unsigned int virq, unsigned int vector)
 904 {
 905         struct mpic *mpic = mpic_from_irq(virq);
 906         unsigned int src = virq_to_hw(virq);
 907         unsigned int vecpri;
 908
 909         DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
 910             mpic, virq, src, vector);
 911
 912         if (src >= mpic->irq_count)
 913                 return;
 914
 915         vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 916         vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
 917         vecpri |= vector;
 918         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 919 }
 920
 921 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
 922 {
 923         struct mpic *mpic = mpic_from_irq(virq);
 924         unsigned int src = virq_to_hw(virq);
 925
 926         DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
 927             mpic, virq, src, cpuid);
 928
 929         if (src >= mpic->irq_count)
 930                 return;
 931
 932         mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 933 }
 934
 935 static struct irq_chip mpic_irq_chip = {
 936         .irq_mask       = mpic_mask_irq,
 937         .irq_unmask     = mpic_unmask_irq,
 938         .irq_eoi        = mpic_end_irq,
 939         .irq_set_type   = mpic_set_irq_type,
 940 };
 941
 942 #ifdef CONFIG_SMP
 943 static struct irq_chip mpic_ipi_chip = {
 944         .irq_mask       = mpic_mask_ipi,
 945         .irq_unmask     = mpic_unmask_ipi,
 946         .irq_eoi        = mpic_end_ipi,
 947 };
 948 #endif /* CONFIG_SMP */
 949
 950 static struct irq_chip mpic_tm_chip = {
 951         .irq_mask       = mpic_mask_tm,
 952         .irq_unmask     = mpic_unmask_tm,
 953         .irq_eoi        = mpic_end_irq,
 954 };
 955
 956 #ifdef CONFIG_MPIC_U3_HT_IRQS
 957 static struct irq_chip mpic_irq_ht_chip = {
 958         .irq_startup    = mpic_startup_ht_irq,
 959         .irq_shutdown   = mpic_shutdown_ht_irq,
 960         .irq_mask       = mpic_mask_irq,
 961         .irq_unmask     = mpic_unmask_ht_irq,
 962         .irq_eoi        = mpic_end_ht_irq,
 963         .irq_set_type   = mpic_set_irq_type,
 964 };
 965 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 966
 967
 968 static int mpic_host_match(struct irq_host *h, struct device_node *node)
 969 {
 970         /* Exact match, unless mpic node is NULL */
 971         return h->of_node == NULL || h->of_node == node;
 972 }
 973
 974 static int mpic_host_map(struct irq_host *h, unsigned int virq,
 975                          irq_hw_number_t hw)
 976 {
 977         struct mpic *mpic = h->host_data;
 978         struct irq_chip *chip;
 979
 980         DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
 981
 982         if (hw == mpic->spurious_vec)
 983                 return -EINVAL;
 984         if (mpic->protected && test_bit(hw, mpic->protected))
 985                 return -EINVAL;
 986
 987 #ifdef CONFIG_SMP
 988         else if (hw >= mpic->ipi_vecs[0]) {
 989                 WARN_ON(mpic->flags & MPIC_SECONDARY);
 990
 991                 DBG("mpic: mapping as IPI\n");
 992                 irq_set_chip_data(virq, mpic);
 993                 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
 994                                          handle_percpu_irq);
 995                 return 0;
 996         }
 997 #endif /* CONFIG_SMP */
 998
 999         if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1000                 WARN_ON(mpic->flags & MPIC_SECONDARY);
1001
1002                 DBG("mpic: mapping as timer\n");
1003                 irq_set_chip_data(virq, mpic);
1004                 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1005                                          handle_fasteoi_irq);
1006                 return 0;
1007         }
1008
1009         if (hw >= mpic->irq_count)
1010                 return -EINVAL;
1011
1012         mpic_msi_reserve_hwirq(mpic, hw);
1013
1014         /* Default chip */
1015         chip = &mpic->hc_irq;
1016
1017 #ifdef CONFIG_MPIC_U3_HT_IRQS
1018         /* Check for HT interrupts, override vecpri */
1019         if (mpic_is_ht_interrupt(mpic, hw))
1020                 chip = &mpic->hc_ht_irq;
1021 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1022
1023         DBG("mpic: mapping to irq chip @%p\n", chip);
1024
1025         irq_set_chip_data(virq, mpic);
1026         irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1027
1028         /* Set default irq type */
1029         irq_set_irq_type(virq, IRQ_TYPE_NONE);
1030
1031         /* If the MPIC was reset, then all vectors have already been
1032          * initialized.  Otherwise, a per source lazy initialization
1033          * is done here.
1034          */
1035         if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1036                 mpic_set_vector(virq, hw);
1037                 mpic_set_destination(virq, mpic_processor_id(mpic));
1038                 mpic_irq_set_priority(virq, 8);
1039         }
1040
1041         return 0;
1042 }
1043
1044 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1045                            const u32 *intspec, unsigned int intsize,
1046                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1047
1048 {
1049         struct mpic *mpic = h->host_data;
1050         static unsigned char map_mpic_senses[4] = {
1051                 IRQ_TYPE_EDGE_RISING,
1052                 IRQ_TYPE_LEVEL_LOW,
1053                 IRQ_TYPE_LEVEL_HIGH,
1054                 IRQ_TYPE_EDGE_FALLING,
1055         };
1056
1057         *out_hwirq = intspec[0];
1058         if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1059                 /*
1060                  * Freescale MPIC with extended intspec:
1061                  * First two cells are as usual.  Third specifies
1062                  * an "interrupt type".  Fourth is type-specific data.
1063                  *
1064                  * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1065                  */
1066                 switch (intspec[2]) {
1067                 case 0:
1068                 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1069                         break;
1070                 case 2:
1071                         if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1072                                 return -EINVAL;
1073
1074                         *out_hwirq = mpic->ipi_vecs[intspec[0]];
1075                         break;
1076                 case 3:
1077                         if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1078                                 return -EINVAL;
1079
1080                         *out_hwirq = mpic->timer_vecs[intspec[0]];
1081                         break;
1082                 default:
1083                         pr_debug("%s: unknown irq type %u\n",
1084                                  __func__, intspec[2]);
1085                         return -EINVAL;
1086                 }
1087
1088                 *out_flags = map_mpic_senses[intspec[1] & 3];
1089         } else if (intsize > 1) {
1090                 u32 mask = 0x3;
1091
1092                 /* Apple invented a new race of encoding on machines with
1093                  * an HT APIC. They encode, among others, the index within
1094                  * the HT APIC. We don't care about it here since thankfully,
1095                  * it appears that they have the APIC already properly
1096                  * configured, and thus our current fixup code that reads the
1097                  * APIC config works fine. However, we still need to mask out
1098                  * bits in the specifier to make sure we only get bit 0 which
1099                  * is the level/edge bit (the only sense bit exposed by Apple),
1100                  * as their bit 1 means something else.
1101                  */
1102                 if (machine_is(powermac))
1103                         mask = 0x1;
1104                 *out_flags = map_mpic_senses[intspec[1] & mask];
1105         } else
1106                 *out_flags = IRQ_TYPE_NONE;
1107
1108         DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1109             intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1110
1111         return 0;
1112 }
1113
1114 /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1115 static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1116 {
1117         struct irq_chip *chip = irq_desc_get_chip(desc);
1118         struct mpic *mpic = irq_desc_get_handler_data(desc);
1119         unsigned int virq;
1120
1121         BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1122
1123         virq = mpic_get_one_irq(mpic);
1124         if (virq != NO_IRQ)
1125                 generic_handle_irq(virq);
1126
1127         chip->irq_eoi(&desc->irq_data);
1128 }
1129
1130 static struct irq_host_ops mpic_host_ops = {
1131         .match = mpic_host_match,
1132         .map = mpic_host_map,
1133         .xlate = mpic_host_xlate,
1134 };
1135
1136 /*
1137  * Exported functions
1138  */
1139
1140 struct mpic * __init mpic_alloc(struct device_node *node,
1141                                 phys_addr_t phys_addr,
1142                                 unsigned int flags,
1143                                 unsigned int isu_size,
1144                                 unsigned int irq_count,
1145                                 const char *name)
1146 {
1147         int i, psize, intvec_top;
1148         struct mpic *mpic;
1149         u32 greg_feature;
1150         const char *vers;
1151         const u32 *psrc;
1152
1153         /* Default MPIC search parameters */
1154         static const struct of_device_id __initconst mpic_device_id[] = {
1155                 { .type       = "open-pic", },
1156                 { .compatible = "open-pic", },
1157                 {},
1158         };
1159
1160         /*
1161          * If we were not passed a device-tree node, then perform the default
1162          * search for standardized a standardized OpenPIC.
1163          */
1164         if (node) {
1165                 node = of_node_get(node);
1166         } else {
1167                 node = of_find_matching_node(NULL, mpic_device_id);
1168                 if (!node)
1169                         return NULL;
1170         }
1171
1172         /* Pick the physical address from the device tree if unspecified */
1173         if (!phys_addr) {
1174                 /* Check if it is DCR-based */
1175                 if (of_get_property(node, "dcr-reg", NULL)) {
1176                         flags |= MPIC_USES_DCR;
1177                 } else {
1178                         struct resource r;
1179                         if (of_address_to_resource(node, 0, &r))
1180                                 goto err_of_node_put;
1181                         phys_addr = r.start;
1182                 }
1183         }
1184
1185         mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1186         if (mpic == NULL)
1187                 goto err_of_node_put;
1188
1189         mpic->name = name;
1190         mpic->node = node;
1191         mpic->paddr = phys_addr;
1192
1193         mpic->hc_irq = mpic_irq_chip;
1194         mpic->hc_irq.name = name;
1195         if (!(flags & MPIC_SECONDARY))
1196                 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1197 #ifdef CONFIG_MPIC_U3_HT_IRQS
1198         mpic->hc_ht_irq = mpic_irq_ht_chip;
1199         mpic->hc_ht_irq.name = name;
1200         if (!(flags & MPIC_SECONDARY))
1201                 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1202 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1203
1204 #ifdef CONFIG_SMP
1205         mpic->hc_ipi = mpic_ipi_chip;
1206         mpic->hc_ipi.name = name;
1207 #endif /* CONFIG_SMP */
1208
1209         mpic->hc_tm = mpic_tm_chip;
1210         mpic->hc_tm.name = name;
1211
1212         mpic->flags = flags;
1213         mpic->isu_size = isu_size;
1214         mpic->irq_count = irq_count;
1215         mpic->num_sources = 0; /* so far */
1216
1217         if (flags & MPIC_LARGE_VECTORS)
1218                 intvec_top = 2047;
1219         else
1220                 intvec_top = 255;
1221
1222         mpic->timer_vecs[0] = intvec_top - 12;
1223         mpic->timer_vecs[1] = intvec_top - 11;
1224         mpic->timer_vecs[2] = intvec_top - 10;
1225         mpic->timer_vecs[3] = intvec_top - 9;
1226         mpic->timer_vecs[4] = intvec_top - 8;
1227         mpic->timer_vecs[5] = intvec_top - 7;
1228         mpic->timer_vecs[6] = intvec_top - 6;
1229         mpic->timer_vecs[7] = intvec_top - 5;
1230         mpic->ipi_vecs[0]   = intvec_top - 4;
1231         mpic->ipi_vecs[1]   = intvec_top - 3;
1232         mpic->ipi_vecs[2]   = intvec_top - 2;
1233         mpic->ipi_vecs[3]   = intvec_top - 1;
1234         mpic->spurious_vec  = intvec_top;
1235
1236         /* Check for "big-endian" in device-tree */
1237         if (of_get_property(mpic->node, "big-endian", NULL) != NULL)
1238                 mpic->flags |= MPIC_BIG_ENDIAN;
1239         if (of_device_is_compatible(mpic->node, "fsl,mpic"))
1240                 mpic->flags |= MPIC_FSL;
1241
1242         /* Look for protected sources */
1243         psrc = of_get_property(mpic->node, "protected-sources", &psize);
1244         if (psrc) {
1245                 /* Allocate a bitmap with one bit per interrupt */
1246                 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1247                 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1248                 BUG_ON(mpic->protected == NULL);
1249                 for (i = 0; i < psize/sizeof(u32); i++) {
1250                         if (psrc[i] > intvec_top)
1251                                 continue;
1252                         __set_bit(psrc[i], mpic->protected);
1253                 }
1254         }
1255
1256 #ifdef CONFIG_MPIC_WEIRD
1257         mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1258 #endif
1259
1260         /* default register type */
1261         if (flags & MPIC_BIG_ENDIAN)
1262                 mpic->reg_type = mpic_access_mmio_be;
1263         else
1264                 mpic->reg_type = mpic_access_mmio_le;
1265
1266         /*
1267          * An MPIC with a "dcr-reg" property must be accessed that way, but
1268          * only if the kernel includes DCR support.
1269          */
1270 #ifdef CONFIG_PPC_DCR
1271         if (flags & MPIC_USES_DCR)
1272                 mpic->reg_type = mpic_access_dcr;
1273 #else
1274         BUG_ON(flags & MPIC_USES_DCR);
1275 #endif
1276
1277         /* Map the global registers */
1278         mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1279         mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1280
1281         /* Reset */
1282
1283         /* When using a device-node, reset requests are only honored if the MPIC
1284          * is allowed to reset.
1285          */
1286         if (of_get_property(mpic->node, "pic-no-reset", NULL))
1287                 mpic->flags |= MPIC_NO_RESET;
1288
1289         if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1290                 printk(KERN_DEBUG "mpic: Resetting\n");
1291                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1292                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1293                            | MPIC_GREG_GCONF_RESET);
1294                 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1295                        & MPIC_GREG_GCONF_RESET)
1296                         mb();
1297         }
1298
1299         /* CoreInt */
1300         if (flags & MPIC_ENABLE_COREINT)
1301                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1302                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1303                            | MPIC_GREG_GCONF_COREINT);
1304
1305         if (flags & MPIC_ENABLE_MCK)
1306                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1307                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1308                            | MPIC_GREG_GCONF_MCK);
1309
1310         /*
1311          * Read feature register.  For non-ISU MPICs, num sources as well. On
1312          * ISU MPICs, sources are counted as ISUs are added
1313          */
1314         greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1315         if (isu_size == 0) {
1316                 if (flags & MPIC_BROKEN_FRR_NIRQS)
1317                         mpic->num_sources = mpic->irq_count;
1318                 else
1319                         mpic->num_sources =
1320                                 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1321                                  >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1322         }
1323
1324         /*
1325          * The MPIC driver will crash if there are more cores than we
1326          * can initialize, so we may as well catch that problem here.
1327          */
1328         BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1329
1330         /* Map the per-CPU registers */
1331         for_each_possible_cpu(i) {
1332                 unsigned int cpu = get_hard_smp_processor_id(i);
1333
1334                 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1335                          MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1336                          0x1000);
1337         }
1338
1339         /* Initialize main ISU if none provided */
1340         if (mpic->isu_size == 0) {
1341                 mpic->isu_size = mpic->num_sources;
1342                 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1343                          MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1344         }
1345         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1346         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1347
1348         mpic->irqhost = irq_alloc_host(mpic->node, IRQ_HOST_MAP_LINEAR,
1349                                        isu_size ? isu_size : mpic->num_sources,
1350                                        &mpic_host_ops,
1351                                        flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1352
1353         /*
1354          * FIXME: The code leaks the MPIC object and mappings here; this
1355          * is very unlikely to fail but it ought to be fixed anyways.
1356          */
1357         if (mpic->irqhost == NULL)
1358                 return NULL;
1359
1360         mpic->irqhost->host_data = mpic;
1361
1362         /* Display version */
1363         switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1364         case 1:
1365                 vers = "1.0";
1366                 break;
1367         case 2:
1368                 vers = "1.2";
1369                 break;
1370         case 3:
1371                 vers = "1.3";
1372                 break;
1373         default:
1374                 vers = "<unknown>";
1375                 break;
1376         }
1377         printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1378                " max %d CPUs\n",
1379                name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1380         printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1381                mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1382
1383         mpic->next = mpics;
1384         mpics = mpic;
1385
1386         if (!(flags & MPIC_SECONDARY)) {
1387                 mpic_primary = mpic;
1388                 irq_set_default_host(mpic->irqhost);
1389         }
1390
1391         return mpic;
1392
1393 err_of_node_put:
1394         of_node_put(node);
1395         return NULL;
1396 }
1397
1398 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1399                             phys_addr_t paddr)
1400 {
1401         unsigned int isu_first = isu_num * mpic->isu_size;
1402
1403         BUG_ON(isu_num >= MPIC_MAX_ISU);
1404
1405         mpic_map(mpic,
1406                  paddr, &mpic->isus[isu_num], 0,
1407                  MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1408
1409         if ((isu_first + mpic->isu_size) > mpic->num_sources)
1410                 mpic->num_sources = isu_first + mpic->isu_size;
1411 }
1412
1413 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1414 {
1415         mpic->senses = senses;
1416         mpic->senses_count = count;
1417 }
1418
1419 void __init mpic_init(struct mpic *mpic)
1420 {
1421         int i, cpu;
1422
1423         BUG_ON(mpic->num_sources == 0);
1424
1425         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1426
1427         /* Set current processor priority to max */
1428         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1429
1430         /* Initialize timers to our reserved vectors and mask them for now */
1431         for (i = 0; i < 4; i++) {
1432                 mpic_write(mpic->tmregs,
1433                            i * MPIC_INFO(TIMER_STRIDE) +
1434                            MPIC_INFO(TIMER_DESTINATION),
1435                            1 << hard_smp_processor_id());
1436                 mpic_write(mpic->tmregs,
1437                            i * MPIC_INFO(TIMER_STRIDE) +
1438                            MPIC_INFO(TIMER_VECTOR_PRI),
1439                            MPIC_VECPRI_MASK |
1440                            (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1441                            (mpic->timer_vecs[0] + i));
1442         }
1443
1444         /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1445         mpic_test_broken_ipi(mpic);
1446         for (i = 0; i < 4; i++) {
1447                 mpic_ipi_write(i,
1448                                MPIC_VECPRI_MASK |
1449                                (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1450                                (mpic->ipi_vecs[0] + i));
1451         }
1452
1453         /* Initialize interrupt sources */
1454         if (mpic->irq_count == 0)
1455                 mpic->irq_count = mpic->num_sources;
1456
1457         /* Do the HT PIC fixups on U3 broken mpic */
1458         DBG("MPIC flags: %x\n", mpic->flags);
1459         if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1460                 mpic_scan_ht_pics(mpic);
1461                 mpic_u3msi_init(mpic);
1462         }
1463
1464         mpic_pasemi_msi_init(mpic);
1465
1466         cpu = mpic_processor_id(mpic);
1467
1468         if (!(mpic->flags & MPIC_NO_RESET)) {
1469                 for (i = 0; i < mpic->num_sources; i++) {
1470                         /* start with vector = source number, and masked */
1471                         u32 vecpri = MPIC_VECPRI_MASK | i |
1472                                 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1473
1474                         /* check if protected */
1475                         if (mpic->protected && test_bit(i, mpic->protected))
1476                                 continue;
1477                         /* init hw */
1478                         mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1479                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1480                 }
1481         }
1482
1483         /* Init spurious vector */
1484         mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1485
1486         /* Disable 8259 passthrough, if supported */
1487         if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1488                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1489                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1490                            | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1491
1492         if (mpic->flags & MPIC_NO_BIAS)
1493                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1494                         mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1495                         | MPIC_GREG_GCONF_NO_BIAS);
1496
1497         /* Set current processor priority to 0 */
1498         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1499
1500 #ifdef CONFIG_PM
1501         /* allocate memory to save mpic state */
1502         mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1503                                   GFP_KERNEL);
1504         BUG_ON(mpic->save_data == NULL);
1505 #endif
1506
1507         /* Check if this MPIC is chained from a parent interrupt controller */
1508         if (mpic->flags & MPIC_SECONDARY) {
1509                 int virq = irq_of_parse_and_map(mpic->node, 0);
1510                 if (virq != NO_IRQ) {
1511                         printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1512                                         mpic->node->full_name, virq);
1513                         irq_set_handler_data(virq, mpic);
1514                         irq_set_chained_handler(virq, &mpic_cascade);
1515                 }
1516         }
1517 }
1518
1519 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1520 {
1521         u32 v;
1522
1523         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1524         v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1525         v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1526         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1527 }
1528
1529 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1530 {
1531         unsigned long flags;
1532         u32 v;
1533
1534         raw_spin_lock_irqsave(&mpic_lock, flags);
1535         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1536         if (enable)
1537                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1538         else
1539                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1540         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1541         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1542 }
1543
1544 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1545 {
1546         struct mpic *mpic = mpic_find(irq);
1547         unsigned int src = virq_to_hw(irq);
1548         unsigned long flags;
1549         u32 reg;
1550
1551         if (!mpic)
1552                 return;
1553
1554         raw_spin_lock_irqsave(&mpic_lock, flags);
1555         if (mpic_is_ipi(mpic, irq)) {
1556                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1557                         ~MPIC_VECPRI_PRIORITY_MASK;
1558                 mpic_ipi_write(src - mpic->ipi_vecs[0],
1559                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1560         } else if (mpic_is_tm(mpic, irq)) {
1561                 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1562                         ~MPIC_VECPRI_PRIORITY_MASK;
1563                 mpic_tm_write(src - mpic->timer_vecs[0],
1564                               reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1565         } else {
1566                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1567                         & ~MPIC_VECPRI_PRIORITY_MASK;
1568                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1569                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1570         }
1571         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1572 }
1573
1574 void mpic_setup_this_cpu(void)
1575 {
1576 #ifdef CONFIG_SMP
1577         struct mpic *mpic = mpic_primary;
1578         unsigned long flags;
1579         u32 msk = 1 << hard_smp_processor_id();
1580         unsigned int i;
1581
1582         BUG_ON(mpic == NULL);
1583
1584         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1585
1586         raw_spin_lock_irqsave(&mpic_lock, flags);
1587
1588         /* let the mpic know we want intrs. default affinity is 0xffffffff
1589          * until changed via /proc. That's how it's done on x86. If we want
1590          * it differently, then we should make sure we also change the default
1591          * values of irq_desc[].affinity in irq.c.
1592          */
1593         if (distribute_irqs) {
1594                 for (i = 0; i < mpic->num_sources ; i++)
1595                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1596                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1597         }
1598
1599         /* Set current processor priority to 0 */
1600         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1601
1602         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1603 #endif /* CONFIG_SMP */
1604 }
1605
1606 int mpic_cpu_get_priority(void)
1607 {
1608         struct mpic *mpic = mpic_primary;
1609
1610         return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1611 }
1612
1613 void mpic_cpu_set_priority(int prio)
1614 {
1615         struct mpic *mpic = mpic_primary;
1616
1617         prio &= MPIC_CPU_TASKPRI_MASK;
1618         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1619 }
1620
1621 void mpic_teardown_this_cpu(int secondary)
1622 {
1623         struct mpic *mpic = mpic_primary;
1624         unsigned long flags;
1625         u32 msk = 1 << hard_smp_processor_id();
1626         unsigned int i;
1627
1628         BUG_ON(mpic == NULL);
1629
1630         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1631         raw_spin_lock_irqsave(&mpic_lock, flags);
1632
1633         /* let the mpic know we don't want intrs.  */
1634         for (i = 0; i < mpic->num_sources ; i++)
1635                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1636                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1637
1638         /* Set current processor priority to max */
1639         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1640         /* We need to EOI the IPI since not all platforms reset the MPIC
1641          * on boot and new interrupts wouldn't get delivered otherwise.
1642          */
1643         mpic_eoi(mpic);
1644
1645         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1646 }
1647
1648
1649 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1650 {
1651         u32 src;
1652
1653         src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1654 #ifdef DEBUG_LOW
1655         DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1656 #endif
1657         if (unlikely(src == mpic->spurious_vec)) {
1658                 if (mpic->flags & MPIC_SPV_EOI)
1659                         mpic_eoi(mpic);
1660                 return NO_IRQ;
1661         }
1662         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1663                 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1664                                    mpic->name, (int)src);
1665                 mpic_eoi(mpic);
1666                 return NO_IRQ;
1667         }
1668
1669         return irq_linear_revmap(mpic->irqhost, src);
1670 }
1671
1672 unsigned int mpic_get_one_irq(struct mpic *mpic)
1673 {
1674         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1675 }
1676
1677 unsigned int mpic_get_irq(void)
1678 {
1679         struct mpic *mpic = mpic_primary;
1680
1681         BUG_ON(mpic == NULL);
1682
1683         return mpic_get_one_irq(mpic);
1684 }
1685
1686 unsigned int mpic_get_coreint_irq(void)
1687 {
1688 #ifdef CONFIG_BOOKE
1689         struct mpic *mpic = mpic_primary;
1690         u32 src;
1691
1692         BUG_ON(mpic == NULL);
1693
1694         src = mfspr(SPRN_EPR);
1695
1696         if (unlikely(src == mpic->spurious_vec)) {
1697                 if (mpic->flags & MPIC_SPV_EOI)
1698                         mpic_eoi(mpic);
1699                 return NO_IRQ;
1700         }
1701         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1702                 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1703                                    mpic->name, (int)src);
1704                 return NO_IRQ;
1705         }
1706
1707         return irq_linear_revmap(mpic->irqhost, src);
1708 #else
1709         return NO_IRQ;
1710 #endif
1711 }
1712
1713 unsigned int mpic_get_mcirq(void)
1714 {
1715         struct mpic *mpic = mpic_primary;
1716
1717         BUG_ON(mpic == NULL);
1718
1719         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1720 }
1721
1722 #ifdef CONFIG_SMP
1723 void mpic_request_ipis(void)
1724 {
1725         struct mpic *mpic = mpic_primary;
1726         int i;
1727         BUG_ON(mpic == NULL);
1728
1729         printk(KERN_INFO "mpic: requesting IPIs...\n");
1730
1731         for (i = 0; i < 4; i++) {
1732                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1733                                                        mpic->ipi_vecs[0] + i);
1734                 if (vipi == NO_IRQ) {
1735                         printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1736                         continue;
1737                 }
1738                 smp_request_message_ipi(vipi, i);
1739         }
1740 }
1741
1742 void smp_mpic_message_pass(int cpu, int msg)
1743 {
1744         struct mpic *mpic = mpic_primary;
1745         u32 physmask;
1746
1747         BUG_ON(mpic == NULL);
1748
1749         /* make sure we're sending something that translates to an IPI */
1750         if ((unsigned int)msg > 3) {
1751                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1752                        smp_processor_id(), msg);
1753                 return;
1754         }
1755
1756 #ifdef DEBUG_IPI
1757         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1758 #endif
1759
1760         physmask = 1 << get_hard_smp_processor_id(cpu);
1761
1762         mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1763                        msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1764 }
1765
1766 int __init smp_mpic_probe(void)
1767 {
1768         int nr_cpus;
1769
1770         DBG("smp_mpic_probe()...\n");
1771
1772         nr_cpus = cpumask_weight(cpu_possible_mask);
1773
1774         DBG("nr_cpus: %d\n", nr_cpus);
1775
1776         if (nr_cpus > 1)
1777                 mpic_request_ipis();
1778
1779         return nr_cpus;
1780 }
1781
1782 void __devinit smp_mpic_setup_cpu(int cpu)
1783 {
1784         mpic_setup_this_cpu();
1785 }
1786
1787 void mpic_reset_core(int cpu)
1788 {
1789         struct mpic *mpic = mpic_primary;
1790         u32 pir;
1791         int cpuid = get_hard_smp_processor_id(cpu);
1792         int i;
1793
1794         /* Set target bit for core reset */
1795         pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1796         pir |= (1 << cpuid);
1797         mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1798         mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1799
1800         /* Restore target bit after reset complete */
1801         pir &= ~(1 << cpuid);
1802         mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1803         mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1804
1805         /* Perform 15 EOI on each reset core to clear pending interrupts.
1806          * This is required for FSL CoreNet based devices */
1807         if (mpic->flags & MPIC_FSL) {
1808                 for (i = 0; i < 15; i++) {
1809                         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1810                                       MPIC_CPU_EOI, 0);
1811                 }
1812         }
1813 }
1814 #endif /* CONFIG_SMP */
1815
1816 #ifdef CONFIG_PM
1817 static void mpic_suspend_one(struct mpic *mpic)
1818 {
1819         int i;
1820
1821         for (i = 0; i < mpic->num_sources; i++) {
1822                 mpic->save_data[i].vecprio =
1823                         mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1824                 mpic->save_data[i].dest =
1825                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1826         }
1827 }
1828
1829 static int mpic_suspend(void)
1830 {
1831         struct mpic *mpic = mpics;
1832
1833         while (mpic) {
1834                 mpic_suspend_one(mpic);
1835                 mpic = mpic->next;
1836         }
1837
1838         return 0;
1839 }
1840
1841 static void mpic_resume_one(struct mpic *mpic)
1842 {
1843         int i;
1844
1845         for (i = 0; i < mpic->num_sources; i++) {
1846                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1847                                mpic->save_data[i].vecprio);
1848                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1849                                mpic->save_data[i].dest);
1850
1851 #ifdef CONFIG_MPIC_U3_HT_IRQS
1852         if (mpic->fixups) {
1853                 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1854
1855                 if (fixup->base) {
1856                         /* we use the lowest bit in an inverted meaning */
1857                         if ((mpic->save_data[i].fixup_data & 1) == 0)
1858                                 continue;
1859
1860                         /* Enable and configure */
1861                         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1862
1863                         writel(mpic->save_data[i].fixup_data & ~1,
1864                                fixup->base + 4);
1865                 }
1866         }
1867 #endif
1868         } /* end for loop */
1869 }
1870
1871 static void mpic_resume(void)
1872 {
1873         struct mpic *mpic = mpics;
1874
1875         while (mpic) {
1876                 mpic_resume_one(mpic);
1877                 mpic = mpic->next;
1878         }
1879 }
1880
1881 static struct syscore_ops mpic_syscore_ops = {
1882         .resume = mpic_resume,
1883         .suspend = mpic_suspend,
1884 };
1885
1886 static int mpic_init_sys(void)
1887 {
1888         register_syscore_ops(&mpic_syscore_ops);
1889         return 0;
1890 }
1891
1892 device_initcall(mpic_init_sys);
1893 #endif