arch/ppc/syslib/open_pic.c

   1 /*
   2  *  arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive
   8  *  for more details.
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/errno.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/signal.h>
  22 #include <asm/io.h>
  23 #include <asm/irq.h>
  24 #include <asm/sections.h>
  25 #include <asm/open_pic.h>
  26 #include <asm/i8259.h>
  27
  28 #include "open_pic_defs.h"
  29
  30 #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)
  31 #define OPENPIC_BIG_ENDIAN
  32 #endif
  33
  34 void __iomem *OpenPIC_Addr;
  35 static volatile struct OpenPIC __iomem *OpenPIC = NULL;
  36
  37 /*
  38  * We define OpenPIC_InitSenses table thusly:
  39  * bit 0x1: sense, 0 for edge and 1 for level.
  40  * bit 0x2: polarity, 0 for negative, 1 for positive.
  41  */
  42 u_int OpenPIC_NumInitSenses __initdata = 0;
  43 u_char *OpenPIC_InitSenses __initdata = NULL;
  44 extern int use_of_interrupt_tree;
  45
  46 static u_int NumProcessors;
  47 static u_int NumSources;
  48 static int open_pic_irq_offset;
  49 static volatile OpenPIC_Source __iomem *ISR[NR_IRQS];
  50 static int openpic_cascade_irq = -1;
  51 static int (*openpic_cascade_fn)(struct pt_regs *);
  52
  53 /* Global Operations */
  54 static void openpic_disable_8259_pass_through(void);
  55 static void openpic_set_spurious(u_int vector);
  56
  57 #ifdef CONFIG_SMP
  58 /* Interprocessor Interrupts */
  59 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
  60 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
  61 #endif
  62
  63 /* Timer Interrupts */
  64 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
  65 static void openpic_maptimer(u_int timer, cpumask_t cpumask);
  66
  67 /* Interrupt Sources */
  68 static void openpic_enable_irq(u_int irq);
  69 static void openpic_disable_irq(u_int irq);
  70 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  71                             int is_level);
  72 static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask);
  73
  74 /*
  75  * These functions are not used but the code is kept here
  76  * for completeness and future reference.
  77  */
  78 #ifdef notused
  79 static void openpic_enable_8259_pass_through(void);
  80 static u_int openpic_get_spurious(void);
  81 static void openpic_set_sense(u_int irq, int sense);
  82 #endif /* notused */
  83
  84 /*
  85  * Description of the openpic for the higher-level irq code
  86  */
  87 static void openpic_end_irq(unsigned int irq_nr);
  88 static void openpic_ack_irq(unsigned int irq_nr);
  89 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
  90
  91 struct hw_interrupt_type open_pic = {
  92         .typename       = " OpenPIC  ",
  93         .enable         = openpic_enable_irq,
  94         .disable        = openpic_disable_irq,
  95         .ack            = openpic_ack_irq,
  96         .end            = openpic_end_irq,
  97         .set_affinity   = openpic_set_affinity,
  98 };
  99
 100 #ifdef CONFIG_SMP
 101 static void openpic_end_ipi(unsigned int irq_nr);
 102 static void openpic_ack_ipi(unsigned int irq_nr);
 103 static void openpic_enable_ipi(unsigned int irq_nr);
 104 static void openpic_disable_ipi(unsigned int irq_nr);
 105
 106 struct hw_interrupt_type open_pic_ipi = {
 107         .typename       = " OpenPIC  ",
 108         .enable         = openpic_enable_ipi,
 109         .disable        = openpic_disable_ipi,
 110         .ack            = openpic_ack_ipi,
 111         .end            = openpic_end_ipi,
 112 };
 113 #endif /* CONFIG_SMP */
 114
 115 /*
 116  *  Accesses to the current processor's openpic registers
 117  */
 118 #ifdef CONFIG_SMP
 119 #define THIS_CPU                Processor[cpu]
 120 #define DECL_THIS_CPU           int cpu = smp_hw_index[smp_processor_id()]
 121 #define CHECK_THIS_CPU          check_arg_cpu(cpu)
 122 #else
 123 #define THIS_CPU                Processor[0]
 124 #define DECL_THIS_CPU
 125 #define CHECK_THIS_CPU
 126 #endif /* CONFIG_SMP */
 127
 128 #if 1
 129 #define check_arg_ipi(ipi) \
 130     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
 131         printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
 132 #define check_arg_timer(timer) \
 133     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
 134         printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
 135 #define check_arg_vec(vec) \
 136     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
 137         printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
 138 #define check_arg_pri(pri) \
 139     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
 140         printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
 141 /*
 142  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
 143  * data has probably been corrupted and we're going to panic or deadlock later
 144  * anyway --Troy
 145  */
 146 #define check_arg_irq(irq) \
 147     if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
 148         || ISR[irq - open_pic_irq_offset] == 0) { \
 149       printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
 150       dump_stack(); }
 151 #define check_arg_cpu(cpu) \
 152     if (cpu < 0 || cpu >= NumProcessors){ \
 153         printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
 154         dump_stack(); }
 155 #else
 156 #define check_arg_ipi(ipi)      do {} while (0)
 157 #define check_arg_timer(timer)  do {} while (0)
 158 #define check_arg_vec(vec)      do {} while (0)
 159 #define check_arg_pri(pri)      do {} while (0)
 160 #define check_arg_irq(irq)      do {} while (0)
 161 #define check_arg_cpu(cpu)      do {} while (0)
 162 #endif
 163
 164 u_int openpic_read(volatile u_int __iomem *addr)
 165 {
 166         u_int val;
 167
 168 #ifdef OPENPIC_BIG_ENDIAN
 169         val = in_be32(addr);
 170 #else
 171         val = in_le32(addr);
 172 #endif
 173         return val;
 174 }
 175
 176 static inline void openpic_write(volatile u_int __iomem *addr, u_int val)
 177 {
 178 #ifdef OPENPIC_BIG_ENDIAN
 179         out_be32(addr, val);
 180 #else
 181         out_le32(addr, val);
 182 #endif
 183 }
 184
 185 static inline u_int openpic_readfield(volatile u_int __iomem *addr, u_int mask)
 186 {
 187         u_int val = openpic_read(addr);
 188         return val & mask;
 189 }
 190
 191 inline void openpic_writefield(volatile u_int __iomem *addr, u_int mask,
 192                                u_int field)
 193 {
 194         u_int val = openpic_read(addr);
 195         openpic_write(addr, (val & ~mask) | (field & mask));
 196 }
 197
 198 static inline void openpic_clearfield(volatile u_int __iomem *addr, u_int mask)
 199 {
 200         openpic_writefield(addr, mask, 0);
 201 }
 202
 203 static inline void openpic_setfield(volatile u_int __iomem *addr, u_int mask)
 204 {
 205         openpic_writefield(addr, mask, mask);
 206 }
 207
 208 static void openpic_safe_writefield(volatile u_int __iomem *addr, u_int mask,
 209                                     u_int field)
 210 {
 211         openpic_setfield(addr, OPENPIC_MASK);
 212         while (openpic_read(addr) & OPENPIC_ACTIVITY);
 213         openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 214 }
 215
 216 #ifdef CONFIG_SMP
 217 /* yes this is right ... bug, feature, you decide! -- tgall */
 218 u_int openpic_read_IPI(volatile u_int __iomem * addr)
 219 {
 220          u_int val = 0;
 221 #if defined(OPENPIC_BIG_ENDIAN) || defined(CONFIG_POWER3)
 222         val = in_be32(addr);
 223 #else
 224         val = in_le32(addr);
 225 #endif
 226         return val;
 227 }
 228
 229 /* because of the power3 be / le above, this is needed */
 230 inline void openpic_writefield_IPI(volatile u_int __iomem * addr, u_int mask, u_int field)
 231 {
 232         u_int  val = openpic_read_IPI(addr);
 233         openpic_write(addr, (val & ~mask) | (field & mask));
 234 }
 235
 236 static inline void openpic_clearfield_IPI(volatile u_int __iomem *addr, u_int mask)
 237 {
 238         openpic_writefield_IPI(addr, mask, 0);
 239 }
 240
 241 static inline void openpic_setfield_IPI(volatile u_int __iomem *addr, u_int mask)
 242 {
 243         openpic_writefield_IPI(addr, mask, mask);
 244 }
 245
 246 static void openpic_safe_writefield_IPI(volatile u_int __iomem *addr, u_int mask, u_int field)
 247 {
 248         openpic_setfield_IPI(addr, OPENPIC_MASK);
 249
 250         /* wait until it's not in use */
 251         /* BenH: Is this code really enough ? I would rather check the result
 252          *       and eventually retry ...
 253          */
 254         while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
 255
 256         openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 257 }
 258 #endif /* CONFIG_SMP */
 259
 260 #ifdef CONFIG_EPIC_SERIAL_MODE
 261 /* On platforms that may use EPIC serial mode, the default is enabled. */
 262 int epic_serial_mode = 1;
 263
 264 static void __init openpic_eicr_set_clk(u_int clkval)
 265 {
 266         openpic_writefield(&OpenPIC->Global.Global_Configuration1,
 267                         OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
 268 }
 269
 270 static void __init openpic_enable_sie(void)
 271 {
 272         openpic_setfield(&OpenPIC->Global.Global_Configuration1,
 273                         OPENPIC_EICR_SIE);
 274 }
 275 #endif
 276
 277 #if defined(CONFIG_EPIC_SERIAL_MODE)
 278 static void openpic_reset(void)
 279 {
 280         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 281                          OPENPIC_CONFIG_RESET);
 282         while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
 283                                  OPENPIC_CONFIG_RESET))
 284                 mb();
 285 }
 286 #endif
 287
 288 void __init openpic_set_sources(int first_irq, int num_irqs, void __iomem *first_ISR)
 289 {
 290         volatile OpenPIC_Source __iomem *src = first_ISR;
 291         int i, last_irq;
 292
 293         last_irq = first_irq + num_irqs;
 294         if (last_irq > NumSources)
 295                 NumSources = last_irq;
 296         if (src == 0)
 297                 src = &((struct OpenPIC __iomem *)OpenPIC_Addr)->Source[first_irq];
 298         for (i = first_irq; i < last_irq; ++i, ++src)
 299                 ISR[i] = src;
 300 }
 301
 302 /*
 303  * The `offset' parameter defines where the interrupts handled by the
 304  * OpenPIC start in the space of interrupt numbers that the kernel knows
 305  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
 306  * kernel's interrupt numbering scheme.
 307  * We assume there is only one OpenPIC.
 308  */
 309 void __init openpic_init(int offset)
 310 {
 311         u_int t, i;
 312         u_int timerfreq;
 313         const char *version;
 314
 315         if (!OpenPIC_Addr) {
 316                 printk("No OpenPIC found !\n");
 317                 return;
 318         }
 319         OpenPIC = (volatile struct OpenPIC __iomem *)OpenPIC_Addr;
 320
 321 #ifdef CONFIG_EPIC_SERIAL_MODE
 322         /* Have to start from ground zero.
 323         */
 324         openpic_reset();
 325 #endif
 326
 327         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
 328
 329         t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
 330         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
 331         case 1:
 332                 version = "1.0";
 333                 break;
 334         case 2:
 335                 version = "1.2";
 336                 break;
 337         case 3:
 338                 version = "1.3";
 339                 break;
 340         default:
 341                 version = "?";
 342                 break;
 343         }
 344         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
 345                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
 346         if (NumSources == 0)
 347                 openpic_set_sources(0,
 348                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
 349                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
 350                                     NULL);
 351         printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
 352                version, NumProcessors, NumSources, OpenPIC);
 353         timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
 354         if (timerfreq)
 355                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
 356                        timerfreq / 1000000, timerfreq % 1000000);
 357
 358         open_pic_irq_offset = offset;
 359
 360         /* Initialize timer interrupts */
 361         if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
 362         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
 363                 /* Disabled, Priority 0 */
 364                 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
 365                 /* No processor */
 366                 openpic_maptimer(i, CPU_MASK_NONE);
 367         }
 368
 369 #ifdef CONFIG_SMP
 370         /* Initialize IPI interrupts */
 371         if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
 372         for (i = 0; i < OPENPIC_NUM_IPI; i++) {
 373                 /* Disabled, increased priorities 10..13 */
 374                 openpic_initipi(i, OPENPIC_PRIORITY_IPI_BASE+i,
 375                                 OPENPIC_VEC_IPI+i+offset);
 376                 /* IPIs are per-CPU */
 377                 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
 378                 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
 379         }
 380 #endif
 381
 382         /* Initialize external interrupts */
 383         if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
 384
 385         openpic_set_priority(0xf);
 386
 387         /* Init all external sources, including possibly the cascade. */
 388         for (i = 0; i < NumSources; i++) {
 389                 int sense;
 390
 391                 if (ISR[i] == 0)
 392                         continue;
 393
 394                 /* the bootloader may have left it enabled (bad !) */
 395                 openpic_disable_irq(i+offset);
 396
 397                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
 398                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
 399
 400                 if (sense & IRQ_SENSE_MASK)
 401                         irq_desc[i+offset].status = IRQ_LEVEL;
 402
 403                 /* Enabled, Default priority */
 404                 openpic_initirq(i, OPENPIC_PRIORITY_DEFAULT, i+offset,
 405                                 (sense & IRQ_POLARITY_MASK),
 406                                 (sense & IRQ_SENSE_MASK));
 407                 /* Processor 0 */
 408                 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
 409         }
 410
 411         /* Init descriptors */
 412         for (i = offset; i < NumSources + offset; i++)
 413                 irq_desc[i].handler = &open_pic;
 414
 415         /* Initialize the spurious interrupt */
 416         if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
 417         openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
 418         openpic_disable_8259_pass_through();
 419 #ifdef CONFIG_EPIC_SERIAL_MODE
 420         if (epic_serial_mode) {
 421                 openpic_eicr_set_clk(7);        /* Slowest value until we know better */
 422                 openpic_enable_sie();
 423         }
 424 #endif
 425         openpic_set_priority(0);
 426
 427         if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
 428 }
 429
 430 #ifdef notused
 431 static void openpic_enable_8259_pass_through(void)
 432 {
 433         openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
 434                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 435 }
 436 #endif /* notused */
 437
 438 static void openpic_disable_8259_pass_through(void)
 439 {
 440         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 441                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 442 }
 443
 444 /*
 445  *  Find out the current interrupt
 446  */
 447 u_int openpic_irq(void)
 448 {
 449         u_int vec;
 450         DECL_THIS_CPU;
 451
 452         CHECK_THIS_CPU;
 453         vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
 454                                 OPENPIC_VECTOR_MASK);
 455         return vec;
 456 }
 457
 458 void openpic_eoi(void)
 459 {
 460         DECL_THIS_CPU;
 461
 462         CHECK_THIS_CPU;
 463         openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
 464         /* Handle PCI write posting */
 465         (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
 466 }
 467
 468 u_int openpic_get_priority(void)
 469 {
 470         DECL_THIS_CPU;
 471
 472         CHECK_THIS_CPU;
 473         return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 474                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
 475 }
 476
 477 void openpic_set_priority(u_int pri)
 478 {
 479         DECL_THIS_CPU;
 480
 481         CHECK_THIS_CPU;
 482         check_arg_pri(pri);
 483         openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 484                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
 485 }
 486
 487 /*
 488  *  Get/set the spurious vector
 489  */
 490 #ifdef notused
 491 static u_int openpic_get_spurious(void)
 492 {
 493         return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
 494                                  OPENPIC_VECTOR_MASK);
 495 }
 496 #endif /* notused */
 497
 498 static void openpic_set_spurious(u_int vec)
 499 {
 500         check_arg_vec(vec);
 501         openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
 502                            vec);
 503 }
 504
 505 #ifdef CONFIG_SMP
 506 /*
 507  * Convert a cpu mask from logical to physical cpu numbers.
 508  */
 509 static inline cpumask_t physmask(cpumask_t cpumask)
 510 {
 511         int i;
 512         cpumask_t mask = CPU_MASK_NONE;
 513
 514         cpus_and(cpumask, cpu_online_map, cpumask);
 515
 516         for (i = 0; i < NR_CPUS; i++)
 517                 if (cpu_isset(i, cpumask))
 518                         cpu_set(smp_hw_index[i], mask);
 519
 520         return mask;
 521 }
 522 #else
 523 #define physmask(cpumask)       (cpumask)
 524 #endif
 525
 526 void openpic_reset_processor_phys(u_int mask)
 527 {
 528         openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
 529 }
 530
 531 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
 532 static DEFINE_SPINLOCK(openpic_setup_lock);
 533 #endif
 534
 535 #ifdef CONFIG_SMP
 536 /*
 537  *  Initialize an interprocessor interrupt (and disable it)
 538  *
 539  *  ipi: OpenPIC interprocessor interrupt number
 540  *  pri: interrupt source priority
 541  *  vec: the vector it will produce
 542  */
 543 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
 544 {
 545         check_arg_ipi(ipi);
 546         check_arg_pri(pri);
 547         check_arg_vec(vec);
 548         openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
 549                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 550                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 551 }
 552
 553 /*
 554  *  Send an IPI to one or more CPUs
 555  *
 556  *  Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
 557  *  and not a system-wide interrupt number
 558  */
 559 void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
 560 {
 561         DECL_THIS_CPU;
 562
 563         CHECK_THIS_CPU;
 564         check_arg_ipi(ipi);
 565         openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
 566                       cpus_addr(physmask(cpumask))[0]);
 567 }
 568
 569 void openpic_request_IPIs(void)
 570 {
 571         int i;
 572
 573         /*
 574          * Make sure this matches what is defined in smp.c for
 575          * smp_message_{pass|recv}() or what shows up in
 576          * /proc/interrupts will be wrong!!! --Troy */
 577
 578         if (OpenPIC == NULL)
 579                 return;
 580
 581         /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
 582         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
 583                     openpic_ipi_action, SA_INTERRUPT,
 584                     "IPI0 (call function)", NULL);
 585         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
 586                     openpic_ipi_action, SA_INTERRUPT,
 587                     "IPI1 (reschedule)", NULL);
 588         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
 589                     openpic_ipi_action, SA_INTERRUPT,
 590                     "IPI2 (invalidate tlb)", NULL);
 591         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
 592                     openpic_ipi_action, SA_INTERRUPT,
 593                     "IPI3 (xmon break)", NULL);
 594
 595         for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
 596                 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
 597 }
 598
 599 /*
 600  * Do per-cpu setup for SMP systems.
 601  *
 602  * Get IPI's working and start taking interrupts.
 603  *   -- Cort
 604  */
 605
 606 void __devinit do_openpic_setup_cpu(void)
 607 {
 608 #ifdef CONFIG_IRQ_ALL_CPUS
 609         int i;
 610         cpumask_t msk = CPU_MASK_NONE;
 611 #endif
 612         spin_lock(&openpic_setup_lock);
 613
 614 #ifdef CONFIG_IRQ_ALL_CPUS
 615         cpu_set(smp_hw_index[smp_processor_id()], msk);
 616
 617         /* let the openpic know we want intrs. default affinity
 618          * is 0xffffffff until changed via /proc
 619          * That's how it's done on x86. If we want it differently, then
 620          * we should make sure we also change the default values of irq_affinity
 621          * in irq.c.
 622          */
 623         for (i = 0; i < NumSources; i++)
 624                 openpic_mapirq(i, msk, CPU_MASK_ALL);
 625 #endif /* CONFIG_IRQ_ALL_CPUS */
 626         openpic_set_priority(0);
 627
 628         spin_unlock(&openpic_setup_lock);
 629 }
 630 #endif /* CONFIG_SMP */
 631
 632 /*
 633  *  Initialize a timer interrupt (and disable it)
 634  *
 635  *  timer: OpenPIC timer number
 636  *  pri: interrupt source priority
 637  *  vec: the vector it will produce
 638  */
 639 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
 640 {
 641         check_arg_timer(timer);
 642         check_arg_pri(pri);
 643         check_arg_vec(vec);
 644         openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
 645                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 646                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 647 }
 648
 649 /*
 650  *  Map a timer interrupt to one or more CPUs
 651  */
 652 static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
 653 {
 654         cpumask_t phys = physmask(cpumask);
 655         check_arg_timer(timer);
 656         openpic_write(&OpenPIC->Global.Timer[timer].Destination,
 657                       cpus_addr(phys)[0]);
 658 }
 659
 660 /*
 661  * Change the priority of an interrupt
 662  */
 663 void __init
 664 openpic_set_irq_priority(u_int irq, u_int pri)
 665 {
 666         check_arg_irq(irq);
 667         openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
 668                                 OPENPIC_PRIORITY_MASK,
 669                                 pri << OPENPIC_PRIORITY_SHIFT);
 670 }
 671
 672 /*
 673  * Initalize the interrupt source which will generate an NMI.
 674  * This raises the interrupt's priority from 8 to 9.
 675  *
 676  * irq: The logical IRQ which generates an NMI.
 677  */
 678 void __init
 679 openpic_init_nmi_irq(u_int irq)
 680 {
 681         check_arg_irq(irq);
 682         openpic_set_irq_priority(irq, OPENPIC_PRIORITY_NMI);
 683 }
 684
 685 /*
 686  *
 687  * All functions below take an offset'ed irq argument
 688  *
 689  */
 690
 691 /*
 692  * Hookup a cascade to the OpenPIC.
 693  */
 694
 695 static struct irqaction openpic_cascade_irqaction = {
 696         .handler = no_action,
 697         .flags = SA_INTERRUPT,
 698         .mask = CPU_MASK_NONE,
 699 };
 700
 701 void __init
 702 openpic_hookup_cascade(u_int irq, char *name,
 703         int (*cascade_fn)(struct pt_regs *))
 704 {
 705         openpic_cascade_irq = irq;
 706         openpic_cascade_fn = cascade_fn;
 707
 708         if (setup_irq(irq, &openpic_cascade_irqaction))
 709                 printk("Unable to get OpenPIC IRQ %d for cascade\n",
 710                                 irq - open_pic_irq_offset);
 711 }
 712
 713 /*
 714  *  Enable/disable an external interrupt source
 715  *
 716  *  Externally called, irq is an offseted system-wide interrupt number
 717  */
 718 static void openpic_enable_irq(u_int irq)
 719 {
 720         volatile u_int __iomem *vpp;
 721
 722         check_arg_irq(irq);
 723         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 724         openpic_clearfield(vpp, OPENPIC_MASK);
 725         /* make sure mask gets to controller before we return to user */
 726         do {
 727                 mb(); /* sync is probably useless here */
 728         } while (openpic_readfield(vpp, OPENPIC_MASK));
 729 }
 730
 731 static void openpic_disable_irq(u_int irq)
 732 {
 733         volatile u_int __iomem *vpp;
 734         u32 vp;
 735
 736         check_arg_irq(irq);
 737         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 738         openpic_setfield(vpp, OPENPIC_MASK);
 739         /* make sure mask gets to controller before we return to user */
 740         do {
 741                 mb();  /* sync is probably useless here */
 742                 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
 743         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
 744 }
 745
 746 #ifdef CONFIG_SMP
 747 /*
 748  *  Enable/disable an IPI interrupt source
 749  *
 750  *  Externally called, irq is an offseted system-wide interrupt number
 751  */
 752 void openpic_enable_ipi(u_int irq)
 753 {
 754         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 755         check_arg_ipi(irq);
 756         openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 757
 758 }
 759
 760 void openpic_disable_ipi(u_int irq)
 761 {
 762         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 763         check_arg_ipi(irq);
 764         openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 765 }
 766 #endif
 767
 768 /*
 769  *  Initialize an interrupt source (and disable it!)
 770  *
 771  *  irq: OpenPIC interrupt number
 772  *  pri: interrupt source priority
 773  *  vec: the vector it will produce
 774  *  pol: polarity (1 for positive, 0 for negative)
 775  *  sense: 1 for level, 0 for edge
 776  */
 777 static void __init
 778 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
 779 {
 780         openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 781                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 782                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
 783                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
 784                                 (pol ? OPENPIC_POLARITY_POSITIVE :
 785                                         OPENPIC_POLARITY_NEGATIVE) |
 786                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
 787 }
 788
 789 /*
 790  *  Map an interrupt source to one or more CPUs
 791  */
 792 static void openpic_mapirq(u_int irq, cpumask_t physmask, cpumask_t keepmask)
 793 {
 794         if (ISR[irq] == 0)
 795                 return;
 796         if (!cpus_empty(keepmask)) {
 797                 cpumask_t irqdest = { .bits[0] = openpic_read(&ISR[irq]->Destination) };
 798                 cpus_and(irqdest, irqdest, keepmask);
 799                 cpus_or(physmask, physmask, irqdest);
 800         }
 801         openpic_write(&ISR[irq]->Destination, cpus_addr(physmask)[0]);
 802 }
 803
 804 #ifdef notused
 805 /*
 806  *  Set the sense for an interrupt source (and disable it!)
 807  *
 808  *  sense: 1 for level, 0 for edge
 809  */
 810 static void openpic_set_sense(u_int irq, int sense)
 811 {
 812         if (ISR[irq] != 0)
 813                 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 814                                         OPENPIC_SENSE_LEVEL,
 815                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
 816 }
 817 #endif /* notused */
 818
 819 /* No spinlocks, should not be necessary with the OpenPIC
 820  * (1 register = 1 interrupt and we have the desc lock).
 821  */
 822 static void openpic_ack_irq(unsigned int irq_nr)
 823 {
 824 #ifdef __SLOW_VERSION__
 825         openpic_disable_irq(irq_nr);
 826         openpic_eoi();
 827 #else
 828         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 829                 openpic_eoi();
 830 #endif
 831 }
 832
 833 static void openpic_end_irq(unsigned int irq_nr)
 834 {
 835 #ifdef __SLOW_VERSION__
 836         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 837             && irq_desc[irq_nr].action)
 838                 openpic_enable_irq(irq_nr);
 839 #else
 840         if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
 841                 openpic_eoi();
 842 #endif
 843 }
 844
 845 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask)
 846 {
 847         openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), CPU_MASK_NONE);
 848 }
 849
 850 #ifdef CONFIG_SMP
 851 static void openpic_ack_ipi(unsigned int irq_nr)
 852 {
 853         openpic_eoi();
 854 }
 855
 856 static void openpic_end_ipi(unsigned int irq_nr)
 857 {
 858 }
 859
 860 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
 861 {
 862         smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
 863         return IRQ_HANDLED;
 864 }
 865
 866 #endif /* CONFIG_SMP */
 867
 868 int
 869 openpic_get_irq(struct pt_regs *regs)
 870 {
 871         int irq = openpic_irq();
 872
 873         /*
 874          * Check for the cascade interrupt and call the cascaded
 875          * interrupt controller function (usually i8259_irq) if so.
 876          * This should move to irq.c eventually.  -- paulus
 877          */
 878         if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
 879                 int cirq = openpic_cascade_fn(regs);
 880
 881                 /* Allow for the cascade being shared with other devices */
 882                 if (cirq != -1) {
 883                         irq = cirq;
 884                         openpic_eoi();
 885                 }
 886         } else if (irq == OPENPIC_VEC_SPURIOUS)
 887                 irq = -1;
 888         return irq;
 889 }
 890
 891 #ifdef CONFIG_SMP
 892 void
 893 smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
 894 {
 895         cpumask_t mask = CPU_MASK_ALL;
 896         /* make sure we're sending something that translates to an IPI */
 897         if (msg > 0x3) {
 898                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
 899                        smp_processor_id(), msg);
 900                 return;
 901         }
 902         switch (target) {
 903         case MSG_ALL:
 904                 openpic_cause_IPI(msg, mask);
 905                 break;
 906         case MSG_ALL_BUT_SELF:
 907                 cpu_clear(smp_processor_id(), mask);
 908                 openpic_cause_IPI(msg, mask);
 909                 break;
 910         default:
 911                 openpic_cause_IPI(msg, cpumask_of_cpu(target));
 912                 break;
 913         }
 914 }
 915 #endif /* CONFIG_SMP */
 916
 917 #ifdef CONFIG_PM
 918
 919 /*
 920  * We implement the IRQ controller as a sysdev and put it
 921  * to sleep at powerdown stage (the callback is named suspend,
 922  * but it's old semantics, for the Device Model, it's really
 923  * powerdown). The possible problem is that another sysdev that
 924  * happens to be suspend after this one will have interrupts off,
 925  * that may be an issue... For now, this isn't an issue on pmac
 926  * though...
 927  */
 928
 929 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
 930 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
 931 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
 932 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
 933 static int openpic_suspend_count;
 934
 935 static void openpic_cached_enable_irq(u_int irq)
 936 {
 937         check_arg_irq(irq);
 938         save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
 939 }
 940
 941 static void openpic_cached_disable_irq(u_int irq)
 942 {
 943         check_arg_irq(irq);
 944         save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
 945 }
 946
 947 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 948  * we need something better to deal with that... Maybe switch to S1 for
 949  * cpufreq changes
 950  */
 951 int openpic_suspend(struct sys_device *sysdev, pm_message_t state)
 952 {
 953         int     i;
 954         unsigned long flags;
 955
 956         spin_lock_irqsave(&openpic_setup_lock, flags);
 957
 958         if (openpic_suspend_count++ > 0) {
 959                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 960                 return 0;
 961         }
 962
 963         openpic_set_priority(0xf);
 964
 965         open_pic.enable = openpic_cached_enable_irq;
 966         open_pic.disable = openpic_cached_disable_irq;
 967
 968         for (i=0; i<NumProcessors; i++) {
 969                 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
 970                 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
 971                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
 972         }
 973
 974         for (i=0; i<OPENPIC_NUM_IPI; i++)
 975                 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
 976         for (i=0; i<NumSources; i++) {
 977                 if (ISR[i] == 0)
 978                         continue;
 979                 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
 980                 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
 981         }
 982
 983         spin_unlock_irqrestore(&openpic_setup_lock, flags);
 984
 985         return 0;
 986 }
 987
 988 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 989  * we need something better to deal with that... Maybe switch to S1 for
 990  * cpufreq changes
 991  */
 992 int openpic_resume(struct sys_device *sysdev)
 993 {
 994         int             i;
 995         unsigned long   flags;
 996         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 997                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
 998                                         OPENPIC_MASK;
 999
1000         spin_lock_irqsave(&openpic_setup_lock, flags);
1001
1002         if ((--openpic_suspend_count) > 0) {
1003                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
1004                 return 0;
1005         }
1006
1007         /* OpenPIC sometimes seem to need some time to be fully back up... */
1008         do {
1009                 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
1010         } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
1011                         != OPENPIC_VEC_SPURIOUS);
1012
1013         openpic_disable_8259_pass_through();
1014
1015         for (i=0; i<OPENPIC_NUM_IPI; i++)
1016                 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
1017                               save_ipi_vp[i]);
1018         for (i=0; i<NumSources; i++) {
1019                 if (ISR[i] == 0)
1020                         continue;
1021                 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
1022                 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1023                 /* make sure mask gets to controller before we return to user */
1024                 do {
1025                         openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1026                 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1027                          != (save_irq_src_vp[i] & vppmask));
1028         }
1029         for (i=0; i<NumProcessors; i++)
1030                 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1031                               save_cpu_task_pri[i]);
1032
1033         open_pic.enable = openpic_enable_irq;
1034         open_pic.disable = openpic_disable_irq;
1035
1036         openpic_set_priority(0);
1037
1038         spin_unlock_irqrestore(&openpic_setup_lock, flags);
1039
1040         return 0;
1041 }
1042
1043 #endif /* CONFIG_PM */
1044
1045 static struct sysdev_class openpic_sysclass = {
1046         set_kset_name("openpic"),
1047 };
1048
1049 static struct sys_device device_openpic = {
1050         .id             = 0,
1051         .cls            = &openpic_sysclass,
1052 };
1053
1054 static struct sysdev_driver driver_openpic = {
1055 #ifdef CONFIG_PM
1056         .suspend        = &openpic_suspend,
1057         .resume         = &openpic_resume,
1058 #endif /* CONFIG_PM */
1059 };
1060
1061 static int __init init_openpic_sysfs(void)
1062 {
1063         int rc;
1064
1065         if (!OpenPIC_Addr)
1066                 return -ENODEV;
1067         printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1068         rc = sysdev_class_register(&openpic_sysclass);
1069         if (rc) {
1070                 printk(KERN_ERR "Failed registering openpic sys class\n");
1071                 return -ENODEV;
1072         }
1073         rc = sysdev_register(&device_openpic);
1074         if (rc) {
1075                 printk(KERN_ERR "Failed registering openpic sys device\n");
1076                 return -ENODEV;
1077         }
1078         rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1079         if (rc) {
1080                 printk(KERN_ERR "Failed registering openpic sys driver\n");
1081                 return -ENODEV;
1082         }
1083         return 0;
1084 }
1085
1086 subsys_initcall(init_openpic_sysfs);
1087