arch/sh/kernel/cpu/sh4a/setup-sh7757.c

   1 /*
   2  * SH7757 Setup
   3  *
   4  * Copyright (C) 2009, 2011  Renesas Solutions Corp.
   5  *
   6  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/sh_timer.h>
  20 #include <linux/sh_dma.h>
  21 #include <linux/sh_intc.h>
  22 #include <linux/usb/ohci_pdriver.h>
  23 #include <cpu/dma-register.h>
  24 #include <cpu/sh7757.h>
  25
  26 static struct plat_sci_port scif2_platform_data = {
  27         .mapbase        = 0xfe4b0000,           /* SCIF2 */
  28         .flags          = UPF_BOOT_AUTOCONF,
  29         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  30         .scbrr_algo_id  = SCBRR_ALGO_2,
  31         .type           = PORT_SCIF,
  32         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
  33 };
  34
  35 static struct platform_device scif2_device = {
  36         .name           = "sh-sci",
  37         .id             = 0,
  38         .dev            = {
  39                 .platform_data  = &scif2_platform_data,
  40         },
  41 };
  42
  43 static struct plat_sci_port scif3_platform_data = {
  44         .mapbase        = 0xfe4c0000,           /* SCIF3 */
  45         .flags          = UPF_BOOT_AUTOCONF,
  46         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  47         .scbrr_algo_id  = SCBRR_ALGO_2,
  48         .type           = PORT_SCIF,
  49         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xb80)),
  50 };
  51
  52 static struct platform_device scif3_device = {
  53         .name           = "sh-sci",
  54         .id             = 1,
  55         .dev            = {
  56                 .platform_data  = &scif3_platform_data,
  57         },
  58 };
  59
  60 static struct plat_sci_port scif4_platform_data = {
  61         .mapbase        = 0xfe4d0000,           /* SCIF4 */
  62         .flags          = UPF_BOOT_AUTOCONF,
  63         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  64         .scbrr_algo_id  = SCBRR_ALGO_2,
  65         .type           = PORT_SCIF,
  66         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xF00)),
  67 };
  68
  69 static struct platform_device scif4_device = {
  70         .name           = "sh-sci",
  71         .id             = 2,
  72         .dev            = {
  73                 .platform_data  = &scif4_platform_data,
  74         },
  75 };
  76
  77 static struct sh_timer_config tmu0_platform_data = {
  78         .channel_offset = 0x04,
  79         .timer_bit = 0,
  80         .clockevent_rating = 200,
  81 };
  82
  83 static struct resource tmu0_resources[] = {
  84         [0] = {
  85                 .start  = 0xfe430008,
  86                 .end    = 0xfe430013,
  87                 .flags  = IORESOURCE_MEM,
  88         },
  89         [1] = {
  90                 .start  = evt2irq(0x580),
  91                 .flags  = IORESOURCE_IRQ,
  92         },
  93 };
  94
  95 static struct platform_device tmu0_device = {
  96         .name           = "sh_tmu",
  97         .id             = 0,
  98         .dev = {
  99                 .platform_data  = &tmu0_platform_data,
 100         },
 101         .resource       = tmu0_resources,
 102         .num_resources  = ARRAY_SIZE(tmu0_resources),
 103 };
 104
 105 static struct sh_timer_config tmu1_platform_data = {
 106         .channel_offset = 0x10,
 107         .timer_bit = 1,
 108         .clocksource_rating = 200,
 109 };
 110
 111 static struct resource tmu1_resources[] = {
 112         [0] = {
 113                 .start  = 0xfe430014,
 114                 .end    = 0xfe43001f,
 115                 .flags  = IORESOURCE_MEM,
 116         },
 117         [1] = {
 118                 .start  = evt2irq(0x5a0),
 119                 .flags  = IORESOURCE_IRQ,
 120         },
 121 };
 122
 123 static struct platform_device tmu1_device = {
 124         .name           = "sh_tmu",
 125         .id             = 1,
 126         .dev = {
 127                 .platform_data  = &tmu1_platform_data,
 128         },
 129         .resource       = tmu1_resources,
 130         .num_resources  = ARRAY_SIZE(tmu1_resources),
 131 };
 132
 133 static struct resource spi0_resources[] = {
 134         [0] = {
 135                 .start  = 0xfe002000,
 136                 .end    = 0xfe0020ff,
 137                 .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 138         },
 139         [1] = {
 140                 .start  = evt2irq(0xcc0),
 141                 .flags  = IORESOURCE_IRQ,
 142         },
 143 };
 144
 145 /* DMA */
 146 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
 147         {
 148                 .slave_id       = SHDMA_SLAVE_SDHI_TX,
 149                 .addr           = 0x1fe50030,
 150                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 151                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 152                 .mid_rid        = 0xc5,
 153         },
 154         {
 155                 .slave_id       = SHDMA_SLAVE_SDHI_RX,
 156                 .addr           = 0x1fe50030,
 157                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 158                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 159                 .mid_rid        = 0xc6,
 160         },
 161         {
 162                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 163                 .addr           = 0x1fcb0034,
 164                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 165                                   TS_INDEX2VAL(XMIT_SZ_32BIT),
 166                 .mid_rid        = 0xd3,
 167         },
 168         {
 169                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 170                 .addr           = 0x1fcb0034,
 171                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 172                                   TS_INDEX2VAL(XMIT_SZ_32BIT),
 173                 .mid_rid        = 0xd7,
 174         },
 175 };
 176
 177 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
 178         {
 179                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 180                 .addr           = 0x1f4b000c,
 181                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 182                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 183                 .mid_rid        = 0x21,
 184         },
 185         {
 186                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 187                 .addr           = 0x1f4b0014,
 188                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 189                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 190                 .mid_rid        = 0x22,
 191         },
 192         {
 193                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 194                 .addr           = 0x1f4c000c,
 195                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 196                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 197                 .mid_rid        = 0x29,
 198         },
 199         {
 200                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 201                 .addr           = 0x1f4c0014,
 202                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 203                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 204                 .mid_rid        = 0x2a,
 205         },
 206         {
 207                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 208                 .addr           = 0x1f4d000c,
 209                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 210                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 211                 .mid_rid        = 0x41,
 212         },
 213         {
 214                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 215                 .addr           = 0x1f4d0014,
 216                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 217                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 218                 .mid_rid        = 0x42,
 219         },
 220         {
 221                 .slave_id       = SHDMA_SLAVE_RSPI_TX,
 222                 .addr           = 0xfe480004,
 223                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 224                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 225                 .mid_rid        = 0xc1,
 226         },
 227         {
 228                 .slave_id       = SHDMA_SLAVE_RSPI_RX,
 229                 .addr           = 0xfe480004,
 230                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 231                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 232                 .mid_rid        = 0xc2,
 233         },
 234 };
 235
 236 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
 237         {
 238                 .slave_id       = SHDMA_SLAVE_RIIC0_TX,
 239                 .addr           = 0x1e500012,
 240                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 241                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 242                 .mid_rid        = 0x21,
 243         },
 244         {
 245                 .slave_id       = SHDMA_SLAVE_RIIC0_RX,
 246                 .addr           = 0x1e500013,
 247                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 248                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 249                 .mid_rid        = 0x22,
 250         },
 251         {
 252                 .slave_id       = SHDMA_SLAVE_RIIC1_TX,
 253                 .addr           = 0x1e510012,
 254                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 255                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 256                 .mid_rid        = 0x29,
 257         },
 258         {
 259                 .slave_id       = SHDMA_SLAVE_RIIC1_RX,
 260                 .addr           = 0x1e510013,
 261                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 262                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 263                 .mid_rid        = 0x2a,
 264         },
 265         {
 266                 .slave_id       = SHDMA_SLAVE_RIIC2_TX,
 267                 .addr           = 0x1e520012,
 268                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 269                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 270                 .mid_rid        = 0xa1,
 271         },
 272         {
 273                 .slave_id       = SHDMA_SLAVE_RIIC2_RX,
 274                 .addr           = 0x1e520013,
 275                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 276                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 277                 .mid_rid        = 0xa2,
 278         },
 279         {
 280                 .slave_id       = SHDMA_SLAVE_RIIC3_TX,
 281                 .addr           = 0x1e530012,
 282                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 283                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 284                 .mid_rid        = 0xa9,
 285         },
 286         {
 287                 .slave_id       = SHDMA_SLAVE_RIIC3_RX,
 288                 .addr           = 0x1e530013,
 289                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 290                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 291                 .mid_rid        = 0xaf,
 292         },
 293         {
 294                 .slave_id       = SHDMA_SLAVE_RIIC4_TX,
 295                 .addr           = 0x1e540012,
 296                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 297                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 298                 .mid_rid        = 0xc5,
 299         },
 300         {
 301                 .slave_id       = SHDMA_SLAVE_RIIC4_RX,
 302                 .addr           = 0x1e540013,
 303                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 304                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 305                 .mid_rid        = 0xc6,
 306         },
 307 };
 308
 309 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
 310         {
 311                 .slave_id       = SHDMA_SLAVE_RIIC5_TX,
 312                 .addr           = 0x1e550012,
 313                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 314                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 315                 .mid_rid        = 0x21,
 316         },
 317         {
 318                 .slave_id       = SHDMA_SLAVE_RIIC5_RX,
 319                 .addr           = 0x1e550013,
 320                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 321                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 322                 .mid_rid        = 0x22,
 323         },
 324         {
 325                 .slave_id       = SHDMA_SLAVE_RIIC6_TX,
 326                 .addr           = 0x1e560012,
 327                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 328                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 329                 .mid_rid        = 0x29,
 330         },
 331         {
 332                 .slave_id       = SHDMA_SLAVE_RIIC6_RX,
 333                 .addr           = 0x1e560013,
 334                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 335                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 336                 .mid_rid        = 0x2a,
 337         },
 338         {
 339                 .slave_id       = SHDMA_SLAVE_RIIC7_TX,
 340                 .addr           = 0x1e570012,
 341                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 342                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 343                 .mid_rid        = 0x41,
 344         },
 345         {
 346                 .slave_id       = SHDMA_SLAVE_RIIC7_RX,
 347                 .addr           = 0x1e570013,
 348                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 349                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 350                 .mid_rid        = 0x42,
 351         },
 352         {
 353                 .slave_id       = SHDMA_SLAVE_RIIC8_TX,
 354                 .addr           = 0x1e580012,
 355                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 356                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 357                 .mid_rid        = 0x45,
 358         },
 359         {
 360                 .slave_id       = SHDMA_SLAVE_RIIC8_RX,
 361                 .addr           = 0x1e580013,
 362                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 363                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 364                 .mid_rid        = 0x46,
 365         },
 366         {
 367                 .slave_id       = SHDMA_SLAVE_RIIC9_TX,
 368                 .addr           = 0x1e590012,
 369                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 370                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 371                 .mid_rid        = 0x51,
 372         },
 373         {
 374                 .slave_id       = SHDMA_SLAVE_RIIC9_RX,
 375                 .addr           = 0x1e590013,
 376                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 377                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 378                 .mid_rid        = 0x52,
 379         },
 380 };
 381
 382 static const struct sh_dmae_channel sh7757_dmae_channels[] = {
 383         {
 384                 .offset = 0,
 385                 .dmars = 0,
 386                 .dmars_bit = 0,
 387         }, {
 388                 .offset = 0x10,
 389                 .dmars = 0,
 390                 .dmars_bit = 8,
 391         }, {
 392                 .offset = 0x20,
 393                 .dmars = 4,
 394                 .dmars_bit = 0,
 395         }, {
 396                 .offset = 0x30,
 397                 .dmars = 4,
 398                 .dmars_bit = 8,
 399         }, {
 400                 .offset = 0x50,
 401                 .dmars = 8,
 402                 .dmars_bit = 0,
 403         }, {
 404                 .offset = 0x60,
 405                 .dmars = 8,
 406                 .dmars_bit = 8,
 407         }
 408 };
 409
 410 static const unsigned int ts_shift[] = TS_SHIFT;
 411
 412 static struct sh_dmae_pdata dma0_platform_data = {
 413         .slave          = sh7757_dmae0_slaves,
 414         .slave_num      = ARRAY_SIZE(sh7757_dmae0_slaves),
 415         .channel        = sh7757_dmae_channels,
 416         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 417         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 418         .ts_low_mask    = CHCR_TS_LOW_MASK,
 419         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 420         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 421         .ts_shift       = ts_shift,
 422         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 423         .dmaor_init     = DMAOR_INIT,
 424 };
 425
 426 static struct sh_dmae_pdata dma1_platform_data = {
 427         .slave          = sh7757_dmae1_slaves,
 428         .slave_num      = ARRAY_SIZE(sh7757_dmae1_slaves),
 429         .channel        = sh7757_dmae_channels,
 430         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 431         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 432         .ts_low_mask    = CHCR_TS_LOW_MASK,
 433         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 434         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 435         .ts_shift       = ts_shift,
 436         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 437         .dmaor_init     = DMAOR_INIT,
 438 };
 439
 440 static struct sh_dmae_pdata dma2_platform_data = {
 441         .slave          = sh7757_dmae2_slaves,
 442         .slave_num      = ARRAY_SIZE(sh7757_dmae2_slaves),
 443         .channel        = sh7757_dmae_channels,
 444         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 445         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 446         .ts_low_mask    = CHCR_TS_LOW_MASK,
 447         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 448         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 449         .ts_shift       = ts_shift,
 450         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 451         .dmaor_init     = DMAOR_INIT,
 452 };
 453
 454 static struct sh_dmae_pdata dma3_platform_data = {
 455         .slave          = sh7757_dmae3_slaves,
 456         .slave_num      = ARRAY_SIZE(sh7757_dmae3_slaves),
 457         .channel        = sh7757_dmae_channels,
 458         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 459         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 460         .ts_low_mask    = CHCR_TS_LOW_MASK,
 461         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 462         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 463         .ts_shift       = ts_shift,
 464         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 465         .dmaor_init     = DMAOR_INIT,
 466 };
 467
 468 /* channel 0 to 5 */
 469 static struct resource sh7757_dmae0_resources[] = {
 470         [0] = {
 471                 /* Channel registers and DMAOR */
 472                 .start  = 0xff608020,
 473                 .end    = 0xff60808f,
 474                 .flags  = IORESOURCE_MEM,
 475         },
 476         [1] = {
 477                 /* DMARSx */
 478                 .start  = 0xff609000,
 479                 .end    = 0xff60900b,
 480                 .flags  = IORESOURCE_MEM,
 481         },
 482         {
 483                 .name   = "error_irq",
 484                 .start  = evt2irq(0x640),
 485                 .end    = evt2irq(0x640),
 486                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 487         },
 488 };
 489
 490 /* channel 6 to 11 */
 491 static struct resource sh7757_dmae1_resources[] = {
 492         [0] = {
 493                 /* Channel registers and DMAOR */
 494                 .start  = 0xff618020,
 495                 .end    = 0xff61808f,
 496                 .flags  = IORESOURCE_MEM,
 497         },
 498         [1] = {
 499                 /* DMARSx */
 500                 .start  = 0xff619000,
 501                 .end    = 0xff61900b,
 502                 .flags  = IORESOURCE_MEM,
 503         },
 504         {
 505                 .name   = "error_irq",
 506                 .start  = evt2irq(0x640),
 507                 .end    = evt2irq(0x640),
 508                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 509         },
 510         {
 511                 /* IRQ for channels 4 */
 512                 .start  = evt2irq(0x7c0),
 513                 .end    = evt2irq(0x7c0),
 514                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 515         },
 516         {
 517                 /* IRQ for channels 5 */
 518                 .start  = evt2irq(0x7c0),
 519                 .end    = evt2irq(0x7c0),
 520                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 521         },
 522         {
 523                 /* IRQ for channels 6 */
 524                 .start  = evt2irq(0xd00),
 525                 .end    = evt2irq(0xd00),
 526                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 527         },
 528         {
 529                 /* IRQ for channels 7 */
 530                 .start  = evt2irq(0xd00),
 531                 .end    = evt2irq(0xd00),
 532                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 533         },
 534         {
 535                 /* IRQ for channels 8 */
 536                 .start  = evt2irq(0xd00),
 537                 .end    = evt2irq(0xd00),
 538                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 539         },
 540         {
 541                 /* IRQ for channels 9 */
 542                 .start  = evt2irq(0xd00),
 543                 .end    = evt2irq(0xd00),
 544                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 545         },
 546         {
 547                 /* IRQ for channels 10 */
 548                 .start  = evt2irq(0xd00),
 549                 .end    = evt2irq(0xd00),
 550                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 551         },
 552         {
 553                 /* IRQ for channels 11 */
 554                 .start  = evt2irq(0xd00),
 555                 .end    = evt2irq(0xd00),
 556                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 557         },
 558 };
 559
 560 /* channel 12 to 17 */
 561 static struct resource sh7757_dmae2_resources[] = {
 562         [0] = {
 563                 /* Channel registers and DMAOR */
 564                 .start  = 0xff708020,
 565                 .end    = 0xff70808f,
 566                 .flags  = IORESOURCE_MEM,
 567         },
 568         [1] = {
 569                 /* DMARSx */
 570                 .start  = 0xff709000,
 571                 .end    = 0xff70900b,
 572                 .flags  = IORESOURCE_MEM,
 573         },
 574         {
 575                 .name   = "error_irq",
 576                 .start  = evt2irq(0x2a60),
 577                 .end    = evt2irq(0x2a60),
 578                 .flags  = IORESOURCE_IRQ,
 579         },
 580         {
 581                 /* IRQ for channels 12 to 16 */
 582                 .start  = evt2irq(0x2400),
 583                 .end    = evt2irq(0x2480),
 584                 .flags  = IORESOURCE_IRQ,
 585         },
 586         {
 587                 /* IRQ for channel 17 */
 588                 .start  = evt2irq(0x24e0),
 589                 .end    = evt2irq(0x24e0),
 590                 .flags  = IORESOURCE_IRQ,
 591         },
 592 };
 593
 594 /* channel 18 to 23 */
 595 static struct resource sh7757_dmae3_resources[] = {
 596         [0] = {
 597                 /* Channel registers and DMAOR */
 598                 .start  = 0xff718020,
 599                 .end    = 0xff71808f,
 600                 .flags  = IORESOURCE_MEM,
 601         },
 602         [1] = {
 603                 /* DMARSx */
 604                 .start  = 0xff719000,
 605                 .end    = 0xff71900b,
 606                 .flags  = IORESOURCE_MEM,
 607         },
 608         {
 609                 .name   = "error_irq",
 610                 .start  = evt2irq(0x2a80),
 611                 .end    = evt2irq(0x2a80),
 612                 .flags  = IORESOURCE_IRQ,
 613         },
 614         {
 615                 /* IRQ for channels 18 to 22 */
 616                 .start  = evt2irq(0x2500),
 617                 .end    = evt2irq(0x2580),
 618                 .flags  = IORESOURCE_IRQ,
 619         },
 620         {
 621                 /* IRQ for channel 23 */
 622                 .start  = evt2irq(0x2600),
 623                 .end    = evt2irq(0x2600),
 624                 .flags  = IORESOURCE_IRQ,
 625         },
 626 };
 627
 628 static struct platform_device dma0_device = {
 629         .name           = "sh-dma-engine",
 630         .id             = 0,
 631         .resource       = sh7757_dmae0_resources,
 632         .num_resources  = ARRAY_SIZE(sh7757_dmae0_resources),
 633         .dev            = {
 634                 .platform_data  = &dma0_platform_data,
 635         },
 636 };
 637
 638 static struct platform_device dma1_device = {
 639         .name           = "sh-dma-engine",
 640         .id             = 1,
 641         .resource       = sh7757_dmae1_resources,
 642         .num_resources  = ARRAY_SIZE(sh7757_dmae1_resources),
 643         .dev            = {
 644                 .platform_data  = &dma1_platform_data,
 645         },
 646 };
 647
 648 static struct platform_device dma2_device = {
 649         .name           = "sh-dma-engine",
 650         .id             = 2,
 651         .resource       = sh7757_dmae2_resources,
 652         .num_resources  = ARRAY_SIZE(sh7757_dmae2_resources),
 653         .dev            = {
 654                 .platform_data  = &dma2_platform_data,
 655         },
 656 };
 657
 658 static struct platform_device dma3_device = {
 659         .name           = "sh-dma-engine",
 660         .id             = 3,
 661         .resource       = sh7757_dmae3_resources,
 662         .num_resources  = ARRAY_SIZE(sh7757_dmae3_resources),
 663         .dev            = {
 664                 .platform_data  = &dma3_platform_data,
 665         },
 666 };
 667
 668 static struct platform_device spi0_device = {
 669         .name   = "sh_spi",
 670         .id     = 0,
 671         .dev    = {
 672                 .dma_mask               = NULL,
 673                 .coherent_dma_mask      = 0xffffffff,
 674         },
 675         .num_resources  = ARRAY_SIZE(spi0_resources),
 676         .resource       = spi0_resources,
 677 };
 678
 679 static struct resource spi1_resources[] = {
 680         {
 681                 .start  = 0xffd8ee70,
 682                 .end    = 0xffd8eeff,
 683                 .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
 684         },
 685         {
 686                 .start  = evt2irq(0x8c0),
 687                 .flags  = IORESOURCE_IRQ,
 688         },
 689 };
 690
 691 static struct platform_device spi1_device = {
 692         .name   = "sh_spi",
 693         .id     = 1,
 694         .num_resources  = ARRAY_SIZE(spi1_resources),
 695         .resource       = spi1_resources,
 696 };
 697
 698 static struct resource rspi_resources[] = {
 699         {
 700                 .start  = 0xfe480000,
 701                 .end    = 0xfe4800ff,
 702                 .flags  = IORESOURCE_MEM,
 703         },
 704         {
 705                 .start  = evt2irq(0x1d80),
 706                 .flags  = IORESOURCE_IRQ,
 707         },
 708 };
 709
 710 static struct platform_device rspi_device = {
 711         .name   = "rspi",
 712         .id     = 2,
 713         .num_resources  = ARRAY_SIZE(rspi_resources),
 714         .resource       = rspi_resources,
 715 };
 716
 717 static struct resource usb_ehci_resources[] = {
 718         [0] = {
 719                 .start  = 0xfe4f1000,
 720                 .end    = 0xfe4f10ff,
 721                 .flags  = IORESOURCE_MEM,
 722         },
 723         [1] = {
 724                 .start  = evt2irq(0x920),
 725                 .end    = evt2irq(0x920),
 726                 .flags  = IORESOURCE_IRQ,
 727         },
 728 };
 729
 730 static struct platform_device usb_ehci_device = {
 731         .name           = "sh_ehci",
 732         .id             = -1,
 733         .dev = {
 734                 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
 735                 .coherent_dma_mask = DMA_BIT_MASK(32),
 736         },
 737         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
 738         .resource       = usb_ehci_resources,
 739 };
 740
 741 static struct resource usb_ohci_resources[] = {
 742         [0] = {
 743                 .start  = 0xfe4f1800,
 744                 .end    = 0xfe4f18ff,
 745                 .flags  = IORESOURCE_MEM,
 746         },
 747         [1] = {
 748                 .start  = evt2irq(0x920),
 749                 .end    = evt2irq(0x920),
 750                 .flags  = IORESOURCE_IRQ,
 751         },
 752 };
 753
 754 static struct usb_ohci_pdata usb_ohci_pdata;
 755
 756 static struct platform_device usb_ohci_device = {
 757         .name           = "ohci-platform",
 758         .id             = -1,
 759         .dev = {
 760                 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
 761                 .coherent_dma_mask = DMA_BIT_MASK(32),
 762                 .platform_data  = &usb_ohci_pdata,
 763         },
 764         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 765         .resource       = usb_ohci_resources,
 766 };
 767
 768 static struct platform_device *sh7757_devices[] __initdata = {
 769         &scif2_device,
 770         &scif3_device,
 771         &scif4_device,
 772         &tmu0_device,
 773         &tmu1_device,
 774         &dma0_device,
 775         &dma1_device,
 776         &dma2_device,
 777         &dma3_device,
 778         &spi0_device,
 779         &spi1_device,
 780         &rspi_device,
 781         &usb_ehci_device,
 782         &usb_ohci_device,
 783 };
 784
 785 static int __init sh7757_devices_setup(void)
 786 {
 787         return platform_add_devices(sh7757_devices,
 788                                     ARRAY_SIZE(sh7757_devices));
 789 }
 790 arch_initcall(sh7757_devices_setup);
 791
 792 static struct platform_device *sh7757_early_devices[] __initdata = {
 793         &scif2_device,
 794         &scif3_device,
 795         &scif4_device,
 796         &tmu0_device,
 797         &tmu1_device,
 798 };
 799
 800 void __init plat_early_device_setup(void)
 801 {
 802         early_platform_add_devices(sh7757_early_devices,
 803                                    ARRAY_SIZE(sh7757_early_devices));
 804 }
 805
 806 enum {
 807         UNUSED = 0,
 808
 809         /* interrupt sources */
 810
 811         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 812         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 813         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 814         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 815
 816         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 817         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 818         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 819         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 820         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 821
 822         SDHI, DVC,
 823         IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
 824         TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 825         HUDI,
 826         ARC4,
 827         DMAC0_5, DMAC6_7, DMAC8_11,
 828         SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
 829         USB0, USB1,
 830         JMC,
 831         SPI0, SPI1,
 832         TMR01, TMR23, TMR45,
 833         FRT,
 834         LPC, LPC5, LPC6, LPC7, LPC8,
 835         PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
 836         ETHERC,
 837         ADC0, ADC1,
 838         SIM,
 839         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
 840         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
 841         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
 842         IIC3_0, IIC3_1, IIC3_2, IIC3_3,
 843         IIC4_0, IIC4_1, IIC4_2, IIC4_3,
 844         IIC5_0, IIC5_1, IIC5_2, IIC5_3,
 845         IIC6_0, IIC6_1, IIC6_2, IIC6_3,
 846         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
 847         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
 848         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
 849         ONFICTL,
 850         MMC1, MMC2,
 851         ECCU,
 852         PCIC,
 853         G200,
 854         RSPI,
 855         SGPIO,
 856         DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
 857         DMINT20, DMINT21, DMINT22, DMINT23,
 858         DDRECC,
 859         TSIP,
 860         PCIE_BRIDGE,
 861         WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
 862         GETHER0, GETHER1, GETHER2,
 863         PBIA, PBIB, PBIC,
 864         DMAE2, DMAE3,
 865         SERMUX2, SERMUX3,
 866
 867         /* interrupt groups */
 868
 869         TMU012, TMU345,
 870 };
 871
 872 static struct intc_vect vectors[] __initdata = {
 873         INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
 874         INTC_VECT(SDHI, 0x4c0),
 875         INTC_VECT(DVC, 0x4e0),
 876         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
 877         INTC_VECT(IRQ10, 0x540),
 878         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 879         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 880         INTC_VECT(HUDI, 0x600),
 881         INTC_VECT(ARC4, 0x620),
 882         INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
 883         INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
 884         INTC_VECT(DMAC0_5, 0x6c0),
 885         INTC_VECT(IRQ11, 0x6e0),
 886         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
 887         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
 888         INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
 889         INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
 890         INTC_VECT(USB0, 0x840),
 891         INTC_VECT(IRQ12, 0x880),
 892         INTC_VECT(JMC, 0x8a0),
 893         INTC_VECT(SPI1, 0x8c0),
 894         INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
 895         INTC_VECT(USB1, 0x920),
 896         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
 897         INTC_VECT(TMR45, 0xa40),
 898         INTC_VECT(FRT, 0xa80),
 899         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
 900         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
 901         INTC_VECT(LPC, 0xb20),
 902         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
 903         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
 904         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
 905         INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
 906         INTC_VECT(PECI2, 0xc40),
 907         INTC_VECT(IRQ15, 0xc60),
 908         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
 909         INTC_VECT(SPI0, 0xcc0),
 910         INTC_VECT(ADC1, 0xce0),
 911         INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
 912         INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
 913         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 914         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 915         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 916         INTC_VECT(TMU5, 0xe40),
 917         INTC_VECT(ADC0, 0xe60),
 918         INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
 919         INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
 920         INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
 921         INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
 922         INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
 923         INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
 924         INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
 925         INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
 926         INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
 927         INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
 928         INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
 929         INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
 930         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
 931         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
 932         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
 933         INTC_VECT(IIC6_2, 0x1920),
 934         INTC_VECT(ONFICTL, 0x1960),
 935         INTC_VECT(IIC6_3, 0x1980),
 936         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
 937         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
 938         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
 939         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
 940         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
 941         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
 942         INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
 943         INTC_VECT(ECCU, 0x1cc0),
 944         INTC_VECT(PCIC, 0x1ce0),
 945         INTC_VECT(G200, 0x1d00),
 946         INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
 947         INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
 948         INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
 949         INTC_VECT(PECI5, 0x1f00),
 950         INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
 951         INTC_VECT(SGPIO, 0x1fc0),
 952         INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
 953         INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
 954         INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
 955         INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
 956         INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
 957         INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
 958         INTC_VECT(DDRECC, 0x2620),
 959         INTC_VECT(TSIP, 0x2640),
 960         INTC_VECT(PCIE_BRIDGE, 0x27c0),
 961         INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
 962         INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
 963         INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
 964         INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
 965         INTC_VECT(WDT8B, 0x2900),
 966         INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
 967         INTC_VECT(GETHER2, 0x29a0),
 968         INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
 969         INTC_VECT(PBIC, 0x2a40),
 970         INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
 971         INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
 972         INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
 973         INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
 974 };
 975
 976 static struct intc_group groups[] __initdata = {
 977         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 978         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 979 };
 980
 981 static struct intc_mask_reg mask_registers[] __initdata = {
 982         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 983           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 984
 985         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 986           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 987             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 988             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 989             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 990             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 991             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 992             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 993             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 994
 995         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 996           { 0, 0, 0, 0, 0, 0, 0, 0,
 997             0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
 998             TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
 999             HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
1000              } },
1001
1002         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
1003           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
1004             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
1005             ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
1006             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
1007              } },
1008
1009         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
1010           { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
1011             0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
1012             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
1013             IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
1014              } },
1015
1016         { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
1017           { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
1018             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
1019             PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
1020             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
1021              } },
1022
1023         { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
1024           { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
1025             0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
1026             PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
1027             DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
1028              } },
1029
1030         { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
1031           { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
1032             DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
1033             0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
1034             DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
1035              } },
1036 };
1037
1038 #define INTPRI          0xffd00010
1039 #define INT2PRI0        0xffd40000
1040 #define INT2PRI1        0xffd40004
1041 #define INT2PRI2        0xffd40008
1042 #define INT2PRI3        0xffd4000c
1043 #define INT2PRI4        0xffd40010
1044 #define INT2PRI5        0xffd40014
1045 #define INT2PRI6        0xffd40018
1046 #define INT2PRI7        0xffd4001c
1047 #define INT2PRI8        0xffd400a0
1048 #define INT2PRI9        0xffd400a4
1049 #define INT2PRI10       0xffd400a8
1050 #define INT2PRI11       0xffd400ac
1051 #define INT2PRI12       0xffd400b0
1052 #define INT2PRI13       0xffd400b4
1053 #define INT2PRI14       0xffd400b8
1054 #define INT2PRI15       0xffd400bc
1055 #define INT2PRI16       0xffd10000
1056 #define INT2PRI17       0xffd10004
1057 #define INT2PRI18       0xffd10008
1058 #define INT2PRI19       0xffd1000c
1059 #define INT2PRI20       0xffd10010
1060 #define INT2PRI21       0xffd10014
1061 #define INT2PRI22       0xffd10018
1062 #define INT2PRI23       0xffd1001c
1063 #define INT2PRI24       0xffd100a0
1064 #define INT2PRI25       0xffd100a4
1065 #define INT2PRI26       0xffd100a8
1066 #define INT2PRI27       0xffd100ac
1067 #define INT2PRI28       0xffd100b0
1068 #define INT2PRI29       0xffd100b4
1069 #define INT2PRI30       0xffd100b8
1070 #define INT2PRI31       0xffd100bc
1071 #define INT2PRI32       0xffd20000
1072 #define INT2PRI33       0xffd20004
1073 #define INT2PRI34       0xffd20008
1074 #define INT2PRI35       0xffd2000c
1075 #define INT2PRI36       0xffd20010
1076 #define INT2PRI37       0xffd20014
1077 #define INT2PRI38       0xffd20018
1078 #define INT2PRI39       0xffd2001c
1079 #define INT2PRI40       0xffd200a0
1080 #define INT2PRI41       0xffd200a4
1081 #define INT2PRI42       0xffd200a8
1082 #define INT2PRI43       0xffd200ac
1083 #define INT2PRI44       0xffd200b0
1084 #define INT2PRI45       0xffd200b4
1085 #define INT2PRI46       0xffd200b8
1086 #define INT2PRI47       0xffd200bc
1087
1088 static struct intc_prio_reg prio_registers[] __initdata = {
1089         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
1090                               IRQ4, IRQ5, IRQ6, IRQ7 } },
1091
1092         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
1093         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
1094         { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
1095         { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
1096         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
1097         { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
1098         { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
1099         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
1100         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
1101         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
1102         { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
1103         { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
1104         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
1105         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
1106
1107         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
1108         { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
1109         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1110         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1111         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1112         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
1113         { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1114         { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1115         { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
1116         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
1117         { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1118         { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1119         { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
1120         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
1121         { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
1122         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1123         { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1124         { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1125         { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1126         { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1127         { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1128         { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1129         { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1130         { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1131         { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1132         { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1133         { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1134         { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1135         { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1136         { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1137         { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1138         { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1139 };
1140
1141 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1142         { 0xffd100f8, 32, 2, /* ICR2 */   { IRQ15, IRQ14, IRQ13, IRQ12,
1143                                             IRQ11, IRQ10, IRQ9, IRQ8 } },
1144 };
1145
1146 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
1147                          mask_registers, prio_registers,
1148                          sense_registers_irq8to15);
1149
1150 /* Support for external interrupt pins in IRQ mode */
1151 static struct intc_vect vectors_irq0123[] __initdata = {
1152         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
1153         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
1154 };
1155
1156 static struct intc_vect vectors_irq4567[] __initdata = {
1157         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
1158         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
1159 };
1160
1161 static struct intc_sense_reg sense_registers[] __initdata = {
1162         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
1163                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
1164 };
1165
1166 static struct intc_mask_reg ack_registers[] __initdata = {
1167         { 0xffd00024, 0, 32, /* INTREQ */
1168           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1169 };
1170
1171 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
1172                              vectors_irq0123, NULL, mask_registers,
1173                              prio_registers, sense_registers, ack_registers);
1174
1175 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
1176                              vectors_irq4567, NULL, mask_registers,
1177                              prio_registers, sense_registers, ack_registers);
1178
1179 /* External interrupt pins in IRL mode */
1180 static struct intc_vect vectors_irl0123[] __initdata = {
1181         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1182         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1183         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1184         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1185         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1186         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1187         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1188         INTC_VECT(IRL0_HHHL, 0x3c0),
1189 };
1190
1191 static struct intc_vect vectors_irl4567[] __initdata = {
1192         INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
1193         INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
1194         INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
1195         INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
1196         INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
1197         INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
1198         INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
1199         INTC_VECT(IRL4_HHHL, 0x3c0),
1200 };
1201
1202 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
1203                          NULL, mask_registers, NULL, NULL);
1204
1205 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
1206                          NULL, mask_registers, NULL, NULL);
1207
1208 #define INTC_ICR0       0xffd00000
1209 #define INTC_INTMSK0    0xffd00044
1210 #define INTC_INTMSK1    0xffd00048
1211 #define INTC_INTMSK2    0xffd40080
1212 #define INTC_INTMSKCLR1 0xffd00068
1213 #define INTC_INTMSKCLR2 0xffd40084
1214
1215 void __init plat_irq_setup(void)
1216 {
1217         /* disable IRQ3-0 + IRQ7-4 */
1218         __raw_writel(0xff000000, INTC_INTMSK0);
1219
1220         /* disable IRL3-0 + IRL7-4 */
1221         __raw_writel(0xc0000000, INTC_INTMSK1);
1222         __raw_writel(0xfffefffe, INTC_INTMSK2);
1223
1224         /* select IRL mode for IRL3-0 + IRL7-4 */
1225         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
1226
1227         /* disable holding function, ie enable "SH-4 Mode" */
1228         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
1229
1230         register_intc_controller(&intc_desc);
1231 }
1232
1233 void __init plat_irq_setup_pins(int mode)
1234 {
1235         switch (mode) {
1236         case IRQ_MODE_IRQ7654:
1237                 /* select IRQ mode for IRL7-4 */
1238                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
1239                 register_intc_controller(&intc_desc_irq4567);
1240                 break;
1241         case IRQ_MODE_IRQ3210:
1242                 /* select IRQ mode for IRL3-0 */
1243                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
1244                 register_intc_controller(&intc_desc_irq0123);
1245                 break;
1246         case IRQ_MODE_IRL7654:
1247                 /* enable IRL7-4 but don't provide any masking */
1248                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1249                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1250                 break;
1251         case IRQ_MODE_IRL3210:
1252                 /* enable IRL0-3 but don't provide any masking */
1253                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1254                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1255                 break;
1256         case IRQ_MODE_IRL7654_MASK:
1257                 /* enable IRL7-4 and mask using cpu intc controller */
1258                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1259                 register_intc_controller(&intc_desc_irl4567);
1260                 break;
1261         case IRQ_MODE_IRL3210_MASK:
1262                 /* enable IRL0-3 and mask using cpu intc controller */
1263                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1264                 register_intc_controller(&intc_desc_irl0123);
1265                 break;
1266         default:
1267                 BUG();
1268         }
1269 }
1270
1271 void __init plat_mem_setup(void)
1272 {
1273 }