arch/x86/include/asm/vmx.h

   1 /*
   2  * vmx.h: VMX Architecture related definitions
   3  * Copyright (c) 2004, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  * A few random additions are:
  19  * Copyright (C) 2006 Qumranet
  20  *    Avi Kivity <avi@qumranet.com>
  21  *    Yaniv Kamay <yaniv@qumranet.com>
  22  *
  23  */
  24 #ifndef VMX_H
  25 #define VMX_H
  26
  27
  28 #include <linux/types.h>
  29 #include <uapi/asm/vmx.h>
  30
  31 /*
  32  * Definitions of Primary Processor-Based VM-Execution Controls.
  33  */
  34 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
  35 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
  36 #define CPU_BASED_HLT_EXITING                   0x00000080
  37 #define CPU_BASED_INVLPG_EXITING                0x00000200
  38 #define CPU_BASED_MWAIT_EXITING                 0x00000400
  39 #define CPU_BASED_RDPMC_EXITING                 0x00000800
  40 #define CPU_BASED_RDTSC_EXITING                 0x00001000
  41 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
  42 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
  43 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
  44 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
  45 #define CPU_BASED_TPR_SHADOW                    0x00200000
  46 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
  47 #define CPU_BASED_MOV_DR_EXITING                0x00800000
  48 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
  49 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
  50 #define CPU_BASED_MONITOR_TRAP_FLAG             0x08000000
  51 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
  52 #define CPU_BASED_MONITOR_EXITING               0x20000000
  53 #define CPU_BASED_PAUSE_EXITING                 0x40000000
  54 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
  55
  56 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR     0x0401e172
  57
  58 /*
  59  * Definitions of Secondary Processor-Based VM-Execution Controls.
  60  */
  61 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
  62 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
  63 #define SECONDARY_EXEC_RDTSCP                   0x00000008
  64 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
  65 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
  66 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
  67 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
  68 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
  69 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
  70 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
  71 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
  72 #define SECONDARY_EXEC_SHADOW_VMCS              0x00004000
  73 #define SECONDARY_EXEC_ENABLE_PML               0x00020000
  74 #define SECONDARY_EXEC_XSAVES                   0x00100000
  75
  76
  77 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
  78 #define PIN_BASED_NMI_EXITING                   0x00000008
  79 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
  80 #define PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
  81 #define PIN_BASED_POSTED_INTR                   0x00000080
  82
  83 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR     0x00000016
  84
  85 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
  86 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
  87 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
  88 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
  89 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
  90 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
  91 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
  92 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
  93 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
  94 #define VM_EXIT_CLEAR_BNDCFGS                   0x00800000
  95
  96 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR       0x00036dff
  97
  98 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
  99 #define VM_ENTRY_IA32E_MODE                     0x00000200
 100 #define VM_ENTRY_SMM                            0x00000400
 101 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
 102 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
 103 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
 104 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
 105 #define VM_ENTRY_LOAD_BNDCFGS                   0x00010000
 106
 107 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR      0x000011ff
 108
 109 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK     0x0000001f
 110 #define VMX_MISC_SAVE_EFER_LMA                  0x00000020
 111 #define VMX_MISC_ACTIVITY_HLT                   0x00000040
 112
 113 /* VMCS Encodings */
 114 enum vmcs_field {
 115         VIRTUAL_PROCESSOR_ID            = 0x00000000,
 116         POSTED_INTR_NV                  = 0x00000002,
 117         GUEST_ES_SELECTOR               = 0x00000800,
 118         GUEST_CS_SELECTOR               = 0x00000802,
 119         GUEST_SS_SELECTOR               = 0x00000804,
 120         GUEST_DS_SELECTOR               = 0x00000806,
 121         GUEST_FS_SELECTOR               = 0x00000808,
 122         GUEST_GS_SELECTOR               = 0x0000080a,
 123         GUEST_LDTR_SELECTOR             = 0x0000080c,
 124         GUEST_TR_SELECTOR               = 0x0000080e,
 125         GUEST_INTR_STATUS               = 0x00000810,
 126         GUEST_PML_INDEX                 = 0x00000812,
 127         HOST_ES_SELECTOR                = 0x00000c00,
 128         HOST_CS_SELECTOR                = 0x00000c02,
 129         HOST_SS_SELECTOR                = 0x00000c04,
 130         HOST_DS_SELECTOR                = 0x00000c06,
 131         HOST_FS_SELECTOR                = 0x00000c08,
 132         HOST_GS_SELECTOR                = 0x00000c0a,
 133         HOST_TR_SELECTOR                = 0x00000c0c,
 134         IO_BITMAP_A                     = 0x00002000,
 135         IO_BITMAP_A_HIGH                = 0x00002001,
 136         IO_BITMAP_B                     = 0x00002002,
 137         IO_BITMAP_B_HIGH                = 0x00002003,
 138         MSR_BITMAP                      = 0x00002004,
 139         MSR_BITMAP_HIGH                 = 0x00002005,
 140         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
 141         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
 142         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
 143         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
 144         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
 145         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
 146         PML_ADDRESS                     = 0x0000200e,
 147         PML_ADDRESS_HIGH                = 0x0000200f,
 148         TSC_OFFSET                      = 0x00002010,
 149         TSC_OFFSET_HIGH                 = 0x00002011,
 150         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
 151         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
 152         APIC_ACCESS_ADDR                = 0x00002014,
 153         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
 154         POSTED_INTR_DESC_ADDR           = 0x00002016,
 155         POSTED_INTR_DESC_ADDR_HIGH      = 0x00002017,
 156         EPT_POINTER                     = 0x0000201a,
 157         EPT_POINTER_HIGH                = 0x0000201b,
 158         EOI_EXIT_BITMAP0                = 0x0000201c,
 159         EOI_EXIT_BITMAP0_HIGH           = 0x0000201d,
 160         EOI_EXIT_BITMAP1                = 0x0000201e,
 161         EOI_EXIT_BITMAP1_HIGH           = 0x0000201f,
 162         EOI_EXIT_BITMAP2                = 0x00002020,
 163         EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
 164         EOI_EXIT_BITMAP3                = 0x00002022,
 165         EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
 166         VMREAD_BITMAP                   = 0x00002026,
 167         VMWRITE_BITMAP                  = 0x00002028,
 168         XSS_EXIT_BITMAP                 = 0x0000202C,
 169         XSS_EXIT_BITMAP_HIGH            = 0x0000202D,
 170         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
 171         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
 172         VMCS_LINK_POINTER               = 0x00002800,
 173         VMCS_LINK_POINTER_HIGH          = 0x00002801,
 174         GUEST_IA32_DEBUGCTL             = 0x00002802,
 175         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
 176         GUEST_IA32_PAT                  = 0x00002804,
 177         GUEST_IA32_PAT_HIGH             = 0x00002805,
 178         GUEST_IA32_EFER                 = 0x00002806,
 179         GUEST_IA32_EFER_HIGH            = 0x00002807,
 180         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
 181         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
 182         GUEST_PDPTR0                    = 0x0000280a,
 183         GUEST_PDPTR0_HIGH               = 0x0000280b,
 184         GUEST_PDPTR1                    = 0x0000280c,
 185         GUEST_PDPTR1_HIGH               = 0x0000280d,
 186         GUEST_PDPTR2                    = 0x0000280e,
 187         GUEST_PDPTR2_HIGH               = 0x0000280f,
 188         GUEST_PDPTR3                    = 0x00002810,
 189         GUEST_PDPTR3_HIGH               = 0x00002811,
 190         GUEST_BNDCFGS                   = 0x00002812,
 191         GUEST_BNDCFGS_HIGH              = 0x00002813,
 192         HOST_IA32_PAT                   = 0x00002c00,
 193         HOST_IA32_PAT_HIGH              = 0x00002c01,
 194         HOST_IA32_EFER                  = 0x00002c02,
 195         HOST_IA32_EFER_HIGH             = 0x00002c03,
 196         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
 197         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
 198         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
 199         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
 200         EXCEPTION_BITMAP                = 0x00004004,
 201         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
 202         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
 203         CR3_TARGET_COUNT                = 0x0000400a,
 204         VM_EXIT_CONTROLS                = 0x0000400c,
 205         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
 206         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
 207         VM_ENTRY_CONTROLS               = 0x00004012,
 208         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
 209         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
 210         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
 211         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
 212         TPR_THRESHOLD                   = 0x0000401c,
 213         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
 214         PLE_GAP                         = 0x00004020,
 215         PLE_WINDOW                      = 0x00004022,
 216         VM_INSTRUCTION_ERROR            = 0x00004400,
 217         VM_EXIT_REASON                  = 0x00004402,
 218         VM_EXIT_INTR_INFO               = 0x00004404,
 219         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
 220         IDT_VECTORING_INFO_FIELD        = 0x00004408,
 221         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
 222         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
 223         VMX_INSTRUCTION_INFO            = 0x0000440e,
 224         GUEST_ES_LIMIT                  = 0x00004800,
 225         GUEST_CS_LIMIT                  = 0x00004802,
 226         GUEST_SS_LIMIT                  = 0x00004804,
 227         GUEST_DS_LIMIT                  = 0x00004806,
 228         GUEST_FS_LIMIT                  = 0x00004808,
 229         GUEST_GS_LIMIT                  = 0x0000480a,
 230         GUEST_LDTR_LIMIT                = 0x0000480c,
 231         GUEST_TR_LIMIT                  = 0x0000480e,
 232         GUEST_GDTR_LIMIT                = 0x00004810,
 233         GUEST_IDTR_LIMIT                = 0x00004812,
 234         GUEST_ES_AR_BYTES               = 0x00004814,
 235         GUEST_CS_AR_BYTES               = 0x00004816,
 236         GUEST_SS_AR_BYTES               = 0x00004818,
 237         GUEST_DS_AR_BYTES               = 0x0000481a,
 238         GUEST_FS_AR_BYTES               = 0x0000481c,
 239         GUEST_GS_AR_BYTES               = 0x0000481e,
 240         GUEST_LDTR_AR_BYTES             = 0x00004820,
 241         GUEST_TR_AR_BYTES               = 0x00004822,
 242         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
 243         GUEST_ACTIVITY_STATE            = 0X00004826,
 244         GUEST_SYSENTER_CS               = 0x0000482A,
 245         VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
 246         HOST_IA32_SYSENTER_CS           = 0x00004c00,
 247         CR0_GUEST_HOST_MASK             = 0x00006000,
 248         CR4_GUEST_HOST_MASK             = 0x00006002,
 249         CR0_READ_SHADOW                 = 0x00006004,
 250         CR4_READ_SHADOW                 = 0x00006006,
 251         CR3_TARGET_VALUE0               = 0x00006008,
 252         CR3_TARGET_VALUE1               = 0x0000600a,
 253         CR3_TARGET_VALUE2               = 0x0000600c,
 254         CR3_TARGET_VALUE3               = 0x0000600e,
 255         EXIT_QUALIFICATION              = 0x00006400,
 256         GUEST_LINEAR_ADDRESS            = 0x0000640a,
 257         GUEST_CR0                       = 0x00006800,
 258         GUEST_CR3                       = 0x00006802,
 259         GUEST_CR4                       = 0x00006804,
 260         GUEST_ES_BASE                   = 0x00006806,
 261         GUEST_CS_BASE                   = 0x00006808,
 262         GUEST_SS_BASE                   = 0x0000680a,
 263         GUEST_DS_BASE                   = 0x0000680c,
 264         GUEST_FS_BASE                   = 0x0000680e,
 265         GUEST_GS_BASE                   = 0x00006810,
 266         GUEST_LDTR_BASE                 = 0x00006812,
 267         GUEST_TR_BASE                   = 0x00006814,
 268         GUEST_GDTR_BASE                 = 0x00006816,
 269         GUEST_IDTR_BASE                 = 0x00006818,
 270         GUEST_DR7                       = 0x0000681a,
 271         GUEST_RSP                       = 0x0000681c,
 272         GUEST_RIP                       = 0x0000681e,
 273         GUEST_RFLAGS                    = 0x00006820,
 274         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
 275         GUEST_SYSENTER_ESP              = 0x00006824,
 276         GUEST_SYSENTER_EIP              = 0x00006826,
 277         HOST_CR0                        = 0x00006c00,
 278         HOST_CR3                        = 0x00006c02,
 279         HOST_CR4                        = 0x00006c04,
 280         HOST_FS_BASE                    = 0x00006c06,
 281         HOST_GS_BASE                    = 0x00006c08,
 282         HOST_TR_BASE                    = 0x00006c0a,
 283         HOST_GDTR_BASE                  = 0x00006c0c,
 284         HOST_IDTR_BASE                  = 0x00006c0e,
 285         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
 286         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
 287         HOST_RSP                        = 0x00006c14,
 288         HOST_RIP                        = 0x00006c16,
 289 };
 290
 291 /*
 292  * Interruption-information format
 293  */
 294 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
 295 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
 296 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
 297 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
 298 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
 299 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
 300
 301 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
 302 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
 303 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
 304 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
 305
 306 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
 307 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
 308 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
 309 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
 310 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
 311
 312 /* GUEST_INTERRUPTIBILITY_INFO flags. */
 313 #define GUEST_INTR_STATE_STI            0x00000001
 314 #define GUEST_INTR_STATE_MOV_SS         0x00000002
 315 #define GUEST_INTR_STATE_SMI            0x00000004
 316 #define GUEST_INTR_STATE_NMI            0x00000008
 317
 318 /* GUEST_ACTIVITY_STATE flags */
 319 #define GUEST_ACTIVITY_ACTIVE           0
 320 #define GUEST_ACTIVITY_HLT              1
 321 #define GUEST_ACTIVITY_SHUTDOWN         2
 322 #define GUEST_ACTIVITY_WAIT_SIPI        3
 323
 324 /*
 325  * Exit Qualifications for MOV for Control Register Access
 326  */
 327 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
 328 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
 329 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
 330 #define LMSW_SOURCE_DATA_SHIFT 16
 331 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
 332 #define REG_EAX                         (0 << 8)
 333 #define REG_ECX                         (1 << 8)
 334 #define REG_EDX                         (2 << 8)
 335 #define REG_EBX                         (3 << 8)
 336 #define REG_ESP                         (4 << 8)
 337 #define REG_EBP                         (5 << 8)
 338 #define REG_ESI                         (6 << 8)
 339 #define REG_EDI                         (7 << 8)
 340 #define REG_R8                         (8 << 8)
 341 #define REG_R9                         (9 << 8)
 342 #define REG_R10                        (10 << 8)
 343 #define REG_R11                        (11 << 8)
 344 #define REG_R12                        (12 << 8)
 345 #define REG_R13                        (13 << 8)
 346 #define REG_R14                        (14 << 8)
 347 #define REG_R15                        (15 << 8)
 348
 349 /*
 350  * Exit Qualifications for MOV for Debug Register Access
 351  */
 352 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
 353 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
 354 #define TYPE_MOV_TO_DR                  (0 << 4)
 355 #define TYPE_MOV_FROM_DR                (1 << 4)
 356 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
 357
 358
 359 /*
 360  * Exit Qualifications for APIC-Access
 361  */
 362 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
 363 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
 364 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
 365 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
 366 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
 367 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
 368 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
 369 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
 370
 371 /* segment AR in VMCS -- these are different from what LAR reports */
 372 #define VMX_SEGMENT_AR_L_MASK (1 << 13)
 373
 374 #define VMX_AR_TYPE_ACCESSES_MASK 1
 375 #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
 376 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
 377 #define VMX_AR_TYPE_CODE_MASK (1 << 3)
 378 #define VMX_AR_TYPE_MASK 0x0f
 379 #define VMX_AR_TYPE_BUSY_64_TSS 11
 380 #define VMX_AR_TYPE_BUSY_32_TSS 11
 381 #define VMX_AR_TYPE_BUSY_16_TSS 3
 382 #define VMX_AR_TYPE_LDT 2
 383
 384 #define VMX_AR_UNUSABLE_MASK (1 << 16)
 385 #define VMX_AR_S_MASK (1 << 4)
 386 #define VMX_AR_P_MASK (1 << 7)
 387 #define VMX_AR_L_MASK (1 << 13)
 388 #define VMX_AR_DB_MASK (1 << 14)
 389 #define VMX_AR_G_MASK (1 << 15)
 390 #define VMX_AR_DPL_SHIFT 5
 391 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
 392
 393 #define VMX_AR_RESERVD_MASK 0xfffe0f00
 394
 395 #define TSS_PRIVATE_MEMSLOT                     (KVM_USER_MEM_SLOTS + 0)
 396 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_USER_MEM_SLOTS + 1)
 397 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_USER_MEM_SLOTS + 2)
 398
 399 #define VMX_NR_VPIDS                            (1 << 16)
 400 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
 401 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
 402
 403 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
 404 #define VMX_EPT_EXTENT_CONTEXT                  1
 405 #define VMX_EPT_EXTENT_GLOBAL                   2
 406 #define VMX_EPT_EXTENT_SHIFT                    24
 407
 408 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
 409 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
 410 #define VMX_EPTP_UC_BIT                         (1ull << 8)
 411 #define VMX_EPTP_WB_BIT                         (1ull << 14)
 412 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
 413 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
 414 #define VMX_EPT_INVEPT_BIT                      (1ull << 20)
 415 #define VMX_EPT_AD_BIT                              (1ull << 21)
 416 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 417 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 418
 419 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
 420 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
 421
 422 #define VMX_EPT_DEFAULT_GAW                     3
 423 #define VMX_EPT_MAX_GAW                         0x4
 424 #define VMX_EPT_MT_EPTE_SHIFT                   3
 425 #define VMX_EPT_GAW_EPTP_SHIFT                  3
 426 #define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
 427 #define VMX_EPT_DEFAULT_MT                      0x6ull
 428 #define VMX_EPT_READABLE_MASK                   0x1ull
 429 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 430 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
 431 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
 432 #define VMX_EPT_ACCESS_BIT                              (1ull << 8)
 433 #define VMX_EPT_DIRTY_BIT                               (1ull << 9)
 434
 435 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 436
 437
 438 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
 439 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
 440 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
 441 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
 442 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
 443 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
 444 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
 445 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
 446 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
 447 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
 448 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
 449
 450 struct vmx_msr_entry {
 451         u32 index;
 452         u32 reserved;
 453         u64 value;
 454 } __aligned(16);
 455
 456 /*
 457  * Exit Qualifications for entry failure during or after loading guest state
 458  */
 459 #define ENTRY_FAIL_DEFAULT              0
 460 #define ENTRY_FAIL_PDPTE                2
 461 #define ENTRY_FAIL_NMI                  3
 462 #define ENTRY_FAIL_VMCS_LINK_PTR        4
 463
 464 /*
 465  * VM-instruction error numbers
 466  */
 467 enum vm_instruction_error_number {
 468         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
 469         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
 470         VMXERR_VMCLEAR_VMXON_POINTER = 3,
 471         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
 472         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
 473         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
 474         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
 475         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
 476         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
 477         VMXERR_VMPTRLD_VMXON_POINTER = 10,
 478         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
 479         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
 480         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
 481         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
 482         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
 483         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
 484         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
 485         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
 486         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
 487         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
 488         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
 489         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
 490         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
 491         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
 492         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
 493 };
 494
 495 #endif