1 #ifndef _ASM_X86_MSR_INDEX_H
2 #define _ASM_X86_MSR_INDEX_H
4 /* CPU model specific register (MSR) numbers */
6 /* x86-64 specific MSRs */
7 #define MSR_EFER 0xc0000080 /* extended feature register */
8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
19 #define _EFER_LME 8 /* Long mode enable */
20 #define _EFER_LMA 10 /* Long mode active (read-only) */
21 #define _EFER_NX 11 /* No execute enable */
22 #define _EFER_SVME 12 /* Enable virtualization */
23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
26 #define EFER_SCE (1<<_EFER_SCE)
27 #define EFER_LME (1<<_EFER_LME)
28 #define EFER_LMA (1<<_EFER_LMA)
29 #define EFER_NX (1<<_EFER_NX)
30 #define EFER_SVME (1<<_EFER_SVME)
31 #define EFER_LMSLE (1<<_EFER_LMSLE)
32 #define EFER_FFXSR (1<<_EFER_FFXSR)
34 /* Intel MSRs. Some also available on other CPUs */
35 #define MSR_IA32_PERFCTR0 0x000000c1
36 #define MSR_IA32_PERFCTR1 0x000000c2
37 #define MSR_FSB_FREQ 0x000000cd
38 #define MSR_NHM_PLATFORM_INFO 0x000000ce
40 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
41 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
42 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
43 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
44 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
45 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
47 #define MSR_PLATFORM_INFO 0x000000ce
48 #define MSR_MTRRcap 0x000000fe
49 #define MSR_IA32_BBL_CR_CTL 0x00000119
50 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
52 #define MSR_IA32_SYSENTER_CS 0x00000174
53 #define MSR_IA32_SYSENTER_ESP 0x00000175
54 #define MSR_IA32_SYSENTER_EIP 0x00000176
56 #define MSR_IA32_MCG_CAP 0x00000179
57 #define MSR_IA32_MCG_STATUS 0x0000017a
58 #define MSR_IA32_MCG_CTL 0x0000017b
60 #define MSR_OFFCORE_RSP_0 0x000001a6
61 #define MSR_OFFCORE_RSP_1 0x000001a7
62 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
63 #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
65 #define MSR_LBR_SELECT 0x000001c8
66 #define MSR_LBR_TOS 0x000001c9
67 #define MSR_LBR_NHM_FROM 0x00000680
68 #define MSR_LBR_NHM_TO 0x000006c0
69 #define MSR_LBR_CORE_FROM 0x00000040
70 #define MSR_LBR_CORE_TO 0x00000060
72 #define MSR_IA32_PEBS_ENABLE 0x000003f1
73 #define MSR_IA32_DS_AREA 0x00000600
74 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
75 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
77 #define MSR_MTRRfix64K_00000 0x00000250
78 #define MSR_MTRRfix16K_80000 0x00000258
79 #define MSR_MTRRfix16K_A0000 0x00000259
80 #define MSR_MTRRfix4K_C0000 0x00000268
81 #define MSR_MTRRfix4K_C8000 0x00000269
82 #define MSR_MTRRfix4K_D0000 0x0000026a
83 #define MSR_MTRRfix4K_D8000 0x0000026b
84 #define MSR_MTRRfix4K_E0000 0x0000026c
85 #define MSR_MTRRfix4K_E8000 0x0000026d
86 #define MSR_MTRRfix4K_F0000 0x0000026e
87 #define MSR_MTRRfix4K_F8000 0x0000026f
88 #define MSR_MTRRdefType 0x000002ff
90 #define MSR_IA32_CR_PAT 0x00000277
92 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
93 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
94 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
95 #define MSR_IA32_LASTINTFROMIP 0x000001dd
96 #define MSR_IA32_LASTINTTOIP 0x000001de
98 /* DEBUGCTLMSR bits (others vary by model): */
99 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
100 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
101 #define DEBUGCTLMSR_TR (1UL << 6)
102 #define DEBUGCTLMSR_BTS (1UL << 7)
103 #define DEBUGCTLMSR_BTINT (1UL << 8)
104 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
105 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
106 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
108 #define MSR_IA32_POWER_CTL 0x000001fc
110 #define MSR_IA32_MC0_CTL 0x00000400
111 #define MSR_IA32_MC0_STATUS 0x00000401
112 #define MSR_IA32_MC0_ADDR 0x00000402
113 #define MSR_IA32_MC0_MISC 0x00000403
115 /* C-state Residency Counters */
116 #define MSR_PKG_C3_RESIDENCY 0x000003f8
117 #define MSR_PKG_C6_RESIDENCY 0x000003f9
118 #define MSR_PKG_C7_RESIDENCY 0x000003fa
119 #define MSR_CORE_C3_RESIDENCY 0x000003fc
120 #define MSR_CORE_C6_RESIDENCY 0x000003fd
121 #define MSR_CORE_C7_RESIDENCY 0x000003fe
122 #define MSR_PKG_C2_RESIDENCY 0x0000060d
123 #define MSR_PKG_C8_RESIDENCY 0x00000630
124 #define MSR_PKG_C9_RESIDENCY 0x00000631
125 #define MSR_PKG_C10_RESIDENCY 0x00000632
127 /* Run Time Average Power Limiting (RAPL) Interface */
129 #define MSR_RAPL_POWER_UNIT 0x00000606
131 #define MSR_PKG_POWER_LIMIT 0x00000610
132 #define MSR_PKG_ENERGY_STATUS 0x00000611
133 #define MSR_PKG_PERF_STATUS 0x00000613
134 #define MSR_PKG_POWER_INFO 0x00000614
136 #define MSR_DRAM_POWER_LIMIT 0x00000618
137 #define MSR_DRAM_ENERGY_STATUS 0x00000619
138 #define MSR_DRAM_PERF_STATUS 0x0000061b
139 #define MSR_DRAM_POWER_INFO 0x0000061c
141 #define MSR_PP0_POWER_LIMIT 0x00000638
142 #define MSR_PP0_ENERGY_STATUS 0x00000639
143 #define MSR_PP0_POLICY 0x0000063a
144 #define MSR_PP0_PERF_STATUS 0x0000063b
146 #define MSR_PP1_POWER_LIMIT 0x00000640
147 #define MSR_PP1_ENERGY_STATUS 0x00000641
148 #define MSR_PP1_POLICY 0x00000642
150 #define MSR_CORE_C1_RES 0x00000660
152 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
153 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
155 /* Hardware P state interface */
156 #define MSR_PPERF 0x0000064e
157 #define MSR_PERF_LIMIT_REASONS 0x0000064f
158 #define MSR_PM_ENABLE 0x00000770
159 #define MSR_HWP_CAPABILITIES 0x00000771
160 #define MSR_HWP_REQUEST_PKG 0x00000772
161 #define MSR_HWP_INTERRUPT 0x00000773
162 #define MSR_HWP_REQUEST 0x00000774
163 #define MSR_HWP_STATUS 0x00000777
166 #define HWP_BASE_BIT (1<<7)
167 #define HWP_NOTIFICATIONS_BIT (1<<8)
168 #define HWP_ACTIVITY_WINDOW_BIT (1<<9)
169 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
170 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
172 /* IA32_HWP_CAPABILITIES */
173 #define HWP_HIGHEST_PERF(x) (x & 0xff)
174 #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8)
175 #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16)
176 #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24)
178 /* IA32_HWP_REQUEST */
179 #define HWP_MIN_PERF(x) (x & 0xff)
180 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
181 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
182 #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24)
183 #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32)
184 #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42)
186 /* IA32_HWP_STATUS */
187 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
188 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
190 /* IA32_HWP_INTERRUPT */
191 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
192 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
194 #define MSR_AMD64_MC0_MASK 0xc0010044
196 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
197 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
198 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
199 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
201 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
203 /* These are consecutive and not in the normal 4er MCE bank block */
204 #define MSR_IA32_MC0_CTL2 0x00000280
205 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
207 #define MSR_P6_PERFCTR0 0x000000c1
208 #define MSR_P6_PERFCTR1 0x000000c2
209 #define MSR_P6_EVNTSEL0 0x00000186
210 #define MSR_P6_EVNTSEL1 0x00000187
212 #define MSR_KNC_PERFCTR0 0x00000020
213 #define MSR_KNC_PERFCTR1 0x00000021
214 #define MSR_KNC_EVNTSEL0 0x00000028
215 #define MSR_KNC_EVNTSEL1 0x00000029
217 /* Alternative perfctr range with full access. */
218 #define MSR_IA32_PMC0 0x000004c1
220 /* AMD64 MSRs. Not complete. See the architecture manual for a more
223 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
224 #define MSR_AMD64_TSC_RATIO 0xc0000104
225 #define MSR_AMD64_NB_CFG 0xc001001f
226 #define MSR_AMD64_PATCH_LOADER 0xc0010020
227 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
228 #define MSR_AMD64_OSVW_STATUS 0xc0010141
229 #define MSR_AMD64_LS_CFG 0xc0011020
230 #define MSR_AMD64_DC_CFG 0xc0011022
231 #define MSR_AMD64_BU_CFG2 0xc001102a
232 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
233 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
234 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
235 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
236 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
237 #define MSR_AMD64_IBSOPCTL 0xc0011033
238 #define MSR_AMD64_IBSOPRIP 0xc0011034
239 #define MSR_AMD64_IBSOPDATA 0xc0011035
240 #define MSR_AMD64_IBSOPDATA2 0xc0011036
241 #define MSR_AMD64_IBSOPDATA3 0xc0011037
242 #define MSR_AMD64_IBSDCLINAD 0xc0011038
243 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
244 #define MSR_AMD64_IBSOP_REG_COUNT 7
245 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
246 #define MSR_AMD64_IBSCTL 0xc001103a
247 #define MSR_AMD64_IBSBRTARGET 0xc001103b
248 #define MSR_AMD64_IBSOPDATA4 0xc001103d
249 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
252 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
253 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
254 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
255 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
256 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
257 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
260 #define MSR_F15H_PERF_CTL 0xc0010200
261 #define MSR_F15H_PERF_CTR 0xc0010201
262 #define MSR_F15H_NB_PERF_CTL 0xc0010240
263 #define MSR_F15H_NB_PERF_CTR 0xc0010241
266 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
267 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
268 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
269 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
270 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
271 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
272 #define MSR_FAM10H_NODE_ID 0xc001100c
275 #define MSR_K8_TOP_MEM1 0xc001001a
276 #define MSR_K8_TOP_MEM2 0xc001001d
277 #define MSR_K8_SYSCFG 0xc0010010
278 #define MSR_K8_INT_PENDING_MSG 0xc0010055
279 /* C1E active bits in int pending message */
280 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
281 #define MSR_K8_TSEG_ADDR 0xc0010112
282 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
283 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
284 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
287 #define MSR_K7_EVNTSEL0 0xc0010000
288 #define MSR_K7_PERFCTR0 0xc0010004
289 #define MSR_K7_EVNTSEL1 0xc0010001
290 #define MSR_K7_PERFCTR1 0xc0010005
291 #define MSR_K7_EVNTSEL2 0xc0010002
292 #define MSR_K7_PERFCTR2 0xc0010006
293 #define MSR_K7_EVNTSEL3 0xc0010003
294 #define MSR_K7_PERFCTR3 0xc0010007
295 #define MSR_K7_CLK_CTL 0xc001001b
296 #define MSR_K7_HWCR 0xc0010015
297 #define MSR_K7_FID_VID_CTL 0xc0010041
298 #define MSR_K7_FID_VID_STATUS 0xc0010042
301 #define MSR_K6_WHCR 0xc0000082
302 #define MSR_K6_UWCCR 0xc0000085
303 #define MSR_K6_EPMR 0xc0000086
304 #define MSR_K6_PSOR 0xc0000087
305 #define MSR_K6_PFIR 0xc0000088
307 /* Centaur-Hauls/IDT defined MSRs. */
308 #define MSR_IDT_FCR1 0x00000107
309 #define MSR_IDT_FCR2 0x00000108
310 #define MSR_IDT_FCR3 0x00000109
311 #define MSR_IDT_FCR4 0x0000010a
313 #define MSR_IDT_MCR0 0x00000110
314 #define MSR_IDT_MCR1 0x00000111
315 #define MSR_IDT_MCR2 0x00000112
316 #define MSR_IDT_MCR3 0x00000113
317 #define MSR_IDT_MCR4 0x00000114
318 #define MSR_IDT_MCR5 0x00000115
319 #define MSR_IDT_MCR6 0x00000116
320 #define MSR_IDT_MCR7 0x00000117
321 #define MSR_IDT_MCR_CTRL 0x00000120
323 /* VIA Cyrix defined MSRs*/
324 #define MSR_VIA_FCR 0x00001107
325 #define MSR_VIA_LONGHAUL 0x0000110a
326 #define MSR_VIA_RNG 0x0000110b
327 #define MSR_VIA_BCR2 0x00001147
329 /* Transmeta defined MSRs */
330 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
331 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
332 #define MSR_TMTA_LRTI_READOUT 0x80868018
333 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
335 /* Intel defined MSRs. */
336 #define MSR_IA32_P5_MC_ADDR 0x00000000
337 #define MSR_IA32_P5_MC_TYPE 0x00000001
338 #define MSR_IA32_TSC 0x00000010
339 #define MSR_IA32_PLATFORM_ID 0x00000017
340 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
341 #define MSR_EBC_FREQUENCY_ID 0x0000002c
342 #define MSR_SMI_COUNT 0x00000034
343 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
344 #define MSR_IA32_TSC_ADJUST 0x0000003b
345 #define MSR_IA32_BNDCFGS 0x00000d90
347 #define MSR_IA32_XSS 0x00000da0
349 #define FEATURE_CONTROL_LOCKED (1<<0)
350 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
351 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
353 #define MSR_IA32_APICBASE 0x0000001b
354 #define MSR_IA32_APICBASE_BSP (1<<8)
355 #define MSR_IA32_APICBASE_ENABLE (1<<11)
356 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
358 #define MSR_IA32_TSCDEADLINE 0x000006e0
360 #define MSR_IA32_UCODE_WRITE 0x00000079
361 #define MSR_IA32_UCODE_REV 0x0000008b
363 #define MSR_IA32_PERF_STATUS 0x00000198
364 #define MSR_IA32_PERF_CTL 0x00000199
365 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
366 #define MSR_AMD_PERF_STATUS 0xc0010063
367 #define MSR_AMD_PERF_CTL 0xc0010062
369 #define MSR_IA32_MPERF 0x000000e7
370 #define MSR_IA32_APERF 0x000000e8
372 #define MSR_IA32_THERM_CONTROL 0x0000019a
373 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
375 #define THERM_INT_HIGH_ENABLE (1 << 0)
376 #define THERM_INT_LOW_ENABLE (1 << 1)
377 #define THERM_INT_PLN_ENABLE (1 << 24)
379 #define MSR_IA32_THERM_STATUS 0x0000019c
381 #define THERM_STATUS_PROCHOT (1 << 0)
382 #define THERM_STATUS_POWER_LIMIT (1 << 10)
384 #define MSR_THERM2_CTL 0x0000019d
386 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
388 #define MSR_IA32_MISC_ENABLE 0x000001a0
390 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
392 #define MSR_MISC_PWR_MGMT 0x000001aa
394 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
395 #define ENERGY_PERF_BIAS_PERFORMANCE 0
396 #define ENERGY_PERF_BIAS_NORMAL 6
397 #define ENERGY_PERF_BIAS_POWERSAVE 15
399 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
401 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
402 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
404 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
406 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
407 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
408 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
410 /* Thermal Thresholds Support */
411 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
412 #define THERM_SHIFT_THRESHOLD0 8
413 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
414 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
415 #define THERM_SHIFT_THRESHOLD1 16
416 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
417 #define THERM_STATUS_THRESHOLD0 (1 << 6)
418 #define THERM_LOG_THRESHOLD0 (1 << 7)
419 #define THERM_STATUS_THRESHOLD1 (1 << 8)
420 #define THERM_LOG_THRESHOLD1 (1 << 9)
422 /* MISC_ENABLE bits: architectural */
423 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
424 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
425 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1
426 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
427 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7
428 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
429 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
430 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
431 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
432 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
433 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
434 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
435 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
436 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
437 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
438 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
439 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
440 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
441 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
442 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
444 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
445 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
446 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
447 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3
448 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
449 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
450 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
451 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
452 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
453 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
454 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
455 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
456 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
457 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10
458 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
459 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
460 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
461 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13
462 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
463 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
464 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
465 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
466 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
467 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
468 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
469 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
470 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
471 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
472 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
473 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
474 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
476 #define MSR_IA32_TSC_DEADLINE 0x000006E0
478 /* P4/Xeon+ specific */
479 #define MSR_IA32_MCG_EAX 0x00000180
480 #define MSR_IA32_MCG_EBX 0x00000181
481 #define MSR_IA32_MCG_ECX 0x00000182
482 #define MSR_IA32_MCG_EDX 0x00000183
483 #define MSR_IA32_MCG_ESI 0x00000184
484 #define MSR_IA32_MCG_EDI 0x00000185
485 #define MSR_IA32_MCG_EBP 0x00000186
486 #define MSR_IA32_MCG_ESP 0x00000187
487 #define MSR_IA32_MCG_EFLAGS 0x00000188
488 #define MSR_IA32_MCG_EIP 0x00000189
489 #define MSR_IA32_MCG_RESERVED 0x0000018a
491 /* Pentium IV performance counter MSRs */
492 #define MSR_P4_BPU_PERFCTR0 0x00000300
493 #define MSR_P4_BPU_PERFCTR1 0x00000301
494 #define MSR_P4_BPU_PERFCTR2 0x00000302
495 #define MSR_P4_BPU_PERFCTR3 0x00000303
496 #define MSR_P4_MS_PERFCTR0 0x00000304
497 #define MSR_P4_MS_PERFCTR1 0x00000305
498 #define MSR_P4_MS_PERFCTR2 0x00000306
499 #define MSR_P4_MS_PERFCTR3 0x00000307
500 #define MSR_P4_FLAME_PERFCTR0 0x00000308
501 #define MSR_P4_FLAME_PERFCTR1 0x00000309
502 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
503 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
504 #define MSR_P4_IQ_PERFCTR0 0x0000030c
505 #define MSR_P4_IQ_PERFCTR1 0x0000030d
506 #define MSR_P4_IQ_PERFCTR2 0x0000030e
507 #define MSR_P4_IQ_PERFCTR3 0x0000030f
508 #define MSR_P4_IQ_PERFCTR4 0x00000310
509 #define MSR_P4_IQ_PERFCTR5 0x00000311
510 #define MSR_P4_BPU_CCCR0 0x00000360
511 #define MSR_P4_BPU_CCCR1 0x00000361
512 #define MSR_P4_BPU_CCCR2 0x00000362
513 #define MSR_P4_BPU_CCCR3 0x00000363
514 #define MSR_P4_MS_CCCR0 0x00000364
515 #define MSR_P4_MS_CCCR1 0x00000365
516 #define MSR_P4_MS_CCCR2 0x00000366
517 #define MSR_P4_MS_CCCR3 0x00000367
518 #define MSR_P4_FLAME_CCCR0 0x00000368
519 #define MSR_P4_FLAME_CCCR1 0x00000369
520 #define MSR_P4_FLAME_CCCR2 0x0000036a
521 #define MSR_P4_FLAME_CCCR3 0x0000036b
522 #define MSR_P4_IQ_CCCR0 0x0000036c
523 #define MSR_P4_IQ_CCCR1 0x0000036d
524 #define MSR_P4_IQ_CCCR2 0x0000036e
525 #define MSR_P4_IQ_CCCR3 0x0000036f
526 #define MSR_P4_IQ_CCCR4 0x00000370
527 #define MSR_P4_IQ_CCCR5 0x00000371
528 #define MSR_P4_ALF_ESCR0 0x000003ca
529 #define MSR_P4_ALF_ESCR1 0x000003cb
530 #define MSR_P4_BPU_ESCR0 0x000003b2
531 #define MSR_P4_BPU_ESCR1 0x000003b3
532 #define MSR_P4_BSU_ESCR0 0x000003a0
533 #define MSR_P4_BSU_ESCR1 0x000003a1
534 #define MSR_P4_CRU_ESCR0 0x000003b8
535 #define MSR_P4_CRU_ESCR1 0x000003b9
536 #define MSR_P4_CRU_ESCR2 0x000003cc
537 #define MSR_P4_CRU_ESCR3 0x000003cd
538 #define MSR_P4_CRU_ESCR4 0x000003e0
539 #define MSR_P4_CRU_ESCR5 0x000003e1
540 #define MSR_P4_DAC_ESCR0 0x000003a8
541 #define MSR_P4_DAC_ESCR1 0x000003a9
542 #define MSR_P4_FIRM_ESCR0 0x000003a4
543 #define MSR_P4_FIRM_ESCR1 0x000003a5
544 #define MSR_P4_FLAME_ESCR0 0x000003a6
545 #define MSR_P4_FLAME_ESCR1 0x000003a7
546 #define MSR_P4_FSB_ESCR0 0x000003a2
547 #define MSR_P4_FSB_ESCR1 0x000003a3
548 #define MSR_P4_IQ_ESCR0 0x000003ba
549 #define MSR_P4_IQ_ESCR1 0x000003bb
550 #define MSR_P4_IS_ESCR0 0x000003b4
551 #define MSR_P4_IS_ESCR1 0x000003b5
552 #define MSR_P4_ITLB_ESCR0 0x000003b6
553 #define MSR_P4_ITLB_ESCR1 0x000003b7
554 #define MSR_P4_IX_ESCR0 0x000003c8
555 #define MSR_P4_IX_ESCR1 0x000003c9
556 #define MSR_P4_MOB_ESCR0 0x000003aa
557 #define MSR_P4_MOB_ESCR1 0x000003ab
558 #define MSR_P4_MS_ESCR0 0x000003c0
559 #define MSR_P4_MS_ESCR1 0x000003c1
560 #define MSR_P4_PMH_ESCR0 0x000003ac
561 #define MSR_P4_PMH_ESCR1 0x000003ad
562 #define MSR_P4_RAT_ESCR0 0x000003bc
563 #define MSR_P4_RAT_ESCR1 0x000003bd
564 #define MSR_P4_SAAT_ESCR0 0x000003ae
565 #define MSR_P4_SAAT_ESCR1 0x000003af
566 #define MSR_P4_SSU_ESCR0 0x000003be
567 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
569 #define MSR_P4_TBPU_ESCR0 0x000003c2
570 #define MSR_P4_TBPU_ESCR1 0x000003c3
571 #define MSR_P4_TC_ESCR0 0x000003c4
572 #define MSR_P4_TC_ESCR1 0x000003c5
573 #define MSR_P4_U2L_ESCR0 0x000003b0
574 #define MSR_P4_U2L_ESCR1 0x000003b1
576 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
578 /* Intel Core-based CPU performance counters */
579 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
580 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
581 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
582 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
583 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
584 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
585 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
587 /* Geode defined MSRs */
588 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
591 #define MSR_IA32_VMX_BASIC 0x00000480
592 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
593 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
594 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
595 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
596 #define MSR_IA32_VMX_MISC 0x00000485
597 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
598 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
599 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
600 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
601 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
602 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
603 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
604 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
605 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
606 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
607 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
608 #define MSR_IA32_VMX_VMFUNC 0x00000491
610 /* VMX_BASIC bits and bitmasks */
611 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
612 #define VMX_BASIC_TRUE_CTLS (1ULL << 55)
613 #define VMX_BASIC_64 0x0001000000000000LLU
614 #define VMX_BASIC_MEM_TYPE_SHIFT 50
615 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
616 #define VMX_BASIC_MEM_TYPE_WB 6LLU
617 #define VMX_BASIC_INOUT 0x0040000000000000LLU
619 /* MSR_IA32_VMX_MISC bits */
620 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
621 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
624 #define MSR_VM_CR 0xc0010114
625 #define MSR_VM_IGNNE 0xc0010115
626 #define MSR_VM_HSAVE_PA 0xc0010117
628 #endif /* _ASM_X86_MSR_INDEX_H */