arch/x86/kernel/apic/apic_numachip.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Numascale NumaConnect-Specific APIC Code
   7  *
   8  * Copyright (C) 2011 Numascale AS. All rights reserved.
   9  *
  10  * Send feedback to <support@numascale.com>
  11  *
  12  */
  13
  14 #include <linux/init.h>
  15
  16 #include <asm/numachip/numachip.h>
  17 #include <asm/numachip/numachip_csr.h>
  18 #include <asm/ipi.h>
  19 #include <asm/apic_flat_64.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/pci_x86.h>
  22
  23 u8 numachip_system __read_mostly;
  24 static const struct apic apic_numachip1;
  25 static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
  26
  27 static unsigned int numachip1_get_apic_id(unsigned long x)
  28 {
  29         unsigned long value;
  30         unsigned int id = (x >> 24) & 0xff;
  31
  32         if (static_cpu_has_safe(X86_FEATURE_NODEID_MSR)) {
  33                 rdmsrl(MSR_FAM10H_NODE_ID, value);
  34                 id |= (value << 2) & 0xff00;
  35         }
  36
  37         return id;
  38 }
  39
  40 static unsigned long numachip1_set_apic_id(unsigned int id)
  41 {
  42         unsigned long x;
  43
  44         x = ((id & 0xffU) << 24);
  45         return x;
  46 }
  47
  48 static int numachip_apic_id_valid(int apicid)
  49 {
  50         /* Trust what bootloader passes in MADT */
  51         return 1;
  52 }
  53
  54 static int numachip_apic_id_registered(void)
  55 {
  56         return 1;
  57 }
  58
  59 static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
  60 {
  61         return initial_apic_id >> index_msb;
  62 }
  63
  64 static void numachip1_apic_icr_write(int apicid, unsigned int val)
  65 {
  66         write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
  67 }
  68
  69 static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
  70 {
  71         numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
  72         numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
  73                 (start_rip >> 12));
  74
  75         return 0;
  76 }
  77
  78 static void numachip_send_IPI_one(int cpu, int vector)
  79 {
  80         int apicid = per_cpu(x86_cpu_to_apicid, cpu);
  81         unsigned int dmode;
  82
  83         dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
  84         numachip_apic_icr_write(apicid, dmode | vector);
  85 }
  86
  87 static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
  88 {
  89         unsigned int cpu;
  90
  91         for_each_cpu(cpu, mask)
  92                 numachip_send_IPI_one(cpu, vector);
  93 }
  94
  95 static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
  96                                                 int vector)
  97 {
  98         unsigned int this_cpu = smp_processor_id();
  99         unsigned int cpu;
 100
 101         for_each_cpu(cpu, mask) {
 102                 if (cpu != this_cpu)
 103                         numachip_send_IPI_one(cpu, vector);
 104         }
 105 }
 106
 107 static void numachip_send_IPI_allbutself(int vector)
 108 {
 109         unsigned int this_cpu = smp_processor_id();
 110         unsigned int cpu;
 111
 112         for_each_online_cpu(cpu) {
 113                 if (cpu != this_cpu)
 114                         numachip_send_IPI_one(cpu, vector);
 115         }
 116 }
 117
 118 static void numachip_send_IPI_all(int vector)
 119 {
 120         numachip_send_IPI_mask(cpu_online_mask, vector);
 121 }
 122
 123 static void numachip_send_IPI_self(int vector)
 124 {
 125         apic_write(APIC_SELF_IPI, vector);
 126 }
 127
 128 static int __init numachip1_probe(void)
 129 {
 130         return apic == &apic_numachip1;
 131 }
 132
 133 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 134 {
 135         u64 val;
 136         u32 nodes = 1;
 137
 138         this_cpu_write(cpu_llc_id, node);
 139
 140         /* Account for nodes per socket in multi-core-module processors */
 141         if (static_cpu_has_safe(X86_FEATURE_NODEID_MSR)) {
 142                 rdmsrl(MSR_FAM10H_NODE_ID, val);
 143                 nodes = ((val >> 3) & 7) + 1;
 144         }
 145
 146         c->phys_proc_id = node / nodes;
 147 }
 148
 149 static int __init numachip_system_init(void)
 150 {
 151         /* Map the LCSR area and set up the apic_icr_write function */
 152         switch (numachip_system) {
 153         case 1:
 154                 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
 155                 numachip_apic_icr_write = numachip1_apic_icr_write;
 156                 x86_init.pci.arch_init = pci_numachip_init;
 157                 break;
 158         default:
 159                 return 0;
 160         }
 161
 162         x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
 163
 164         return 0;
 165 }
 166 early_initcall(numachip_system_init);
 167
 168 static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 169 {
 170         if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
 171             (strncmp(oem_table_id, "NCONNECT", 8) != 0))
 172                 return 0;
 173
 174         numachip_system = 1;
 175
 176         return 1;
 177 }
 178
 179 static const struct apic apic_numachip1 __refconst = {
 180         .name                           = "NumaConnect system",
 181         .probe                          = numachip1_probe,
 182         .acpi_madt_oem_check            = numachip1_acpi_madt_oem_check,
 183         .apic_id_valid                  = numachip_apic_id_valid,
 184         .apic_id_registered             = numachip_apic_id_registered,
 185
 186         .irq_delivery_mode              = dest_Fixed,
 187         .irq_dest_mode                  = 0, /* physical */
 188
 189         .target_cpus                    = online_target_cpus,
 190         .disable_esr                    = 0,
 191         .dest_logical                   = 0,
 192         .check_apicid_used              = NULL,
 193
 194         .vector_allocation_domain       = default_vector_allocation_domain,
 195         .init_apic_ldr                  = flat_init_apic_ldr,
 196
 197         .ioapic_phys_id_map             = NULL,
 198         .setup_apic_routing             = NULL,
 199         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 200         .apicid_to_cpu_present          = NULL,
 201         .check_phys_apicid_present      = default_check_phys_apicid_present,
 202         .phys_pkg_id                    = numachip_phys_pkg_id,
 203
 204         .get_apic_id                    = numachip1_get_apic_id,
 205         .set_apic_id                    = numachip1_set_apic_id,
 206         .apic_id_mask                   = 0xffU << 24,
 207
 208         .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
 209
 210         .send_IPI_mask                  = numachip_send_IPI_mask,
 211         .send_IPI_mask_allbutself       = numachip_send_IPI_mask_allbutself,
 212         .send_IPI_allbutself            = numachip_send_IPI_allbutself,
 213         .send_IPI_all                   = numachip_send_IPI_all,
 214         .send_IPI_self                  = numachip_send_IPI_self,
 215
 216         .wakeup_secondary_cpu           = numachip_wakeup_secondary,
 217         .inquire_remote_apic            = NULL, /* REMRD not supported */
 218
 219         .read                           = native_apic_mem_read,
 220         .write                          = native_apic_mem_write,
 221         .eoi_write                      = native_apic_mem_write,
 222         .icr_read                       = native_apic_icr_read,
 223         .icr_write                      = native_apic_icr_write,
 224         .wait_icr_idle                  = native_apic_wait_icr_idle,
 225         .safe_wait_icr_idle             = native_safe_apic_wait_icr_idle,
 226 };
 227
 228 apic_driver(apic_numachip1);