arch/x86/kernel/apic/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <asm/apic.h>
  66
  67 #define __apicdebuginit(type) static type __init
  68
  69 /*
  70  *      Is the SiS APIC rmw bug present ?
  71  *      -1 = don't know, 0 = no, 1 = yes
  72  */
  73 int sis_apic_bug = -1;
  74
  75 static DEFINE_SPINLOCK(ioapic_lock);
  76 static DEFINE_SPINLOCK(vector_lock);
  77
  78 /*
  79  * # of IRQ routing registers
  80  */
  81 int nr_ioapic_registers[MAX_IO_APICS];
  82
  83 /* I/O APIC entries */
  84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  85 int nr_ioapics;
  86
  87 /* MP IRQ source entries */
  88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  89
  90 /* # of MP IRQ source entries */
  91 int mp_irq_entries;
  92
  93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  94 int mp_bus_id_to_type[MAX_MP_BUSSES];
  95 #endif
  96
  97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  98
  99 int skip_ioapic_setup;
 100
 101 void arch_disable_smp_support(void)
 102 {
 103 #ifdef CONFIG_PCI
 104         noioapicquirk = 1;
 105         noioapicreroute = -1;
 106 #endif
 107         skip_ioapic_setup = 1;
 108 }
 109
 110 static int __init parse_noapic(char *str)
 111 {
 112         /* disable IO-APIC */
 113         arch_disable_smp_support();
 114         return 0;
 115 }
 116 early_param("noapic", parse_noapic);
 117
 118 struct irq_pin_list;
 119
 120 /*
 121  * This is performance-critical, we want to do it O(1)
 122  *
 123  * the indexing order of this array favors 1:1 mappings
 124  * between pins and IRQs.
 125  */
 126
 127 struct irq_pin_list {
 128         int apic, pin;
 129         struct irq_pin_list *next;
 130 };
 131
 132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 133 {
 134         struct irq_pin_list *pin;
 135         int node;
 136
 137         node = cpu_to_node(cpu);
 138
 139         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 140
 141         return pin;
 142 }
 143
 144 struct irq_cfg {
 145         struct irq_pin_list *irq_2_pin;
 146         cpumask_var_t domain;
 147         cpumask_var_t old_domain;
 148         unsigned move_cleanup_count;
 149         u8 vector;
 150         u8 move_in_progress : 1;
 151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 152         u8 move_desc_pending : 1;
 153 #endif
 154 };
 155
 156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 157 #ifdef CONFIG_SPARSE_IRQ
 158 static struct irq_cfg irq_cfgx[] = {
 159 #else
 160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 161 #endif
 162         [0]  = { .vector = IRQ0_VECTOR,  },
 163         [1]  = { .vector = IRQ1_VECTOR,  },
 164         [2]  = { .vector = IRQ2_VECTOR,  },
 165         [3]  = { .vector = IRQ3_VECTOR,  },
 166         [4]  = { .vector = IRQ4_VECTOR,  },
 167         [5]  = { .vector = IRQ5_VECTOR,  },
 168         [6]  = { .vector = IRQ6_VECTOR,  },
 169         [7]  = { .vector = IRQ7_VECTOR,  },
 170         [8]  = { .vector = IRQ8_VECTOR,  },
 171         [9]  = { .vector = IRQ9_VECTOR,  },
 172         [10] = { .vector = IRQ10_VECTOR, },
 173         [11] = { .vector = IRQ11_VECTOR, },
 174         [12] = { .vector = IRQ12_VECTOR, },
 175         [13] = { .vector = IRQ13_VECTOR, },
 176         [14] = { .vector = IRQ14_VECTOR, },
 177         [15] = { .vector = IRQ15_VECTOR, },
 178 };
 179
 180 int __init arch_early_irq_init(void)
 181 {
 182         struct irq_cfg *cfg;
 183         struct irq_desc *desc;
 184         int count;
 185         int i;
 186
 187         cfg = irq_cfgx;
 188         count = ARRAY_SIZE(irq_cfgx);
 189
 190         for (i = 0; i < count; i++) {
 191                 desc = irq_to_desc(i);
 192                 desc->chip_data = &cfg[i];
 193                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 194                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 195                 if (i < NR_IRQS_LEGACY)
 196                         cpumask_setall(cfg[i].domain);
 197         }
 198
 199         return 0;
 200 }
 201
 202 #ifdef CONFIG_SPARSE_IRQ
 203 static struct irq_cfg *irq_cfg(unsigned int irq)
 204 {
 205         struct irq_cfg *cfg = NULL;
 206         struct irq_desc *desc;
 207
 208         desc = irq_to_desc(irq);
 209         if (desc)
 210                 cfg = desc->chip_data;
 211
 212         return cfg;
 213 }
 214
 215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 216 {
 217         struct irq_cfg *cfg;
 218         int node;
 219
 220         node = cpu_to_node(cpu);
 221
 222         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 223         if (cfg) {
 224                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 225                         kfree(cfg);
 226                         cfg = NULL;
 227                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 228                                                           GFP_ATOMIC, node)) {
 229                         free_cpumask_var(cfg->domain);
 230                         kfree(cfg);
 231                         cfg = NULL;
 232                 } else {
 233                         cpumask_clear(cfg->domain);
 234                         cpumask_clear(cfg->old_domain);
 235                 }
 236         }
 237
 238         return cfg;
 239 }
 240
 241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 242 {
 243         struct irq_cfg *cfg;
 244
 245         cfg = desc->chip_data;
 246         if (!cfg) {
 247                 desc->chip_data = get_one_free_irq_cfg(cpu);
 248                 if (!desc->chip_data) {
 249                         printk(KERN_ERR "can not alloc irq_cfg\n");
 250                         BUG_ON(1);
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 258
 259 static void
 260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 261 {
 262         struct irq_pin_list *old_entry, *head, *tail, *entry;
 263
 264         cfg->irq_2_pin = NULL;
 265         old_entry = old_cfg->irq_2_pin;
 266         if (!old_entry)
 267                 return;
 268
 269         entry = get_one_free_irq_2_pin(cpu);
 270         if (!entry)
 271                 return;
 272
 273         entry->apic     = old_entry->apic;
 274         entry->pin      = old_entry->pin;
 275         head            = entry;
 276         tail            = entry;
 277         old_entry       = old_entry->next;
 278         while (old_entry) {
 279                 entry = get_one_free_irq_2_pin(cpu);
 280                 if (!entry) {
 281                         entry = head;
 282                         while (entry) {
 283                                 head = entry->next;
 284                                 kfree(entry);
 285                                 entry = head;
 286                         }
 287                         /* still use the old one */
 288                         return;
 289                 }
 290                 entry->apic     = old_entry->apic;
 291                 entry->pin      = old_entry->pin;
 292                 tail->next      = entry;
 293                 tail            = entry;
 294                 old_entry       = old_entry->next;
 295         }
 296
 297         tail->next = NULL;
 298         cfg->irq_2_pin = head;
 299 }
 300
 301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 302 {
 303         struct irq_pin_list *entry, *next;
 304
 305         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 306                 return;
 307
 308         entry = old_cfg->irq_2_pin;
 309
 310         while (entry) {
 311                 next = entry->next;
 312                 kfree(entry);
 313                 entry = next;
 314         }
 315         old_cfg->irq_2_pin = NULL;
 316 }
 317
 318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 319                                  struct irq_desc *desc, int cpu)
 320 {
 321         struct irq_cfg *cfg;
 322         struct irq_cfg *old_cfg;
 323
 324         cfg = get_one_free_irq_cfg(cpu);
 325
 326         if (!cfg)
 327                 return;
 328
 329         desc->chip_data = cfg;
 330
 331         old_cfg = old_desc->chip_data;
 332
 333         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 334
 335         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 336 }
 337
 338 static void free_irq_cfg(struct irq_cfg *old_cfg)
 339 {
 340         kfree(old_cfg);
 341 }
 342
 343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 344 {
 345         struct irq_cfg *old_cfg, *cfg;
 346
 347         old_cfg = old_desc->chip_data;
 348         cfg = desc->chip_data;
 349
 350         if (old_cfg == cfg)
 351                 return;
 352
 353         if (old_cfg) {
 354                 free_irq_2_pin(old_cfg, cfg);
 355                 free_irq_cfg(old_cfg);
 356                 old_desc->chip_data = NULL;
 357         }
 358 }
 359
 360 static void
 361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 362 {
 363         struct irq_cfg *cfg = desc->chip_data;
 364
 365         if (!cfg->move_in_progress) {
 366                 /* it means that domain is not changed */
 367                 if (!cpumask_intersects(desc->affinity, mask))
 368                         cfg->move_desc_pending = 1;
 369         }
 370 }
 371 #endif
 372
 373 #else
 374 static struct irq_cfg *irq_cfg(unsigned int irq)
 375 {
 376         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 377 }
 378
 379 #endif
 380
 381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 382 static inline void
 383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 384 {
 385 }
 386 #endif
 387
 388 struct io_apic {
 389         unsigned int index;
 390         unsigned int unused[3];
 391         unsigned int data;
 392         unsigned int unused2[11];
 393         unsigned int eoi;
 394 };
 395
 396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 397 {
 398         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 399                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 400 }
 401
 402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
 403 {
 404         struct io_apic __iomem *io_apic = io_apic_base(apic);
 405         writel(vector, &io_apic->eoi);
 406 }
 407
 408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 409 {
 410         struct io_apic __iomem *io_apic = io_apic_base(apic);
 411         writel(reg, &io_apic->index);
 412         return readl(&io_apic->data);
 413 }
 414
 415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 416 {
 417         struct io_apic __iomem *io_apic = io_apic_base(apic);
 418         writel(reg, &io_apic->index);
 419         writel(value, &io_apic->data);
 420 }
 421
 422 /*
 423  * Re-write a value: to be used for read-modify-write
 424  * cycles where the read already set up the index register.
 425  *
 426  * Older SiS APIC requires we rewrite the index register
 427  */
 428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 429 {
 430         struct io_apic __iomem *io_apic = io_apic_base(apic);
 431
 432         if (sis_apic_bug)
 433                 writel(reg, &io_apic->index);
 434         writel(value, &io_apic->data);
 435 }
 436
 437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 438 {
 439         struct irq_pin_list *entry;
 440         unsigned long flags;
 441
 442         spin_lock_irqsave(&ioapic_lock, flags);
 443         entry = cfg->irq_2_pin;
 444         for (;;) {
 445                 unsigned int reg;
 446                 int pin;
 447
 448                 if (!entry)
 449                         break;
 450                 pin = entry->pin;
 451                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 452                 /* Is the remote IRR bit set? */
 453                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 454                         spin_unlock_irqrestore(&ioapic_lock, flags);
 455                         return true;
 456                 }
 457                 if (!entry->next)
 458                         break;
 459                 entry = entry->next;
 460         }
 461         spin_unlock_irqrestore(&ioapic_lock, flags);
 462
 463         return false;
 464 }
 465
 466 union entry_union {
 467         struct { u32 w1, w2; };
 468         struct IO_APIC_route_entry entry;
 469 };
 470
 471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 472 {
 473         union entry_union eu;
 474         unsigned long flags;
 475         spin_lock_irqsave(&ioapic_lock, flags);
 476         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 477         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 478         spin_unlock_irqrestore(&ioapic_lock, flags);
 479         return eu.entry;
 480 }
 481
 482 /*
 483  * When we write a new IO APIC routing entry, we need to write the high
 484  * word first! If the mask bit in the low word is clear, we will enable
 485  * the interrupt, and we need to make sure the entry is fully populated
 486  * before that happens.
 487  */
 488 static void
 489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 490 {
 491         union entry_union eu;
 492         eu.entry = e;
 493         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 494         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 495 }
 496
 497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 498 {
 499         unsigned long flags;
 500         spin_lock_irqsave(&ioapic_lock, flags);
 501         __ioapic_write_entry(apic, pin, e);
 502         spin_unlock_irqrestore(&ioapic_lock, flags);
 503 }
 504
 505 /*
 506  * When we mask an IO APIC routing entry, we need to write the low
 507  * word first, in order to set the mask bit before we change the
 508  * high bits!
 509  */
 510 static void ioapic_mask_entry(int apic, int pin)
 511 {
 512         unsigned long flags;
 513         union entry_union eu = { .entry.mask = 1 };
 514
 515         spin_lock_irqsave(&ioapic_lock, flags);
 516         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 517         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 518         spin_unlock_irqrestore(&ioapic_lock, flags);
 519 }
 520
 521 #ifdef CONFIG_SMP
 522 static void send_cleanup_vector(struct irq_cfg *cfg)
 523 {
 524         cpumask_var_t cleanup_mask;
 525
 526         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
 527                 unsigned int i;
 528                 cfg->move_cleanup_count = 0;
 529                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 530                         cfg->move_cleanup_count++;
 531                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 532                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
 533         } else {
 534                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
 535                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
 536                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 537                 free_cpumask_var(cleanup_mask);
 538         }
 539         cfg->move_in_progress = 0;
 540 }
 541
 542 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
 543 {
 544         int apic, pin;
 545         struct irq_pin_list *entry;
 546         u8 vector = cfg->vector;
 547
 548         entry = cfg->irq_2_pin;
 549         for (;;) {
 550                 unsigned int reg;
 551
 552                 if (!entry)
 553                         break;
 554
 555                 apic = entry->apic;
 556                 pin = entry->pin;
 557                 /*
 558                  * With interrupt-remapping, destination information comes
 559                  * from interrupt-remapping table entry.
 560                  */
 561                 if (!irq_remapped(irq))
 562                         io_apic_write(apic, 0x11 + pin*2, dest);
 563                 reg = io_apic_read(apic, 0x10 + pin*2);
 564                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
 565                 reg |= vector;
 566                 io_apic_modify(apic, 0x10 + pin*2, reg);
 567                 if (!entry->next)
 568                         break;
 569                 entry = entry->next;
 570         }
 571 }
 572
 573 static int
 574 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
 575
 576 /*
 577  * Either sets desc->affinity to a valid value, and returns
 578  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
 579  * leaves desc->affinity untouched.
 580  */
 581 static unsigned int
 582 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
 583 {
 584         struct irq_cfg *cfg;
 585         unsigned int irq;
 586
 587         if (!cpumask_intersects(mask, cpu_online_mask))
 588                 return BAD_APICID;
 589
 590         irq = desc->irq;
 591         cfg = desc->chip_data;
 592         if (assign_irq_vector(irq, cfg, mask))
 593                 return BAD_APICID;
 594
 595         cpumask_and(desc->affinity, cfg->domain, mask);
 596         set_extra_move_desc(desc, mask);
 597
 598         return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
 599 }
 600
 601 static void
 602 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 603 {
 604         struct irq_cfg *cfg;
 605         unsigned long flags;
 606         unsigned int dest;
 607         unsigned int irq;
 608
 609         irq = desc->irq;
 610         cfg = desc->chip_data;
 611
 612         spin_lock_irqsave(&ioapic_lock, flags);
 613         dest = set_desc_affinity(desc, mask);
 614         if (dest != BAD_APICID) {
 615                 /* Only the high 8 bits are valid. */
 616                 dest = SET_APIC_LOGICAL_ID(dest);
 617                 __target_IO_APIC_irq(irq, dest, cfg);
 618         }
 619         spin_unlock_irqrestore(&ioapic_lock, flags);
 620 }
 621
 622 static void
 623 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
 624 {
 625         struct irq_desc *desc;
 626
 627         desc = irq_to_desc(irq);
 628
 629         set_ioapic_affinity_irq_desc(desc, mask);
 630 }
 631 #endif /* CONFIG_SMP */
 632
 633 /*
 634  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 635  * shared ISA-space IRQs, so we have to support them. We are super
 636  * fast in the common case, and fast for shared ISA-space IRQs.
 637  */
 638 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 639 {
 640         struct irq_pin_list *entry;
 641
 642         entry = cfg->irq_2_pin;
 643         if (!entry) {
 644                 entry = get_one_free_irq_2_pin(cpu);
 645                 if (!entry) {
 646                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 647                                         apic, pin);
 648                         return;
 649                 }
 650                 cfg->irq_2_pin = entry;
 651                 entry->apic = apic;
 652                 entry->pin = pin;
 653                 return;
 654         }
 655
 656         while (entry->next) {
 657                 /* not again, please */
 658                 if (entry->apic == apic && entry->pin == pin)
 659                         return;
 660
 661                 entry = entry->next;
 662         }
 663
 664         entry->next = get_one_free_irq_2_pin(cpu);
 665         entry = entry->next;
 666         entry->apic = apic;
 667         entry->pin = pin;
 668 }
 669
 670 /*
 671  * Reroute an IRQ to a different pin.
 672  */
 673 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 674                                       int oldapic, int oldpin,
 675                                       int newapic, int newpin)
 676 {
 677         struct irq_pin_list *entry = cfg->irq_2_pin;
 678         int replaced = 0;
 679
 680         while (entry) {
 681                 if (entry->apic == oldapic && entry->pin == oldpin) {
 682                         entry->apic = newapic;
 683                         entry->pin = newpin;
 684                         replaced = 1;
 685                         /* every one is different, right? */
 686                         break;
 687                 }
 688                 entry = entry->next;
 689         }
 690
 691         /* why? call replace before add? */
 692         if (!replaced)
 693                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 694 }
 695
 696 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 697                                 int mask_and, int mask_or,
 698                                 void (*final)(struct irq_pin_list *entry))
 699 {
 700         int pin;
 701         struct irq_pin_list *entry;
 702
 703         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 704                 unsigned int reg;
 705                 pin = entry->pin;
 706                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 707                 reg &= mask_and;
 708                 reg |= mask_or;
 709                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 710                 if (final)
 711                         final(entry);
 712         }
 713 }
 714
 715 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 716 {
 717         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 718 }
 719
 720 #ifdef CONFIG_X86_64
 721 static void io_apic_sync(struct irq_pin_list *entry)
 722 {
 723         /*
 724          * Synchronize the IO-APIC and the CPU by doing
 725          * a dummy read from the IO-APIC
 726          */
 727         struct io_apic __iomem *io_apic;
 728         io_apic = io_apic_base(entry->apic);
 729         readl(&io_apic->data);
 730 }
 731
 732 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 733 {
 734         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 735 }
 736 #else /* CONFIG_X86_32 */
 737 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 738 {
 739         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 740 }
 741
 742 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 743 {
 744         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 745                         IO_APIC_REDIR_MASKED, NULL);
 746 }
 747
 748 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 749 {
 750         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 751                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 752 }
 753 #endif /* CONFIG_X86_32 */
 754
 755 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 756 {
 757         struct irq_cfg *cfg = desc->chip_data;
 758         unsigned long flags;
 759
 760         BUG_ON(!cfg);
 761
 762         spin_lock_irqsave(&ioapic_lock, flags);
 763         __mask_IO_APIC_irq(cfg);
 764         spin_unlock_irqrestore(&ioapic_lock, flags);
 765 }
 766
 767 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 768 {
 769         struct irq_cfg *cfg = desc->chip_data;
 770         unsigned long flags;
 771
 772         spin_lock_irqsave(&ioapic_lock, flags);
 773         __unmask_IO_APIC_irq(cfg);
 774         spin_unlock_irqrestore(&ioapic_lock, flags);
 775 }
 776
 777 static void mask_IO_APIC_irq(unsigned int irq)
 778 {
 779         struct irq_desc *desc = irq_to_desc(irq);
 780
 781         mask_IO_APIC_irq_desc(desc);
 782 }
 783 static void unmask_IO_APIC_irq(unsigned int irq)
 784 {
 785         struct irq_desc *desc = irq_to_desc(irq);
 786
 787         unmask_IO_APIC_irq_desc(desc);
 788 }
 789
 790 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 791 {
 792         struct IO_APIC_route_entry entry;
 793
 794         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 795         entry = ioapic_read_entry(apic, pin);
 796         if (entry.delivery_mode == dest_SMI)
 797                 return;
 798         /*
 799          * Disable it in the IO-APIC irq-routing table:
 800          */
 801         ioapic_mask_entry(apic, pin);
 802 }
 803
 804 static void clear_IO_APIC (void)
 805 {
 806         int apic, pin;
 807
 808         for (apic = 0; apic < nr_ioapics; apic++)
 809                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 810                         clear_IO_APIC_pin(apic, pin);
 811 }
 812
 813 #ifdef CONFIG_X86_32
 814 /*
 815  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 816  * specific CPU-side IRQs.
 817  */
 818
 819 #define MAX_PIRQS 8
 820 static int pirq_entries[MAX_PIRQS] = {
 821         [0 ... MAX_PIRQS - 1] = -1
 822 };
 823
 824 static int __init ioapic_pirq_setup(char *str)
 825 {
 826         int i, max;
 827         int ints[MAX_PIRQS+1];
 828
 829         get_options(str, ARRAY_SIZE(ints), ints);
 830
 831         apic_printk(APIC_VERBOSE, KERN_INFO
 832                         "PIRQ redirection, working around broken MP-BIOS.\n");
 833         max = MAX_PIRQS;
 834         if (ints[0] < MAX_PIRQS)
 835                 max = ints[0];
 836
 837         for (i = 0; i < max; i++) {
 838                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 839                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 840                 /*
 841                  * PIRQs are mapped upside down, usually.
 842                  */
 843                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 844         }
 845         return 1;
 846 }
 847
 848 __setup("pirq=", ioapic_pirq_setup);
 849 #endif /* CONFIG_X86_32 */
 850
 851 #ifdef CONFIG_INTR_REMAP
 852 /* I/O APIC RTE contents at the OS boot up */
 853 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
 854
 855 /*
 856  * Saves and masks all the unmasked IO-APIC RTE's
 857  */
 858 int save_mask_IO_APIC_setup(void)
 859 {
 860         union IO_APIC_reg_01 reg_01;
 861         unsigned long flags;
 862         int apic, pin;
 863
 864         /*
 865          * The number of IO-APIC IRQ registers (== #pins):
 866          */
 867         for (apic = 0; apic < nr_ioapics; apic++) {
 868                 spin_lock_irqsave(&ioapic_lock, flags);
 869                 reg_01.raw = io_apic_read(apic, 1);
 870                 spin_unlock_irqrestore(&ioapic_lock, flags);
 871                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
 872         }
 873
 874         for (apic = 0; apic < nr_ioapics; apic++) {
 875                 early_ioapic_entries[apic] =
 876                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 877                                 nr_ioapic_registers[apic], GFP_KERNEL);
 878                 if (!early_ioapic_entries[apic])
 879                         goto nomem;
 880         }
 881
 882         for (apic = 0; apic < nr_ioapics; apic++)
 883                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 884                         struct IO_APIC_route_entry entry;
 885
 886                         entry = early_ioapic_entries[apic][pin] =
 887                                 ioapic_read_entry(apic, pin);
 888                         if (!entry.mask) {
 889                                 entry.mask = 1;
 890                                 ioapic_write_entry(apic, pin, entry);
 891                         }
 892                 }
 893
 894         return 0;
 895
 896 nomem:
 897         while (apic >= 0)
 898                 kfree(early_ioapic_entries[apic--]);
 899         memset(early_ioapic_entries, 0,
 900                 ARRAY_SIZE(early_ioapic_entries));
 901
 902         return -ENOMEM;
 903 }
 904
 905 void restore_IO_APIC_setup(void)
 906 {
 907         int apic, pin;
 908
 909         for (apic = 0; apic < nr_ioapics; apic++) {
 910                 if (!early_ioapic_entries[apic])
 911                         break;
 912                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 913                         ioapic_write_entry(apic, pin,
 914                                            early_ioapic_entries[apic][pin]);
 915                 kfree(early_ioapic_entries[apic]);
 916                 early_ioapic_entries[apic] = NULL;
 917         }
 918 }
 919
 920 void reinit_intr_remapped_IO_APIC(int intr_remapping)
 921 {
 922         /*
 923          * for now plain restore of previous settings.
 924          * TBD: In the case of OS enabling interrupt-remapping,
 925          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 926          * table entries. for now, do a plain restore, and wait for
 927          * the setup_IO_APIC_irqs() to do proper initialization.
 928          */
 929         restore_IO_APIC_setup();
 930 }
 931 #endif
 932
 933 /*
 934  * Find the IRQ entry number of a certain pin.
 935  */
 936 static int find_irq_entry(int apic, int pin, int type)
 937 {
 938         int i;
 939
 940         for (i = 0; i < mp_irq_entries; i++)
 941                 if (mp_irqs[i].irqtype == type &&
 942                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 943                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 944                     mp_irqs[i].dstirq == pin)
 945                         return i;
 946
 947         return -1;
 948 }
 949
 950 /*
 951  * Find the pin to which IRQ[irq] (ISA) is connected
 952  */
 953 static int __init find_isa_irq_pin(int irq, int type)
 954 {
 955         int i;
 956
 957         for (i = 0; i < mp_irq_entries; i++) {
 958                 int lbus = mp_irqs[i].srcbus;
 959
 960                 if (test_bit(lbus, mp_bus_not_pci) &&
 961                     (mp_irqs[i].irqtype == type) &&
 962                     (mp_irqs[i].srcbusirq == irq))
 963
 964                         return mp_irqs[i].dstirq;
 965         }
 966         return -1;
 967 }
 968
 969 static int __init find_isa_irq_apic(int irq, int type)
 970 {
 971         int i;
 972
 973         for (i = 0; i < mp_irq_entries; i++) {
 974                 int lbus = mp_irqs[i].srcbus;
 975
 976                 if (test_bit(lbus, mp_bus_not_pci) &&
 977                     (mp_irqs[i].irqtype == type) &&
 978                     (mp_irqs[i].srcbusirq == irq))
 979                         break;
 980         }
 981         if (i < mp_irq_entries) {
 982                 int apic;
 983                 for(apic = 0; apic < nr_ioapics; apic++) {
 984                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
 985                                 return apic;
 986                 }
 987         }
 988
 989         return -1;
 990 }
 991
 992 /*
 993  * Find a specific PCI IRQ entry.
 994  * Not an __init, possibly needed by modules
 995  */
 996 static int pin_2_irq(int idx, int apic, int pin);
 997
 998 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 999 {
1000         int apic, i, best_guess = -1;
1001
1002         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1003                 bus, slot, pin);
1004         if (test_bit(bus, mp_bus_not_pci)) {
1005                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1006                 return -1;
1007         }
1008         for (i = 0; i < mp_irq_entries; i++) {
1009                 int lbus = mp_irqs[i].srcbus;
1010
1011                 for (apic = 0; apic < nr_ioapics; apic++)
1012                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1013                             mp_irqs[i].dstapic == MP_APIC_ALL)
1014                                 break;
1015
1016                 if (!test_bit(lbus, mp_bus_not_pci) &&
1017                     !mp_irqs[i].irqtype &&
1018                     (bus == lbus) &&
1019                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1020                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1021
1022                         if (!(apic || IO_APIC_IRQ(irq)))
1023                                 continue;
1024
1025                         if (pin == (mp_irqs[i].srcbusirq & 3))
1026                                 return irq;
1027                         /*
1028                          * Use the first all-but-pin matching entry as a
1029                          * best-guess fuzzy result for broken mptables.
1030                          */
1031                         if (best_guess < 0)
1032                                 best_guess = irq;
1033                 }
1034         }
1035         return best_guess;
1036 }
1037
1038 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1039
1040 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1041 /*
1042  * EISA Edge/Level control register, ELCR
1043  */
1044 static int EISA_ELCR(unsigned int irq)
1045 {
1046         if (irq < NR_IRQS_LEGACY) {
1047                 unsigned int port = 0x4d0 + (irq >> 3);
1048                 return (inb(port) >> (irq & 7)) & 1;
1049         }
1050         apic_printk(APIC_VERBOSE, KERN_INFO
1051                         "Broken MPtable reports ISA irq %d\n", irq);
1052         return 0;
1053 }
1054
1055 #endif
1056
1057 /* ISA interrupts are always polarity zero edge triggered,
1058  * when listed as conforming in the MP table. */
1059
1060 #define default_ISA_trigger(idx)        (0)
1061 #define default_ISA_polarity(idx)       (0)
1062
1063 /* EISA interrupts are always polarity zero and can be edge or level
1064  * trigger depending on the ELCR value.  If an interrupt is listed as
1065  * EISA conforming in the MP table, that means its trigger type must
1066  * be read in from the ELCR */
1067
1068 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1069 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1070
1071 /* PCI interrupts are always polarity one level triggered,
1072  * when listed as conforming in the MP table. */
1073
1074 #define default_PCI_trigger(idx)        (1)
1075 #define default_PCI_polarity(idx)       (1)
1076
1077 /* MCA interrupts are always polarity zero level triggered,
1078  * when listed as conforming in the MP table. */
1079
1080 #define default_MCA_trigger(idx)        (1)
1081 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1082
1083 static int MPBIOS_polarity(int idx)
1084 {
1085         int bus = mp_irqs[idx].srcbus;
1086         int polarity;
1087
1088         /*
1089          * Determine IRQ line polarity (high active or low active):
1090          */
1091         switch (mp_irqs[idx].irqflag & 3)
1092         {
1093                 case 0: /* conforms, ie. bus-type dependent polarity */
1094                         if (test_bit(bus, mp_bus_not_pci))
1095                                 polarity = default_ISA_polarity(idx);
1096                         else
1097                                 polarity = default_PCI_polarity(idx);
1098                         break;
1099                 case 1: /* high active */
1100                 {
1101                         polarity = 0;
1102                         break;
1103                 }
1104                 case 2: /* reserved */
1105                 {
1106                         printk(KERN_WARNING "broken BIOS!!\n");
1107                         polarity = 1;
1108                         break;
1109                 }
1110                 case 3: /* low active */
1111                 {
1112                         polarity = 1;
1113                         break;
1114                 }
1115                 default: /* invalid */
1116                 {
1117                         printk(KERN_WARNING "broken BIOS!!\n");
1118                         polarity = 1;
1119                         break;
1120                 }
1121         }
1122         return polarity;
1123 }
1124
1125 static int MPBIOS_trigger(int idx)
1126 {
1127         int bus = mp_irqs[idx].srcbus;
1128         int trigger;
1129
1130         /*
1131          * Determine IRQ trigger mode (edge or level sensitive):
1132          */
1133         switch ((mp_irqs[idx].irqflag>>2) & 3)
1134         {
1135                 case 0: /* conforms, ie. bus-type dependent */
1136                         if (test_bit(bus, mp_bus_not_pci))
1137                                 trigger = default_ISA_trigger(idx);
1138                         else
1139                                 trigger = default_PCI_trigger(idx);
1140 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1141                         switch (mp_bus_id_to_type[bus]) {
1142                                 case MP_BUS_ISA: /* ISA pin */
1143                                 {
1144                                         /* set before the switch */
1145                                         break;
1146                                 }
1147                                 case MP_BUS_EISA: /* EISA pin */
1148                                 {
1149                                         trigger = default_EISA_trigger(idx);
1150                                         break;
1151                                 }
1152                                 case MP_BUS_PCI: /* PCI pin */
1153                                 {
1154                                         /* set before the switch */
1155                                         break;
1156                                 }
1157                                 case MP_BUS_MCA: /* MCA pin */
1158                                 {
1159                                         trigger = default_MCA_trigger(idx);
1160                                         break;
1161                                 }
1162                                 default:
1163                                 {
1164                                         printk(KERN_WARNING "broken BIOS!!\n");
1165                                         trigger = 1;
1166                                         break;
1167                                 }
1168                         }
1169 #endif
1170                         break;
1171                 case 1: /* edge */
1172                 {
1173                         trigger = 0;
1174                         break;
1175                 }
1176                 case 2: /* reserved */
1177                 {
1178                         printk(KERN_WARNING "broken BIOS!!\n");
1179                         trigger = 1;
1180                         break;
1181                 }
1182                 case 3: /* level */
1183                 {
1184                         trigger = 1;
1185                         break;
1186                 }
1187                 default: /* invalid */
1188                 {
1189                         printk(KERN_WARNING "broken BIOS!!\n");
1190                         trigger = 0;
1191                         break;
1192                 }
1193         }
1194         return trigger;
1195 }
1196
1197 static inline int irq_polarity(int idx)
1198 {
1199         return MPBIOS_polarity(idx);
1200 }
1201
1202 static inline int irq_trigger(int idx)
1203 {
1204         return MPBIOS_trigger(idx);
1205 }
1206
1207 int (*ioapic_renumber_irq)(int ioapic, int irq);
1208 static int pin_2_irq(int idx, int apic, int pin)
1209 {
1210         int irq, i;
1211         int bus = mp_irqs[idx].srcbus;
1212
1213         /*
1214          * Debugging check, we are in big trouble if this message pops up!
1215          */
1216         if (mp_irqs[idx].dstirq != pin)
1217                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1218
1219         if (test_bit(bus, mp_bus_not_pci)) {
1220                 irq = mp_irqs[idx].srcbusirq;
1221         } else {
1222                 /*
1223                  * PCI IRQs are mapped in order
1224                  */
1225                 i = irq = 0;
1226                 while (i < apic)
1227                         irq += nr_ioapic_registers[i++];
1228                 irq += pin;
1229                 /*
1230                  * For MPS mode, so far only needed by ES7000 platform
1231                  */
1232                 if (ioapic_renumber_irq)
1233                         irq = ioapic_renumber_irq(apic, irq);
1234         }
1235
1236 #ifdef CONFIG_X86_32
1237         /*
1238          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1239          */
1240         if ((pin >= 16) && (pin <= 23)) {
1241                 if (pirq_entries[pin-16] != -1) {
1242                         if (!pirq_entries[pin-16]) {
1243                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1244                                                 "disabling PIRQ%d\n", pin-16);
1245                         } else {
1246                                 irq = pirq_entries[pin-16];
1247                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1248                                                 "using PIRQ%d -> IRQ %d\n",
1249                                                 pin-16, irq);
1250                         }
1251                 }
1252         }
1253 #endif
1254
1255         return irq;
1256 }
1257
1258 void lock_vector_lock(void)
1259 {
1260         /* Used to the online set of cpus does not change
1261          * during assign_irq_vector.
1262          */
1263         spin_lock(&vector_lock);
1264 }
1265
1266 void unlock_vector_lock(void)
1267 {
1268         spin_unlock(&vector_lock);
1269 }
1270
1271 static int
1272 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1273 {
1274         /*
1275          * NOTE! The local APIC isn't very good at handling
1276          * multiple interrupts at the same interrupt level.
1277          * As the interrupt level is determined by taking the
1278          * vector number and shifting that right by 4, we
1279          * want to spread these out a bit so that they don't
1280          * all fall in the same interrupt level.
1281          *
1282          * Also, we've got to be careful not to trash gate
1283          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1284          */
1285         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1286         unsigned int old_vector;
1287         int cpu, err;
1288         cpumask_var_t tmp_mask;
1289
1290         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1291                 return -EBUSY;
1292
1293         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1294                 return -ENOMEM;
1295
1296         old_vector = cfg->vector;
1297         if (old_vector) {
1298                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1299                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1300                 if (!cpumask_empty(tmp_mask)) {
1301                         free_cpumask_var(tmp_mask);
1302                         return 0;
1303                 }
1304         }
1305
1306         /* Only try and allocate irqs on cpus that are present */
1307         err = -ENOSPC;
1308         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1309                 int new_cpu;
1310                 int vector, offset;
1311
1312                 apic->vector_allocation_domain(cpu, tmp_mask);
1313
1314                 vector = current_vector;
1315                 offset = current_offset;
1316 next:
1317                 vector += 8;
1318                 if (vector >= first_system_vector) {
1319                         /* If out of vectors on large boxen, must share them. */
1320                         offset = (offset + 1) % 8;
1321                         vector = FIRST_DEVICE_VECTOR + offset;
1322                 }
1323                 if (unlikely(current_vector == vector))
1324                         continue;
1325
1326                 if (test_bit(vector, used_vectors))
1327                         goto next;
1328
1329                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1330                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1331                                 goto next;
1332                 /* Found one! */
1333                 current_vector = vector;
1334                 current_offset = offset;
1335                 if (old_vector) {
1336                         cfg->move_in_progress = 1;
1337                         cpumask_copy(cfg->old_domain, cfg->domain);
1338                 }
1339                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1340                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1341                 cfg->vector = vector;
1342                 cpumask_copy(cfg->domain, tmp_mask);
1343                 err = 0;
1344                 break;
1345         }
1346         free_cpumask_var(tmp_mask);
1347         return err;
1348 }
1349
1350 static int
1351 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1352 {
1353         int err;
1354         unsigned long flags;
1355
1356         spin_lock_irqsave(&vector_lock, flags);
1357         err = __assign_irq_vector(irq, cfg, mask);
1358         spin_unlock_irqrestore(&vector_lock, flags);
1359         return err;
1360 }
1361
1362 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1363 {
1364         int cpu, vector;
1365
1366         BUG_ON(!cfg->vector);
1367
1368         vector = cfg->vector;
1369         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1370                 per_cpu(vector_irq, cpu)[vector] = -1;
1371
1372         cfg->vector = 0;
1373         cpumask_clear(cfg->domain);
1374
1375         if (likely(!cfg->move_in_progress))
1376                 return;
1377         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1378                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1379                                                                 vector++) {
1380                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1381                                 continue;
1382                         per_cpu(vector_irq, cpu)[vector] = -1;
1383                         break;
1384                 }
1385         }
1386         cfg->move_in_progress = 0;
1387 }
1388
1389 void __setup_vector_irq(int cpu)
1390 {
1391         /* Initialize vector_irq on a new cpu */
1392         /* This function must be called with vector_lock held */
1393         int irq, vector;
1394         struct irq_cfg *cfg;
1395         struct irq_desc *desc;
1396
1397         /* Mark the inuse vectors */
1398         for_each_irq_desc(irq, desc) {
1399                 cfg = desc->chip_data;
1400                 if (!cpumask_test_cpu(cpu, cfg->domain))
1401                         continue;
1402                 vector = cfg->vector;
1403                 per_cpu(vector_irq, cpu)[vector] = irq;
1404         }
1405         /* Mark the free vectors */
1406         for (vector = 0; vector < NR_VECTORS; ++vector) {
1407                 irq = per_cpu(vector_irq, cpu)[vector];
1408                 if (irq < 0)
1409                         continue;
1410
1411                 cfg = irq_cfg(irq);
1412                 if (!cpumask_test_cpu(cpu, cfg->domain))
1413                         per_cpu(vector_irq, cpu)[vector] = -1;
1414         }
1415 }
1416
1417 static struct irq_chip ioapic_chip;
1418 static struct irq_chip ir_ioapic_chip;
1419 static struct irq_chip msi_ir_chip;
1420
1421 #define IOAPIC_AUTO     -1
1422 #define IOAPIC_EDGE     0
1423 #define IOAPIC_LEVEL    1
1424
1425 #ifdef CONFIG_X86_32
1426 static inline int IO_APIC_irq_trigger(int irq)
1427 {
1428         int apic, idx, pin;
1429
1430         for (apic = 0; apic < nr_ioapics; apic++) {
1431                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1432                         idx = find_irq_entry(apic, pin, mp_INT);
1433                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1434                                 return irq_trigger(idx);
1435                 }
1436         }
1437         /*
1438          * nonexistent IRQs are edge default
1439          */
1440         return 0;
1441 }
1442 #else
1443 static inline int IO_APIC_irq_trigger(int irq)
1444 {
1445         return 1;
1446 }
1447 #endif
1448
1449 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1450 {
1451
1452         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1453             trigger == IOAPIC_LEVEL)
1454                 desc->status |= IRQ_LEVEL;
1455         else
1456                 desc->status &= ~IRQ_LEVEL;
1457
1458         if (irq_remapped(irq)) {
1459                 desc->status |= IRQ_MOVE_PCNTXT;
1460                 if (trigger)
1461                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1462                                                       handle_fasteoi_irq,
1463                                                      "fasteoi");
1464                 else
1465                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1466                                                       handle_edge_irq, "edge");
1467                 return;
1468         }
1469
1470         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1471             trigger == IOAPIC_LEVEL)
1472                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1473                                               handle_fasteoi_irq,
1474                                               "fasteoi");
1475         else
1476                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1477                                               handle_edge_irq, "edge");
1478 }
1479
1480 int setup_ioapic_entry(int apic_id, int irq,
1481                        struct IO_APIC_route_entry *entry,
1482                        unsigned int destination, int trigger,
1483                        int polarity, int vector, int pin)
1484 {
1485         /*
1486          * add it to the IO-APIC irq-routing table:
1487          */
1488         memset(entry,0,sizeof(*entry));
1489
1490         if (intr_remapping_enabled) {
1491                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1492                 struct irte irte;
1493                 struct IR_IO_APIC_route_entry *ir_entry =
1494                         (struct IR_IO_APIC_route_entry *) entry;
1495                 int index;
1496
1497                 if (!iommu)
1498                         panic("No mapping iommu for ioapic %d\n", apic_id);
1499
1500                 index = alloc_irte(iommu, irq, 1);
1501                 if (index < 0)
1502                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1503
1504                 memset(&irte, 0, sizeof(irte));
1505
1506                 irte.present = 1;
1507                 irte.dst_mode = apic->irq_dest_mode;
1508                 /*
1509                  * Trigger mode in the IRTE will always be edge, and the
1510                  * actual level or edge trigger will be setup in the IO-APIC
1511                  * RTE. This will help simplify level triggered irq migration.
1512                  * For more details, see the comments above explainig IO-APIC
1513                  * irq migration in the presence of interrupt-remapping.
1514                  */
1515                 irte.trigger_mode = 0;
1516                 irte.dlvry_mode = apic->irq_delivery_mode;
1517                 irte.vector = vector;
1518                 irte.dest_id = IRTE_DEST(destination);
1519
1520                 modify_irte(irq, &irte);
1521
1522                 ir_entry->index2 = (index >> 15) & 0x1;
1523                 ir_entry->zero = 0;
1524                 ir_entry->format = 1;
1525                 ir_entry->index = (index & 0x7fff);
1526                 /*
1527                  * IO-APIC RTE will be configured with virtual vector.
1528                  * irq handler will do the explicit EOI to the io-apic.
1529                  */
1530                 ir_entry->vector = pin;
1531         } else {
1532                 entry->delivery_mode = apic->irq_delivery_mode;
1533                 entry->dest_mode = apic->irq_dest_mode;
1534                 entry->dest = destination;
1535                 entry->vector = vector;
1536         }
1537
1538         entry->mask = 0;                                /* enable IRQ */
1539         entry->trigger = trigger;
1540         entry->polarity = polarity;
1541
1542         /* Mask level triggered irqs.
1543          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1544          */
1545         if (trigger)
1546                 entry->mask = 1;
1547         return 0;
1548 }
1549
1550 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1551                               int trigger, int polarity)
1552 {
1553         struct irq_cfg *cfg;
1554         struct IO_APIC_route_entry entry;
1555         unsigned int dest;
1556
1557         if (!IO_APIC_IRQ(irq))
1558                 return;
1559
1560         cfg = desc->chip_data;
1561
1562         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1563                 return;
1564
1565         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1566
1567         apic_printk(APIC_VERBOSE,KERN_DEBUG
1568                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1569                     "IRQ %d Mode:%i Active:%i)\n",
1570                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1571                     irq, trigger, polarity);
1572
1573
1574         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1575                                dest, trigger, polarity, cfg->vector, pin)) {
1576                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1577                        mp_ioapics[apic_id].apicid, pin);
1578                 __clear_irq_vector(irq, cfg);
1579                 return;
1580         }
1581
1582         ioapic_register_intr(irq, desc, trigger);
1583         if (irq < NR_IRQS_LEGACY)
1584                 disable_8259A_irq(irq);
1585
1586         ioapic_write_entry(apic_id, pin, entry);
1587 }
1588
1589 static void __init setup_IO_APIC_irqs(void)
1590 {
1591         int apic_id, pin, idx, irq;
1592         int notcon = 0;
1593         struct irq_desc *desc;
1594         struct irq_cfg *cfg;
1595         int cpu = boot_cpu_id;
1596
1597         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1598
1599         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1600                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1601
1602                         idx = find_irq_entry(apic_id, pin, mp_INT);
1603                         if (idx == -1) {
1604                                 if (!notcon) {
1605                                         notcon = 1;
1606                                         apic_printk(APIC_VERBOSE,
1607                                                 KERN_DEBUG " %d-%d",
1608                                                 mp_ioapics[apic_id].apicid, pin);
1609                                 } else
1610                                         apic_printk(APIC_VERBOSE, " %d-%d",
1611                                                 mp_ioapics[apic_id].apicid, pin);
1612                                 continue;
1613                         }
1614                         if (notcon) {
1615                                 apic_printk(APIC_VERBOSE,
1616                                         " (apicid-pin) not connected\n");
1617                                 notcon = 0;
1618                         }
1619
1620                         irq = pin_2_irq(idx, apic_id, pin);
1621
1622                         /*
1623                          * Skip the timer IRQ if there's a quirk handler
1624                          * installed and if it returns 1:
1625                          */
1626                         if (apic->multi_timer_check &&
1627                                         apic->multi_timer_check(apic_id, irq))
1628                                 continue;
1629
1630                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1631                         if (!desc) {
1632                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1633                                 continue;
1634                         }
1635                         cfg = desc->chip_data;
1636                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1637
1638                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1639                                         irq_trigger(idx), irq_polarity(idx));
1640                 }
1641         }
1642
1643         if (notcon)
1644                 apic_printk(APIC_VERBOSE,
1645                         " (apicid-pin) not connected\n");
1646 }
1647
1648 /*
1649  * Set up the timer pin, possibly with the 8259A-master behind.
1650  */
1651 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1652                                         int vector)
1653 {
1654         struct IO_APIC_route_entry entry;
1655
1656         if (intr_remapping_enabled)
1657                 return;
1658
1659         memset(&entry, 0, sizeof(entry));
1660
1661         /*
1662          * We use logical delivery to get the timer IRQ
1663          * to the first CPU.
1664          */
1665         entry.dest_mode = apic->irq_dest_mode;
1666         entry.mask = 0;                 /* don't mask IRQ for edge */
1667         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1668         entry.delivery_mode = apic->irq_delivery_mode;
1669         entry.polarity = 0;
1670         entry.trigger = 0;
1671         entry.vector = vector;
1672
1673         /*
1674          * The timer IRQ doesn't have to know that behind the
1675          * scene we may have a 8259A-master in AEOI mode ...
1676          */
1677         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1678
1679         /*
1680          * Add it to the IO-APIC irq-routing table:
1681          */
1682         ioapic_write_entry(apic_id, pin, entry);
1683 }
1684
1685
1686 __apicdebuginit(void) print_IO_APIC(void)
1687 {
1688         int apic, i;
1689         union IO_APIC_reg_00 reg_00;
1690         union IO_APIC_reg_01 reg_01;
1691         union IO_APIC_reg_02 reg_02;
1692         union IO_APIC_reg_03 reg_03;
1693         unsigned long flags;
1694         struct irq_cfg *cfg;
1695         struct irq_desc *desc;
1696         unsigned int irq;
1697
1698         if (apic_verbosity == APIC_QUIET)
1699                 return;
1700
1701         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1702         for (i = 0; i < nr_ioapics; i++)
1703                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1704                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1705
1706         /*
1707          * We are a bit conservative about what we expect.  We have to
1708          * know about every hardware change ASAP.
1709          */
1710         printk(KERN_INFO "testing the IO APIC.......................\n");
1711
1712         for (apic = 0; apic < nr_ioapics; apic++) {
1713
1714         spin_lock_irqsave(&ioapic_lock, flags);
1715         reg_00.raw = io_apic_read(apic, 0);
1716         reg_01.raw = io_apic_read(apic, 1);
1717         if (reg_01.bits.version >= 0x10)
1718                 reg_02.raw = io_apic_read(apic, 2);
1719         if (reg_01.bits.version >= 0x20)
1720                 reg_03.raw = io_apic_read(apic, 3);
1721         spin_unlock_irqrestore(&ioapic_lock, flags);
1722
1723         printk("\n");
1724         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1725         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1726         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1727         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1728         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1729
1730         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1731         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1732
1733         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1734         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1735
1736         /*
1737          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1738          * but the value of reg_02 is read as the previous read register
1739          * value, so ignore it if reg_02 == reg_01.
1740          */
1741         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1742                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1743                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1744         }
1745
1746         /*
1747          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1748          * or reg_03, but the value of reg_0[23] is read as the previous read
1749          * register value, so ignore it if reg_03 == reg_0[12].
1750          */
1751         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1752             reg_03.raw != reg_01.raw) {
1753                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1754                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1755         }
1756
1757         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1758
1759         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1760                           " Stat Dmod Deli Vect:   \n");
1761
1762         for (i = 0; i <= reg_01.bits.entries; i++) {
1763                 struct IO_APIC_route_entry entry;
1764
1765                 entry = ioapic_read_entry(apic, i);
1766
1767                 printk(KERN_DEBUG " %02x %03X ",
1768                         i,
1769                         entry.dest
1770                 );
1771
1772                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1773                         entry.mask,
1774                         entry.trigger,
1775                         entry.irr,
1776                         entry.polarity,
1777                         entry.delivery_status,
1778                         entry.dest_mode,
1779                         entry.delivery_mode,
1780                         entry.vector
1781                 );
1782         }
1783         }
1784         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1785         for_each_irq_desc(irq, desc) {
1786                 struct irq_pin_list *entry;
1787
1788                 cfg = desc->chip_data;
1789                 entry = cfg->irq_2_pin;
1790                 if (!entry)
1791                         continue;
1792                 printk(KERN_DEBUG "IRQ%d ", irq);
1793                 for (;;) {
1794                         printk("-> %d:%d", entry->apic, entry->pin);
1795                         if (!entry->next)
1796                                 break;
1797                         entry = entry->next;
1798                 }
1799                 printk("\n");
1800         }
1801
1802         printk(KERN_INFO ".................................... done.\n");
1803
1804         return;
1805 }
1806
1807 __apicdebuginit(void) print_APIC_bitfield(int base)
1808 {
1809         unsigned int v;
1810         int i, j;
1811
1812         if (apic_verbosity == APIC_QUIET)
1813                 return;
1814
1815         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1816         for (i = 0; i < 8; i++) {
1817                 v = apic_read(base + i*0x10);
1818                 for (j = 0; j < 32; j++) {
1819                         if (v & (1<<j))
1820                                 printk("1");
1821                         else
1822                                 printk("0");
1823                 }
1824                 printk("\n");
1825         }
1826 }
1827
1828 __apicdebuginit(void) print_local_APIC(void *dummy)
1829 {
1830         unsigned int v, ver, maxlvt;
1831         u64 icr;
1832
1833         if (apic_verbosity == APIC_QUIET)
1834                 return;
1835
1836         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1837                 smp_processor_id(), hard_smp_processor_id());
1838         v = apic_read(APIC_ID);
1839         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1840         v = apic_read(APIC_LVR);
1841         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1842         ver = GET_APIC_VERSION(v);
1843         maxlvt = lapic_get_maxlvt();
1844
1845         v = apic_read(APIC_TASKPRI);
1846         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1847
1848         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1849                 if (!APIC_XAPIC(ver)) {
1850                         v = apic_read(APIC_ARBPRI);
1851                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1852                                v & APIC_ARBPRI_MASK);
1853                 }
1854                 v = apic_read(APIC_PROCPRI);
1855                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1856         }
1857
1858         /*
1859          * Remote read supported only in the 82489DX and local APIC for
1860          * Pentium processors.
1861          */
1862         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1863                 v = apic_read(APIC_RRR);
1864                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1865         }
1866
1867         v = apic_read(APIC_LDR);
1868         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1869         if (!x2apic_enabled()) {
1870                 v = apic_read(APIC_DFR);
1871                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1872         }
1873         v = apic_read(APIC_SPIV);
1874         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1875
1876         printk(KERN_DEBUG "... APIC ISR field:\n");
1877         print_APIC_bitfield(APIC_ISR);
1878         printk(KERN_DEBUG "... APIC TMR field:\n");
1879         print_APIC_bitfield(APIC_TMR);
1880         printk(KERN_DEBUG "... APIC IRR field:\n");
1881         print_APIC_bitfield(APIC_IRR);
1882
1883         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1884                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1885                         apic_write(APIC_ESR, 0);
1886
1887                 v = apic_read(APIC_ESR);
1888                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1889         }
1890
1891         icr = apic_icr_read();
1892         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1893         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1894
1895         v = apic_read(APIC_LVTT);
1896         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1897
1898         if (maxlvt > 3) {                       /* PC is LVT#4. */
1899                 v = apic_read(APIC_LVTPC);
1900                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1901         }
1902         v = apic_read(APIC_LVT0);
1903         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1904         v = apic_read(APIC_LVT1);
1905         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1906
1907         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1908                 v = apic_read(APIC_LVTERR);
1909                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1910         }
1911
1912         v = apic_read(APIC_TMICT);
1913         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1914         v = apic_read(APIC_TMCCT);
1915         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1916         v = apic_read(APIC_TDCR);
1917         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1918         printk("\n");
1919 }
1920
1921 __apicdebuginit(void) print_all_local_APICs(void)
1922 {
1923         int cpu;
1924
1925         preempt_disable();
1926         for_each_online_cpu(cpu)
1927                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1928         preempt_enable();
1929 }
1930
1931 __apicdebuginit(void) print_PIC(void)
1932 {
1933         unsigned int v;
1934         unsigned long flags;
1935
1936         if (apic_verbosity == APIC_QUIET)
1937                 return;
1938
1939         printk(KERN_DEBUG "\nprinting PIC contents\n");
1940
1941         spin_lock_irqsave(&i8259A_lock, flags);
1942
1943         v = inb(0xa1) << 8 | inb(0x21);
1944         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1945
1946         v = inb(0xa0) << 8 | inb(0x20);
1947         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1948
1949         outb(0x0b,0xa0);
1950         outb(0x0b,0x20);
1951         v = inb(0xa0) << 8 | inb(0x20);
1952         outb(0x0a,0xa0);
1953         outb(0x0a,0x20);
1954
1955         spin_unlock_irqrestore(&i8259A_lock, flags);
1956
1957         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1958
1959         v = inb(0x4d1) << 8 | inb(0x4d0);
1960         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1961 }
1962
1963 __apicdebuginit(int) print_all_ICs(void)
1964 {
1965         print_PIC();
1966         print_all_local_APICs();
1967         print_IO_APIC();
1968
1969         return 0;
1970 }
1971
1972 fs_initcall(print_all_ICs);
1973
1974
1975 /* Where if anywhere is the i8259 connect in external int mode */
1976 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1977
1978 void __init enable_IO_APIC(void)
1979 {
1980         union IO_APIC_reg_01 reg_01;
1981         int i8259_apic, i8259_pin;
1982         int apic;
1983         unsigned long flags;
1984
1985         /*
1986          * The number of IO-APIC IRQ registers (== #pins):
1987          */
1988         for (apic = 0; apic < nr_ioapics; apic++) {
1989                 spin_lock_irqsave(&ioapic_lock, flags);
1990                 reg_01.raw = io_apic_read(apic, 1);
1991                 spin_unlock_irqrestore(&ioapic_lock, flags);
1992                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1993         }
1994         for(apic = 0; apic < nr_ioapics; apic++) {
1995                 int pin;
1996                 /* See if any of the pins is in ExtINT mode */
1997                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1998                         struct IO_APIC_route_entry entry;
1999                         entry = ioapic_read_entry(apic, pin);
2000
2001                         /* If the interrupt line is enabled and in ExtInt mode
2002                          * I have found the pin where the i8259 is connected.
2003                          */
2004                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2005                                 ioapic_i8259.apic = apic;
2006                                 ioapic_i8259.pin  = pin;
2007                                 goto found_i8259;
2008                         }
2009                 }
2010         }
2011  found_i8259:
2012         /* Look to see what if the MP table has reported the ExtINT */
2013         /* If we could not find the appropriate pin by looking at the ioapic
2014          * the i8259 probably is not connected the ioapic but give the
2015          * mptable a chance anyway.
2016          */
2017         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2018         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2019         /* Trust the MP table if nothing is setup in the hardware */
2020         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2021                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2022                 ioapic_i8259.pin  = i8259_pin;
2023                 ioapic_i8259.apic = i8259_apic;
2024         }
2025         /* Complain if the MP table and the hardware disagree */
2026         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2027                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2028         {
2029                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2030         }
2031
2032         /*
2033          * Do not trust the IO-APIC being empty at bootup
2034          */
2035         clear_IO_APIC();
2036 }
2037
2038 /*
2039  * Not an __init, needed by the reboot code
2040  */
2041 void disable_IO_APIC(void)
2042 {
2043         /*
2044          * Clear the IO-APIC before rebooting:
2045          */
2046         clear_IO_APIC();
2047
2048         /*
2049          * If the i8259 is routed through an IOAPIC
2050          * Put that IOAPIC in virtual wire mode
2051          * so legacy interrupts can be delivered.
2052          *
2053          * With interrupt-remapping, for now we will use virtual wire A mode,
2054          * as virtual wire B is little complex (need to configure both
2055          * IOAPIC RTE aswell as interrupt-remapping table entry).
2056          * As this gets called during crash dump, keep this simple for now.
2057          */
2058         if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2059                 struct IO_APIC_route_entry entry;
2060
2061                 memset(&entry, 0, sizeof(entry));
2062                 entry.mask            = 0; /* Enabled */
2063                 entry.trigger         = 0; /* Edge */
2064                 entry.irr             = 0;
2065                 entry.polarity        = 0; /* High */
2066                 entry.delivery_status = 0;
2067                 entry.dest_mode       = 0; /* Physical */
2068                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2069                 entry.vector          = 0;
2070                 entry.dest            = read_apic_id();
2071
2072                 /*
2073                  * Add it to the IO-APIC irq-routing table:
2074                  */
2075                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2076         }
2077
2078         /*
2079          * Use virtual wire A mode when interrupt remapping is enabled.
2080          */
2081         disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2082 }
2083
2084 #ifdef CONFIG_X86_32
2085 /*
2086  * function to set the IO-APIC physical IDs based on the
2087  * values stored in the MPC table.
2088  *
2089  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2090  */
2091
2092 static void __init setup_ioapic_ids_from_mpc(void)
2093 {
2094         union IO_APIC_reg_00 reg_00;
2095         physid_mask_t phys_id_present_map;
2096         int apic_id;
2097         int i;
2098         unsigned char old_id;
2099         unsigned long flags;
2100
2101         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2102                 return;
2103
2104         /*
2105          * Don't check I/O APIC IDs for xAPIC systems.  They have
2106          * no meaning without the serial APIC bus.
2107          */
2108         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2109                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2110                 return;
2111         /*
2112          * This is broken; anything with a real cpu count has to
2113          * circumvent this idiocy regardless.
2114          */
2115         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2116
2117         /*
2118          * Set the IOAPIC ID to the value stored in the MPC table.
2119          */
2120         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2121
2122                 /* Read the register 0 value */
2123                 spin_lock_irqsave(&ioapic_lock, flags);
2124                 reg_00.raw = io_apic_read(apic_id, 0);
2125                 spin_unlock_irqrestore(&ioapic_lock, flags);
2126
2127                 old_id = mp_ioapics[apic_id].apicid;
2128
2129                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2130                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2131                                 apic_id, mp_ioapics[apic_id].apicid);
2132                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2133                                 reg_00.bits.ID);
2134                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2135                 }
2136
2137                 /*
2138                  * Sanity check, is the ID really free? Every APIC in a
2139                  * system must have a unique ID or we get lots of nice
2140                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2141                  */
2142                 if (apic->check_apicid_used(phys_id_present_map,
2143                                         mp_ioapics[apic_id].apicid)) {
2144                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2145                                 apic_id, mp_ioapics[apic_id].apicid);
2146                         for (i = 0; i < get_physical_broadcast(); i++)
2147                                 if (!physid_isset(i, phys_id_present_map))
2148                                         break;
2149                         if (i >= get_physical_broadcast())
2150                                 panic("Max APIC ID exceeded!\n");
2151                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2152                                 i);
2153                         physid_set(i, phys_id_present_map);
2154                         mp_ioapics[apic_id].apicid = i;
2155                 } else {
2156                         physid_mask_t tmp;
2157                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2158                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2159                                         "phys_id_present_map\n",
2160                                         mp_ioapics[apic_id].apicid);
2161                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2162                 }
2163
2164
2165                 /*
2166                  * We need to adjust the IRQ routing table
2167                  * if the ID changed.
2168                  */
2169                 if (old_id != mp_ioapics[apic_id].apicid)
2170                         for (i = 0; i < mp_irq_entries; i++)
2171                                 if (mp_irqs[i].dstapic == old_id)
2172                                         mp_irqs[i].dstapic
2173                                                 = mp_ioapics[apic_id].apicid;
2174
2175                 /*
2176                  * Read the right value from the MPC table and
2177                  * write it into the ID register.
2178                  */
2179                 apic_printk(APIC_VERBOSE, KERN_INFO
2180                         "...changing IO-APIC physical APIC ID to %d ...",
2181                         mp_ioapics[apic_id].apicid);
2182
2183                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2184                 spin_lock_irqsave(&ioapic_lock, flags);
2185                 io_apic_write(apic_id, 0, reg_00.raw);
2186                 spin_unlock_irqrestore(&ioapic_lock, flags);
2187
2188                 /*
2189                  * Sanity check
2190                  */
2191                 spin_lock_irqsave(&ioapic_lock, flags);
2192                 reg_00.raw = io_apic_read(apic_id, 0);
2193                 spin_unlock_irqrestore(&ioapic_lock, flags);
2194                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2195                         printk("could not set ID!\n");
2196                 else
2197                         apic_printk(APIC_VERBOSE, " ok.\n");
2198         }
2199 }
2200 #endif
2201
2202 int no_timer_check __initdata;
2203
2204 static int __init notimercheck(char *s)
2205 {
2206         no_timer_check = 1;
2207         return 1;
2208 }
2209 __setup("no_timer_check", notimercheck);
2210
2211 /*
2212  * There is a nasty bug in some older SMP boards, their mptable lies
2213  * about the timer IRQ. We do the following to work around the situation:
2214  *
2215  *      - timer IRQ defaults to IO-APIC IRQ
2216  *      - if this function detects that timer IRQs are defunct, then we fall
2217  *        back to ISA timer IRQs
2218  */
2219 static int __init timer_irq_works(void)
2220 {
2221         unsigned long t1 = jiffies;
2222         unsigned long flags;
2223
2224         if (no_timer_check)
2225                 return 1;
2226
2227         local_save_flags(flags);
2228         local_irq_enable();
2229         /* Let ten ticks pass... */
2230         mdelay((10 * 1000) / HZ);
2231         local_irq_restore(flags);
2232
2233         /*
2234          * Expect a few ticks at least, to be sure some possible
2235          * glue logic does not lock up after one or two first
2236          * ticks in a non-ExtINT mode.  Also the local APIC
2237          * might have cached one ExtINT interrupt.  Finally, at
2238          * least one tick may be lost due to delays.
2239          */
2240
2241         /* jiffies wrap? */
2242         if (time_after(jiffies, t1 + 4))
2243                 return 1;
2244         return 0;
2245 }
2246
2247 /*
2248  * In the SMP+IOAPIC case it might happen that there are an unspecified
2249  * number of pending IRQ events unhandled. These cases are very rare,
2250  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2251  * better to do it this way as thus we do not have to be aware of
2252  * 'pending' interrupts in the IRQ path, except at this point.
2253  */
2254 /*
2255  * Edge triggered needs to resend any interrupt
2256  * that was delayed but this is now handled in the device
2257  * independent code.
2258  */
2259
2260 /*
2261  * Starting up a edge-triggered IO-APIC interrupt is
2262  * nasty - we need to make sure that we get the edge.
2263  * If it is already asserted for some reason, we need
2264  * return 1 to indicate that is was pending.
2265  *
2266  * This is not complete - we should be able to fake
2267  * an edge even if it isn't on the 8259A...
2268  */
2269
2270 static unsigned int startup_ioapic_irq(unsigned int irq)
2271 {
2272         int was_pending = 0;
2273         unsigned long flags;
2274         struct irq_cfg *cfg;
2275
2276         spin_lock_irqsave(&ioapic_lock, flags);
2277         if (irq < NR_IRQS_LEGACY) {
2278                 disable_8259A_irq(irq);
2279                 if (i8259A_irq_pending(irq))
2280                         was_pending = 1;
2281         }
2282         cfg = irq_cfg(irq);
2283         __unmask_IO_APIC_irq(cfg);
2284         spin_unlock_irqrestore(&ioapic_lock, flags);
2285
2286         return was_pending;
2287 }
2288
2289 #ifdef CONFIG_X86_64
2290 static int ioapic_retrigger_irq(unsigned int irq)
2291 {
2292
2293         struct irq_cfg *cfg = irq_cfg(irq);
2294         unsigned long flags;
2295
2296         spin_lock_irqsave(&vector_lock, flags);
2297         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2298         spin_unlock_irqrestore(&vector_lock, flags);
2299
2300         return 1;
2301 }
2302 #else
2303 static int ioapic_retrigger_irq(unsigned int irq)
2304 {
2305         apic->send_IPI_self(irq_cfg(irq)->vector);
2306
2307         return 1;
2308 }
2309 #endif
2310
2311 /*
2312  * Level and edge triggered IO-APIC interrupts need different handling,
2313  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2314  * handled with the level-triggered descriptor, but that one has slightly
2315  * more overhead. Level-triggered interrupts cannot be handled with the
2316  * edge-triggered handler, without risking IRQ storms and other ugly
2317  * races.
2318  */
2319
2320 #ifdef CONFIG_SMP
2321
2322 #ifdef CONFIG_INTR_REMAP
2323
2324 /*
2325  * Migrate the IO-APIC irq in the presence of intr-remapping.
2326  *
2327  * For both level and edge triggered, irq migration is a simple atomic
2328  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2329  *
2330  * For level triggered, we eliminate the io-apic RTE modification (with the
2331  * updated vector information), by using a virtual vector (io-apic pin number).
2332  * Real vector that is used for interrupting cpu will be coming from
2333  * the interrupt-remapping table entry.
2334  */
2335 static void
2336 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2337 {
2338         struct irq_cfg *cfg;
2339         struct irte irte;
2340         unsigned int dest;
2341         unsigned int irq;
2342
2343         if (!cpumask_intersects(mask, cpu_online_mask))
2344                 return;
2345
2346         irq = desc->irq;
2347         if (get_irte(irq, &irte))
2348                 return;
2349
2350         cfg = desc->chip_data;
2351         if (assign_irq_vector(irq, cfg, mask))
2352                 return;
2353
2354         set_extra_move_desc(desc, mask);
2355
2356         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2357
2358         irte.vector = cfg->vector;
2359         irte.dest_id = IRTE_DEST(dest);
2360
2361         /*
2362          * Modified the IRTE and flushes the Interrupt entry cache.
2363          */
2364         modify_irte(irq, &irte);
2365
2366         if (cfg->move_in_progress)
2367                 send_cleanup_vector(cfg);
2368
2369         cpumask_copy(desc->affinity, mask);
2370 }
2371
2372 /*
2373  * Migrates the IRQ destination in the process context.
2374  */
2375 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2376                                             const struct cpumask *mask)
2377 {
2378         migrate_ioapic_irq_desc(desc, mask);
2379 }
2380 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2381                                        const struct cpumask *mask)
2382 {
2383         struct irq_desc *desc = irq_to_desc(irq);
2384
2385         set_ir_ioapic_affinity_irq_desc(desc, mask);
2386 }
2387 #else
2388 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2389                                                    const struct cpumask *mask)
2390 {
2391 }
2392 #endif
2393
2394 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2395 {
2396         unsigned vector, me;
2397
2398         ack_APIC_irq();
2399         exit_idle();
2400         irq_enter();
2401
2402         me = smp_processor_id();
2403         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2404                 unsigned int irq;
2405                 struct irq_desc *desc;
2406                 struct irq_cfg *cfg;
2407                 irq = __get_cpu_var(vector_irq)[vector];
2408
2409                 if (irq == -1)
2410                         continue;
2411
2412                 desc = irq_to_desc(irq);
2413                 if (!desc)
2414                         continue;
2415
2416                 cfg = irq_cfg(irq);
2417                 spin_lock(&desc->lock);
2418                 if (!cfg->move_cleanup_count)
2419                         goto unlock;
2420
2421                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2422                         goto unlock;
2423
2424                 __get_cpu_var(vector_irq)[vector] = -1;
2425                 cfg->move_cleanup_count--;
2426 unlock:
2427                 spin_unlock(&desc->lock);
2428         }
2429
2430         irq_exit();
2431 }
2432
2433 static void irq_complete_move(struct irq_desc **descp)
2434 {
2435         struct irq_desc *desc = *descp;
2436         struct irq_cfg *cfg = desc->chip_data;
2437         unsigned vector, me;
2438
2439         if (likely(!cfg->move_in_progress)) {
2440 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2441                 if (likely(!cfg->move_desc_pending))
2442                         return;
2443
2444                 /* domain has not changed, but affinity did */
2445                 me = smp_processor_id();
2446                 if (cpumask_test_cpu(me, desc->affinity)) {
2447                         *descp = desc = move_irq_desc(desc, me);
2448                         /* get the new one */
2449                         cfg = desc->chip_data;
2450                         cfg->move_desc_pending = 0;
2451                 }
2452 #endif
2453                 return;
2454         }
2455
2456         vector = ~get_irq_regs()->orig_ax;
2457         me = smp_processor_id();
2458
2459         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2460 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2461                 *descp = desc = move_irq_desc(desc, me);
2462                 /* get the new one */
2463                 cfg = desc->chip_data;
2464 #endif
2465                 send_cleanup_vector(cfg);
2466         }
2467 }
2468 #else
2469 static inline void irq_complete_move(struct irq_desc **descp) {}
2470 #endif
2471
2472 #ifdef CONFIG_INTR_REMAP
2473 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2474 {
2475         int apic, pin;
2476         struct irq_pin_list *entry;
2477
2478         entry = cfg->irq_2_pin;
2479         for (;;) {
2480
2481                 if (!entry)
2482                         break;
2483
2484                 apic = entry->apic;
2485                 pin = entry->pin;
2486                 io_apic_eoi(apic, pin);
2487                 entry = entry->next;
2488         }
2489 }
2490
2491 static void
2492 eoi_ioapic_irq(struct irq_desc *desc)
2493 {
2494         struct irq_cfg *cfg;
2495         unsigned long flags;
2496         unsigned int irq;
2497
2498         irq = desc->irq;
2499         cfg = desc->chip_data;
2500
2501         spin_lock_irqsave(&ioapic_lock, flags);
2502         __eoi_ioapic_irq(irq, cfg);
2503         spin_unlock_irqrestore(&ioapic_lock, flags);
2504 }
2505
2506 static void ack_x2apic_level(unsigned int irq)
2507 {
2508         struct irq_desc *desc = irq_to_desc(irq);
2509         ack_x2APIC_irq();
2510         eoi_ioapic_irq(desc);
2511 }
2512
2513 static void ack_x2apic_edge(unsigned int irq)
2514 {
2515         ack_x2APIC_irq();
2516 }
2517
2518 #endif
2519
2520 static void ack_apic_edge(unsigned int irq)
2521 {
2522         struct irq_desc *desc = irq_to_desc(irq);
2523
2524         irq_complete_move(&desc);
2525         move_native_irq(irq);
2526         ack_APIC_irq();
2527 }
2528
2529 atomic_t irq_mis_count;
2530
2531 static void ack_apic_level(unsigned int irq)
2532 {
2533         struct irq_desc *desc = irq_to_desc(irq);
2534
2535 #ifdef CONFIG_X86_32
2536         unsigned long v;
2537         int i;
2538 #endif
2539         struct irq_cfg *cfg;
2540         int do_unmask_irq = 0;
2541
2542         irq_complete_move(&desc);
2543 #ifdef CONFIG_GENERIC_PENDING_IRQ
2544         /* If we are moving the irq we need to mask it */
2545         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2546                 do_unmask_irq = 1;
2547                 mask_IO_APIC_irq_desc(desc);
2548         }
2549 #endif
2550
2551 #ifdef CONFIG_X86_32
2552         /*
2553         * It appears there is an erratum which affects at least version 0x11
2554         * of I/O APIC (that's the 82093AA and cores integrated into various
2555         * chipsets).  Under certain conditions a level-triggered interrupt is
2556         * erroneously delivered as edge-triggered one but the respective IRR
2557         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2558         * message but it will never arrive and further interrupts are blocked
2559         * from the source.  The exact reason is so far unknown, but the
2560         * phenomenon was observed when two consecutive interrupt requests
2561         * from a given source get delivered to the same CPU and the source is
2562         * temporarily disabled in between.
2563         *
2564         * A workaround is to simulate an EOI message manually.  We achieve it
2565         * by setting the trigger mode to edge and then to level when the edge
2566         * trigger mode gets detected in the TMR of a local APIC for a
2567         * level-triggered interrupt.  We mask the source for the time of the
2568         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2569         * The idea is from Manfred Spraul.  --macro
2570         */
2571         cfg = desc->chip_data;
2572         i = cfg->vector;
2573
2574         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2575 #endif
2576
2577         /*
2578          * We must acknowledge the irq before we move it or the acknowledge will
2579          * not propagate properly.
2580          */
2581         ack_APIC_irq();
2582
2583         /* Now we can move and renable the irq */
2584         if (unlikely(do_unmask_irq)) {
2585                 /* Only migrate the irq if the ack has been received.
2586                  *
2587                  * On rare occasions the broadcast level triggered ack gets
2588                  * delayed going to ioapics, and if we reprogram the
2589                  * vector while Remote IRR is still set the irq will never
2590                  * fire again.
2591                  *
2592                  * To prevent this scenario we read the Remote IRR bit
2593                  * of the ioapic.  This has two effects.
2594                  * - On any sane system the read of the ioapic will
2595                  *   flush writes (and acks) going to the ioapic from
2596                  *   this cpu.
2597                  * - We get to see if the ACK has actually been delivered.
2598                  *
2599                  * Based on failed experiments of reprogramming the
2600                  * ioapic entry from outside of irq context starting
2601                  * with masking the ioapic entry and then polling until
2602                  * Remote IRR was clear before reprogramming the
2603                  * ioapic I don't trust the Remote IRR bit to be
2604                  * completey accurate.
2605                  *
2606                  * However there appears to be no other way to plug
2607                  * this race, so if the Remote IRR bit is not
2608                  * accurate and is causing problems then it is a hardware bug
2609                  * and you can go talk to the chipset vendor about it.
2610                  */
2611                 cfg = desc->chip_data;
2612                 if (!io_apic_level_ack_pending(cfg))
2613                         move_masked_irq(irq);
2614                 unmask_IO_APIC_irq_desc(desc);
2615         }
2616
2617 #ifdef CONFIG_X86_32
2618         if (!(v & (1 << (i & 0x1f)))) {
2619                 atomic_inc(&irq_mis_count);
2620                 spin_lock(&ioapic_lock);
2621                 __mask_and_edge_IO_APIC_irq(cfg);
2622                 __unmask_and_level_IO_APIC_irq(cfg);
2623                 spin_unlock(&ioapic_lock);
2624         }
2625 #endif
2626 }
2627
2628 static struct irq_chip ioapic_chip __read_mostly = {
2629         .name           = "IO-APIC",
2630         .startup        = startup_ioapic_irq,
2631         .mask           = mask_IO_APIC_irq,
2632         .unmask         = unmask_IO_APIC_irq,
2633         .ack            = ack_apic_edge,
2634         .eoi            = ack_apic_level,
2635 #ifdef CONFIG_SMP
2636         .set_affinity   = set_ioapic_affinity_irq,
2637 #endif
2638         .retrigger      = ioapic_retrigger_irq,
2639 };
2640
2641 #ifdef CONFIG_INTR_REMAP
2642 static struct irq_chip ir_ioapic_chip __read_mostly = {
2643         .name           = "IR-IO-APIC",
2644         .startup        = startup_ioapic_irq,
2645         .mask           = mask_IO_APIC_irq,
2646         .unmask         = unmask_IO_APIC_irq,
2647         .ack            = ack_x2apic_edge,
2648         .eoi            = ack_x2apic_level,
2649 #ifdef CONFIG_SMP
2650         .set_affinity   = set_ir_ioapic_affinity_irq,
2651 #endif
2652         .retrigger      = ioapic_retrigger_irq,
2653 };
2654 #endif
2655
2656 static inline void init_IO_APIC_traps(void)
2657 {
2658         int irq;
2659         struct irq_desc *desc;
2660         struct irq_cfg *cfg;
2661
2662         /*
2663          * NOTE! The local APIC isn't very good at handling
2664          * multiple interrupts at the same interrupt level.
2665          * As the interrupt level is determined by taking the
2666          * vector number and shifting that right by 4, we
2667          * want to spread these out a bit so that they don't
2668          * all fall in the same interrupt level.
2669          *
2670          * Also, we've got to be careful not to trash gate
2671          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2672          */
2673         for_each_irq_desc(irq, desc) {
2674                 cfg = desc->chip_data;
2675                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2676                         /*
2677                          * Hmm.. We don't have an entry for this,
2678                          * so default to an old-fashioned 8259
2679                          * interrupt if we can..
2680                          */
2681                         if (irq < NR_IRQS_LEGACY)
2682                                 make_8259A_irq(irq);
2683                         else
2684                                 /* Strange. Oh, well.. */
2685                                 desc->chip = &no_irq_chip;
2686                 }
2687         }
2688 }
2689
2690 /*
2691  * The local APIC irq-chip implementation:
2692  */
2693
2694 static void mask_lapic_irq(unsigned int irq)
2695 {
2696         unsigned long v;
2697
2698         v = apic_read(APIC_LVT0);
2699         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2700 }
2701
2702 static void unmask_lapic_irq(unsigned int irq)
2703 {
2704         unsigned long v;
2705
2706         v = apic_read(APIC_LVT0);
2707         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2708 }
2709
2710 static void ack_lapic_irq(unsigned int irq)
2711 {
2712         ack_APIC_irq();
2713 }
2714
2715 static struct irq_chip lapic_chip __read_mostly = {
2716         .name           = "local-APIC",
2717         .mask           = mask_lapic_irq,
2718         .unmask         = unmask_lapic_irq,
2719         .ack            = ack_lapic_irq,
2720 };
2721
2722 static void lapic_register_intr(int irq, struct irq_desc *desc)
2723 {
2724         desc->status &= ~IRQ_LEVEL;
2725         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2726                                       "edge");
2727 }
2728
2729 static void __init setup_nmi(void)
2730 {
2731         /*
2732          * Dirty trick to enable the NMI watchdog ...
2733          * We put the 8259A master into AEOI mode and
2734          * unmask on all local APICs LVT0 as NMI.
2735          *
2736          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2737          * is from Maciej W. Rozycki - so we do not have to EOI from
2738          * the NMI handler or the timer interrupt.
2739          */
2740         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2741
2742         enable_NMI_through_LVT0();
2743
2744         apic_printk(APIC_VERBOSE, " done.\n");
2745 }
2746
2747 /*
2748  * This looks a bit hackish but it's about the only one way of sending
2749  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2750  * not support the ExtINT mode, unfortunately.  We need to send these
2751  * cycles as some i82489DX-based boards have glue logic that keeps the
2752  * 8259A interrupt line asserted until INTA.  --macro
2753  */
2754 static inline void __init unlock_ExtINT_logic(void)
2755 {
2756         int apic, pin, i;
2757         struct IO_APIC_route_entry entry0, entry1;
2758         unsigned char save_control, save_freq_select;
2759
2760         pin  = find_isa_irq_pin(8, mp_INT);
2761         if (pin == -1) {
2762                 WARN_ON_ONCE(1);
2763                 return;
2764         }
2765         apic = find_isa_irq_apic(8, mp_INT);
2766         if (apic == -1) {
2767                 WARN_ON_ONCE(1);
2768                 return;
2769         }
2770
2771         entry0 = ioapic_read_entry(apic, pin);
2772         clear_IO_APIC_pin(apic, pin);
2773
2774         memset(&entry1, 0, sizeof(entry1));
2775
2776         entry1.dest_mode = 0;                   /* physical delivery */
2777         entry1.mask = 0;                        /* unmask IRQ now */
2778         entry1.dest = hard_smp_processor_id();
2779         entry1.delivery_mode = dest_ExtINT;
2780         entry1.polarity = entry0.polarity;
2781         entry1.trigger = 0;
2782         entry1.vector = 0;
2783
2784         ioapic_write_entry(apic, pin, entry1);
2785
2786         save_control = CMOS_READ(RTC_CONTROL);
2787         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2788         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2789                    RTC_FREQ_SELECT);
2790         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2791
2792         i = 100;
2793         while (i-- > 0) {
2794                 mdelay(10);
2795                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2796                         i -= 10;
2797         }
2798
2799         CMOS_WRITE(save_control, RTC_CONTROL);
2800         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2801         clear_IO_APIC_pin(apic, pin);
2802
2803         ioapic_write_entry(apic, pin, entry0);
2804 }
2805
2806 static int disable_timer_pin_1 __initdata;
2807 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2808 static int __init disable_timer_pin_setup(char *arg)
2809 {
2810         disable_timer_pin_1 = 1;
2811         return 0;
2812 }
2813 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2814
2815 int timer_through_8259 __initdata;
2816
2817 /*
2818  * This code may look a bit paranoid, but it's supposed to cooperate with
2819  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2820  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2821  * fanatically on his truly buggy board.
2822  *
2823  * FIXME: really need to revamp this for all platforms.
2824  */
2825 static inline void __init check_timer(void)
2826 {
2827         struct irq_desc *desc = irq_to_desc(0);
2828         struct irq_cfg *cfg = desc->chip_data;
2829         int cpu = boot_cpu_id;
2830         int apic1, pin1, apic2, pin2;
2831         unsigned long flags;
2832         int no_pin1 = 0;
2833
2834         local_irq_save(flags);
2835
2836         /*
2837          * get/set the timer IRQ vector:
2838          */
2839         disable_8259A_irq(0);
2840         assign_irq_vector(0, cfg, apic->target_cpus());
2841
2842         /*
2843          * As IRQ0 is to be enabled in the 8259A, the virtual
2844          * wire has to be disabled in the local APIC.  Also
2845          * timer interrupts need to be acknowledged manually in
2846          * the 8259A for the i82489DX when using the NMI
2847          * watchdog as that APIC treats NMIs as level-triggered.
2848          * The AEOI mode will finish them in the 8259A
2849          * automatically.
2850          */
2851         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2852         init_8259A(1);
2853 #ifdef CONFIG_X86_32
2854         {
2855                 unsigned int ver;
2856
2857                 ver = apic_read(APIC_LVR);
2858                 ver = GET_APIC_VERSION(ver);
2859                 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2860         }
2861 #endif
2862
2863         pin1  = find_isa_irq_pin(0, mp_INT);
2864         apic1 = find_isa_irq_apic(0, mp_INT);
2865         pin2  = ioapic_i8259.pin;
2866         apic2 = ioapic_i8259.apic;
2867
2868         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2869                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2870                     cfg->vector, apic1, pin1, apic2, pin2);
2871
2872         /*
2873          * Some BIOS writers are clueless and report the ExtINTA
2874          * I/O APIC input from the cascaded 8259A as the timer
2875          * interrupt input.  So just in case, if only one pin
2876          * was found above, try it both directly and through the
2877          * 8259A.
2878          */
2879         if (pin1 == -1) {
2880                 if (intr_remapping_enabled)
2881                         panic("BIOS bug: timer not connected to IO-APIC");
2882                 pin1 = pin2;
2883                 apic1 = apic2;
2884                 no_pin1 = 1;
2885         } else if (pin2 == -1) {
2886                 pin2 = pin1;
2887                 apic2 = apic1;
2888         }
2889
2890         if (pin1 != -1) {
2891                 /*
2892                  * Ok, does IRQ0 through the IOAPIC work?
2893                  */
2894                 if (no_pin1) {
2895                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2896                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2897                 } else {
2898                         /* for edge trigger, setup_IO_APIC_irq already
2899                          * leave it unmasked.
2900                          * so only need to unmask if it is level-trigger
2901                          * do we really have level trigger timer?
2902                          */
2903                         int idx;
2904                         idx = find_irq_entry(apic1, pin1, mp_INT);
2905                         if (idx != -1 && irq_trigger(idx))
2906                                 unmask_IO_APIC_irq_desc(desc);
2907                 }
2908                 if (timer_irq_works()) {
2909                         if (nmi_watchdog == NMI_IO_APIC) {
2910                                 setup_nmi();
2911                                 enable_8259A_irq(0);
2912                         }
2913                         if (disable_timer_pin_1 > 0)
2914                                 clear_IO_APIC_pin(0, pin1);
2915                         goto out;
2916                 }
2917                 if (intr_remapping_enabled)
2918                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2919                 local_irq_disable();
2920                 clear_IO_APIC_pin(apic1, pin1);
2921                 if (!no_pin1)
2922                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2923                                     "8254 timer not connected to IO-APIC\n");
2924
2925                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2926                             "(IRQ0) through the 8259A ...\n");
2927                 apic_printk(APIC_QUIET, KERN_INFO
2928                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2929                 /*
2930                  * legacy devices should be connected to IO APIC #0
2931                  */
2932                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2933                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2934                 enable_8259A_irq(0);
2935                 if (timer_irq_works()) {
2936                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2937                         timer_through_8259 = 1;
2938                         if (nmi_watchdog == NMI_IO_APIC) {
2939                                 disable_8259A_irq(0);
2940                                 setup_nmi();
2941                                 enable_8259A_irq(0);
2942                         }
2943                         goto out;
2944                 }
2945                 /*
2946                  * Cleanup, just in case ...
2947                  */
2948                 local_irq_disable();
2949                 disable_8259A_irq(0);
2950                 clear_IO_APIC_pin(apic2, pin2);
2951                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2952         }
2953
2954         if (nmi_watchdog == NMI_IO_APIC) {
2955                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2956                             "through the IO-APIC - disabling NMI Watchdog!\n");
2957                 nmi_watchdog = NMI_NONE;
2958         }
2959 #ifdef CONFIG_X86_32
2960         timer_ack = 0;
2961 #endif
2962
2963         apic_printk(APIC_QUIET, KERN_INFO
2964                     "...trying to set up timer as Virtual Wire IRQ...\n");
2965
2966         lapic_register_intr(0, desc);
2967         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2968         enable_8259A_irq(0);
2969
2970         if (timer_irq_works()) {
2971                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2972                 goto out;
2973         }
2974         local_irq_disable();
2975         disable_8259A_irq(0);
2976         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2977         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2978
2979         apic_printk(APIC_QUIET, KERN_INFO
2980                     "...trying to set up timer as ExtINT IRQ...\n");
2981
2982         init_8259A(0);
2983         make_8259A_irq(0);
2984         apic_write(APIC_LVT0, APIC_DM_EXTINT);
2985
2986         unlock_ExtINT_logic();
2987
2988         if (timer_irq_works()) {
2989                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2990                 goto out;
2991         }
2992         local_irq_disable();
2993         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2994         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2995                 "report.  Then try booting with the 'noapic' option.\n");
2996 out:
2997         local_irq_restore(flags);
2998 }
2999
3000 /*
3001  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3002  * to devices.  However there may be an I/O APIC pin available for
3003  * this interrupt regardless.  The pin may be left unconnected, but
3004  * typically it will be reused as an ExtINT cascade interrupt for
3005  * the master 8259A.  In the MPS case such a pin will normally be
3006  * reported as an ExtINT interrupt in the MP table.  With ACPI
3007  * there is no provision for ExtINT interrupts, and in the absence
3008  * of an override it would be treated as an ordinary ISA I/O APIC
3009  * interrupt, that is edge-triggered and unmasked by default.  We
3010  * used to do this, but it caused problems on some systems because
3011  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3012  * the same ExtINT cascade interrupt to drive the local APIC of the
3013  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3014  * the I/O APIC in all cases now.  No actual device should request
3015  * it anyway.  --macro
3016  */
3017 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3018
3019 void __init setup_IO_APIC(void)
3020 {
3021
3022         /*
3023          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3024          */
3025
3026         io_apic_irqs = ~PIC_IRQS;
3027
3028         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3029         /*
3030          * Set up IO-APIC IRQ routing.
3031          */
3032 #ifdef CONFIG_X86_32
3033         if (!acpi_ioapic)
3034                 setup_ioapic_ids_from_mpc();
3035 #endif
3036         sync_Arb_IDs();
3037         setup_IO_APIC_irqs();
3038         init_IO_APIC_traps();
3039         check_timer();
3040 }
3041
3042 /*
3043  *      Called after all the initialization is done. If we didnt find any
3044  *      APIC bugs then we can allow the modify fast path
3045  */
3046
3047 static int __init io_apic_bug_finalize(void)
3048 {
3049         if (sis_apic_bug == -1)
3050                 sis_apic_bug = 0;
3051         return 0;
3052 }
3053
3054 late_initcall(io_apic_bug_finalize);
3055
3056 struct sysfs_ioapic_data {
3057         struct sys_device dev;
3058         struct IO_APIC_route_entry entry[0];
3059 };
3060 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3061
3062 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3063 {
3064         struct IO_APIC_route_entry *entry;
3065         struct sysfs_ioapic_data *data;
3066         int i;
3067
3068         data = container_of(dev, struct sysfs_ioapic_data, dev);
3069         entry = data->entry;
3070         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3071                 *entry = ioapic_read_entry(dev->id, i);
3072
3073         return 0;
3074 }
3075
3076 static int ioapic_resume(struct sys_device *dev)
3077 {
3078         struct IO_APIC_route_entry *entry;
3079         struct sysfs_ioapic_data *data;
3080         unsigned long flags;
3081         union IO_APIC_reg_00 reg_00;
3082         int i;
3083
3084         data = container_of(dev, struct sysfs_ioapic_data, dev);
3085         entry = data->entry;
3086
3087         spin_lock_irqsave(&ioapic_lock, flags);
3088         reg_00.raw = io_apic_read(dev->id, 0);
3089         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3090                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3091                 io_apic_write(dev->id, 0, reg_00.raw);
3092         }
3093         spin_unlock_irqrestore(&ioapic_lock, flags);
3094         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3095                 ioapic_write_entry(dev->id, i, entry[i]);
3096
3097         return 0;
3098 }
3099
3100 static struct sysdev_class ioapic_sysdev_class = {
3101         .name = "ioapic",
3102         .suspend = ioapic_suspend,
3103         .resume = ioapic_resume,
3104 };
3105
3106 static int __init ioapic_init_sysfs(void)
3107 {
3108         struct sys_device * dev;
3109         int i, size, error;
3110
3111         error = sysdev_class_register(&ioapic_sysdev_class);
3112         if (error)
3113                 return error;
3114
3115         for (i = 0; i < nr_ioapics; i++ ) {
3116                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3117                         * sizeof(struct IO_APIC_route_entry);
3118                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3119                 if (!mp_ioapic_data[i]) {
3120                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3121                         continue;
3122                 }
3123                 dev = &mp_ioapic_data[i]->dev;
3124                 dev->id = i;
3125                 dev->cls = &ioapic_sysdev_class;
3126                 error = sysdev_register(dev);
3127                 if (error) {
3128                         kfree(mp_ioapic_data[i]);
3129                         mp_ioapic_data[i] = NULL;
3130                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3131                         continue;
3132                 }
3133         }
3134
3135         return 0;
3136 }
3137
3138 device_initcall(ioapic_init_sysfs);
3139
3140 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3141 /*
3142  * Dynamic irq allocate and deallocation
3143  */
3144 unsigned int create_irq_nr(unsigned int irq_want)
3145 {
3146         /* Allocate an unused irq */
3147         unsigned int irq;
3148         unsigned int new;
3149         unsigned long flags;
3150         struct irq_cfg *cfg_new = NULL;
3151         int cpu = boot_cpu_id;
3152         struct irq_desc *desc_new = NULL;
3153
3154         irq = 0;
3155         if (irq_want < nr_irqs_gsi)
3156                 irq_want = nr_irqs_gsi;
3157
3158         spin_lock_irqsave(&vector_lock, flags);
3159         for (new = irq_want; new < nr_irqs; new++) {
3160                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3161                 if (!desc_new) {
3162                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3163                         continue;
3164                 }
3165                 cfg_new = desc_new->chip_data;
3166
3167                 if (cfg_new->vector != 0)
3168                         continue;
3169                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3170                         irq = new;
3171                 break;
3172         }
3173         spin_unlock_irqrestore(&vector_lock, flags);
3174
3175         if (irq > 0) {
3176                 dynamic_irq_init(irq);
3177                 /* restore it, in case dynamic_irq_init clear it */
3178                 if (desc_new)
3179                         desc_new->chip_data = cfg_new;
3180         }
3181         return irq;
3182 }
3183
3184 int create_irq(void)
3185 {
3186         unsigned int irq_want;
3187         int irq;
3188
3189         irq_want = nr_irqs_gsi;
3190         irq = create_irq_nr(irq_want);
3191
3192         if (irq == 0)
3193                 irq = -1;
3194
3195         return irq;
3196 }
3197
3198 void destroy_irq(unsigned int irq)
3199 {
3200         unsigned long flags;
3201         struct irq_cfg *cfg;
3202         struct irq_desc *desc;
3203
3204         /* store it, in case dynamic_irq_cleanup clear it */
3205         desc = irq_to_desc(irq);
3206         cfg = desc->chip_data;
3207         dynamic_irq_cleanup(irq);
3208         /* connect back irq_cfg */
3209         if (desc)
3210                 desc->chip_data = cfg;
3211
3212         free_irte(irq);
3213         spin_lock_irqsave(&vector_lock, flags);
3214         __clear_irq_vector(irq, cfg);
3215         spin_unlock_irqrestore(&vector_lock, flags);
3216 }
3217
3218 /*
3219  * MSI message composition
3220  */
3221 #ifdef CONFIG_PCI_MSI
3222 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3223 {
3224         struct irq_cfg *cfg;
3225         int err;
3226         unsigned dest;
3227
3228         if (disable_apic)
3229                 return -ENXIO;
3230
3231         cfg = irq_cfg(irq);
3232         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3233         if (err)
3234                 return err;
3235
3236         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3237
3238         if (irq_remapped(irq)) {
3239                 struct irte irte;
3240                 int ir_index;
3241                 u16 sub_handle;
3242
3243                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3244                 BUG_ON(ir_index == -1);
3245
3246                 memset (&irte, 0, sizeof(irte));
3247
3248                 irte.present = 1;
3249                 irte.dst_mode = apic->irq_dest_mode;
3250                 irte.trigger_mode = 0; /* edge */
3251                 irte.dlvry_mode = apic->irq_delivery_mode;
3252                 irte.vector = cfg->vector;
3253                 irte.dest_id = IRTE_DEST(dest);
3254
3255                 modify_irte(irq, &irte);
3256
3257                 msg->address_hi = MSI_ADDR_BASE_HI;
3258                 msg->data = sub_handle;
3259                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3260                                   MSI_ADDR_IR_SHV |
3261                                   MSI_ADDR_IR_INDEX1(ir_index) |
3262                                   MSI_ADDR_IR_INDEX2(ir_index);
3263         } else {
3264                 if (x2apic_enabled())
3265                         msg->address_hi = MSI_ADDR_BASE_HI |
3266                                           MSI_ADDR_EXT_DEST_ID(dest);
3267                 else
3268                         msg->address_hi = MSI_ADDR_BASE_HI;
3269
3270                 msg->address_lo =
3271                         MSI_ADDR_BASE_LO |
3272                         ((apic->irq_dest_mode == 0) ?
3273                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3274                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3275                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3276                                 MSI_ADDR_REDIRECTION_CPU:
3277                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3278                         MSI_ADDR_DEST_ID(dest);
3279
3280                 msg->data =
3281                         MSI_DATA_TRIGGER_EDGE |
3282                         MSI_DATA_LEVEL_ASSERT |
3283                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3284                                 MSI_DATA_DELIVERY_FIXED:
3285                                 MSI_DATA_DELIVERY_LOWPRI) |
3286                         MSI_DATA_VECTOR(cfg->vector);
3287         }
3288         return err;
3289 }
3290
3291 #ifdef CONFIG_SMP
3292 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3293 {
3294         struct irq_desc *desc = irq_to_desc(irq);
3295         struct irq_cfg *cfg;
3296         struct msi_msg msg;
3297         unsigned int dest;
3298
3299         dest = set_desc_affinity(desc, mask);
3300         if (dest == BAD_APICID)
3301                 return;
3302
3303         cfg = desc->chip_data;
3304
3305         read_msi_msg_desc(desc, &msg);
3306
3307         msg.data &= ~MSI_DATA_VECTOR_MASK;
3308         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3309         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3310         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3311
3312         write_msi_msg_desc(desc, &msg);
3313 }
3314 #ifdef CONFIG_INTR_REMAP
3315 /*
3316  * Migrate the MSI irq to another cpumask. This migration is
3317  * done in the process context using interrupt-remapping hardware.
3318  */
3319 static void
3320 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3321 {
3322         struct irq_desc *desc = irq_to_desc(irq);
3323         struct irq_cfg *cfg = desc->chip_data;
3324         unsigned int dest;
3325         struct irte irte;
3326
3327         if (get_irte(irq, &irte))
3328                 return;
3329
3330         dest = set_desc_affinity(desc, mask);
3331         if (dest == BAD_APICID)
3332                 return;
3333
3334         irte.vector = cfg->vector;
3335         irte.dest_id = IRTE_DEST(dest);
3336
3337         /*
3338          * atomically update the IRTE with the new destination and vector.
3339          */
3340         modify_irte(irq, &irte);
3341
3342         /*
3343          * After this point, all the interrupts will start arriving
3344          * at the new destination. So, time to cleanup the previous
3345          * vector allocation.
3346          */
3347         if (cfg->move_in_progress)
3348                 send_cleanup_vector(cfg);
3349 }
3350
3351 #endif
3352 #endif /* CONFIG_SMP */
3353
3354 /*
3355  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3356  * which implement the MSI or MSI-X Capability Structure.
3357  */
3358 static struct irq_chip msi_chip = {
3359         .name           = "PCI-MSI",
3360         .unmask         = unmask_msi_irq,
3361         .mask           = mask_msi_irq,
3362         .ack            = ack_apic_edge,
3363 #ifdef CONFIG_SMP
3364         .set_affinity   = set_msi_irq_affinity,
3365 #endif
3366         .retrigger      = ioapic_retrigger_irq,
3367 };
3368
3369 #ifdef CONFIG_INTR_REMAP
3370 static struct irq_chip msi_ir_chip = {
3371         .name           = "IR-PCI-MSI",
3372         .unmask         = unmask_msi_irq,
3373         .mask           = mask_msi_irq,
3374         .ack            = ack_x2apic_edge,
3375 #ifdef CONFIG_SMP
3376         .set_affinity   = ir_set_msi_irq_affinity,
3377 #endif
3378         .retrigger      = ioapic_retrigger_irq,
3379 };
3380 #endif
3381
3382 /*
3383  * Map the PCI dev to the corresponding remapping hardware unit
3384  * and allocate 'nvec' consecutive interrupt-remapping table entries
3385  * in it.
3386  */
3387 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3388 {
3389         struct intel_iommu *iommu;
3390         int index;
3391
3392         iommu = map_dev_to_ir(dev);
3393         if (!iommu) {
3394                 printk(KERN_ERR
3395                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3396                 return -ENOENT;
3397         }
3398
3399         index = alloc_irte(iommu, irq, nvec);
3400         if (index < 0) {
3401                 printk(KERN_ERR
3402                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3403                        pci_name(dev));
3404                 return -ENOSPC;
3405         }
3406         return index;
3407 }
3408
3409 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3410 {
3411         int ret;
3412         struct msi_msg msg;
3413
3414         ret = msi_compose_msg(dev, irq, &msg);
3415         if (ret < 0)
3416                 return ret;
3417
3418         set_irq_msi(irq, msidesc);
3419         write_msi_msg(irq, &msg);
3420
3421         if (irq_remapped(irq)) {
3422                 struct irq_desc *desc = irq_to_desc(irq);
3423                 /*
3424                  * irq migration in process context
3425                  */
3426                 desc->status |= IRQ_MOVE_PCNTXT;
3427                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3428         } else
3429                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3430
3431         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3432
3433         return 0;
3434 }
3435
3436 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3437 {
3438         unsigned int irq;
3439         int ret, sub_handle;
3440         struct msi_desc *msidesc;
3441         unsigned int irq_want;
3442         struct intel_iommu *iommu = 0;
3443         int index = 0;
3444
3445         irq_want = nr_irqs_gsi;
3446         sub_handle = 0;
3447         list_for_each_entry(msidesc, &dev->msi_list, list) {
3448                 irq = create_irq_nr(irq_want);
3449                 if (irq == 0)
3450                         return -1;
3451                 irq_want = irq + 1;
3452                 if (!intr_remapping_enabled)
3453                         goto no_ir;
3454
3455                 if (!sub_handle) {
3456                         /*
3457                          * allocate the consecutive block of IRTE's
3458                          * for 'nvec'
3459                          */
3460                         index = msi_alloc_irte(dev, irq, nvec);
3461                         if (index < 0) {
3462                                 ret = index;
3463                                 goto error;
3464                         }
3465                 } else {
3466                         iommu = map_dev_to_ir(dev);
3467                         if (!iommu) {
3468                                 ret = -ENOENT;
3469                                 goto error;
3470                         }
3471                         /*
3472                          * setup the mapping between the irq and the IRTE
3473                          * base index, the sub_handle pointing to the
3474                          * appropriate interrupt remap table entry.
3475                          */
3476                         set_irte_irq(irq, iommu, index, sub_handle);
3477                 }
3478 no_ir:
3479                 ret = setup_msi_irq(dev, msidesc, irq);
3480                 if (ret < 0)
3481                         goto error;
3482                 sub_handle++;
3483         }
3484         return 0;
3485
3486 error:
3487         destroy_irq(irq);
3488         return ret;
3489 }
3490
3491 void arch_teardown_msi_irq(unsigned int irq)
3492 {
3493         destroy_irq(irq);
3494 }
3495
3496 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3497 #ifdef CONFIG_SMP
3498 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3499 {
3500         struct irq_desc *desc = irq_to_desc(irq);
3501         struct irq_cfg *cfg;
3502         struct msi_msg msg;
3503         unsigned int dest;
3504
3505         dest = set_desc_affinity(desc, mask);
3506         if (dest == BAD_APICID)
3507                 return;
3508
3509         cfg = desc->chip_data;
3510
3511         dmar_msi_read(irq, &msg);
3512
3513         msg.data &= ~MSI_DATA_VECTOR_MASK;
3514         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3515         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3516         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3517
3518         dmar_msi_write(irq, &msg);
3519 }
3520
3521 #endif /* CONFIG_SMP */
3522
3523 struct irq_chip dmar_msi_type = {
3524         .name = "DMAR_MSI",
3525         .unmask = dmar_msi_unmask,
3526         .mask = dmar_msi_mask,
3527         .ack = ack_apic_edge,
3528 #ifdef CONFIG_SMP
3529         .set_affinity = dmar_msi_set_affinity,
3530 #endif
3531         .retrigger = ioapic_retrigger_irq,
3532 };
3533
3534 int arch_setup_dmar_msi(unsigned int irq)
3535 {
3536         int ret;
3537         struct msi_msg msg;
3538
3539         ret = msi_compose_msg(NULL, irq, &msg);
3540         if (ret < 0)
3541                 return ret;
3542         dmar_msi_write(irq, &msg);
3543         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3544                 "edge");
3545         return 0;
3546 }
3547 #endif
3548
3549 #ifdef CONFIG_HPET_TIMER
3550
3551 #ifdef CONFIG_SMP
3552 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3553 {
3554         struct irq_desc *desc = irq_to_desc(irq);
3555         struct irq_cfg *cfg;
3556         struct msi_msg msg;
3557         unsigned int dest;
3558
3559         dest = set_desc_affinity(desc, mask);
3560         if (dest == BAD_APICID)
3561                 return;
3562
3563         cfg = desc->chip_data;
3564
3565         hpet_msi_read(irq, &msg);
3566
3567         msg.data &= ~MSI_DATA_VECTOR_MASK;
3568         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3569         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3570         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3571
3572         hpet_msi_write(irq, &msg);
3573 }
3574
3575 #endif /* CONFIG_SMP */
3576
3577 struct irq_chip hpet_msi_type = {
3578         .name = "HPET_MSI",
3579         .unmask = hpet_msi_unmask,
3580         .mask = hpet_msi_mask,
3581         .ack = ack_apic_edge,
3582 #ifdef CONFIG_SMP
3583         .set_affinity = hpet_msi_set_affinity,
3584 #endif
3585         .retrigger = ioapic_retrigger_irq,
3586 };
3587
3588 int arch_setup_hpet_msi(unsigned int irq)
3589 {
3590         int ret;
3591         struct msi_msg msg;
3592
3593         ret = msi_compose_msg(NULL, irq, &msg);
3594         if (ret < 0)
3595                 return ret;
3596
3597         hpet_msi_write(irq, &msg);
3598         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3599                 "edge");
3600
3601         return 0;
3602 }
3603 #endif
3604
3605 #endif /* CONFIG_PCI_MSI */
3606 /*
3607  * Hypertransport interrupt support
3608  */
3609 #ifdef CONFIG_HT_IRQ
3610
3611 #ifdef CONFIG_SMP
3612
3613 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3614 {
3615         struct ht_irq_msg msg;
3616         fetch_ht_irq_msg(irq, &msg);
3617
3618         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3619         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3620
3621         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3622         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3623
3624         write_ht_irq_msg(irq, &msg);
3625 }
3626
3627 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3628 {
3629         struct irq_desc *desc = irq_to_desc(irq);
3630         struct irq_cfg *cfg;
3631         unsigned int dest;
3632
3633         dest = set_desc_affinity(desc, mask);
3634         if (dest == BAD_APICID)
3635                 return;
3636
3637         cfg = desc->chip_data;
3638
3639         target_ht_irq(irq, dest, cfg->vector);
3640 }
3641
3642 #endif
3643
3644 static struct irq_chip ht_irq_chip = {
3645         .name           = "PCI-HT",
3646         .mask           = mask_ht_irq,
3647         .unmask         = unmask_ht_irq,
3648         .ack            = ack_apic_edge,
3649 #ifdef CONFIG_SMP
3650         .set_affinity   = set_ht_irq_affinity,
3651 #endif
3652         .retrigger      = ioapic_retrigger_irq,
3653 };
3654
3655 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3656 {
3657         struct irq_cfg *cfg;
3658         int err;
3659
3660         if (disable_apic)
3661                 return -ENXIO;
3662
3663         cfg = irq_cfg(irq);
3664         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3665         if (!err) {
3666                 struct ht_irq_msg msg;
3667                 unsigned dest;
3668
3669                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3670                                                     apic->target_cpus());
3671
3672                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3673
3674                 msg.address_lo =
3675                         HT_IRQ_LOW_BASE |
3676                         HT_IRQ_LOW_DEST_ID(dest) |
3677                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3678                         ((apic->irq_dest_mode == 0) ?
3679                                 HT_IRQ_LOW_DM_PHYSICAL :
3680                                 HT_IRQ_LOW_DM_LOGICAL) |
3681                         HT_IRQ_LOW_RQEOI_EDGE |
3682                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3683                                 HT_IRQ_LOW_MT_FIXED :
3684                                 HT_IRQ_LOW_MT_ARBITRATED) |
3685                         HT_IRQ_LOW_IRQ_MASKED;
3686
3687                 write_ht_irq_msg(irq, &msg);
3688
3689                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3690                                               handle_edge_irq, "edge");
3691
3692                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3693         }
3694         return err;
3695 }
3696 #endif /* CONFIG_HT_IRQ */
3697
3698 #ifdef CONFIG_X86_UV
3699 /*
3700  * Re-target the irq to the specified CPU and enable the specified MMR located
3701  * on the specified blade to allow the sending of MSIs to the specified CPU.
3702  */
3703 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3704                        unsigned long mmr_offset)
3705 {
3706         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3707         struct irq_cfg *cfg;
3708         int mmr_pnode;
3709         unsigned long mmr_value;
3710         struct uv_IO_APIC_route_entry *entry;
3711         unsigned long flags;
3712         int err;
3713
3714         cfg = irq_cfg(irq);
3715
3716         err = assign_irq_vector(irq, cfg, eligible_cpu);
3717         if (err != 0)
3718                 return err;
3719
3720         spin_lock_irqsave(&vector_lock, flags);
3721         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3722                                       irq_name);
3723         spin_unlock_irqrestore(&vector_lock, flags);
3724
3725         mmr_value = 0;
3726         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3727         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3728
3729         entry->vector = cfg->vector;
3730         entry->delivery_mode = apic->irq_delivery_mode;
3731         entry->dest_mode = apic->irq_dest_mode;
3732         entry->polarity = 0;
3733         entry->trigger = 0;
3734         entry->mask = 0;
3735         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3736
3737         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3738         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3739
3740         return irq;
3741 }
3742
3743 /*
3744  * Disable the specified MMR located on the specified blade so that MSIs are
3745  * longer allowed to be sent.
3746  */
3747 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3748 {
3749         unsigned long mmr_value;
3750         struct uv_IO_APIC_route_entry *entry;
3751         int mmr_pnode;
3752
3753         mmr_value = 0;
3754         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3755         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3756
3757         entry->mask = 1;
3758
3759         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3760         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3761 }
3762 #endif /* CONFIG_X86_64 */
3763
3764 int __init io_apic_get_redir_entries (int ioapic)
3765 {
3766         union IO_APIC_reg_01    reg_01;
3767         unsigned long flags;
3768
3769         spin_lock_irqsave(&ioapic_lock, flags);
3770         reg_01.raw = io_apic_read(ioapic, 1);
3771         spin_unlock_irqrestore(&ioapic_lock, flags);
3772
3773         return reg_01.bits.entries;
3774 }
3775
3776 void __init probe_nr_irqs_gsi(void)
3777 {
3778         int nr = 0;
3779
3780         nr = acpi_probe_gsi();
3781         if (nr > nr_irqs_gsi) {
3782                 nr_irqs_gsi = nr;
3783         } else {
3784                 /* for acpi=off or acpi is not compiled in */
3785                 int idx;
3786
3787                 nr = 0;
3788                 for (idx = 0; idx < nr_ioapics; idx++)
3789                         nr += io_apic_get_redir_entries(idx) + 1;
3790
3791                 if (nr > nr_irqs_gsi)
3792                         nr_irqs_gsi = nr;
3793         }
3794
3795         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3796 }
3797
3798 #ifdef CONFIG_SPARSE_IRQ
3799 int __init arch_probe_nr_irqs(void)
3800 {
3801         int nr;
3802
3803         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3804                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3805
3806         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3807 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3808         /*
3809          * for MSI and HT dyn irq
3810          */
3811         nr += nr_irqs_gsi * 16;
3812 #endif
3813         if (nr < nr_irqs)
3814                 nr_irqs = nr;
3815
3816         return 0;
3817 }
3818 #endif
3819
3820 /* --------------------------------------------------------------------------
3821                           ACPI-based IOAPIC Configuration
3822    -------------------------------------------------------------------------- */
3823
3824 #ifdef CONFIG_ACPI
3825
3826 #ifdef CONFIG_X86_32
3827 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3828 {
3829         union IO_APIC_reg_00 reg_00;
3830         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3831         physid_mask_t tmp;
3832         unsigned long flags;
3833         int i = 0;
3834
3835         /*
3836          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3837          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3838          * supports up to 16 on one shared APIC bus.
3839          *
3840          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3841          *      advantage of new APIC bus architecture.
3842          */
3843
3844         if (physids_empty(apic_id_map))
3845                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3846
3847         spin_lock_irqsave(&ioapic_lock, flags);
3848         reg_00.raw = io_apic_read(ioapic, 0);
3849         spin_unlock_irqrestore(&ioapic_lock, flags);
3850
3851         if (apic_id >= get_physical_broadcast()) {
3852                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3853                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3854                 apic_id = reg_00.bits.ID;
3855         }
3856
3857         /*
3858          * Every APIC in a system must have a unique ID or we get lots of nice
3859          * 'stuck on smp_invalidate_needed IPI wait' messages.
3860          */
3861         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3862
3863                 for (i = 0; i < get_physical_broadcast(); i++) {
3864                         if (!apic->check_apicid_used(apic_id_map, i))
3865                                 break;
3866                 }
3867
3868                 if (i == get_physical_broadcast())
3869                         panic("Max apic_id exceeded!\n");
3870
3871                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3872                         "trying %d\n", ioapic, apic_id, i);
3873
3874                 apic_id = i;
3875         }
3876
3877         tmp = apic->apicid_to_cpu_present(apic_id);
3878         physids_or(apic_id_map, apic_id_map, tmp);
3879
3880         if (reg_00.bits.ID != apic_id) {
3881                 reg_00.bits.ID = apic_id;
3882
3883                 spin_lock_irqsave(&ioapic_lock, flags);
3884                 io_apic_write(ioapic, 0, reg_00.raw);
3885                 reg_00.raw = io_apic_read(ioapic, 0);
3886                 spin_unlock_irqrestore(&ioapic_lock, flags);
3887
3888                 /* Sanity check */
3889                 if (reg_00.bits.ID != apic_id) {
3890                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3891                         return -1;
3892                 }
3893         }
3894
3895         apic_printk(APIC_VERBOSE, KERN_INFO
3896                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3897
3898         return apic_id;
3899 }
3900
3901 int __init io_apic_get_version(int ioapic)
3902 {
3903         union IO_APIC_reg_01    reg_01;
3904         unsigned long flags;
3905
3906         spin_lock_irqsave(&ioapic_lock, flags);
3907         reg_01.raw = io_apic_read(ioapic, 1);
3908         spin_unlock_irqrestore(&ioapic_lock, flags);
3909
3910         return reg_01.bits.version;
3911 }
3912 #endif
3913
3914 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3915 {
3916         struct irq_desc *desc;
3917         struct irq_cfg *cfg;
3918         int cpu = boot_cpu_id;
3919
3920         if (!IO_APIC_IRQ(irq)) {
3921                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3922                         ioapic);
3923                 return -EINVAL;
3924         }
3925
3926         desc = irq_to_desc_alloc_cpu(irq, cpu);
3927         if (!desc) {
3928                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3929                 return 0;
3930         }
3931
3932         /*
3933          * IRQs < 16 are already in the irq_2_pin[] map
3934          */
3935         if (irq >= NR_IRQS_LEGACY) {
3936                 cfg = desc->chip_data;
3937                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3938         }
3939
3940         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3941
3942         return 0;
3943 }
3944
3945
3946 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3947 {
3948         int i;
3949
3950         if (skip_ioapic_setup)
3951                 return -1;
3952
3953         for (i = 0; i < mp_irq_entries; i++)
3954                 if (mp_irqs[i].irqtype == mp_INT &&
3955                     mp_irqs[i].srcbusirq == bus_irq)
3956                         break;
3957         if (i >= mp_irq_entries)
3958                 return -1;
3959
3960         *trigger = irq_trigger(i);
3961         *polarity = irq_polarity(i);
3962         return 0;
3963 }
3964
3965 #endif /* CONFIG_ACPI */
3966
3967 /*
3968  * This function currently is only a helper for the i386 smp boot process where
3969  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3970  * so mask in all cases should simply be apic->target_cpus()
3971  */
3972 #ifdef CONFIG_SMP
3973 void __init setup_ioapic_dest(void)
3974 {
3975         int pin, ioapic, irq, irq_entry;
3976         struct irq_desc *desc;
3977         struct irq_cfg *cfg;
3978         const struct cpumask *mask;
3979
3980         if (skip_ioapic_setup == 1)
3981                 return;
3982
3983         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3984                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3985                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3986                         if (irq_entry == -1)
3987                                 continue;
3988                         irq = pin_2_irq(irq_entry, ioapic, pin);
3989
3990                         /* setup_IO_APIC_irqs could fail to get vector for some device
3991                          * when you have too many devices, because at that time only boot
3992                          * cpu is online.
3993                          */
3994                         desc = irq_to_desc(irq);
3995                         cfg = desc->chip_data;
3996                         if (!cfg->vector) {
3997                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
3998                                                   irq_trigger(irq_entry),
3999                                                   irq_polarity(irq_entry));
4000                                 continue;
4001
4002                         }
4003
4004                         /*
4005                          * Honour affinities which have been set in early boot
4006                          */
4007                         if (desc->status &
4008                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4009                                 mask = desc->affinity;
4010                         else
4011                                 mask = apic->target_cpus();
4012
4013                         if (intr_remapping_enabled)
4014                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4015                         else
4016                                 set_ioapic_affinity_irq_desc(desc, mask);
4017                 }
4018
4019         }
4020 }
4021 #endif
4022
4023 #define IOAPIC_RESOURCE_NAME_SIZE 11
4024
4025 static struct resource *ioapic_resources;
4026
4027 static struct resource * __init ioapic_setup_resources(void)
4028 {
4029         unsigned long n;
4030         struct resource *res;
4031         char *mem;
4032         int i;
4033
4034         if (nr_ioapics <= 0)
4035                 return NULL;
4036
4037         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4038         n *= nr_ioapics;
4039
4040         mem = alloc_bootmem(n);
4041         res = (void *)mem;
4042
4043         if (mem != NULL) {
4044                 mem += sizeof(struct resource) * nr_ioapics;
4045
4046                 for (i = 0; i < nr_ioapics; i++) {
4047                         res[i].name = mem;
4048                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4049                         sprintf(mem,  "IOAPIC %u", i);
4050                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4051                 }
4052         }
4053
4054         ioapic_resources = res;
4055
4056         return res;
4057 }
4058
4059 void __init ioapic_init_mappings(void)
4060 {
4061         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4062         struct resource *ioapic_res;
4063         int i;
4064
4065         ioapic_res = ioapic_setup_resources();
4066         for (i = 0; i < nr_ioapics; i++) {
4067                 if (smp_found_config) {
4068                         ioapic_phys = mp_ioapics[i].apicaddr;
4069 #ifdef CONFIG_X86_32
4070                         if (!ioapic_phys) {
4071                                 printk(KERN_ERR
4072                                        "WARNING: bogus zero IO-APIC "
4073                                        "address found in MPTABLE, "
4074                                        "disabling IO/APIC support!\n");
4075                                 smp_found_config = 0;
4076                                 skip_ioapic_setup = 1;
4077                                 goto fake_ioapic_page;
4078                         }
4079 #endif
4080                 } else {
4081 #ifdef CONFIG_X86_32
4082 fake_ioapic_page:
4083 #endif
4084                         ioapic_phys = (unsigned long)
4085                                 alloc_bootmem_pages(PAGE_SIZE);
4086                         ioapic_phys = __pa(ioapic_phys);
4087                 }
4088                 set_fixmap_nocache(idx, ioapic_phys);
4089                 apic_printk(APIC_VERBOSE,
4090                             "mapped IOAPIC to %08lx (%08lx)\n",
4091                             __fix_to_virt(idx), ioapic_phys);
4092                 idx++;
4093
4094                 if (ioapic_res != NULL) {
4095                         ioapic_res->start = ioapic_phys;
4096                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4097                         ioapic_res++;
4098                 }
4099         }
4100 }
4101
4102 static int __init ioapic_insert_resources(void)
4103 {
4104         int i;
4105         struct resource *r = ioapic_resources;
4106
4107         if (!r) {
4108                 printk(KERN_ERR
4109                        "IO APIC resources could be not be allocated.\n");
4110                 return -1;
4111         }
4112
4113         for (i = 0; i < nr_ioapics; i++) {
4114                 insert_resource(&iomem_resource, r);
4115                 r++;
4116         }
4117
4118         return 0;
4119 }
4120
4121 /* Insert the IO APIC resources after PCI initialization has occured to handle
4122  * IO APICS that are mapped in on a BAR in PCI space. */
4123 late_initcall(ioapic_insert_resources);