arch/x86/kernel/cpu/mcheck/mce_amd.c

   1 /*
   2  *  (c) 2005, 2006 Advanced Micro Devices, Inc.
   3  *  Your use of this code is subject to the terms and conditions of the
   4  *  GNU general public license version 2. See "COPYING" or
   5  *  http://www.gnu.org/licenses/gpl.html
   6  *
   7  *  Written by Jacob Shin - AMD, Inc.
   8  *
   9  *  Support : jacob.shin@amd.com
  10  *
  11  *  April 2006
  12  *     - added support for AMD Family 0x10 processors
  13  *
  14  *  All MC4_MISCi registers are shared between multi-cores
  15  */
  16 #include <linux/interrupt.h>
  17 #include <linux/notifier.h>
  18 #include <linux/kobject.h>
  19 #include <linux/percpu.h>
  20 #include <linux/errno.h>
  21 #include <linux/sched.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/slab.h>
  24 #include <linux/init.h>
  25 #include <linux/cpu.h>
  26 #include <linux/smp.h>
  27
  28 #include <asm/apic.h>
  29 #include <asm/idle.h>
  30 #include <asm/mce.h>
  31 #include <asm/msr.h>
  32
  33 #define NR_BANKS          6
  34 #define NR_BLOCKS         9
  35 #define THRESHOLD_MAX     0xFFF
  36 #define INT_TYPE_APIC     0x00020000
  37 #define MASK_VALID_HI     0x80000000
  38 #define MASK_CNTP_HI      0x40000000
  39 #define MASK_LOCKED_HI    0x20000000
  40 #define MASK_LVTOFF_HI    0x00F00000
  41 #define MASK_COUNT_EN_HI  0x00080000
  42 #define MASK_INT_TYPE_HI  0x00060000
  43 #define MASK_OVERFLOW_HI  0x00010000
  44 #define MASK_ERR_COUNT_HI 0x00000FFF
  45 #define MASK_BLKPTR_LO    0xFF000000
  46 #define MCG_XBLK_ADDR     0xC0000400
  47
  48 struct threshold_block {
  49         unsigned int            block;
  50         unsigned int            bank;
  51         unsigned int            cpu;
  52         u32                     address;
  53         u16                     interrupt_enable;
  54         bool                    interrupt_capable;
  55         u16                     threshold_limit;
  56         struct kobject          kobj;
  57         struct list_head        miscj;
  58 };
  59
  60 struct threshold_bank {
  61         struct kobject          *kobj;
  62         struct threshold_block  *blocks;
  63 };
  64 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
  65
  66 static unsigned char shared_bank[NR_BANKS] = {
  67         0, 0, 0, 0, 1
  68 };
  69
  70 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  71
  72 static void amd_threshold_interrupt(void);
  73
  74 /*
  75  * CPU Initialization
  76  */
  77
  78 struct thresh_restart {
  79         struct threshold_block  *b;
  80         int                     reset;
  81         int                     set_lvt_off;
  82         int                     lvt_off;
  83         u16                     old_limit;
  84 };
  85
  86 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
  87 {
  88         /*
  89          * bank 4 supports APIC LVT interrupts implicitly since forever.
  90          */
  91         if (bank == 4)
  92                 return true;
  93
  94         /*
  95          * IntP: interrupt present; if this bit is set, the thresholding
  96          * bank can generate APIC LVT interrupts
  97          */
  98         return msr_high_bits & BIT(28);
  99 }
 100
 101 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 102 {
 103         int msr = (hi & MASK_LVTOFF_HI) >> 20;
 104
 105         if (apic < 0) {
 106                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
 107                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
 108                        b->bank, b->block, b->address, hi, lo);
 109                 return 0;
 110         }
 111
 112         if (apic != msr) {
 113                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 114                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 115                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
 116                 return 0;
 117         }
 118
 119         return 1;
 120 };
 121
 122 /*
 123  * Called via smp_call_function_single(), must be called with correct
 124  * cpu affinity.
 125  */
 126 static void threshold_restart_bank(void *_tr)
 127 {
 128         struct thresh_restart *tr = _tr;
 129         u32 hi, lo;
 130
 131         rdmsr(tr->b->address, lo, hi);
 132
 133         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
 134                 tr->reset = 1;  /* limit cannot be lower than err count */
 135
 136         if (tr->reset) {                /* reset err count and overflow bit */
 137                 hi =
 138                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
 139                     (THRESHOLD_MAX - tr->b->threshold_limit);
 140         } else if (tr->old_limit) {     /* change limit w/o reset */
 141                 int new_count = (hi & THRESHOLD_MAX) +
 142                     (tr->old_limit - tr->b->threshold_limit);
 143
 144                 hi = (hi & ~MASK_ERR_COUNT_HI) |
 145                     (new_count & THRESHOLD_MAX);
 146         }
 147
 148         /* clear IntType */
 149         hi &= ~MASK_INT_TYPE_HI;
 150
 151         if (!tr->b->interrupt_capable)
 152                 goto done;
 153
 154         if (tr->set_lvt_off) {
 155                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
 156                         /* set new lvt offset */
 157                         hi &= ~MASK_LVTOFF_HI;
 158                         hi |= tr->lvt_off << 20;
 159                 }
 160         }
 161
 162         if (tr->b->interrupt_enable)
 163                 hi |= INT_TYPE_APIC;
 164
 165  done:
 166
 167         hi |= MASK_COUNT_EN_HI;
 168         wrmsr(tr->b->address, lo, hi);
 169 }
 170
 171 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 172 {
 173         struct thresh_restart tr = {
 174                 .b                      = b,
 175                 .set_lvt_off            = 1,
 176                 .lvt_off                = offset,
 177         };
 178
 179         b->threshold_limit              = THRESHOLD_MAX;
 180         threshold_restart_bank(&tr);
 181 };
 182
 183 static int setup_APIC_mce(int reserved, int new)
 184 {
 185         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
 186                                               APIC_EILVT_MSG_FIX, 0))
 187                 return new;
 188
 189         return reserved;
 190 }
 191
 192 /* cpu init entry point, called from mce.c with preempt off */
 193 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 194 {
 195         struct threshold_block b;
 196         unsigned int cpu = smp_processor_id();
 197         u32 low = 0, high = 0, address = 0;
 198         unsigned int bank, block;
 199         int offset = -1;
 200
 201         for (bank = 0; bank < NR_BANKS; ++bank) {
 202                 for (block = 0; block < NR_BLOCKS; ++block) {
 203                         if (block == 0)
 204                                 address = MSR_IA32_MC0_MISC + bank * 4;
 205                         else if (block == 1) {
 206                                 address = (low & MASK_BLKPTR_LO) >> 21;
 207                                 if (!address)
 208                                         break;
 209
 210                                 address += MCG_XBLK_ADDR;
 211                         } else
 212                                 ++address;
 213
 214                         if (rdmsr_safe(address, &low, &high))
 215                                 break;
 216
 217                         if (!(high & MASK_VALID_HI))
 218                                 continue;
 219
 220                         if (!(high & MASK_CNTP_HI)  ||
 221                              (high & MASK_LOCKED_HI))
 222                                 continue;
 223
 224                         if (!block)
 225                                 per_cpu(bank_map, cpu) |= (1 << bank);
 226
 227                         memset(&b, 0, sizeof(b));
 228                         b.cpu                   = cpu;
 229                         b.bank                  = bank;
 230                         b.block                 = block;
 231                         b.address               = address;
 232                         b.interrupt_capable     = lvt_interrupt_supported(bank, high);
 233
 234                         if (b.interrupt_capable) {
 235                                 int new = (high & MASK_LVTOFF_HI) >> 20;
 236                                 offset  = setup_APIC_mce(offset, new);
 237                         }
 238
 239                         mce_threshold_block_init(&b, offset);
 240                         mce_threshold_vector = amd_threshold_interrupt;
 241                 }
 242         }
 243 }
 244
 245 /*
 246  * APIC Interrupt Handler
 247  */
 248
 249 /*
 250  * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
 251  * the interrupt goes off when error_count reaches threshold_limit.
 252  * the handler will simply log mcelog w/ software defined bank number.
 253  */
 254 static void amd_threshold_interrupt(void)
 255 {
 256         u32 low = 0, high = 0, address = 0;
 257         unsigned int bank, block;
 258         struct mce m;
 259
 260         mce_setup(&m);
 261
 262         /* assume first bank caused it */
 263         for (bank = 0; bank < NR_BANKS; ++bank) {
 264                 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
 265                         continue;
 266                 for (block = 0; block < NR_BLOCKS; ++block) {
 267                         if (block == 0) {
 268                                 address = MSR_IA32_MC0_MISC + bank * 4;
 269                         } else if (block == 1) {
 270                                 address = (low & MASK_BLKPTR_LO) >> 21;
 271                                 if (!address)
 272                                         break;
 273                                 address += MCG_XBLK_ADDR;
 274                         } else {
 275                                 ++address;
 276                         }
 277
 278                         if (rdmsr_safe(address, &low, &high))
 279                                 break;
 280
 281                         if (!(high & MASK_VALID_HI)) {
 282                                 if (block)
 283                                         continue;
 284                                 else
 285                                         break;
 286                         }
 287
 288                         if (!(high & MASK_CNTP_HI)  ||
 289                              (high & MASK_LOCKED_HI))
 290                                 continue;
 291
 292                         /*
 293                          * Log the machine check that caused the threshold
 294                          * event.
 295                          */
 296                         machine_check_poll(MCP_TIMESTAMP,
 297                                         &__get_cpu_var(mce_poll_banks));
 298
 299                         if (high & MASK_OVERFLOW_HI) {
 300                                 rdmsrl(address, m.misc);
 301                                 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
 302                                        m.status);
 303                                 m.bank = K8_MCE_THRESHOLD_BASE
 304                                        + bank * NR_BLOCKS
 305                                        + block;
 306                                 mce_log(&m);
 307                                 return;
 308                         }
 309                 }
 310         }
 311 }
 312
 313 /*
 314  * Sysfs Interface
 315  */
 316
 317 struct threshold_attr {
 318         struct attribute attr;
 319         ssize_t (*show) (struct threshold_block *, char *);
 320         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
 321 };
 322
 323 #define SHOW_FIELDS(name)                                               \
 324 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
 325 {                                                                       \
 326         return sprintf(buf, "%lx\n", (unsigned long) b->name);          \
 327 }
 328 SHOW_FIELDS(interrupt_enable)
 329 SHOW_FIELDS(threshold_limit)
 330
 331 static ssize_t
 332 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
 333 {
 334         struct thresh_restart tr;
 335         unsigned long new;
 336
 337         if (!b->interrupt_capable)
 338                 return -EINVAL;
 339
 340         if (strict_strtoul(buf, 0, &new) < 0)
 341                 return -EINVAL;
 342
 343         b->interrupt_enable = !!new;
 344
 345         memset(&tr, 0, sizeof(tr));
 346         tr.b            = b;
 347
 348         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 349
 350         return size;
 351 }
 352
 353 static ssize_t
 354 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
 355 {
 356         struct thresh_restart tr;
 357         unsigned long new;
 358
 359         if (strict_strtoul(buf, 0, &new) < 0)
 360                 return -EINVAL;
 361
 362         if (new > THRESHOLD_MAX)
 363                 new = THRESHOLD_MAX;
 364         if (new < 1)
 365                 new = 1;
 366
 367         memset(&tr, 0, sizeof(tr));
 368         tr.old_limit = b->threshold_limit;
 369         b->threshold_limit = new;
 370         tr.b = b;
 371
 372         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 373
 374         return size;
 375 }
 376
 377 struct threshold_block_cross_cpu {
 378         struct threshold_block  *tb;
 379         long                    retval;
 380 };
 381
 382 static void local_error_count_handler(void *_tbcc)
 383 {
 384         struct threshold_block_cross_cpu *tbcc = _tbcc;
 385         struct threshold_block *b = tbcc->tb;
 386         u32 low, high;
 387
 388         rdmsr(b->address, low, high);
 389         tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
 390 }
 391
 392 static ssize_t show_error_count(struct threshold_block *b, char *buf)
 393 {
 394         struct threshold_block_cross_cpu tbcc = { .tb = b, };
 395
 396         smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
 397         return sprintf(buf, "%lx\n", tbcc.retval);
 398 }
 399
 400 static ssize_t store_error_count(struct threshold_block *b,
 401                                  const char *buf, size_t count)
 402 {
 403         struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
 404
 405         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 406         return 1;
 407 }
 408
 409 #define RW_ATTR(val)                                                    \
 410 static struct threshold_attr val = {                                    \
 411         .attr   = {.name = __stringify(val), .mode = 0644 },            \
 412         .show   = show_## val,                                          \
 413         .store  = store_## val,                                         \
 414 };
 415
 416 RW_ATTR(interrupt_enable);
 417 RW_ATTR(threshold_limit);
 418 RW_ATTR(error_count);
 419
 420 static struct attribute *default_attrs[] = {
 421         &threshold_limit.attr,
 422         &error_count.attr,
 423         NULL,   /* possibly interrupt_enable if supported, see below */
 424         NULL,
 425 };
 426
 427 #define to_block(k)     container_of(k, struct threshold_block, kobj)
 428 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
 429
 430 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
 431 {
 432         struct threshold_block *b = to_block(kobj);
 433         struct threshold_attr *a = to_attr(attr);
 434         ssize_t ret;
 435
 436         ret = a->show ? a->show(b, buf) : -EIO;
 437
 438         return ret;
 439 }
 440
 441 static ssize_t store(struct kobject *kobj, struct attribute *attr,
 442                      const char *buf, size_t count)
 443 {
 444         struct threshold_block *b = to_block(kobj);
 445         struct threshold_attr *a = to_attr(attr);
 446         ssize_t ret;
 447
 448         ret = a->store ? a->store(b, buf, count) : -EIO;
 449
 450         return ret;
 451 }
 452
 453 static const struct sysfs_ops threshold_ops = {
 454         .show                   = show,
 455         .store                  = store,
 456 };
 457
 458 static struct kobj_type threshold_ktype = {
 459         .sysfs_ops              = &threshold_ops,
 460         .default_attrs          = default_attrs,
 461 };
 462
 463 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
 464                                                unsigned int bank,
 465                                                unsigned int block,
 466                                                u32 address)
 467 {
 468         struct threshold_block *b = NULL;
 469         u32 low, high;
 470         int err;
 471
 472         if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
 473                 return 0;
 474
 475         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
 476                 return 0;
 477
 478         if (!(high & MASK_VALID_HI)) {
 479                 if (block)
 480                         goto recurse;
 481                 else
 482                         return 0;
 483         }
 484
 485         if (!(high & MASK_CNTP_HI)  ||
 486              (high & MASK_LOCKED_HI))
 487                 goto recurse;
 488
 489         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
 490         if (!b)
 491                 return -ENOMEM;
 492
 493         b->block                = block;
 494         b->bank                 = bank;
 495         b->cpu                  = cpu;
 496         b->address              = address;
 497         b->interrupt_enable     = 0;
 498         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
 499         b->threshold_limit      = THRESHOLD_MAX;
 500
 501         if (b->interrupt_capable)
 502                 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
 503         else
 504                 threshold_ktype.default_attrs[2] = NULL;
 505
 506         INIT_LIST_HEAD(&b->miscj);
 507
 508         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
 509                 list_add(&b->miscj,
 510                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
 511         } else {
 512                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
 513         }
 514
 515         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
 516                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
 517                                    "misc%i", block);
 518         if (err)
 519                 goto out_free;
 520 recurse:
 521         if (!block) {
 522                 address = (low & MASK_BLKPTR_LO) >> 21;
 523                 if (!address)
 524                         return 0;
 525                 address += MCG_XBLK_ADDR;
 526         } else {
 527                 ++address;
 528         }
 529
 530         err = allocate_threshold_blocks(cpu, bank, ++block, address);
 531         if (err)
 532                 goto out_free;
 533
 534         if (b)
 535                 kobject_uevent(&b->kobj, KOBJ_ADD);
 536
 537         return err;
 538
 539 out_free:
 540         if (b) {
 541                 kobject_put(&b->kobj);
 542                 list_del(&b->miscj);
 543                 kfree(b);
 544         }
 545         return err;
 546 }
 547
 548 static __cpuinit long
 549 local_allocate_threshold_blocks(int cpu, unsigned int bank)
 550 {
 551         return allocate_threshold_blocks(cpu, bank, 0,
 552                                          MSR_IA32_MC0_MISC + bank * 4);
 553 }
 554
 555 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 556 {
 557         struct device *dev = per_cpu(mce_device, cpu);
 558         struct threshold_bank *b = NULL;
 559         char name[32];
 560         int err = 0;
 561
 562         sprintf(name, "threshold_bank%i", bank);
 563
 564         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
 565         if (!b) {
 566                 err = -ENOMEM;
 567                 goto out;
 568         }
 569
 570         b->kobj = kobject_create_and_add(name, &dev->kobj);
 571         if (!b->kobj) {
 572                 err = -EINVAL;
 573                 goto out_free;
 574         }
 575
 576         per_cpu(threshold_banks, cpu)[bank] = b;
 577
 578         err = local_allocate_threshold_blocks(cpu, bank);
 579         if (!err)
 580                 goto out;
 581
 582 out_free:
 583         per_cpu(threshold_banks, cpu)[bank] = NULL;
 584         kfree(b);
 585 out:
 586         return err;
 587 }
 588
 589 /* create dir/files for all valid threshold banks */
 590 static __cpuinit int threshold_create_device(unsigned int cpu)
 591 {
 592         unsigned int bank;
 593         int err = 0;
 594
 595         for (bank = 0; bank < NR_BANKS; ++bank) {
 596                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 597                         continue;
 598                 err = threshold_create_bank(cpu, bank);
 599                 if (err)
 600                         return err;
 601         }
 602
 603         return err;
 604 }
 605
 606 static void deallocate_threshold_block(unsigned int cpu,
 607                                                  unsigned int bank)
 608 {
 609         struct threshold_block *pos = NULL;
 610         struct threshold_block *tmp = NULL;
 611         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
 612
 613         if (!head)
 614                 return;
 615
 616         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
 617                 kobject_put(&pos->kobj);
 618                 list_del(&pos->miscj);
 619                 kfree(pos);
 620         }
 621
 622         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
 623         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
 624 }
 625
 626 static void threshold_remove_bank(unsigned int cpu, int bank)
 627 {
 628         struct threshold_bank *b;
 629
 630         b = per_cpu(threshold_banks, cpu)[bank];
 631         if (!b)
 632                 return;
 633         if (!b->blocks)
 634                 goto free_out;
 635
 636         deallocate_threshold_block(cpu, bank);
 637
 638 free_out:
 639         kobject_del(b->kobj);
 640         kobject_put(b->kobj);
 641         kfree(b);
 642         per_cpu(threshold_banks, cpu)[bank] = NULL;
 643 }
 644
 645 static void threshold_remove_device(unsigned int cpu)
 646 {
 647         unsigned int bank;
 648
 649         for (bank = 0; bank < NR_BANKS; ++bank) {
 650                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 651                         continue;
 652                 threshold_remove_bank(cpu, bank);
 653         }
 654 }
 655
 656 /* get notified when a cpu comes on/off */
 657 static void __cpuinit
 658 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
 659 {
 660         switch (action) {
 661         case CPU_ONLINE:
 662         case CPU_ONLINE_FROZEN:
 663                 threshold_create_device(cpu);
 664                 break;
 665         case CPU_DEAD:
 666         case CPU_DEAD_FROZEN:
 667                 threshold_remove_device(cpu);
 668                 break;
 669         default:
 670                 break;
 671         }
 672 }
 673
 674 static __init int threshold_init_device(void)
 675 {
 676         unsigned lcpu = 0;
 677
 678         /* to hit CPUs online before the notifier is up */
 679         for_each_online_cpu(lcpu) {
 680                 int err = threshold_create_device(lcpu);
 681
 682                 if (err)
 683                         return err;
 684         }
 685         threshold_cpu_callback = amd_64_threshold_cpu_callback;
 686
 687         return 0;
 688 }
 689 device_initcall(threshold_init_device);