arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33 #include <asm/smp.h>
  34
  35 #if 0
  36 #undef wrmsrl
  37 #define wrmsrl(msr, val)                                        \
  38 do {                                                            \
  39         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  40                         (unsigned long)(val));                  \
  41         native_write_msr((msr), (u32)((u64)(val)),              \
  42                         (u32)((u64)(val) >> 32));               \
  43 } while (0)
  44 #endif
  45
  46 /*
  47  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  48  */
  49 static unsigned long
  50 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  51 {
  52         unsigned long offset, addr = (unsigned long)from;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 struct intel_percore;
  98
  99 #define MAX_LBR_ENTRIES         16
 100
 101 struct cpu_hw_events {
 102         /*
 103          * Generic x86 PMC bits
 104          */
 105         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 106         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 107         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 108         int                     enabled;
 109
 110         int                     n_events;
 111         int                     n_added;
 112         int                     n_txn;
 113         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 114         u64                     tags[X86_PMC_IDX_MAX];
 115         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 116
 117         unsigned int            group_flag;
 118
 119         /*
 120          * Intel DebugStore bits
 121          */
 122         struct debug_store      *ds;
 123         u64                     pebs_enabled;
 124
 125         /*
 126          * Intel LBR bits
 127          */
 128         int                             lbr_users;
 129         void                            *lbr_context;
 130         struct perf_branch_stack        lbr_stack;
 131         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 132
 133         /*
 134          * Intel percore register state.
 135          * Coordinate shared resources between HT threads.
 136          */
 137         int                             percore_used; /* Used by this CPU? */
 138         struct intel_percore            *per_core;
 139
 140         /*
 141          * AMD specific bits
 142          */
 143         struct amd_nb           *amd_nb;
 144 };
 145
 146 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 147         { .idxmsk64 = (n) },            \
 148         .code = (c),                    \
 149         .cmask = (m),                   \
 150         .weight = (w),                  \
 151 }
 152
 153 #define EVENT_CONSTRAINT(c, n, m)       \
 154         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 155
 156 /*
 157  * Constraint on the Event code.
 158  */
 159 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 160         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 161
 162 /*
 163  * Constraint on the Event code + UMask + fixed-mask
 164  *
 165  * filter mask to validate fixed counter events.
 166  * the following filters disqualify for fixed counters:
 167  *  - inv
 168  *  - edge
 169  *  - cnt-mask
 170  *  The other filters are supported by fixed counters.
 171  *  The any-thread option is supported starting with v3.
 172  */
 173 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 174         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 175
 176 /*
 177  * Constraint on the Event code + UMask
 178  */
 179 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
 180         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 181 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 182         INTEL_UEVENT_CONSTRAINT(c, n)
 183
 184 #define EVENT_CONSTRAINT_END            \
 185         EVENT_CONSTRAINT(0, 0, 0)
 186
 187 #define for_each_event_constraint(e, c) \
 188         for ((e) = (c); (e)->weight; (e)++)
 189
 190 /*
 191  * Extra registers for specific events.
 192  * Some events need large masks and require external MSRs.
 193  * Define a mapping to these extra registers.
 194  */
 195 struct extra_reg {
 196         unsigned int            event;
 197         unsigned int            msr;
 198         u64                     config_mask;
 199         u64                     valid_mask;
 200 };
 201
 202 #define EVENT_EXTRA_REG(e, ms, m, vm) { \
 203         .event = (e),           \
 204         .msr = (ms),            \
 205         .config_mask = (m),     \
 206         .valid_mask = (vm),     \
 207         }
 208 #define INTEL_EVENT_EXTRA_REG(event, msr, vm)   \
 209         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
 210 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0)
 211
 212 union perf_capabilities {
 213         struct {
 214                 u64     lbr_format    : 6;
 215                 u64     pebs_trap     : 1;
 216                 u64     pebs_arch_reg : 1;
 217                 u64     pebs_format   : 4;
 218                 u64     smm_freeze    : 1;
 219         };
 220         u64     capabilities;
 221 };
 222
 223 /*
 224  * struct x86_pmu - generic x86 pmu
 225  */
 226 struct x86_pmu {
 227         /*
 228          * Generic x86 PMC bits
 229          */
 230         const char      *name;
 231         int             version;
 232         int             (*handle_irq)(struct pt_regs *);
 233         void            (*disable_all)(void);
 234         void            (*enable_all)(int added);
 235         void            (*enable)(struct perf_event *);
 236         void            (*disable)(struct perf_event *);
 237         int             (*hw_config)(struct perf_event *event);
 238         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 239         unsigned        eventsel;
 240         unsigned        perfctr;
 241         u64             (*event_map)(int);
 242         int             max_events;
 243         int             num_counters;
 244         int             num_counters_fixed;
 245         int             cntval_bits;
 246         u64             cntval_mask;
 247         int             apic;
 248         u64             max_period;
 249         struct event_constraint *
 250                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 251                                                  struct perf_event *event);
 252
 253         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 254                                                  struct perf_event *event);
 255         struct event_constraint *event_constraints;
 256         struct event_constraint *percore_constraints;
 257         void            (*quirks)(void);
 258         int             perfctr_second_write;
 259
 260         int             (*cpu_prepare)(int cpu);
 261         void            (*cpu_starting)(int cpu);
 262         void            (*cpu_dying)(int cpu);
 263         void            (*cpu_dead)(int cpu);
 264
 265         /*
 266          * Intel Arch Perfmon v2+
 267          */
 268         u64                     intel_ctrl;
 269         union perf_capabilities intel_cap;
 270
 271         /*
 272          * Intel DebugStore bits
 273          */
 274         int             bts, pebs;
 275         int             bts_active, pebs_active;
 276         int             pebs_record_size;
 277         void            (*drain_pebs)(struct pt_regs *regs);
 278         struct event_constraint *pebs_constraints;
 279
 280         /*
 281          * Intel LBR
 282          */
 283         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 284         int             lbr_nr;                    /* hardware stack size */
 285
 286         /*
 287          * Extra registers for events
 288          */
 289         struct extra_reg *extra_regs;
 290 };
 291
 292 static struct x86_pmu x86_pmu __read_mostly;
 293
 294 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 295         .enabled = 1,
 296 };
 297
 298 static int x86_perf_event_set_period(struct perf_event *event);
 299
 300 /*
 301  * Generalized hw caching related hw_event table, filled
 302  * in on a per model basis. A value of 0 means
 303  * 'not supported', -1 means 'hw_event makes no sense on
 304  * this CPU', any other value means the raw hw_event
 305  * ID.
 306  */
 307
 308 #define C(x) PERF_COUNT_HW_CACHE_##x
 309
 310 static u64 __read_mostly hw_cache_event_ids
 311                                 [PERF_COUNT_HW_CACHE_MAX]
 312                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 313                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 314 static u64 __read_mostly hw_cache_extra_regs
 315                                 [PERF_COUNT_HW_CACHE_MAX]
 316                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 317                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 318
 319 /*
 320  * Propagate event elapsed time into the generic event.
 321  * Can only be executed on the CPU where the event is active.
 322  * Returns the delta events processed.
 323  */
 324 static u64
 325 x86_perf_event_update(struct perf_event *event)
 326 {
 327         struct hw_perf_event *hwc = &event->hw;
 328         int shift = 64 - x86_pmu.cntval_bits;
 329         u64 prev_raw_count, new_raw_count;
 330         int idx = hwc->idx;
 331         s64 delta;
 332
 333         if (idx == X86_PMC_IDX_FIXED_BTS)
 334                 return 0;
 335
 336         /*
 337          * Careful: an NMI might modify the previous event value.
 338          *
 339          * Our tactic to handle this is to first atomically read and
 340          * exchange a new raw count - then add that new-prev delta
 341          * count to the generic event atomically:
 342          */
 343 again:
 344         prev_raw_count = local64_read(&hwc->prev_count);
 345         rdmsrl(hwc->event_base, new_raw_count);
 346
 347         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 348                                         new_raw_count) != prev_raw_count)
 349                 goto again;
 350
 351         /*
 352          * Now we have the new raw value and have updated the prev
 353          * timestamp already. We can now calculate the elapsed delta
 354          * (event-)time and add that to the generic event.
 355          *
 356          * Careful, not all hw sign-extends above the physical width
 357          * of the count.
 358          */
 359         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 360         delta >>= shift;
 361
 362         local64_add(delta, &event->count);
 363         local64_sub(delta, &hwc->period_left);
 364
 365         return new_raw_count;
 366 }
 367
 368 /* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */
 369 static inline int x86_pmu_addr_offset(int index)
 370 {
 371         if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
 372                 return index << 1;
 373         return index;
 374 }
 375
 376 static inline unsigned int x86_pmu_config_addr(int index)
 377 {
 378         return x86_pmu.eventsel + x86_pmu_addr_offset(index);
 379 }
 380
 381 static inline unsigned int x86_pmu_event_addr(int index)
 382 {
 383         return x86_pmu.perfctr + x86_pmu_addr_offset(index);
 384 }
 385
 386 /*
 387  * Find and validate any extra registers to set up.
 388  */
 389 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 390 {
 391         struct extra_reg *er;
 392
 393         event->hw.extra_reg = 0;
 394         event->hw.extra_config = 0;
 395
 396         if (!x86_pmu.extra_regs)
 397                 return 0;
 398
 399         for (er = x86_pmu.extra_regs; er->msr; er++) {
 400                 if (er->event != (config & er->config_mask))
 401                         continue;
 402                 if (event->attr.config1 & ~er->valid_mask)
 403                         return -EINVAL;
 404                 event->hw.extra_reg = er->msr;
 405                 event->hw.extra_config = event->attr.config1;
 406                 break;
 407         }
 408         return 0;
 409 }
 410
 411 static atomic_t active_events;
 412 static DEFINE_MUTEX(pmc_reserve_mutex);
 413
 414 #ifdef CONFIG_X86_LOCAL_APIC
 415
 416 static bool reserve_pmc_hardware(void)
 417 {
 418         int i;
 419
 420         for (i = 0; i < x86_pmu.num_counters; i++) {
 421                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 422                         goto perfctr_fail;
 423         }
 424
 425         for (i = 0; i < x86_pmu.num_counters; i++) {
 426                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 427                         goto eventsel_fail;
 428         }
 429
 430         return true;
 431
 432 eventsel_fail:
 433         for (i--; i >= 0; i--)
 434                 release_evntsel_nmi(x86_pmu_config_addr(i));
 435
 436         i = x86_pmu.num_counters;
 437
 438 perfctr_fail:
 439         for (i--; i >= 0; i--)
 440                 release_perfctr_nmi(x86_pmu_event_addr(i));
 441
 442         return false;
 443 }
 444
 445 static void release_pmc_hardware(void)
 446 {
 447         int i;
 448
 449         for (i = 0; i < x86_pmu.num_counters; i++) {
 450                 release_perfctr_nmi(x86_pmu_event_addr(i));
 451                 release_evntsel_nmi(x86_pmu_config_addr(i));
 452         }
 453 }
 454
 455 #else
 456
 457 static bool reserve_pmc_hardware(void) { return true; }
 458 static void release_pmc_hardware(void) {}
 459
 460 #endif
 461
 462 static bool check_hw_exists(void)
 463 {
 464         u64 val, val_new = 0;
 465         int i, reg, ret = 0;
 466
 467         /*
 468          * Check to see if the BIOS enabled any of the counters, if so
 469          * complain and bail.
 470          */
 471         for (i = 0; i < x86_pmu.num_counters; i++) {
 472                 reg = x86_pmu_config_addr(i);
 473                 ret = rdmsrl_safe(reg, &val);
 474                 if (ret)
 475                         goto msr_fail;
 476                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 477                         goto bios_fail;
 478         }
 479
 480         if (x86_pmu.num_counters_fixed) {
 481                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 482                 ret = rdmsrl_safe(reg, &val);
 483                 if (ret)
 484                         goto msr_fail;
 485                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 486                         if (val & (0x03 << i*4))
 487                                 goto bios_fail;
 488                 }
 489         }
 490
 491         /*
 492          * Now write a value and read it back to see if it matches,
 493          * this is needed to detect certain hardware emulators (qemu/kvm)
 494          * that don't trap on the MSR access and always return 0s.
 495          */
 496         val = 0xabcdUL;
 497         ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
 498         ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
 499         if (ret || val != val_new)
 500                 goto msr_fail;
 501
 502         return true;
 503
 504 bios_fail:
 505         printk(KERN_CONT "Broken BIOS detected, using software events only.\n");
 506         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 507         return false;
 508
 509 msr_fail:
 510         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 511         return false;
 512 }
 513
 514 static void reserve_ds_buffers(void);
 515 static void release_ds_buffers(void);
 516
 517 static void hw_perf_event_destroy(struct perf_event *event)
 518 {
 519         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 520                 release_pmc_hardware();
 521                 release_ds_buffers();
 522                 mutex_unlock(&pmc_reserve_mutex);
 523         }
 524 }
 525
 526 static inline int x86_pmu_initialized(void)
 527 {
 528         return x86_pmu.handle_irq != NULL;
 529 }
 530
 531 static inline int
 532 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 533 {
 534         struct perf_event_attr *attr = &event->attr;
 535         unsigned int cache_type, cache_op, cache_result;
 536         u64 config, val;
 537
 538         config = attr->config;
 539
 540         cache_type = (config >>  0) & 0xff;
 541         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 542                 return -EINVAL;
 543
 544         cache_op = (config >>  8) & 0xff;
 545         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 546                 return -EINVAL;
 547
 548         cache_result = (config >> 16) & 0xff;
 549         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 550                 return -EINVAL;
 551
 552         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 553
 554         if (val == 0)
 555                 return -ENOENT;
 556
 557         if (val == -1)
 558                 return -EINVAL;
 559
 560         hwc->config |= val;
 561         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 562         return x86_pmu_extra_regs(val, event);
 563 }
 564
 565 static int x86_setup_perfctr(struct perf_event *event)
 566 {
 567         struct perf_event_attr *attr = &event->attr;
 568         struct hw_perf_event *hwc = &event->hw;
 569         u64 config;
 570
 571         if (!is_sampling_event(event)) {
 572                 hwc->sample_period = x86_pmu.max_period;
 573                 hwc->last_period = hwc->sample_period;
 574                 local64_set(&hwc->period_left, hwc->sample_period);
 575         } else {
 576                 /*
 577                  * If we have a PMU initialized but no APIC
 578                  * interrupts, we cannot sample hardware
 579                  * events (user-space has to fall back and
 580                  * sample via a hrtimer based software event):
 581                  */
 582                 if (!x86_pmu.apic)
 583                         return -EOPNOTSUPP;
 584         }
 585
 586         if (attr->type == PERF_TYPE_RAW)
 587                 return x86_pmu_extra_regs(event->attr.config, event);
 588
 589         if (attr->type == PERF_TYPE_HW_CACHE)
 590                 return set_ext_hw_attr(hwc, event);
 591
 592         if (attr->config >= x86_pmu.max_events)
 593                 return -EINVAL;
 594
 595         /*
 596          * The generic map:
 597          */
 598         config = x86_pmu.event_map(attr->config);
 599
 600         if (config == 0)
 601                 return -ENOENT;
 602
 603         if (config == -1LL)
 604                 return -EINVAL;
 605
 606         /*
 607          * Branch tracing:
 608          */
 609         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 610             (hwc->sample_period == 1)) {
 611                 /* BTS is not supported by this architecture. */
 612                 if (!x86_pmu.bts_active)
 613                         return -EOPNOTSUPP;
 614
 615                 /* BTS is currently only allowed for user-mode. */
 616                 if (!attr->exclude_kernel)
 617                         return -EOPNOTSUPP;
 618         }
 619
 620         hwc->config |= config;
 621
 622         return 0;
 623 }
 624
 625 static int x86_pmu_hw_config(struct perf_event *event)
 626 {
 627         if (event->attr.precise_ip) {
 628                 int precise = 0;
 629
 630                 /* Support for constant skid */
 631                 if (x86_pmu.pebs_active) {
 632                         precise++;
 633
 634                         /* Support for IP fixup */
 635                         if (x86_pmu.lbr_nr)
 636                                 precise++;
 637                 }
 638
 639                 if (event->attr.precise_ip > precise)
 640                         return -EOPNOTSUPP;
 641         }
 642
 643         /*
 644          * Generate PMC IRQs:
 645          * (keep 'enabled' bit clear for now)
 646          */
 647         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 648
 649         /*
 650          * Count user and OS events unless requested not to
 651          */
 652         if (!event->attr.exclude_user)
 653                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 654         if (!event->attr.exclude_kernel)
 655                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 656
 657         if (event->attr.type == PERF_TYPE_RAW)
 658                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 659
 660         return x86_setup_perfctr(event);
 661 }
 662
 663 /*
 664  * Setup the hardware configuration for a given attr_type
 665  */
 666 static int __x86_pmu_event_init(struct perf_event *event)
 667 {
 668         int err;
 669
 670         if (!x86_pmu_initialized())
 671                 return -ENODEV;
 672
 673         err = 0;
 674         if (!atomic_inc_not_zero(&active_events)) {
 675                 mutex_lock(&pmc_reserve_mutex);
 676                 if (atomic_read(&active_events) == 0) {
 677                         if (!reserve_pmc_hardware())
 678                                 err = -EBUSY;
 679                         else
 680                                 reserve_ds_buffers();
 681                 }
 682                 if (!err)
 683                         atomic_inc(&active_events);
 684                 mutex_unlock(&pmc_reserve_mutex);
 685         }
 686         if (err)
 687                 return err;
 688
 689         event->destroy = hw_perf_event_destroy;
 690
 691         event->hw.idx = -1;
 692         event->hw.last_cpu = -1;
 693         event->hw.last_tag = ~0ULL;
 694
 695         return x86_pmu.hw_config(event);
 696 }
 697
 698 static void x86_pmu_disable_all(void)
 699 {
 700         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 701         int idx;
 702
 703         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 704                 u64 val;
 705
 706                 if (!test_bit(idx, cpuc->active_mask))
 707                         continue;
 708                 rdmsrl(x86_pmu_config_addr(idx), val);
 709                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 710                         continue;
 711                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 712                 wrmsrl(x86_pmu_config_addr(idx), val);
 713         }
 714 }
 715
 716 static void x86_pmu_disable(struct pmu *pmu)
 717 {
 718         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 719
 720         if (!x86_pmu_initialized())
 721                 return;
 722
 723         if (!cpuc->enabled)
 724                 return;
 725
 726         cpuc->n_added = 0;
 727         cpuc->enabled = 0;
 728         barrier();
 729
 730         x86_pmu.disable_all();
 731 }
 732
 733 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 734                                           u64 enable_mask)
 735 {
 736         if (hwc->extra_reg)
 737                 wrmsrl(hwc->extra_reg, hwc->extra_config);
 738         wrmsrl(hwc->config_base, hwc->config | enable_mask);
 739 }
 740
 741 static void x86_pmu_enable_all(int added)
 742 {
 743         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 744         int idx;
 745
 746         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 747                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 748
 749                 if (!test_bit(idx, cpuc->active_mask))
 750                         continue;
 751
 752                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 753         }
 754 }
 755
 756 static struct pmu pmu;
 757
 758 static inline int is_x86_event(struct perf_event *event)
 759 {
 760         return event->pmu == &pmu;
 761 }
 762
 763 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 764 {
 765         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 766         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 767         int i, j, w, wmax, num = 0;
 768         struct hw_perf_event *hwc;
 769
 770         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 771
 772         for (i = 0; i < n; i++) {
 773                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 774                 constraints[i] = c;
 775         }
 776
 777         /*
 778          * fastpath, try to reuse previous register
 779          */
 780         for (i = 0; i < n; i++) {
 781                 hwc = &cpuc->event_list[i]->hw;
 782                 c = constraints[i];
 783
 784                 /* never assigned */
 785                 if (hwc->idx == -1)
 786                         break;
 787
 788                 /* constraint still honored */
 789                 if (!test_bit(hwc->idx, c->idxmsk))
 790                         break;
 791
 792                 /* not already used */
 793                 if (test_bit(hwc->idx, used_mask))
 794                         break;
 795
 796                 __set_bit(hwc->idx, used_mask);
 797                 if (assign)
 798                         assign[i] = hwc->idx;
 799         }
 800         if (i == n)
 801                 goto done;
 802
 803         /*
 804          * begin slow path
 805          */
 806
 807         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 808
 809         /*
 810          * weight = number of possible counters
 811          *
 812          * 1    = most constrained, only works on one counter
 813          * wmax = least constrained, works on any counter
 814          *
 815          * assign events to counters starting with most
 816          * constrained events.
 817          */
 818         wmax = x86_pmu.num_counters;
 819
 820         /*
 821          * when fixed event counters are present,
 822          * wmax is incremented by 1 to account
 823          * for one more choice
 824          */
 825         if (x86_pmu.num_counters_fixed)
 826                 wmax++;
 827
 828         for (w = 1, num = n; num && w <= wmax; w++) {
 829                 /* for each event */
 830                 for (i = 0; num && i < n; i++) {
 831                         c = constraints[i];
 832                         hwc = &cpuc->event_list[i]->hw;
 833
 834                         if (c->weight != w)
 835                                 continue;
 836
 837                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 838                                 if (!test_bit(j, used_mask))
 839                                         break;
 840                         }
 841
 842                         if (j == X86_PMC_IDX_MAX)
 843                                 break;
 844
 845                         __set_bit(j, used_mask);
 846
 847                         if (assign)
 848                                 assign[i] = j;
 849                         num--;
 850                 }
 851         }
 852 done:
 853         /*
 854          * scheduling failed or is just a simulation,
 855          * free resources if necessary
 856          */
 857         if (!assign || num) {
 858                 for (i = 0; i < n; i++) {
 859                         if (x86_pmu.put_event_constraints)
 860                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 861                 }
 862         }
 863         return num ? -ENOSPC : 0;
 864 }
 865
 866 /*
 867  * dogrp: true if must collect siblings events (group)
 868  * returns total number of events and error code
 869  */
 870 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 871 {
 872         struct perf_event *event;
 873         int n, max_count;
 874
 875         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 876
 877         /* current number of events already accepted */
 878         n = cpuc->n_events;
 879
 880         if (is_x86_event(leader)) {
 881                 if (n >= max_count)
 882                         return -ENOSPC;
 883                 cpuc->event_list[n] = leader;
 884                 n++;
 885         }
 886         if (!dogrp)
 887                 return n;
 888
 889         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 890                 if (!is_x86_event(event) ||
 891                     event->state <= PERF_EVENT_STATE_OFF)
 892                         continue;
 893
 894                 if (n >= max_count)
 895                         return -ENOSPC;
 896
 897                 cpuc->event_list[n] = event;
 898                 n++;
 899         }
 900         return n;
 901 }
 902
 903 static inline void x86_assign_hw_event(struct perf_event *event,
 904                                 struct cpu_hw_events *cpuc, int i)
 905 {
 906         struct hw_perf_event *hwc = &event->hw;
 907
 908         hwc->idx = cpuc->assign[i];
 909         hwc->last_cpu = smp_processor_id();
 910         hwc->last_tag = ++cpuc->tags[i];
 911
 912         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 913                 hwc->config_base = 0;
 914                 hwc->event_base = 0;
 915         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 916                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 917                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0;
 918         } else {
 919                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 920                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 921         }
 922 }
 923
 924 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 925                                         struct cpu_hw_events *cpuc,
 926                                         int i)
 927 {
 928         return hwc->idx == cpuc->assign[i] &&
 929                 hwc->last_cpu == smp_processor_id() &&
 930                 hwc->last_tag == cpuc->tags[i];
 931 }
 932
 933 static void x86_pmu_start(struct perf_event *event, int flags);
 934 static void x86_pmu_stop(struct perf_event *event, int flags);
 935
 936 static void x86_pmu_enable(struct pmu *pmu)
 937 {
 938         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 939         struct perf_event *event;
 940         struct hw_perf_event *hwc;
 941         int i, added = cpuc->n_added;
 942
 943         if (!x86_pmu_initialized())
 944                 return;
 945
 946         if (cpuc->enabled)
 947                 return;
 948
 949         if (cpuc->n_added) {
 950                 int n_running = cpuc->n_events - cpuc->n_added;
 951                 /*
 952                  * apply assignment obtained either from
 953                  * hw_perf_group_sched_in() or x86_pmu_enable()
 954                  *
 955                  * step1: save events moving to new counters
 956                  * step2: reprogram moved events into new counters
 957                  */
 958                 for (i = 0; i < n_running; i++) {
 959                         event = cpuc->event_list[i];
 960                         hwc = &event->hw;
 961
 962                         /*
 963                          * we can avoid reprogramming counter if:
 964                          * - assigned same counter as last time
 965                          * - running on same CPU as last time
 966                          * - no other event has used the counter since
 967                          */
 968                         if (hwc->idx == -1 ||
 969                             match_prev_assignment(hwc, cpuc, i))
 970                                 continue;
 971
 972                         /*
 973                          * Ensure we don't accidentally enable a stopped
 974                          * counter simply because we rescheduled.
 975                          */
 976                         if (hwc->state & PERF_HES_STOPPED)
 977                                 hwc->state |= PERF_HES_ARCH;
 978
 979                         x86_pmu_stop(event, PERF_EF_UPDATE);
 980                 }
 981
 982                 for (i = 0; i < cpuc->n_events; i++) {
 983                         event = cpuc->event_list[i];
 984                         hwc = &event->hw;
 985
 986                         if (!match_prev_assignment(hwc, cpuc, i))
 987                                 x86_assign_hw_event(event, cpuc, i);
 988                         else if (i < n_running)
 989                                 continue;
 990
 991                         if (hwc->state & PERF_HES_ARCH)
 992                                 continue;
 993
 994                         x86_pmu_start(event, PERF_EF_RELOAD);
 995                 }
 996                 cpuc->n_added = 0;
 997                 perf_events_lapic_init();
 998         }
 999
1000         cpuc->enabled = 1;
1001         barrier();
1002
1003         x86_pmu.enable_all(added);
1004 }
1005
1006 static inline void x86_pmu_disable_event(struct perf_event *event)
1007 {
1008         struct hw_perf_event *hwc = &event->hw;
1009
1010         wrmsrl(hwc->config_base, hwc->config);
1011 }
1012
1013 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1014
1015 /*
1016  * Set the next IRQ period, based on the hwc->period_left value.
1017  * To be called with the event disabled in hw:
1018  */
1019 static int
1020 x86_perf_event_set_period(struct perf_event *event)
1021 {
1022         struct hw_perf_event *hwc = &event->hw;
1023         s64 left = local64_read(&hwc->period_left);
1024         s64 period = hwc->sample_period;
1025         int ret = 0, idx = hwc->idx;
1026
1027         if (idx == X86_PMC_IDX_FIXED_BTS)
1028                 return 0;
1029
1030         /*
1031          * If we are way outside a reasonable range then just skip forward:
1032          */
1033         if (unlikely(left <= -period)) {
1034                 left = period;
1035                 local64_set(&hwc->period_left, left);
1036                 hwc->last_period = period;
1037                 ret = 1;
1038         }
1039
1040         if (unlikely(left <= 0)) {
1041                 left += period;
1042                 local64_set(&hwc->period_left, left);
1043                 hwc->last_period = period;
1044                 ret = 1;
1045         }
1046         /*
1047          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1048          */
1049         if (unlikely(left < 2))
1050                 left = 2;
1051
1052         if (left > x86_pmu.max_period)
1053                 left = x86_pmu.max_period;
1054
1055         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1056
1057         /*
1058          * The hw event starts counting from this event offset,
1059          * mark it to be able to extra future deltas:
1060          */
1061         local64_set(&hwc->prev_count, (u64)-left);
1062
1063         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1064
1065         /*
1066          * Due to erratum on certan cpu we need
1067          * a second write to be sure the register
1068          * is updated properly
1069          */
1070         if (x86_pmu.perfctr_second_write) {
1071                 wrmsrl(hwc->event_base,
1072                         (u64)(-left) & x86_pmu.cntval_mask);
1073         }
1074
1075         perf_event_update_userpage(event);
1076
1077         return ret;
1078 }
1079
1080 static void x86_pmu_enable_event(struct perf_event *event)
1081 {
1082         if (__this_cpu_read(cpu_hw_events.enabled))
1083                 __x86_pmu_enable_event(&event->hw,
1084                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1085 }
1086
1087 /*
1088  * Add a single event to the PMU.
1089  *
1090  * The event is added to the group of enabled events
1091  * but only if it can be scehduled with existing events.
1092  */
1093 static int x86_pmu_add(struct perf_event *event, int flags)
1094 {
1095         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1096         struct hw_perf_event *hwc;
1097         int assign[X86_PMC_IDX_MAX];
1098         int n, n0, ret;
1099
1100         hwc = &event->hw;
1101
1102         perf_pmu_disable(event->pmu);
1103         n0 = cpuc->n_events;
1104         ret = n = collect_events(cpuc, event, false);
1105         if (ret < 0)
1106                 goto out;
1107
1108         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1109         if (!(flags & PERF_EF_START))
1110                 hwc->state |= PERF_HES_ARCH;
1111
1112         /*
1113          * If group events scheduling transaction was started,
1114          * skip the schedulability test here, it will be peformed
1115          * at commit time (->commit_txn) as a whole
1116          */
1117         if (cpuc->group_flag & PERF_EVENT_TXN)
1118                 goto done_collect;
1119
1120         ret = x86_pmu.schedule_events(cpuc, n, assign);
1121         if (ret)
1122                 goto out;
1123         /*
1124          * copy new assignment, now we know it is possible
1125          * will be used by hw_perf_enable()
1126          */
1127         memcpy(cpuc->assign, assign, n*sizeof(int));
1128
1129 done_collect:
1130         cpuc->n_events = n;
1131         cpuc->n_added += n - n0;
1132         cpuc->n_txn += n - n0;
1133
1134         ret = 0;
1135 out:
1136         perf_pmu_enable(event->pmu);
1137         return ret;
1138 }
1139
1140 static void x86_pmu_start(struct perf_event *event, int flags)
1141 {
1142         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1143         int idx = event->hw.idx;
1144
1145         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1146                 return;
1147
1148         if (WARN_ON_ONCE(idx == -1))
1149                 return;
1150
1151         if (flags & PERF_EF_RELOAD) {
1152                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1153                 x86_perf_event_set_period(event);
1154         }
1155
1156         event->hw.state = 0;
1157
1158         cpuc->events[idx] = event;
1159         __set_bit(idx, cpuc->active_mask);
1160         __set_bit(idx, cpuc->running);
1161         x86_pmu.enable(event);
1162         perf_event_update_userpage(event);
1163 }
1164
1165 void perf_event_print_debug(void)
1166 {
1167         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1168         u64 pebs;
1169         struct cpu_hw_events *cpuc;
1170         unsigned long flags;
1171         int cpu, idx;
1172
1173         if (!x86_pmu.num_counters)
1174                 return;
1175
1176         local_irq_save(flags);
1177
1178         cpu = smp_processor_id();
1179         cpuc = &per_cpu(cpu_hw_events, cpu);
1180
1181         if (x86_pmu.version >= 2) {
1182                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1183                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1184                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1185                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1186                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1187
1188                 pr_info("\n");
1189                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1190                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1191                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1192                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1193                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1194         }
1195         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1196
1197         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1198                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1199                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1200
1201                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1202
1203                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1204                         cpu, idx, pmc_ctrl);
1205                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1206                         cpu, idx, pmc_count);
1207                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1208                         cpu, idx, prev_left);
1209         }
1210         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1211                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1212
1213                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1214                         cpu, idx, pmc_count);
1215         }
1216         local_irq_restore(flags);
1217 }
1218
1219 static void x86_pmu_stop(struct perf_event *event, int flags)
1220 {
1221         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1222         struct hw_perf_event *hwc = &event->hw;
1223
1224         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1225                 x86_pmu.disable(event);
1226                 cpuc->events[hwc->idx] = NULL;
1227                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1228                 hwc->state |= PERF_HES_STOPPED;
1229         }
1230
1231         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1232                 /*
1233                  * Drain the remaining delta count out of a event
1234                  * that we are disabling:
1235                  */
1236                 x86_perf_event_update(event);
1237                 hwc->state |= PERF_HES_UPTODATE;
1238         }
1239 }
1240
1241 static void x86_pmu_del(struct perf_event *event, int flags)
1242 {
1243         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1244         int i;
1245
1246         /*
1247          * If we're called during a txn, we don't need to do anything.
1248          * The events never got scheduled and ->cancel_txn will truncate
1249          * the event_list.
1250          */
1251         if (cpuc->group_flag & PERF_EVENT_TXN)
1252                 return;
1253
1254         x86_pmu_stop(event, PERF_EF_UPDATE);
1255
1256         for (i = 0; i < cpuc->n_events; i++) {
1257                 if (event == cpuc->event_list[i]) {
1258
1259                         if (x86_pmu.put_event_constraints)
1260                                 x86_pmu.put_event_constraints(cpuc, event);
1261
1262                         while (++i < cpuc->n_events)
1263                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1264
1265                         --cpuc->n_events;
1266                         break;
1267                 }
1268         }
1269         perf_event_update_userpage(event);
1270 }
1271
1272 static int x86_pmu_handle_irq(struct pt_regs *regs)
1273 {
1274         struct perf_sample_data data;
1275         struct cpu_hw_events *cpuc;
1276         struct perf_event *event;
1277         int idx, handled = 0;
1278         u64 val;
1279
1280         perf_sample_data_init(&data, 0);
1281
1282         cpuc = &__get_cpu_var(cpu_hw_events);
1283
1284         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1285                 if (!test_bit(idx, cpuc->active_mask)) {
1286                         /*
1287                          * Though we deactivated the counter some cpus
1288                          * might still deliver spurious interrupts still
1289                          * in flight. Catch them:
1290                          */
1291                         if (__test_and_clear_bit(idx, cpuc->running))
1292                                 handled++;
1293                         continue;
1294                 }
1295
1296                 event = cpuc->events[idx];
1297
1298                 val = x86_perf_event_update(event);
1299                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1300                         continue;
1301
1302                 /*
1303                  * event overflow
1304                  */
1305                 handled++;
1306                 data.period     = event->hw.last_period;
1307
1308                 if (!x86_perf_event_set_period(event))
1309                         continue;
1310
1311                 if (perf_event_overflow(event, 1, &data, regs))
1312                         x86_pmu_stop(event, 0);
1313         }
1314
1315         if (handled)
1316                 inc_irq_stat(apic_perf_irqs);
1317
1318         return handled;
1319 }
1320
1321 void perf_events_lapic_init(void)
1322 {
1323         if (!x86_pmu.apic || !x86_pmu_initialized())
1324                 return;
1325
1326         /*
1327          * Always use NMI for PMU
1328          */
1329         apic_write(APIC_LVTPC, APIC_DM_NMI);
1330 }
1331
1332 struct pmu_nmi_state {
1333         unsigned int    marked;
1334         int             handled;
1335 };
1336
1337 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1338
1339 static int __kprobes
1340 perf_event_nmi_handler(struct notifier_block *self,
1341                          unsigned long cmd, void *__args)
1342 {
1343         struct die_args *args = __args;
1344         unsigned int this_nmi;
1345         int handled;
1346
1347         if (!atomic_read(&active_events))
1348                 return NOTIFY_DONE;
1349
1350         switch (cmd) {
1351         case DIE_NMI:
1352                 break;
1353         case DIE_NMIUNKNOWN:
1354                 this_nmi = percpu_read(irq_stat.__nmi_count);
1355                 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1356                         /* let the kernel handle the unknown nmi */
1357                         return NOTIFY_DONE;
1358                 /*
1359                  * This one is a PMU back-to-back nmi. Two events
1360                  * trigger 'simultaneously' raising two back-to-back
1361                  * NMIs. If the first NMI handles both, the latter
1362                  * will be empty and daze the CPU. So, we drop it to
1363                  * avoid false-positive 'unknown nmi' messages.
1364                  */
1365                 return NOTIFY_STOP;
1366         default:
1367                 return NOTIFY_DONE;
1368         }
1369
1370         apic_write(APIC_LVTPC, APIC_DM_NMI);
1371
1372         handled = x86_pmu.handle_irq(args->regs);
1373         if (!handled)
1374                 return NOTIFY_DONE;
1375
1376         this_nmi = percpu_read(irq_stat.__nmi_count);
1377         if ((handled > 1) ||
1378                 /* the next nmi could be a back-to-back nmi */
1379             ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1380              (__this_cpu_read(pmu_nmi.handled) > 1))) {
1381                 /*
1382                  * We could have two subsequent back-to-back nmis: The
1383                  * first handles more than one counter, the 2nd
1384                  * handles only one counter and the 3rd handles no
1385                  * counter.
1386                  *
1387                  * This is the 2nd nmi because the previous was
1388                  * handling more than one counter. We will mark the
1389                  * next (3rd) and then drop it if unhandled.
1390                  */
1391                 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1392                 __this_cpu_write(pmu_nmi.handled, handled);
1393         }
1394
1395         return NOTIFY_STOP;
1396 }
1397
1398 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1399         .notifier_call          = perf_event_nmi_handler,
1400         .next                   = NULL,
1401         .priority               = NMI_LOCAL_LOW_PRIOR,
1402 };
1403
1404 static struct event_constraint unconstrained;
1405 static struct event_constraint emptyconstraint;
1406
1407 static struct event_constraint *
1408 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1409 {
1410         struct event_constraint *c;
1411
1412         if (x86_pmu.event_constraints) {
1413                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1414                         if ((event->hw.config & c->cmask) == c->code)
1415                                 return c;
1416                 }
1417         }
1418
1419         return &unconstrained;
1420 }
1421
1422 #include "perf_event_amd.c"
1423 #include "perf_event_p6.c"
1424 #include "perf_event_p4.c"
1425 #include "perf_event_intel_lbr.c"
1426 #include "perf_event_intel_ds.c"
1427 #include "perf_event_intel.c"
1428
1429 static int __cpuinit
1430 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1431 {
1432         unsigned int cpu = (long)hcpu;
1433         int ret = NOTIFY_OK;
1434
1435         switch (action & ~CPU_TASKS_FROZEN) {
1436         case CPU_UP_PREPARE:
1437                 if (x86_pmu.cpu_prepare)
1438                         ret = x86_pmu.cpu_prepare(cpu);
1439                 break;
1440
1441         case CPU_STARTING:
1442                 if (x86_pmu.cpu_starting)
1443                         x86_pmu.cpu_starting(cpu);
1444                 break;
1445
1446         case CPU_DYING:
1447                 if (x86_pmu.cpu_dying)
1448                         x86_pmu.cpu_dying(cpu);
1449                 break;
1450
1451         case CPU_UP_CANCELED:
1452         case CPU_DEAD:
1453                 if (x86_pmu.cpu_dead)
1454                         x86_pmu.cpu_dead(cpu);
1455                 break;
1456
1457         default:
1458                 break;
1459         }
1460
1461         return ret;
1462 }
1463
1464 static void __init pmu_check_apic(void)
1465 {
1466         if (cpu_has_apic)
1467                 return;
1468
1469         x86_pmu.apic = 0;
1470         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1471         pr_info("no hardware sampling interrupt available.\n");
1472 }
1473
1474 static int __init init_hw_perf_events(void)
1475 {
1476         struct event_constraint *c;
1477         int err;
1478
1479         pr_info("Performance Events: ");
1480
1481         switch (boot_cpu_data.x86_vendor) {
1482         case X86_VENDOR_INTEL:
1483                 err = intel_pmu_init();
1484                 break;
1485         case X86_VENDOR_AMD:
1486                 err = amd_pmu_init();
1487                 break;
1488         default:
1489                 return 0;
1490         }
1491         if (err != 0) {
1492                 pr_cont("no PMU driver, software events only.\n");
1493                 return 0;
1494         }
1495
1496         pmu_check_apic();
1497
1498         /* sanity check that the hardware exists or is emulated */
1499         if (!check_hw_exists())
1500                 return 0;
1501
1502         pr_cont("%s PMU driver.\n", x86_pmu.name);
1503
1504         if (x86_pmu.quirks)
1505                 x86_pmu.quirks();
1506
1507         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1508                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1509                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1510                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1511         }
1512         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1513
1514         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1515                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1516                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1517                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1518         }
1519
1520         x86_pmu.intel_ctrl |=
1521                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1522
1523         perf_events_lapic_init();
1524         register_die_notifier(&perf_event_nmi_notifier);
1525
1526         unconstrained = (struct event_constraint)
1527                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1528                                    0, x86_pmu.num_counters);
1529
1530         if (x86_pmu.event_constraints) {
1531                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1532                         if (c->cmask != X86_RAW_EVENT_MASK)
1533                                 continue;
1534
1535                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1536                         c->weight += x86_pmu.num_counters;
1537                 }
1538         }
1539
1540         pr_info("... version:                %d\n",     x86_pmu.version);
1541         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1542         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1543         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1544         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1545         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1546         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1547
1548         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1549         perf_cpu_notifier(x86_pmu_notifier);
1550
1551         return 0;
1552 }
1553 early_initcall(init_hw_perf_events);
1554
1555 static inline void x86_pmu_read(struct perf_event *event)
1556 {
1557         x86_perf_event_update(event);
1558 }
1559
1560 /*
1561  * Start group events scheduling transaction
1562  * Set the flag to make pmu::enable() not perform the
1563  * schedulability test, it will be performed at commit time
1564  */
1565 static void x86_pmu_start_txn(struct pmu *pmu)
1566 {
1567         perf_pmu_disable(pmu);
1568         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1569         __this_cpu_write(cpu_hw_events.n_txn, 0);
1570 }
1571
1572 /*
1573  * Stop group events scheduling transaction
1574  * Clear the flag and pmu::enable() will perform the
1575  * schedulability test.
1576  */
1577 static void x86_pmu_cancel_txn(struct pmu *pmu)
1578 {
1579         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1580         /*
1581          * Truncate the collected events.
1582          */
1583         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1584         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1585         perf_pmu_enable(pmu);
1586 }
1587
1588 /*
1589  * Commit group events scheduling transaction
1590  * Perform the group schedulability test as a whole
1591  * Return 0 if success
1592  */
1593 static int x86_pmu_commit_txn(struct pmu *pmu)
1594 {
1595         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1596         int assign[X86_PMC_IDX_MAX];
1597         int n, ret;
1598
1599         n = cpuc->n_events;
1600
1601         if (!x86_pmu_initialized())
1602                 return -EAGAIN;
1603
1604         ret = x86_pmu.schedule_events(cpuc, n, assign);
1605         if (ret)
1606                 return ret;
1607
1608         /*
1609          * copy new assignment, now we know it is possible
1610          * will be used by hw_perf_enable()
1611          */
1612         memcpy(cpuc->assign, assign, n*sizeof(int));
1613
1614         cpuc->group_flag &= ~PERF_EVENT_TXN;
1615         perf_pmu_enable(pmu);
1616         return 0;
1617 }
1618
1619 /*
1620  * validate that we can schedule this event
1621  */
1622 static int validate_event(struct perf_event *event)
1623 {
1624         struct cpu_hw_events *fake_cpuc;
1625         struct event_constraint *c;
1626         int ret = 0;
1627
1628         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1629         if (!fake_cpuc)
1630                 return -ENOMEM;
1631
1632         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1633
1634         if (!c || !c->weight)
1635                 ret = -ENOSPC;
1636
1637         if (x86_pmu.put_event_constraints)
1638                 x86_pmu.put_event_constraints(fake_cpuc, event);
1639
1640         kfree(fake_cpuc);
1641
1642         return ret;
1643 }
1644
1645 /*
1646  * validate a single event group
1647  *
1648  * validation include:
1649  *      - check events are compatible which each other
1650  *      - events do not compete for the same counter
1651  *      - number of events <= number of counters
1652  *
1653  * validation ensures the group can be loaded onto the
1654  * PMU if it was the only group available.
1655  */
1656 static int validate_group(struct perf_event *event)
1657 {
1658         struct perf_event *leader = event->group_leader;
1659         struct cpu_hw_events *fake_cpuc;
1660         int ret, n;
1661
1662         ret = -ENOMEM;
1663         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1664         if (!fake_cpuc)
1665                 goto out;
1666
1667         /*
1668          * the event is not yet connected with its
1669          * siblings therefore we must first collect
1670          * existing siblings, then add the new event
1671          * before we can simulate the scheduling
1672          */
1673         ret = -ENOSPC;
1674         n = collect_events(fake_cpuc, leader, true);
1675         if (n < 0)
1676                 goto out_free;
1677
1678         fake_cpuc->n_events = n;
1679         n = collect_events(fake_cpuc, event, false);
1680         if (n < 0)
1681                 goto out_free;
1682
1683         fake_cpuc->n_events = n;
1684
1685         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1686
1687 out_free:
1688         kfree(fake_cpuc);
1689 out:
1690         return ret;
1691 }
1692
1693 static int x86_pmu_event_init(struct perf_event *event)
1694 {
1695         struct pmu *tmp;
1696         int err;
1697
1698         switch (event->attr.type) {
1699         case PERF_TYPE_RAW:
1700         case PERF_TYPE_HARDWARE:
1701         case PERF_TYPE_HW_CACHE:
1702                 break;
1703
1704         default:
1705                 return -ENOENT;
1706         }
1707
1708         err = __x86_pmu_event_init(event);
1709         if (!err) {
1710                 /*
1711                  * we temporarily connect event to its pmu
1712                  * such that validate_group() can classify
1713                  * it as an x86 event using is_x86_event()
1714                  */
1715                 tmp = event->pmu;
1716                 event->pmu = &pmu;
1717
1718                 if (event->group_leader != event)
1719                         err = validate_group(event);
1720                 else
1721                         err = validate_event(event);
1722
1723                 event->pmu = tmp;
1724         }
1725         if (err) {
1726                 if (event->destroy)
1727                         event->destroy(event);
1728         }
1729
1730         return err;
1731 }
1732
1733 static struct pmu pmu = {
1734         .pmu_enable     = x86_pmu_enable,
1735         .pmu_disable    = x86_pmu_disable,
1736
1737         .event_init     = x86_pmu_event_init,
1738
1739         .add            = x86_pmu_add,
1740         .del            = x86_pmu_del,
1741         .start          = x86_pmu_start,
1742         .stop           = x86_pmu_stop,
1743         .read           = x86_pmu_read,
1744
1745         .start_txn      = x86_pmu_start_txn,
1746         .cancel_txn     = x86_pmu_cancel_txn,
1747         .commit_txn     = x86_pmu_commit_txn,
1748 };
1749
1750 /*
1751  * callchain support
1752  */
1753
1754 static void
1755 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1756 {
1757         /* Ignore warnings */
1758 }
1759
1760 static void backtrace_warning(void *data, char *msg)
1761 {
1762         /* Ignore warnings */
1763 }
1764
1765 static int backtrace_stack(void *data, char *name)
1766 {
1767         return 0;
1768 }
1769
1770 static void backtrace_address(void *data, unsigned long addr, int reliable)
1771 {
1772         struct perf_callchain_entry *entry = data;
1773
1774         perf_callchain_store(entry, addr);
1775 }
1776
1777 static const struct stacktrace_ops backtrace_ops = {
1778         .warning                = backtrace_warning,
1779         .warning_symbol         = backtrace_warning_symbol,
1780         .stack                  = backtrace_stack,
1781         .address                = backtrace_address,
1782         .walk_stack             = print_context_stack_bp,
1783 };
1784
1785 void
1786 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1787 {
1788         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1789                 /* TODO: We don't support guest os callchain now */
1790                 return;
1791         }
1792
1793         perf_callchain_store(entry, regs->ip);
1794
1795         dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
1796 }
1797
1798 #ifdef CONFIG_COMPAT
1799 static inline int
1800 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1801 {
1802         /* 32-bit process in 64-bit kernel. */
1803         struct stack_frame_ia32 frame;
1804         const void __user *fp;
1805
1806         if (!test_thread_flag(TIF_IA32))
1807                 return 0;
1808
1809         fp = compat_ptr(regs->bp);
1810         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1811                 unsigned long bytes;
1812                 frame.next_frame     = 0;
1813                 frame.return_address = 0;
1814
1815                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1816                 if (bytes != sizeof(frame))
1817                         break;
1818
1819                 if (fp < compat_ptr(regs->sp))
1820                         break;
1821
1822                 perf_callchain_store(entry, frame.return_address);
1823                 fp = compat_ptr(frame.next_frame);
1824         }
1825         return 1;
1826 }
1827 #else
1828 static inline int
1829 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1830 {
1831     return 0;
1832 }
1833 #endif
1834
1835 void
1836 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1837 {
1838         struct stack_frame frame;
1839         const void __user *fp;
1840
1841         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1842                 /* TODO: We don't support guest os callchain now */
1843                 return;
1844         }
1845
1846         fp = (void __user *)regs->bp;
1847
1848         perf_callchain_store(entry, regs->ip);
1849
1850         if (perf_callchain_user32(regs, entry))
1851                 return;
1852
1853         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1854                 unsigned long bytes;
1855                 frame.next_frame             = NULL;
1856                 frame.return_address = 0;
1857
1858                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1859                 if (bytes != sizeof(frame))
1860                         break;
1861
1862                 if ((unsigned long)fp < regs->sp)
1863                         break;
1864
1865                 perf_callchain_store(entry, frame.return_address);
1866                 fp = frame.next_frame;
1867         }
1868 }
1869
1870 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1871 {
1872         unsigned long ip;
1873
1874         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1875                 ip = perf_guest_cbs->get_guest_ip();
1876         else
1877                 ip = instruction_pointer(regs);
1878
1879         return ip;
1880 }
1881
1882 unsigned long perf_misc_flags(struct pt_regs *regs)
1883 {
1884         int misc = 0;
1885
1886         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1887                 if (perf_guest_cbs->is_user_mode())
1888                         misc |= PERF_RECORD_MISC_GUEST_USER;
1889                 else
1890                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1891         } else {
1892                 if (user_mode(regs))
1893                         misc |= PERF_RECORD_MISC_USER;
1894                 else
1895                         misc |= PERF_RECORD_MISC_KERNEL;
1896         }
1897
1898         if (regs->flags & PERF_EFLAGS_EXACT)
1899                 misc |= PERF_RECORD_MISC_EXACT_IP;
1900
1901         return misc;
1902 }