2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
29 #include <asm/stacktrace.h>
31 #include <asm/compat.h>
33 #include <asm/alternative.h>
37 #define wrmsrl(msr, val) \
39 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
40 (unsigned long)(val)); \
41 native_write_msr((msr), (u32)((u64)(val)), \
42 (u32)((u64)(val) >> 32)); \
48 * register -------------------------------
49 * | HT | no HT | HT | no HT |
50 *-----------------------------------------
51 * offcore | core | core | cpu | core |
52 * lbr_sel | core | core | cpu | core |
53 * ld_lat | cpu | core | cpu | core |
54 *-----------------------------------------
56 * Given that there is a small number of shared regs,
57 * we can pre-allocate their slot in the per-cpu
58 * per-core reg tables.
61 EXTRA_REG_NONE = -1, /* not used */
63 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
64 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
66 EXTRA_REG_MAX /* number of entries needed */
69 struct event_constraint {
71 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
80 int nb_id; /* NorthBridge id */
81 int refcnt; /* reference count */
82 struct perf_event *owners[X86_PMC_IDX_MAX];
83 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
88 #define MAX_LBR_ENTRIES 16
90 struct cpu_hw_events {
92 * Generic x86 PMC bits
94 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
95 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
96 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
102 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
103 u64 tags[X86_PMC_IDX_MAX];
104 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
106 unsigned int group_flag;
109 * Intel DebugStore bits
111 struct debug_store *ds;
119 struct perf_branch_stack lbr_stack;
120 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
123 * manage shared (per-core, per-cpu) registers
124 * used on Intel NHM/WSM/SNB
126 struct intel_shared_regs *shared_regs;
131 struct amd_nb *amd_nb;
133 void *kfree_on_online;
136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
137 { .idxmsk64 = (n) }, \
143 #define EVENT_CONSTRAINT(c, n, m) \
144 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
147 * Constraint on the Event code.
149 #define INTEL_EVENT_CONSTRAINT(c, n) \
150 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
153 * Constraint on the Event code + UMask + fixed-mask
155 * filter mask to validate fixed counter events.
156 * the following filters disqualify for fixed counters:
160 * The other filters are supported by fixed counters.
161 * The any-thread option is supported starting with v3.
163 #define FIXED_EVENT_CONSTRAINT(c, n) \
164 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
167 * Constraint on the Event code + UMask
169 #define INTEL_UEVENT_CONSTRAINT(c, n) \
170 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
172 #define EVENT_CONSTRAINT_END \
173 EVENT_CONSTRAINT(0, 0, 0)
175 #define for_each_event_constraint(e, c) \
176 for ((e) = (c); (e)->weight; (e)++)
179 * Per register state.
182 raw_spinlock_t lock; /* per-core: protect structure */
183 u64 config; /* extra MSR config */
184 u64 reg; /* extra MSR number */
185 atomic_t ref; /* reference count */
189 * Extra registers for specific events.
191 * Some events need large masks and require external MSRs.
192 * Those extra MSRs end up being shared for all events on
193 * a PMU and sometimes between PMU of sibling HT threads.
194 * In either case, the kernel needs to handle conflicting
195 * accesses to those extra, shared, regs. The data structure
196 * to manage those registers is stored in cpu_hw_event.
203 int idx; /* per_xxx->regs[] reg index */
206 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
209 .config_mask = (m), \
210 .valid_mask = (vm), \
211 .idx = EXTRA_REG_##i \
214 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
215 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
217 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
219 union perf_capabilities {
223 u64 pebs_arch_reg : 1;
231 * struct x86_pmu - generic x86 pmu
235 * Generic x86 PMC bits
239 int (*handle_irq)(struct pt_regs *);
240 void (*disable_all)(void);
241 void (*enable_all)(int added);
242 void (*enable)(struct perf_event *);
243 void (*disable)(struct perf_event *);
244 int (*hw_config)(struct perf_event *event);
245 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
248 u64 (*event_map)(int);
251 int num_counters_fixed;
256 struct event_constraint *
257 (*get_event_constraints)(struct cpu_hw_events *cpuc,
258 struct perf_event *event);
260 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
261 struct perf_event *event);
262 struct event_constraint *event_constraints;
263 void (*quirks)(void);
264 int perfctr_second_write;
266 int (*cpu_prepare)(int cpu);
267 void (*cpu_starting)(int cpu);
268 void (*cpu_dying)(int cpu);
269 void (*cpu_dead)(int cpu);
272 * Intel Arch Perfmon v2+
275 union perf_capabilities intel_cap;
278 * Intel DebugStore bits
281 int bts_active, pebs_active;
282 int pebs_record_size;
283 void (*drain_pebs)(struct pt_regs *regs);
284 struct event_constraint *pebs_constraints;
289 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
290 int lbr_nr; /* hardware stack size */
293 * Extra registers for events
295 struct extra_reg *extra_regs;
296 unsigned int er_flags;
299 #define ERF_NO_HT_SHARING 1
300 #define ERF_HAS_RSP_1 2
302 static struct x86_pmu x86_pmu __read_mostly;
304 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
308 static int x86_perf_event_set_period(struct perf_event *event);
311 * Generalized hw caching related hw_event table, filled
312 * in on a per model basis. A value of 0 means
313 * 'not supported', -1 means 'hw_event makes no sense on
314 * this CPU', any other value means the raw hw_event
318 #define C(x) PERF_COUNT_HW_CACHE_##x
320 static u64 __read_mostly hw_cache_event_ids
321 [PERF_COUNT_HW_CACHE_MAX]
322 [PERF_COUNT_HW_CACHE_OP_MAX]
323 [PERF_COUNT_HW_CACHE_RESULT_MAX];
324 static u64 __read_mostly hw_cache_extra_regs
325 [PERF_COUNT_HW_CACHE_MAX]
326 [PERF_COUNT_HW_CACHE_OP_MAX]
327 [PERF_COUNT_HW_CACHE_RESULT_MAX];
330 * Propagate event elapsed time into the generic event.
331 * Can only be executed on the CPU where the event is active.
332 * Returns the delta events processed.
335 x86_perf_event_update(struct perf_event *event)
337 struct hw_perf_event *hwc = &event->hw;
338 int shift = 64 - x86_pmu.cntval_bits;
339 u64 prev_raw_count, new_raw_count;
343 if (idx == X86_PMC_IDX_FIXED_BTS)
347 * Careful: an NMI might modify the previous event value.
349 * Our tactic to handle this is to first atomically read and
350 * exchange a new raw count - then add that new-prev delta
351 * count to the generic event atomically:
354 prev_raw_count = local64_read(&hwc->prev_count);
355 rdmsrl(hwc->event_base, new_raw_count);
357 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
358 new_raw_count) != prev_raw_count)
362 * Now we have the new raw value and have updated the prev
363 * timestamp already. We can now calculate the elapsed delta
364 * (event-)time and add that to the generic event.
366 * Careful, not all hw sign-extends above the physical width
369 delta = (new_raw_count << shift) - (prev_raw_count << shift);
372 local64_add(delta, &event->count);
373 local64_sub(delta, &hwc->period_left);
375 return new_raw_count;
378 static inline int x86_pmu_addr_offset(int index)
382 /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
383 alternative_io(ASM_NOP2,
385 X86_FEATURE_PERFCTR_CORE,
392 static inline unsigned int x86_pmu_config_addr(int index)
394 return x86_pmu.eventsel + x86_pmu_addr_offset(index);
397 static inline unsigned int x86_pmu_event_addr(int index)
399 return x86_pmu.perfctr + x86_pmu_addr_offset(index);
403 * Find and validate any extra registers to set up.
405 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
407 struct hw_perf_event_extra *reg;
408 struct extra_reg *er;
410 reg = &event->hw.extra_reg;
412 if (!x86_pmu.extra_regs)
415 for (er = x86_pmu.extra_regs; er->msr; er++) {
416 if (er->event != (config & er->config_mask))
418 if (event->attr.config1 & ~er->valid_mask)
422 reg->config = event->attr.config1;
429 static atomic_t active_events;
430 static DEFINE_MUTEX(pmc_reserve_mutex);
432 #ifdef CONFIG_X86_LOCAL_APIC
434 static bool reserve_pmc_hardware(void)
438 for (i = 0; i < x86_pmu.num_counters; i++) {
439 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
443 for (i = 0; i < x86_pmu.num_counters; i++) {
444 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
451 for (i--; i >= 0; i--)
452 release_evntsel_nmi(x86_pmu_config_addr(i));
454 i = x86_pmu.num_counters;
457 for (i--; i >= 0; i--)
458 release_perfctr_nmi(x86_pmu_event_addr(i));
463 static void release_pmc_hardware(void)
467 for (i = 0; i < x86_pmu.num_counters; i++) {
468 release_perfctr_nmi(x86_pmu_event_addr(i));
469 release_evntsel_nmi(x86_pmu_config_addr(i));
475 static bool reserve_pmc_hardware(void) { return true; }
476 static void release_pmc_hardware(void) {}
480 static bool check_hw_exists(void)
482 u64 val, val_new = 0;
486 * Check to see if the BIOS enabled any of the counters, if so
489 for (i = 0; i < x86_pmu.num_counters; i++) {
490 reg = x86_pmu_config_addr(i);
491 ret = rdmsrl_safe(reg, &val);
494 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
498 if (x86_pmu.num_counters_fixed) {
499 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
500 ret = rdmsrl_safe(reg, &val);
503 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
504 if (val & (0x03 << i*4))
510 * Now write a value and read it back to see if it matches,
511 * this is needed to detect certain hardware emulators (qemu/kvm)
512 * that don't trap on the MSR access and always return 0s.
515 ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
516 ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
517 if (ret || val != val_new)
524 * We still allow the PMU driver to operate:
526 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
527 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
532 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
537 static void reserve_ds_buffers(void);
538 static void release_ds_buffers(void);
540 static void hw_perf_event_destroy(struct perf_event *event)
542 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
543 release_pmc_hardware();
544 release_ds_buffers();
545 mutex_unlock(&pmc_reserve_mutex);
549 static inline int x86_pmu_initialized(void)
551 return x86_pmu.handle_irq != NULL;
555 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
557 struct perf_event_attr *attr = &event->attr;
558 unsigned int cache_type, cache_op, cache_result;
561 config = attr->config;
563 cache_type = (config >> 0) & 0xff;
564 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
567 cache_op = (config >> 8) & 0xff;
568 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
571 cache_result = (config >> 16) & 0xff;
572 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
575 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
584 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
585 return x86_pmu_extra_regs(val, event);
588 static int x86_setup_perfctr(struct perf_event *event)
590 struct perf_event_attr *attr = &event->attr;
591 struct hw_perf_event *hwc = &event->hw;
594 if (!is_sampling_event(event)) {
595 hwc->sample_period = x86_pmu.max_period;
596 hwc->last_period = hwc->sample_period;
597 local64_set(&hwc->period_left, hwc->sample_period);
600 * If we have a PMU initialized but no APIC
601 * interrupts, we cannot sample hardware
602 * events (user-space has to fall back and
603 * sample via a hrtimer based software event):
610 * Do not allow config1 (extended registers) to propagate,
611 * there's no sane user-space generalization yet:
613 if (attr->type == PERF_TYPE_RAW)
616 if (attr->type == PERF_TYPE_HW_CACHE)
617 return set_ext_hw_attr(hwc, event);
619 if (attr->config >= x86_pmu.max_events)
625 config = x86_pmu.event_map(attr->config);
636 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
637 !attr->freq && hwc->sample_period == 1) {
638 /* BTS is not supported by this architecture. */
639 if (!x86_pmu.bts_active)
642 /* BTS is currently only allowed for user-mode. */
643 if (!attr->exclude_kernel)
647 hwc->config |= config;
652 static int x86_pmu_hw_config(struct perf_event *event)
654 if (event->attr.precise_ip) {
657 /* Support for constant skid */
658 if (x86_pmu.pebs_active) {
661 /* Support for IP fixup */
666 if (event->attr.precise_ip > precise)
672 * (keep 'enabled' bit clear for now)
674 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
677 * Count user and OS events unless requested not to
679 if (!event->attr.exclude_user)
680 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
681 if (!event->attr.exclude_kernel)
682 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
684 if (event->attr.type == PERF_TYPE_RAW)
685 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
687 return x86_setup_perfctr(event);
691 * Setup the hardware configuration for a given attr_type
693 static int __x86_pmu_event_init(struct perf_event *event)
697 if (!x86_pmu_initialized())
701 if (!atomic_inc_not_zero(&active_events)) {
702 mutex_lock(&pmc_reserve_mutex);
703 if (atomic_read(&active_events) == 0) {
704 if (!reserve_pmc_hardware())
707 reserve_ds_buffers();
710 atomic_inc(&active_events);
711 mutex_unlock(&pmc_reserve_mutex);
716 event->destroy = hw_perf_event_destroy;
719 event->hw.last_cpu = -1;
720 event->hw.last_tag = ~0ULL;
723 event->hw.extra_reg.idx = EXTRA_REG_NONE;
725 return x86_pmu.hw_config(event);
728 static void x86_pmu_disable_all(void)
730 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
733 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
736 if (!test_bit(idx, cpuc->active_mask))
738 rdmsrl(x86_pmu_config_addr(idx), val);
739 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
741 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
742 wrmsrl(x86_pmu_config_addr(idx), val);
746 static void x86_pmu_disable(struct pmu *pmu)
748 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
750 if (!x86_pmu_initialized())
760 x86_pmu.disable_all();
763 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
766 if (hwc->extra_reg.reg)
767 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
768 wrmsrl(hwc->config_base, hwc->config | enable_mask);
771 static void x86_pmu_enable_all(int added)
773 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
776 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
777 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
779 if (!test_bit(idx, cpuc->active_mask))
782 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
786 static struct pmu pmu;
788 static inline int is_x86_event(struct perf_event *event)
790 return event->pmu == &pmu;
793 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
795 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
796 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
797 int i, j, w, wmax, num = 0;
798 struct hw_perf_event *hwc;
800 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
802 for (i = 0; i < n; i++) {
803 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
808 * fastpath, try to reuse previous register
810 for (i = 0; i < n; i++) {
811 hwc = &cpuc->event_list[i]->hw;
818 /* constraint still honored */
819 if (!test_bit(hwc->idx, c->idxmsk))
822 /* not already used */
823 if (test_bit(hwc->idx, used_mask))
826 __set_bit(hwc->idx, used_mask);
828 assign[i] = hwc->idx;
837 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
840 * weight = number of possible counters
842 * 1 = most constrained, only works on one counter
843 * wmax = least constrained, works on any counter
845 * assign events to counters starting with most
846 * constrained events.
848 wmax = x86_pmu.num_counters;
851 * when fixed event counters are present,
852 * wmax is incremented by 1 to account
853 * for one more choice
855 if (x86_pmu.num_counters_fixed)
858 for (w = 1, num = n; num && w <= wmax; w++) {
860 for (i = 0; num && i < n; i++) {
862 hwc = &cpuc->event_list[i]->hw;
867 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
868 if (!test_bit(j, used_mask))
872 if (j == X86_PMC_IDX_MAX)
875 __set_bit(j, used_mask);
884 * scheduling failed or is just a simulation,
885 * free resources if necessary
887 if (!assign || num) {
888 for (i = 0; i < n; i++) {
889 if (x86_pmu.put_event_constraints)
890 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
893 return num ? -ENOSPC : 0;
897 * dogrp: true if must collect siblings events (group)
898 * returns total number of events and error code
900 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
902 struct perf_event *event;
905 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
907 /* current number of events already accepted */
910 if (is_x86_event(leader)) {
913 cpuc->event_list[n] = leader;
919 list_for_each_entry(event, &leader->sibling_list, group_entry) {
920 if (!is_x86_event(event) ||
921 event->state <= PERF_EVENT_STATE_OFF)
927 cpuc->event_list[n] = event;
933 static inline void x86_assign_hw_event(struct perf_event *event,
934 struct cpu_hw_events *cpuc, int i)
936 struct hw_perf_event *hwc = &event->hw;
938 hwc->idx = cpuc->assign[i];
939 hwc->last_cpu = smp_processor_id();
940 hwc->last_tag = ++cpuc->tags[i];
942 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
943 hwc->config_base = 0;
945 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
946 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
947 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
949 hwc->config_base = x86_pmu_config_addr(hwc->idx);
950 hwc->event_base = x86_pmu_event_addr(hwc->idx);
954 static inline int match_prev_assignment(struct hw_perf_event *hwc,
955 struct cpu_hw_events *cpuc,
958 return hwc->idx == cpuc->assign[i] &&
959 hwc->last_cpu == smp_processor_id() &&
960 hwc->last_tag == cpuc->tags[i];
963 static void x86_pmu_start(struct perf_event *event, int flags);
964 static void x86_pmu_stop(struct perf_event *event, int flags);
966 static void x86_pmu_enable(struct pmu *pmu)
968 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
969 struct perf_event *event;
970 struct hw_perf_event *hwc;
971 int i, added = cpuc->n_added;
973 if (!x86_pmu_initialized())
980 int n_running = cpuc->n_events - cpuc->n_added;
982 * apply assignment obtained either from
983 * hw_perf_group_sched_in() or x86_pmu_enable()
985 * step1: save events moving to new counters
986 * step2: reprogram moved events into new counters
988 for (i = 0; i < n_running; i++) {
989 event = cpuc->event_list[i];
993 * we can avoid reprogramming counter if:
994 * - assigned same counter as last time
995 * - running on same CPU as last time
996 * - no other event has used the counter since
998 if (hwc->idx == -1 ||
999 match_prev_assignment(hwc, cpuc, i))
1003 * Ensure we don't accidentally enable a stopped
1004 * counter simply because we rescheduled.
1006 if (hwc->state & PERF_HES_STOPPED)
1007 hwc->state |= PERF_HES_ARCH;
1009 x86_pmu_stop(event, PERF_EF_UPDATE);
1012 for (i = 0; i < cpuc->n_events; i++) {
1013 event = cpuc->event_list[i];
1016 if (!match_prev_assignment(hwc, cpuc, i))
1017 x86_assign_hw_event(event, cpuc, i);
1018 else if (i < n_running)
1021 if (hwc->state & PERF_HES_ARCH)
1024 x86_pmu_start(event, PERF_EF_RELOAD);
1027 perf_events_lapic_init();
1033 x86_pmu.enable_all(added);
1036 static inline void x86_pmu_disable_event(struct perf_event *event)
1038 struct hw_perf_event *hwc = &event->hw;
1040 wrmsrl(hwc->config_base, hwc->config);
1043 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1046 * Set the next IRQ period, based on the hwc->period_left value.
1047 * To be called with the event disabled in hw:
1050 x86_perf_event_set_period(struct perf_event *event)
1052 struct hw_perf_event *hwc = &event->hw;
1053 s64 left = local64_read(&hwc->period_left);
1054 s64 period = hwc->sample_period;
1055 int ret = 0, idx = hwc->idx;
1057 if (idx == X86_PMC_IDX_FIXED_BTS)
1061 * If we are way outside a reasonable range then just skip forward:
1063 if (unlikely(left <= -period)) {
1065 local64_set(&hwc->period_left, left);
1066 hwc->last_period = period;
1070 if (unlikely(left <= 0)) {
1072 local64_set(&hwc->period_left, left);
1073 hwc->last_period = period;
1077 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1079 if (unlikely(left < 2))
1082 if (left > x86_pmu.max_period)
1083 left = x86_pmu.max_period;
1085 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1088 * The hw event starts counting from this event offset,
1089 * mark it to be able to extra future deltas:
1091 local64_set(&hwc->prev_count, (u64)-left);
1093 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1096 * Due to erratum on certan cpu we need
1097 * a second write to be sure the register
1098 * is updated properly
1100 if (x86_pmu.perfctr_second_write) {
1101 wrmsrl(hwc->event_base,
1102 (u64)(-left) & x86_pmu.cntval_mask);
1105 perf_event_update_userpage(event);
1110 static void x86_pmu_enable_event(struct perf_event *event)
1112 if (__this_cpu_read(cpu_hw_events.enabled))
1113 __x86_pmu_enable_event(&event->hw,
1114 ARCH_PERFMON_EVENTSEL_ENABLE);
1118 * Add a single event to the PMU.
1120 * The event is added to the group of enabled events
1121 * but only if it can be scehduled with existing events.
1123 static int x86_pmu_add(struct perf_event *event, int flags)
1125 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1126 struct hw_perf_event *hwc;
1127 int assign[X86_PMC_IDX_MAX];
1132 perf_pmu_disable(event->pmu);
1133 n0 = cpuc->n_events;
1134 ret = n = collect_events(cpuc, event, false);
1138 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1139 if (!(flags & PERF_EF_START))
1140 hwc->state |= PERF_HES_ARCH;
1143 * If group events scheduling transaction was started,
1144 * skip the schedulability test here, it will be performed
1145 * at commit time (->commit_txn) as a whole
1147 if (cpuc->group_flag & PERF_EVENT_TXN)
1150 ret = x86_pmu.schedule_events(cpuc, n, assign);
1154 * copy new assignment, now we know it is possible
1155 * will be used by hw_perf_enable()
1157 memcpy(cpuc->assign, assign, n*sizeof(int));
1161 cpuc->n_added += n - n0;
1162 cpuc->n_txn += n - n0;
1166 perf_pmu_enable(event->pmu);
1170 static void x86_pmu_start(struct perf_event *event, int flags)
1172 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1173 int idx = event->hw.idx;
1175 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1178 if (WARN_ON_ONCE(idx == -1))
1181 if (flags & PERF_EF_RELOAD) {
1182 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1183 x86_perf_event_set_period(event);
1186 event->hw.state = 0;
1188 cpuc->events[idx] = event;
1189 __set_bit(idx, cpuc->active_mask);
1190 __set_bit(idx, cpuc->running);
1191 x86_pmu.enable(event);
1192 perf_event_update_userpage(event);
1195 void perf_event_print_debug(void)
1197 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1199 struct cpu_hw_events *cpuc;
1200 unsigned long flags;
1203 if (!x86_pmu.num_counters)
1206 local_irq_save(flags);
1208 cpu = smp_processor_id();
1209 cpuc = &per_cpu(cpu_hw_events, cpu);
1211 if (x86_pmu.version >= 2) {
1212 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1213 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1214 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1215 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1216 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1219 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1220 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1221 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1222 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1223 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1225 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1227 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1228 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1229 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1231 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1233 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1234 cpu, idx, pmc_ctrl);
1235 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1236 cpu, idx, pmc_count);
1237 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1238 cpu, idx, prev_left);
1240 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1241 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1243 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1244 cpu, idx, pmc_count);
1246 local_irq_restore(flags);
1249 static void x86_pmu_stop(struct perf_event *event, int flags)
1251 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1252 struct hw_perf_event *hwc = &event->hw;
1254 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1255 x86_pmu.disable(event);
1256 cpuc->events[hwc->idx] = NULL;
1257 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1258 hwc->state |= PERF_HES_STOPPED;
1261 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1263 * Drain the remaining delta count out of a event
1264 * that we are disabling:
1266 x86_perf_event_update(event);
1267 hwc->state |= PERF_HES_UPTODATE;
1271 static void x86_pmu_del(struct perf_event *event, int flags)
1273 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1277 * If we're called during a txn, we don't need to do anything.
1278 * The events never got scheduled and ->cancel_txn will truncate
1281 if (cpuc->group_flag & PERF_EVENT_TXN)
1284 x86_pmu_stop(event, PERF_EF_UPDATE);
1286 for (i = 0; i < cpuc->n_events; i++) {
1287 if (event == cpuc->event_list[i]) {
1289 if (x86_pmu.put_event_constraints)
1290 x86_pmu.put_event_constraints(cpuc, event);
1292 while (++i < cpuc->n_events)
1293 cpuc->event_list[i-1] = cpuc->event_list[i];
1299 perf_event_update_userpage(event);
1302 static int x86_pmu_handle_irq(struct pt_regs *regs)
1304 struct perf_sample_data data;
1305 struct cpu_hw_events *cpuc;
1306 struct perf_event *event;
1307 int idx, handled = 0;
1310 perf_sample_data_init(&data, 0);
1312 cpuc = &__get_cpu_var(cpu_hw_events);
1315 * Some chipsets need to unmask the LVTPC in a particular spot
1316 * inside the nmi handler. As a result, the unmasking was pushed
1317 * into all the nmi handlers.
1319 * This generic handler doesn't seem to have any issues where the
1320 * unmasking occurs so it was left at the top.
1322 apic_write(APIC_LVTPC, APIC_DM_NMI);
1324 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1325 if (!test_bit(idx, cpuc->active_mask)) {
1327 * Though we deactivated the counter some cpus
1328 * might still deliver spurious interrupts still
1329 * in flight. Catch them:
1331 if (__test_and_clear_bit(idx, cpuc->running))
1336 event = cpuc->events[idx];
1338 val = x86_perf_event_update(event);
1339 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1346 data.period = event->hw.last_period;
1348 if (!x86_perf_event_set_period(event))
1351 if (perf_event_overflow(event, &data, regs))
1352 x86_pmu_stop(event, 0);
1356 inc_irq_stat(apic_perf_irqs);
1361 void perf_events_lapic_init(void)
1363 if (!x86_pmu.apic || !x86_pmu_initialized())
1367 * Always use NMI for PMU
1369 apic_write(APIC_LVTPC, APIC_DM_NMI);
1372 struct pmu_nmi_state {
1373 unsigned int marked;
1377 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1379 static int __kprobes
1380 perf_event_nmi_handler(struct notifier_block *self,
1381 unsigned long cmd, void *__args)
1383 struct die_args *args = __args;
1384 unsigned int this_nmi;
1387 if (!atomic_read(&active_events))
1393 case DIE_NMIUNKNOWN:
1394 this_nmi = percpu_read(irq_stat.__nmi_count);
1395 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1396 /* let the kernel handle the unknown nmi */
1399 * This one is a PMU back-to-back nmi. Two events
1400 * trigger 'simultaneously' raising two back-to-back
1401 * NMIs. If the first NMI handles both, the latter
1402 * will be empty and daze the CPU. So, we drop it to
1403 * avoid false-positive 'unknown nmi' messages.
1410 handled = x86_pmu.handle_irq(args->regs);
1414 this_nmi = percpu_read(irq_stat.__nmi_count);
1415 if ((handled > 1) ||
1416 /* the next nmi could be a back-to-back nmi */
1417 ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1418 (__this_cpu_read(pmu_nmi.handled) > 1))) {
1420 * We could have two subsequent back-to-back nmis: The
1421 * first handles more than one counter, the 2nd
1422 * handles only one counter and the 3rd handles no
1425 * This is the 2nd nmi because the previous was
1426 * handling more than one counter. We will mark the
1427 * next (3rd) and then drop it if unhandled.
1429 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1430 __this_cpu_write(pmu_nmi.handled, handled);
1436 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1437 .notifier_call = perf_event_nmi_handler,
1439 .priority = NMI_LOCAL_LOW_PRIOR,
1442 static struct event_constraint unconstrained;
1443 static struct event_constraint emptyconstraint;
1445 static struct event_constraint *
1446 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1448 struct event_constraint *c;
1450 if (x86_pmu.event_constraints) {
1451 for_each_event_constraint(c, x86_pmu.event_constraints) {
1452 if ((event->hw.config & c->cmask) == c->code)
1457 return &unconstrained;
1460 #include "perf_event_amd.c"
1461 #include "perf_event_p6.c"
1462 #include "perf_event_p4.c"
1463 #include "perf_event_intel_lbr.c"
1464 #include "perf_event_intel_ds.c"
1465 #include "perf_event_intel.c"
1467 static int __cpuinit
1468 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1470 unsigned int cpu = (long)hcpu;
1471 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1472 int ret = NOTIFY_OK;
1474 switch (action & ~CPU_TASKS_FROZEN) {
1475 case CPU_UP_PREPARE:
1476 cpuc->kfree_on_online = NULL;
1477 if (x86_pmu.cpu_prepare)
1478 ret = x86_pmu.cpu_prepare(cpu);
1482 if (x86_pmu.cpu_starting)
1483 x86_pmu.cpu_starting(cpu);
1487 kfree(cpuc->kfree_on_online);
1491 if (x86_pmu.cpu_dying)
1492 x86_pmu.cpu_dying(cpu);
1495 case CPU_UP_CANCELED:
1497 if (x86_pmu.cpu_dead)
1498 x86_pmu.cpu_dead(cpu);
1508 static void __init pmu_check_apic(void)
1514 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1515 pr_info("no hardware sampling interrupt available.\n");
1518 static int __init init_hw_perf_events(void)
1520 struct event_constraint *c;
1523 pr_info("Performance Events: ");
1525 switch (boot_cpu_data.x86_vendor) {
1526 case X86_VENDOR_INTEL:
1527 err = intel_pmu_init();
1529 case X86_VENDOR_AMD:
1530 err = amd_pmu_init();
1536 pr_cont("no PMU driver, software events only.\n");
1542 /* sanity check that the hardware exists or is emulated */
1543 if (!check_hw_exists())
1546 pr_cont("%s PMU driver.\n", x86_pmu.name);
1551 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1552 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1553 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1554 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1556 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1558 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1559 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1560 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1561 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1564 x86_pmu.intel_ctrl |=
1565 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1567 perf_events_lapic_init();
1568 register_die_notifier(&perf_event_nmi_notifier);
1570 unconstrained = (struct event_constraint)
1571 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1572 0, x86_pmu.num_counters);
1574 if (x86_pmu.event_constraints) {
1575 for_each_event_constraint(c, x86_pmu.event_constraints) {
1576 if (c->cmask != X86_RAW_EVENT_MASK)
1579 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1580 c->weight += x86_pmu.num_counters;
1584 pr_info("... version: %d\n", x86_pmu.version);
1585 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1586 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1587 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1588 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1589 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1590 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1592 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1593 perf_cpu_notifier(x86_pmu_notifier);
1597 early_initcall(init_hw_perf_events);
1599 static inline void x86_pmu_read(struct perf_event *event)
1601 x86_perf_event_update(event);
1605 * Start group events scheduling transaction
1606 * Set the flag to make pmu::enable() not perform the
1607 * schedulability test, it will be performed at commit time
1609 static void x86_pmu_start_txn(struct pmu *pmu)
1611 perf_pmu_disable(pmu);
1612 __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1613 __this_cpu_write(cpu_hw_events.n_txn, 0);
1617 * Stop group events scheduling transaction
1618 * Clear the flag and pmu::enable() will perform the
1619 * schedulability test.
1621 static void x86_pmu_cancel_txn(struct pmu *pmu)
1623 __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1625 * Truncate the collected events.
1627 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1628 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1629 perf_pmu_enable(pmu);
1633 * Commit group events scheduling transaction
1634 * Perform the group schedulability test as a whole
1635 * Return 0 if success
1637 static int x86_pmu_commit_txn(struct pmu *pmu)
1639 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1640 int assign[X86_PMC_IDX_MAX];
1645 if (!x86_pmu_initialized())
1648 ret = x86_pmu.schedule_events(cpuc, n, assign);
1653 * copy new assignment, now we know it is possible
1654 * will be used by hw_perf_enable()
1656 memcpy(cpuc->assign, assign, n*sizeof(int));
1658 cpuc->group_flag &= ~PERF_EVENT_TXN;
1659 perf_pmu_enable(pmu);
1663 * a fake_cpuc is used to validate event groups. Due to
1664 * the extra reg logic, we need to also allocate a fake
1665 * per_core and per_cpu structure. Otherwise, group events
1666 * using extra reg may conflict without the kernel being
1667 * able to catch this when the last event gets added to
1670 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1672 kfree(cpuc->shared_regs);
1676 static struct cpu_hw_events *allocate_fake_cpuc(void)
1678 struct cpu_hw_events *cpuc;
1679 int cpu = raw_smp_processor_id();
1681 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1683 return ERR_PTR(-ENOMEM);
1685 /* only needed, if we have extra_regs */
1686 if (x86_pmu.extra_regs) {
1687 cpuc->shared_regs = allocate_shared_regs(cpu);
1688 if (!cpuc->shared_regs)
1693 free_fake_cpuc(cpuc);
1694 return ERR_PTR(-ENOMEM);
1698 * validate that we can schedule this event
1700 static int validate_event(struct perf_event *event)
1702 struct cpu_hw_events *fake_cpuc;
1703 struct event_constraint *c;
1706 fake_cpuc = allocate_fake_cpuc();
1707 if (IS_ERR(fake_cpuc))
1708 return PTR_ERR(fake_cpuc);
1710 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1712 if (!c || !c->weight)
1715 if (x86_pmu.put_event_constraints)
1716 x86_pmu.put_event_constraints(fake_cpuc, event);
1718 free_fake_cpuc(fake_cpuc);
1724 * validate a single event group
1726 * validation include:
1727 * - check events are compatible which each other
1728 * - events do not compete for the same counter
1729 * - number of events <= number of counters
1731 * validation ensures the group can be loaded onto the
1732 * PMU if it was the only group available.
1734 static int validate_group(struct perf_event *event)
1736 struct perf_event *leader = event->group_leader;
1737 struct cpu_hw_events *fake_cpuc;
1738 int ret = -ENOSPC, n;
1740 fake_cpuc = allocate_fake_cpuc();
1741 if (IS_ERR(fake_cpuc))
1742 return PTR_ERR(fake_cpuc);
1744 * the event is not yet connected with its
1745 * siblings therefore we must first collect
1746 * existing siblings, then add the new event
1747 * before we can simulate the scheduling
1749 n = collect_events(fake_cpuc, leader, true);
1753 fake_cpuc->n_events = n;
1754 n = collect_events(fake_cpuc, event, false);
1758 fake_cpuc->n_events = n;
1760 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1763 free_fake_cpuc(fake_cpuc);
1767 static int x86_pmu_event_init(struct perf_event *event)
1772 switch (event->attr.type) {
1774 case PERF_TYPE_HARDWARE:
1775 case PERF_TYPE_HW_CACHE:
1782 err = __x86_pmu_event_init(event);
1785 * we temporarily connect event to its pmu
1786 * such that validate_group() can classify
1787 * it as an x86 event using is_x86_event()
1792 if (event->group_leader != event)
1793 err = validate_group(event);
1795 err = validate_event(event);
1801 event->destroy(event);
1807 static struct pmu pmu = {
1808 .pmu_enable = x86_pmu_enable,
1809 .pmu_disable = x86_pmu_disable,
1811 .event_init = x86_pmu_event_init,
1815 .start = x86_pmu_start,
1816 .stop = x86_pmu_stop,
1817 .read = x86_pmu_read,
1819 .start_txn = x86_pmu_start_txn,
1820 .cancel_txn = x86_pmu_cancel_txn,
1821 .commit_txn = x86_pmu_commit_txn,
1828 static int backtrace_stack(void *data, char *name)
1833 static void backtrace_address(void *data, unsigned long addr, int reliable)
1835 struct perf_callchain_entry *entry = data;
1837 perf_callchain_store(entry, addr);
1840 static const struct stacktrace_ops backtrace_ops = {
1841 .stack = backtrace_stack,
1842 .address = backtrace_address,
1843 .walk_stack = print_context_stack_bp,
1847 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1849 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1850 /* TODO: We don't support guest os callchain now */
1854 perf_callchain_store(entry, regs->ip);
1856 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1859 #ifdef CONFIG_COMPAT
1861 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1863 /* 32-bit process in 64-bit kernel. */
1864 struct stack_frame_ia32 frame;
1865 const void __user *fp;
1867 if (!test_thread_flag(TIF_IA32))
1870 fp = compat_ptr(regs->bp);
1871 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1872 unsigned long bytes;
1873 frame.next_frame = 0;
1874 frame.return_address = 0;
1876 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1877 if (bytes != sizeof(frame))
1880 if (fp < compat_ptr(regs->sp))
1883 perf_callchain_store(entry, frame.return_address);
1884 fp = compat_ptr(frame.next_frame);
1890 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1897 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1899 struct stack_frame frame;
1900 const void __user *fp;
1902 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1903 /* TODO: We don't support guest os callchain now */
1907 fp = (void __user *)regs->bp;
1909 perf_callchain_store(entry, regs->ip);
1914 if (perf_callchain_user32(regs, entry))
1917 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1918 unsigned long bytes;
1919 frame.next_frame = NULL;
1920 frame.return_address = 0;
1922 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1923 if (bytes != sizeof(frame))
1926 if ((unsigned long)fp < regs->sp)
1929 perf_callchain_store(entry, frame.return_address);
1930 fp = frame.next_frame;
1934 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1938 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1939 ip = perf_guest_cbs->get_guest_ip();
1941 ip = instruction_pointer(regs);
1946 unsigned long perf_misc_flags(struct pt_regs *regs)
1950 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1951 if (perf_guest_cbs->is_user_mode())
1952 misc |= PERF_RECORD_MISC_GUEST_USER;
1954 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1956 if (user_mode(regs))
1957 misc |= PERF_RECORD_MISC_USER;
1959 misc |= PERF_RECORD_MISC_KERNEL;
1962 if (regs->flags & PERF_EFLAGS_EXACT)
1963 misc |= PERF_RECORD_MISC_EXACT_IP;