arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         /*
 422          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 423          * non-nested (L1) guest, it always points to vmcs01. For a nested
 424          * guest (L2), it points to a different VMCS.
 425          */
 426         struct loaded_vmcs    vmcs01;
 427         struct loaded_vmcs   *loaded_vmcs;
 428         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 429         struct msr_autoload {
 430                 unsigned nr;
 431                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 432                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 433         } msr_autoload;
 434         struct {
 435                 int           loaded;
 436                 u16           fs_sel, gs_sel, ldt_sel;
 437 #ifdef CONFIG_X86_64
 438                 u16           ds_sel, es_sel;
 439 #endif
 440                 int           gs_ldt_reload_needed;
 441                 int           fs_reload_needed;
 442         } host_state;
 443         struct {
 444                 int vm86_active;
 445                 ulong save_rflags;
 446                 struct kvm_segment segs[8];
 447         } rmode;
 448         struct {
 449                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 450                 struct kvm_save_segment {
 451                         u16 selector;
 452                         unsigned long base;
 453                         u32 limit;
 454                         u32 ar;
 455                 } seg[8];
 456         } segment_cache;
 457         int vpid;
 458         bool emulation_required;
 459
 460         /* Support for vnmi-less CPUs */
 461         int soft_vnmi_blocked;
 462         ktime_t entry_time;
 463         s64 vnmi_blocked_time;
 464         u32 exit_reason;
 465
 466         bool rdtscp_enabled;
 467
 468         /* Posted interrupt descriptor */
 469         struct pi_desc pi_desc;
 470
 471         /* Support for a guest hypervisor (nested VMX) */
 472         struct nested_vmx nested;
 473 };
 474
 475 enum segment_cache_field {
 476         SEG_FIELD_SEL = 0,
 477         SEG_FIELD_BASE = 1,
 478         SEG_FIELD_LIMIT = 2,
 479         SEG_FIELD_AR = 3,
 480
 481         SEG_FIELD_NR = 4
 482 };
 483
 484 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 485 {
 486         return container_of(vcpu, struct vcpu_vmx, vcpu);
 487 }
 488
 489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 490 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 491 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 492                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 493
 494
 495 static const unsigned long shadow_read_only_fields[] = {
 496         /*
 497          * We do NOT shadow fields that are modified when L0
 498          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 499          * VMXON...) executed by L1.
 500          * For example, VM_INSTRUCTION_ERROR is read
 501          * by L1 if a vmx instruction fails (part of the error path).
 502          * Note the code assumes this logic. If for some reason
 503          * we start shadowing these fields then we need to
 504          * force a shadow sync when L0 emulates vmx instructions
 505          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 506          * by nested_vmx_failValid)
 507          */
 508         VM_EXIT_REASON,
 509         VM_EXIT_INTR_INFO,
 510         VM_EXIT_INSTRUCTION_LEN,
 511         IDT_VECTORING_INFO_FIELD,
 512         IDT_VECTORING_ERROR_CODE,
 513         VM_EXIT_INTR_ERROR_CODE,
 514         EXIT_QUALIFICATION,
 515         GUEST_LINEAR_ADDRESS,
 516         GUEST_PHYSICAL_ADDRESS
 517 };
 518 static const int max_shadow_read_only_fields =
 519         ARRAY_SIZE(shadow_read_only_fields);
 520
 521 static const unsigned long shadow_read_write_fields[] = {
 522         GUEST_RIP,
 523         GUEST_RSP,
 524         GUEST_CR0,
 525         GUEST_CR3,
 526         GUEST_CR4,
 527         GUEST_INTERRUPTIBILITY_INFO,
 528         GUEST_RFLAGS,
 529         GUEST_CS_SELECTOR,
 530         GUEST_CS_AR_BYTES,
 531         GUEST_CS_LIMIT,
 532         GUEST_CS_BASE,
 533         GUEST_ES_BASE,
 534         CR0_GUEST_HOST_MASK,
 535         CR0_READ_SHADOW,
 536         CR4_READ_SHADOW,
 537         TSC_OFFSET,
 538         EXCEPTION_BITMAP,
 539         CPU_BASED_VM_EXEC_CONTROL,
 540         VM_ENTRY_EXCEPTION_ERROR_CODE,
 541         VM_ENTRY_INTR_INFO_FIELD,
 542         VM_ENTRY_INSTRUCTION_LEN,
 543         VM_ENTRY_EXCEPTION_ERROR_CODE,
 544         HOST_FS_BASE,
 545         HOST_GS_BASE,
 546         HOST_FS_SELECTOR,
 547         HOST_GS_SELECTOR
 548 };
 549 static const int max_shadow_read_write_fields =
 550         ARRAY_SIZE(shadow_read_write_fields);
 551
 552 static const unsigned short vmcs_field_to_offset_table[] = {
 553         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 554         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 555         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 556         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 557         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 558         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 559         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 560         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 561         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 562         FIELD(HOST_ES_SELECTOR, host_es_selector),
 563         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 564         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 565         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 566         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 567         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 568         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 569         FIELD64(IO_BITMAP_A, io_bitmap_a),
 570         FIELD64(IO_BITMAP_B, io_bitmap_b),
 571         FIELD64(MSR_BITMAP, msr_bitmap),
 572         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 573         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 574         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 575         FIELD64(TSC_OFFSET, tsc_offset),
 576         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 577         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 578         FIELD64(EPT_POINTER, ept_pointer),
 579         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 580         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 581         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 582         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 583         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 584         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 585         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 586         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 587         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 588         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 589         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 590         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 591         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 592         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 593         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 594         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 595         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 596         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 597         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 598         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 599         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 600         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 601         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 602         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 603         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 604         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 605         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 606         FIELD(TPR_THRESHOLD, tpr_threshold),
 607         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 608         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 609         FIELD(VM_EXIT_REASON, vm_exit_reason),
 610         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 611         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 612         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 613         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 614         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 615         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 616         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 617         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 618         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 619         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 620         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 621         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 622         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 623         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 624         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 625         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 626         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 627         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 628         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 629         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 630         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 631         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 632         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 633         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 634         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 635         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 636         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 637         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 638         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 639         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 640         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 641         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 642         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 643         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 644         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 645         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 646         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 647         FIELD(EXIT_QUALIFICATION, exit_qualification),
 648         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 649         FIELD(GUEST_CR0, guest_cr0),
 650         FIELD(GUEST_CR3, guest_cr3),
 651         FIELD(GUEST_CR4, guest_cr4),
 652         FIELD(GUEST_ES_BASE, guest_es_base),
 653         FIELD(GUEST_CS_BASE, guest_cs_base),
 654         FIELD(GUEST_SS_BASE, guest_ss_base),
 655         FIELD(GUEST_DS_BASE, guest_ds_base),
 656         FIELD(GUEST_FS_BASE, guest_fs_base),
 657         FIELD(GUEST_GS_BASE, guest_gs_base),
 658         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 659         FIELD(GUEST_TR_BASE, guest_tr_base),
 660         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 661         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 662         FIELD(GUEST_DR7, guest_dr7),
 663         FIELD(GUEST_RSP, guest_rsp),
 664         FIELD(GUEST_RIP, guest_rip),
 665         FIELD(GUEST_RFLAGS, guest_rflags),
 666         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 667         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 668         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 669         FIELD(HOST_CR0, host_cr0),
 670         FIELD(HOST_CR3, host_cr3),
 671         FIELD(HOST_CR4, host_cr4),
 672         FIELD(HOST_FS_BASE, host_fs_base),
 673         FIELD(HOST_GS_BASE, host_gs_base),
 674         FIELD(HOST_TR_BASE, host_tr_base),
 675         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 676         FIELD(HOST_IDTR_BASE, host_idtr_base),
 677         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 678         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 679         FIELD(HOST_RSP, host_rsp),
 680         FIELD(HOST_RIP, host_rip),
 681 };
 682 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 683
 684 static inline short vmcs_field_to_offset(unsigned long field)
 685 {
 686         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 687                 return -1;
 688         return vmcs_field_to_offset_table[field];
 689 }
 690
 691 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 692 {
 693         return to_vmx(vcpu)->nested.current_vmcs12;
 694 }
 695
 696 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 697 {
 698         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 699         if (is_error_page(page))
 700                 return NULL;
 701
 702         return page;
 703 }
 704
 705 static void nested_release_page(struct page *page)
 706 {
 707         kvm_release_page_dirty(page);
 708 }
 709
 710 static void nested_release_page_clean(struct page *page)
 711 {
 712         kvm_release_page_clean(page);
 713 }
 714
 715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 716 static u64 construct_eptp(unsigned long root_hpa);
 717 static void kvm_cpu_vmxon(u64 addr);
 718 static void kvm_cpu_vmxoff(void);
 719 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 720 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 721                             struct kvm_segment *var, int seg);
 722 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 723                             struct kvm_segment *var, int seg);
 724 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 725 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 727 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 728 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 729
 730 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 731 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 732 /*
 733  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 734  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 735  */
 736 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 737 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 738
 739 static unsigned long *vmx_io_bitmap_a;
 740 static unsigned long *vmx_io_bitmap_b;
 741 static unsigned long *vmx_msr_bitmap_legacy;
 742 static unsigned long *vmx_msr_bitmap_longmode;
 743 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 744 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 745 static unsigned long *vmx_vmread_bitmap;
 746 static unsigned long *vmx_vmwrite_bitmap;
 747
 748 static bool cpu_has_load_ia32_efer;
 749 static bool cpu_has_load_perf_global_ctrl;
 750
 751 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 752 static DEFINE_SPINLOCK(vmx_vpid_lock);
 753
 754 static struct vmcs_config {
 755         int size;
 756         int order;
 757         u32 revision_id;
 758         u32 pin_based_exec_ctrl;
 759         u32 cpu_based_exec_ctrl;
 760         u32 cpu_based_2nd_exec_ctrl;
 761         u32 vmexit_ctrl;
 762         u32 vmentry_ctrl;
 763 } vmcs_config;
 764
 765 static struct vmx_capability {
 766         u32 ept;
 767         u32 vpid;
 768 } vmx_capability;
 769
 770 #define VMX_SEGMENT_FIELD(seg)                                  \
 771         [VCPU_SREG_##seg] = {                                   \
 772                 .selector = GUEST_##seg##_SELECTOR,             \
 773                 .base = GUEST_##seg##_BASE,                     \
 774                 .limit = GUEST_##seg##_LIMIT,                   \
 775                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 776         }
 777
 778 static const struct kvm_vmx_segment_field {
 779         unsigned selector;
 780         unsigned base;
 781         unsigned limit;
 782         unsigned ar_bytes;
 783 } kvm_vmx_segment_fields[] = {
 784         VMX_SEGMENT_FIELD(CS),
 785         VMX_SEGMENT_FIELD(DS),
 786         VMX_SEGMENT_FIELD(ES),
 787         VMX_SEGMENT_FIELD(FS),
 788         VMX_SEGMENT_FIELD(GS),
 789         VMX_SEGMENT_FIELD(SS),
 790         VMX_SEGMENT_FIELD(TR),
 791         VMX_SEGMENT_FIELD(LDTR),
 792 };
 793
 794 static u64 host_efer;
 795
 796 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 797
 798 /*
 799  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 800  * away by decrementing the array size.
 801  */
 802 static const u32 vmx_msr_index[] = {
 803 #ifdef CONFIG_X86_64
 804         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 805 #endif
 806         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 807 };
 808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 809
 810 static inline bool is_page_fault(u32 intr_info)
 811 {
 812         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 813                              INTR_INFO_VALID_MASK)) ==
 814                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 815 }
 816
 817 static inline bool is_no_device(u32 intr_info)
 818 {
 819         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 820                              INTR_INFO_VALID_MASK)) ==
 821                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 822 }
 823
 824 static inline bool is_invalid_opcode(u32 intr_info)
 825 {
 826         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 827                              INTR_INFO_VALID_MASK)) ==
 828                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 829 }
 830
 831 static inline bool is_external_interrupt(u32 intr_info)
 832 {
 833         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 834                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 835 }
 836
 837 static inline bool is_machine_check(u32 intr_info)
 838 {
 839         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 840                              INTR_INFO_VALID_MASK)) ==
 841                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 842 }
 843
 844 static inline bool cpu_has_vmx_msr_bitmap(void)
 845 {
 846         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 847 }
 848
 849 static inline bool cpu_has_vmx_tpr_shadow(void)
 850 {
 851         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 852 }
 853
 854 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 855 {
 856         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 857 }
 858
 859 static inline bool cpu_has_secondary_exec_ctrls(void)
 860 {
 861         return vmcs_config.cpu_based_exec_ctrl &
 862                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 863 }
 864
 865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 866 {
 867         return vmcs_config.cpu_based_2nd_exec_ctrl &
 868                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 869 }
 870
 871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 872 {
 873         return vmcs_config.cpu_based_2nd_exec_ctrl &
 874                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 875 }
 876
 877 static inline bool cpu_has_vmx_apic_register_virt(void)
 878 {
 879         return vmcs_config.cpu_based_2nd_exec_ctrl &
 880                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 881 }
 882
 883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 884 {
 885         return vmcs_config.cpu_based_2nd_exec_ctrl &
 886                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 887 }
 888
 889 static inline bool cpu_has_vmx_posted_intr(void)
 890 {
 891         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 892 }
 893
 894 static inline bool cpu_has_vmx_apicv(void)
 895 {
 896         return cpu_has_vmx_apic_register_virt() &&
 897                 cpu_has_vmx_virtual_intr_delivery() &&
 898                 cpu_has_vmx_posted_intr();
 899 }
 900
 901 static inline bool cpu_has_vmx_flexpriority(void)
 902 {
 903         return cpu_has_vmx_tpr_shadow() &&
 904                 cpu_has_vmx_virtualize_apic_accesses();
 905 }
 906
 907 static inline bool cpu_has_vmx_ept_execute_only(void)
 908 {
 909         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 910 }
 911
 912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 913 {
 914         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 915 }
 916
 917 static inline bool cpu_has_vmx_eptp_writeback(void)
 918 {
 919         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 920 }
 921
 922 static inline bool cpu_has_vmx_ept_2m_page(void)
 923 {
 924         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 925 }
 926
 927 static inline bool cpu_has_vmx_ept_1g_page(void)
 928 {
 929         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 930 }
 931
 932 static inline bool cpu_has_vmx_ept_4levels(void)
 933 {
 934         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 935 }
 936
 937 static inline bool cpu_has_vmx_ept_ad_bits(void)
 938 {
 939         return vmx_capability.ept & VMX_EPT_AD_BIT;
 940 }
 941
 942 static inline bool cpu_has_vmx_invept_context(void)
 943 {
 944         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 945 }
 946
 947 static inline bool cpu_has_vmx_invept_global(void)
 948 {
 949         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 950 }
 951
 952 static inline bool cpu_has_vmx_invvpid_single(void)
 953 {
 954         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_invvpid_global(void)
 958 {
 959         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_ept(void)
 963 {
 964         return vmcs_config.cpu_based_2nd_exec_ctrl &
 965                 SECONDARY_EXEC_ENABLE_EPT;
 966 }
 967
 968 static inline bool cpu_has_vmx_unrestricted_guest(void)
 969 {
 970         return vmcs_config.cpu_based_2nd_exec_ctrl &
 971                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 972 }
 973
 974 static inline bool cpu_has_vmx_ple(void)
 975 {
 976         return vmcs_config.cpu_based_2nd_exec_ctrl &
 977                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 978 }
 979
 980 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 981 {
 982         return flexpriority_enabled && irqchip_in_kernel(kvm);
 983 }
 984
 985 static inline bool cpu_has_vmx_vpid(void)
 986 {
 987         return vmcs_config.cpu_based_2nd_exec_ctrl &
 988                 SECONDARY_EXEC_ENABLE_VPID;
 989 }
 990
 991 static inline bool cpu_has_vmx_rdtscp(void)
 992 {
 993         return vmcs_config.cpu_based_2nd_exec_ctrl &
 994                 SECONDARY_EXEC_RDTSCP;
 995 }
 996
 997 static inline bool cpu_has_vmx_invpcid(void)
 998 {
 999         return vmcs_config.cpu_based_2nd_exec_ctrl &
1000                 SECONDARY_EXEC_ENABLE_INVPCID;
1001 }
1002
1003 static inline bool cpu_has_virtual_nmis(void)
1004 {
1005         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006 }
1007
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1009 {
1010         return vmcs_config.cpu_based_2nd_exec_ctrl &
1011                 SECONDARY_EXEC_WBINVD_EXITING;
1012 }
1013
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1015 {
1016         u64 vmx_msr;
1017         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018         /* check if the cpu supports writing r/o exit information fields */
1019         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020                 return false;
1021
1022         return vmcs_config.cpu_based_2nd_exec_ctrl &
1023                 SECONDARY_EXEC_SHADOW_VMCS;
1024 }
1025
1026 static inline bool report_flexpriority(void)
1027 {
1028         return flexpriority_enabled;
1029 }
1030
1031 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032 {
1033         return vmcs12->cpu_based_vm_exec_control & bit;
1034 }
1035
1036 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037 {
1038         return (vmcs12->cpu_based_vm_exec_control &
1039                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040                 (vmcs12->secondary_vm_exec_control & bit);
1041 }
1042
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1044 {
1045         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046 }
1047
1048 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049 {
1050         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051 }
1052
1053 static inline bool is_exception(u32 intr_info)
1054 {
1055         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057 }
1058
1059 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
1060 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061                         struct vmcs12 *vmcs12,
1062                         u32 reason, unsigned long qualification);
1063
1064 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1065 {
1066         int i;
1067
1068         for (i = 0; i < vmx->nmsrs; ++i)
1069                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1070                         return i;
1071         return -1;
1072 }
1073
1074 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075 {
1076     struct {
1077         u64 vpid : 16;
1078         u64 rsvd : 48;
1079         u64 gva;
1080     } operand = { vpid, 0, gva };
1081
1082     asm volatile (__ex(ASM_VMX_INVVPID)
1083                   /* CF==1 or ZF==1 --> rc = -1 */
1084                   "; ja 1f ; ud2 ; 1:"
1085                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1086 }
1087
1088 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089 {
1090         struct {
1091                 u64 eptp, gpa;
1092         } operand = {eptp, gpa};
1093
1094         asm volatile (__ex(ASM_VMX_INVEPT)
1095                         /* CF==1 or ZF==1 --> rc = -1 */
1096                         "; ja 1f ; ud2 ; 1:\n"
1097                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1098 }
1099
1100 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1101 {
1102         int i;
1103
1104         i = __find_msr_index(vmx, msr);
1105         if (i >= 0)
1106                 return &vmx->guest_msrs[i];
1107         return NULL;
1108 }
1109
1110 static void vmcs_clear(struct vmcs *vmcs)
1111 {
1112         u64 phys_addr = __pa(vmcs);
1113         u8 error;
1114
1115         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1116                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1117                       : "cc", "memory");
1118         if (error)
1119                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120                        vmcs, phys_addr);
1121 }
1122
1123 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124 {
1125         vmcs_clear(loaded_vmcs->vmcs);
1126         loaded_vmcs->cpu = -1;
1127         loaded_vmcs->launched = 0;
1128 }
1129
1130 static void vmcs_load(struct vmcs *vmcs)
1131 {
1132         u64 phys_addr = __pa(vmcs);
1133         u8 error;
1134
1135         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1136                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1137                         : "cc", "memory");
1138         if (error)
1139                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1140                        vmcs, phys_addr);
1141 }
1142
1143 #ifdef CONFIG_KEXEC
1144 /*
1145  * This bitmap is used to indicate whether the vmclear
1146  * operation is enabled on all cpus. All disabled by
1147  * default.
1148  */
1149 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151 static inline void crash_enable_local_vmclear(int cpu)
1152 {
1153         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154 }
1155
1156 static inline void crash_disable_local_vmclear(int cpu)
1157 {
1158         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159 }
1160
1161 static inline int crash_local_vmclear_enabled(int cpu)
1162 {
1163         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164 }
1165
1166 static void crash_vmclear_local_loaded_vmcss(void)
1167 {
1168         int cpu = raw_smp_processor_id();
1169         struct loaded_vmcs *v;
1170
1171         if (!crash_local_vmclear_enabled(cpu))
1172                 return;
1173
1174         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175                             loaded_vmcss_on_cpu_link)
1176                 vmcs_clear(v->vmcs);
1177 }
1178 #else
1179 static inline void crash_enable_local_vmclear(int cpu) { }
1180 static inline void crash_disable_local_vmclear(int cpu) { }
1181 #endif /* CONFIG_KEXEC */
1182
1183 static void __loaded_vmcs_clear(void *arg)
1184 {
1185         struct loaded_vmcs *loaded_vmcs = arg;
1186         int cpu = raw_smp_processor_id();
1187
1188         if (loaded_vmcs->cpu != cpu)
1189                 return; /* vcpu migration can race with cpu offline */
1190         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1191                 per_cpu(current_vmcs, cpu) = NULL;
1192         crash_disable_local_vmclear(cpu);
1193         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1194
1195         /*
1196          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197          * is before setting loaded_vmcs->vcpu to -1 which is done in
1198          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199          * then adds the vmcs into percpu list before it is deleted.
1200          */
1201         smp_wmb();
1202
1203         loaded_vmcs_init(loaded_vmcs);
1204         crash_enable_local_vmclear(cpu);
1205 }
1206
1207 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1208 {
1209         int cpu = loaded_vmcs->cpu;
1210
1211         if (cpu != -1)
1212                 smp_call_function_single(cpu,
1213                          __loaded_vmcs_clear, loaded_vmcs, 1);
1214 }
1215
1216 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1217 {
1218         if (vmx->vpid == 0)
1219                 return;
1220
1221         if (cpu_has_vmx_invvpid_single())
1222                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1223 }
1224
1225 static inline void vpid_sync_vcpu_global(void)
1226 {
1227         if (cpu_has_vmx_invvpid_global())
1228                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229 }
1230
1231 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232 {
1233         if (cpu_has_vmx_invvpid_single())
1234                 vpid_sync_vcpu_single(vmx);
1235         else
1236                 vpid_sync_vcpu_global();
1237 }
1238
1239 static inline void ept_sync_global(void)
1240 {
1241         if (cpu_has_vmx_invept_global())
1242                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243 }
1244
1245 static inline void ept_sync_context(u64 eptp)
1246 {
1247         if (enable_ept) {
1248                 if (cpu_has_vmx_invept_context())
1249                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250                 else
1251                         ept_sync_global();
1252         }
1253 }
1254
1255 static __always_inline unsigned long vmcs_readl(unsigned long field)
1256 {
1257         unsigned long value;
1258
1259         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260                       : "=a"(value) : "d"(field) : "cc");
1261         return value;
1262 }
1263
1264 static __always_inline u16 vmcs_read16(unsigned long field)
1265 {
1266         return vmcs_readl(field);
1267 }
1268
1269 static __always_inline u32 vmcs_read32(unsigned long field)
1270 {
1271         return vmcs_readl(field);
1272 }
1273
1274 static __always_inline u64 vmcs_read64(unsigned long field)
1275 {
1276 #ifdef CONFIG_X86_64
1277         return vmcs_readl(field);
1278 #else
1279         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280 #endif
1281 }
1282
1283 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284 {
1285         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287         dump_stack();
1288 }
1289
1290 static void vmcs_writel(unsigned long field, unsigned long value)
1291 {
1292         u8 error;
1293
1294         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1295                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1296         if (unlikely(error))
1297                 vmwrite_error(field, value);
1298 }
1299
1300 static void vmcs_write16(unsigned long field, u16 value)
1301 {
1302         vmcs_writel(field, value);
1303 }
1304
1305 static void vmcs_write32(unsigned long field, u32 value)
1306 {
1307         vmcs_writel(field, value);
1308 }
1309
1310 static void vmcs_write64(unsigned long field, u64 value)
1311 {
1312         vmcs_writel(field, value);
1313 #ifndef CONFIG_X86_64
1314         asm volatile ("");
1315         vmcs_writel(field+1, value >> 32);
1316 #endif
1317 }
1318
1319 static void vmcs_clear_bits(unsigned long field, u32 mask)
1320 {
1321         vmcs_writel(field, vmcs_readl(field) & ~mask);
1322 }
1323
1324 static void vmcs_set_bits(unsigned long field, u32 mask)
1325 {
1326         vmcs_writel(field, vmcs_readl(field) | mask);
1327 }
1328
1329 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330 {
1331         vmx->segment_cache.bitmask = 0;
1332 }
1333
1334 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335                                        unsigned field)
1336 {
1337         bool ret;
1338         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342                 vmx->segment_cache.bitmask = 0;
1343         }
1344         ret = vmx->segment_cache.bitmask & mask;
1345         vmx->segment_cache.bitmask |= mask;
1346         return ret;
1347 }
1348
1349 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350 {
1351         u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355         return *p;
1356 }
1357
1358 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359 {
1360         ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364         return *p;
1365 }
1366
1367 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368 {
1369         u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373         return *p;
1374 }
1375
1376 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377 {
1378         u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382         return *p;
1383 }
1384
1385 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386 {
1387         u32 eb;
1388
1389         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391         if ((vcpu->guest_debug &
1392              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394                 eb |= 1u << BP_VECTOR;
1395         if (to_vmx(vcpu)->rmode.vm86_active)
1396                 eb = ~0;
1397         if (enable_ept)
1398                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1399         if (vcpu->fpu_active)
1400                 eb &= ~(1u << NM_VECTOR);
1401
1402         /* When we are running a nested L2 guest and L1 specified for it a
1403          * certain exception bitmap, we must trap the same exceptions and pass
1404          * them to L1. When running L2, we will only handle the exceptions
1405          * specified above if L1 did not want them.
1406          */
1407         if (is_guest_mode(vcpu))
1408                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
1410         vmcs_write32(EXCEPTION_BITMAP, eb);
1411 }
1412
1413 static void clear_atomic_switch_msr_special(unsigned long entry,
1414                 unsigned long exit)
1415 {
1416         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418 }
1419
1420 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421 {
1422         unsigned i;
1423         struct msr_autoload *m = &vmx->msr_autoload;
1424
1425         switch (msr) {
1426         case MSR_EFER:
1427                 if (cpu_has_load_ia32_efer) {
1428                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429                                         VM_EXIT_LOAD_IA32_EFER);
1430                         return;
1431                 }
1432                 break;
1433         case MSR_CORE_PERF_GLOBAL_CTRL:
1434                 if (cpu_has_load_perf_global_ctrl) {
1435                         clear_atomic_switch_msr_special(
1436                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438                         return;
1439                 }
1440                 break;
1441         }
1442
1443         for (i = 0; i < m->nr; ++i)
1444                 if (m->guest[i].index == msr)
1445                         break;
1446
1447         if (i == m->nr)
1448                 return;
1449         --m->nr;
1450         m->guest[i] = m->guest[m->nr];
1451         m->host[i] = m->host[m->nr];
1452         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454 }
1455
1456 static void add_atomic_switch_msr_special(unsigned long entry,
1457                 unsigned long exit, unsigned long guest_val_vmcs,
1458                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459 {
1460         vmcs_write64(guest_val_vmcs, guest_val);
1461         vmcs_write64(host_val_vmcs, host_val);
1462         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464 }
1465
1466 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467                                   u64 guest_val, u64 host_val)
1468 {
1469         unsigned i;
1470         struct msr_autoload *m = &vmx->msr_autoload;
1471
1472         switch (msr) {
1473         case MSR_EFER:
1474                 if (cpu_has_load_ia32_efer) {
1475                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476                                         VM_EXIT_LOAD_IA32_EFER,
1477                                         GUEST_IA32_EFER,
1478                                         HOST_IA32_EFER,
1479                                         guest_val, host_val);
1480                         return;
1481                 }
1482                 break;
1483         case MSR_CORE_PERF_GLOBAL_CTRL:
1484                 if (cpu_has_load_perf_global_ctrl) {
1485                         add_atomic_switch_msr_special(
1486                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1489                                         HOST_IA32_PERF_GLOBAL_CTRL,
1490                                         guest_val, host_val);
1491                         return;
1492                 }
1493                 break;
1494         }
1495
1496         for (i = 0; i < m->nr; ++i)
1497                 if (m->guest[i].index == msr)
1498                         break;
1499
1500         if (i == NR_AUTOLOAD_MSRS) {
1501                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502                                 "Can't add msr %x\n", msr);
1503                 return;
1504         } else if (i == m->nr) {
1505                 ++m->nr;
1506                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508         }
1509
1510         m->guest[i].index = msr;
1511         m->guest[i].value = guest_val;
1512         m->host[i].index = msr;
1513         m->host[i].value = host_val;
1514 }
1515
1516 static void reload_tss(void)
1517 {
1518         /*
1519          * VT restores TR but not its size.  Useless.
1520          */
1521         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1522         struct desc_struct *descs;
1523
1524         descs = (void *)gdt->address;
1525         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526         load_TR_desc();
1527 }
1528
1529 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1530 {
1531         u64 guest_efer;
1532         u64 ignore_bits;
1533
1534         guest_efer = vmx->vcpu.arch.efer;
1535
1536         /*
1537          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1538          * outside long mode
1539          */
1540         ignore_bits = EFER_NX | EFER_SCE;
1541 #ifdef CONFIG_X86_64
1542         ignore_bits |= EFER_LMA | EFER_LME;
1543         /* SCE is meaningful only in long mode on Intel */
1544         if (guest_efer & EFER_LMA)
1545                 ignore_bits &= ~(u64)EFER_SCE;
1546 #endif
1547         guest_efer &= ~ignore_bits;
1548         guest_efer |= host_efer & ignore_bits;
1549         vmx->guest_msrs[efer_offset].data = guest_efer;
1550         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1551
1552         clear_atomic_switch_msr(vmx, MSR_EFER);
1553         /* On ept, can't emulate nx, and must switch nx atomically */
1554         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555                 guest_efer = vmx->vcpu.arch.efer;
1556                 if (!(guest_efer & EFER_LMA))
1557                         guest_efer &= ~EFER_LME;
1558                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559                 return false;
1560         }
1561
1562         return true;
1563 }
1564
1565 static unsigned long segment_base(u16 selector)
1566 {
1567         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1568         struct desc_struct *d;
1569         unsigned long table_base;
1570         unsigned long v;
1571
1572         if (!(selector & ~3))
1573                 return 0;
1574
1575         table_base = gdt->address;
1576
1577         if (selector & 4) {           /* from ldt */
1578                 u16 ldt_selector = kvm_read_ldt();
1579
1580                 if (!(ldt_selector & ~3))
1581                         return 0;
1582
1583                 table_base = segment_base(ldt_selector);
1584         }
1585         d = (struct desc_struct *)(table_base + (selector & ~7));
1586         v = get_desc_base(d);
1587 #ifdef CONFIG_X86_64
1588        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590 #endif
1591         return v;
1592 }
1593
1594 static inline unsigned long kvm_read_tr_base(void)
1595 {
1596         u16 tr;
1597         asm("str %0" : "=g"(tr));
1598         return segment_base(tr);
1599 }
1600
1601 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1602 {
1603         struct vcpu_vmx *vmx = to_vmx(vcpu);
1604         int i;
1605
1606         if (vmx->host_state.loaded)
1607                 return;
1608
1609         vmx->host_state.loaded = 1;
1610         /*
1611          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1612          * allow segment selectors with cpl > 0 or ti == 1.
1613          */
1614         vmx->host_state.ldt_sel = kvm_read_ldt();
1615         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1616         savesegment(fs, vmx->host_state.fs_sel);
1617         if (!(vmx->host_state.fs_sel & 7)) {
1618                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1619                 vmx->host_state.fs_reload_needed = 0;
1620         } else {
1621                 vmcs_write16(HOST_FS_SELECTOR, 0);
1622                 vmx->host_state.fs_reload_needed = 1;
1623         }
1624         savesegment(gs, vmx->host_state.gs_sel);
1625         if (!(vmx->host_state.gs_sel & 7))
1626                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1627         else {
1628                 vmcs_write16(HOST_GS_SELECTOR, 0);
1629                 vmx->host_state.gs_ldt_reload_needed = 1;
1630         }
1631
1632 #ifdef CONFIG_X86_64
1633         savesegment(ds, vmx->host_state.ds_sel);
1634         savesegment(es, vmx->host_state.es_sel);
1635 #endif
1636
1637 #ifdef CONFIG_X86_64
1638         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640 #else
1641         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1643 #endif
1644
1645 #ifdef CONFIG_X86_64
1646         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647         if (is_long_mode(&vmx->vcpu))
1648                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1649 #endif
1650         for (i = 0; i < vmx->save_nmsrs; ++i)
1651                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1652                                    vmx->guest_msrs[i].data,
1653                                    vmx->guest_msrs[i].mask);
1654 }
1655
1656 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1657 {
1658         if (!vmx->host_state.loaded)
1659                 return;
1660
1661         ++vmx->vcpu.stat.host_state_reload;
1662         vmx->host_state.loaded = 0;
1663 #ifdef CONFIG_X86_64
1664         if (is_long_mode(&vmx->vcpu))
1665                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666 #endif
1667         if (vmx->host_state.gs_ldt_reload_needed) {
1668                 kvm_load_ldt(vmx->host_state.ldt_sel);
1669 #ifdef CONFIG_X86_64
1670                 load_gs_index(vmx->host_state.gs_sel);
1671 #else
1672                 loadsegment(gs, vmx->host_state.gs_sel);
1673 #endif
1674         }
1675         if (vmx->host_state.fs_reload_needed)
1676                 loadsegment(fs, vmx->host_state.fs_sel);
1677 #ifdef CONFIG_X86_64
1678         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679                 loadsegment(ds, vmx->host_state.ds_sel);
1680                 loadsegment(es, vmx->host_state.es_sel);
1681         }
1682 #endif
1683         reload_tss();
1684 #ifdef CONFIG_X86_64
1685         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1686 #endif
1687         /*
1688          * If the FPU is not active (through the host task or
1689          * the guest vcpu), then restore the cr0.TS bit.
1690          */
1691         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692                 stts();
1693         load_gdt(&__get_cpu_var(host_gdt));
1694 }
1695
1696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697 {
1698         preempt_disable();
1699         __vmx_load_host_state(vmx);
1700         preempt_enable();
1701 }
1702
1703 /*
1704  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705  * vcpu mutex is already taken.
1706  */
1707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1708 {
1709         struct vcpu_vmx *vmx = to_vmx(vcpu);
1710         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1711
1712         if (!vmm_exclusive)
1713                 kvm_cpu_vmxon(phys_addr);
1714         else if (vmx->loaded_vmcs->cpu != cpu)
1715                 loaded_vmcs_clear(vmx->loaded_vmcs);
1716
1717         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719                 vmcs_load(vmx->loaded_vmcs->vmcs);
1720         }
1721
1722         if (vmx->loaded_vmcs->cpu != cpu) {
1723                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1724                 unsigned long sysenter_esp;
1725
1726                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1727                 local_irq_disable();
1728                 crash_disable_local_vmclear(cpu);
1729
1730                 /*
1731                  * Read loaded_vmcs->cpu should be before fetching
1732                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733                  * See the comments in __loaded_vmcs_clear().
1734                  */
1735                 smp_rmb();
1736
1737                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1739                 crash_enable_local_vmclear(cpu);
1740                 local_irq_enable();
1741
1742                 /*
1743                  * Linux uses per-cpu TSS and GDT, so set these when switching
1744                  * processors.
1745                  */
1746                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1747                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1748
1749                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1751                 vmx->loaded_vmcs->cpu = cpu;
1752         }
1753 }
1754
1755 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756 {
1757         __vmx_load_host_state(to_vmx(vcpu));
1758         if (!vmm_exclusive) {
1759                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760                 vcpu->cpu = -1;
1761                 kvm_cpu_vmxoff();
1762         }
1763 }
1764
1765 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766 {
1767         ulong cr0;
1768
1769         if (vcpu->fpu_active)
1770                 return;
1771         vcpu->fpu_active = 1;
1772         cr0 = vmcs_readl(GUEST_CR0);
1773         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775         vmcs_writel(GUEST_CR0, cr0);
1776         update_exception_bitmap(vcpu);
1777         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1778         if (is_guest_mode(vcpu))
1779                 vcpu->arch.cr0_guest_owned_bits &=
1780                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1781         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1782 }
1783
1784 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
1786 /*
1787  * Return the cr0 value that a nested guest would read. This is a combination
1788  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789  * its hypervisor (cr0_read_shadow).
1790  */
1791 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792 {
1793         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795 }
1796 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797 {
1798         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800 }
1801
1802 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803 {
1804         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805          * set this *before* calling this function.
1806          */
1807         vmx_decache_cr0_guest_bits(vcpu);
1808         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1809         update_exception_bitmap(vcpu);
1810         vcpu->arch.cr0_guest_owned_bits = 0;
1811         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1812         if (is_guest_mode(vcpu)) {
1813                 /*
1814                  * L1's specified read shadow might not contain the TS bit,
1815                  * so now that we turned on shadowing of this bit, we need to
1816                  * set this bit of the shadow. Like in nested_vmx_run we need
1817                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818                  * up-to-date here because we just decached cr0.TS (and we'll
1819                  * only update vmcs12->guest_cr0 on nested exit).
1820                  */
1821                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823                         (vcpu->arch.cr0 & X86_CR0_TS);
1824                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825         } else
1826                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1827 }
1828
1829 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830 {
1831         unsigned long rflags, save_rflags;
1832
1833         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835                 rflags = vmcs_readl(GUEST_RFLAGS);
1836                 if (to_vmx(vcpu)->rmode.vm86_active) {
1837                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840                 }
1841                 to_vmx(vcpu)->rflags = rflags;
1842         }
1843         return to_vmx(vcpu)->rflags;
1844 }
1845
1846 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847 {
1848         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849         to_vmx(vcpu)->rflags = rflags;
1850         if (to_vmx(vcpu)->rmode.vm86_active) {
1851                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1852                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1853         }
1854         vmcs_writel(GUEST_RFLAGS, rflags);
1855 }
1856
1857 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858 {
1859         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860         int ret = 0;
1861
1862         if (interruptibility & GUEST_INTR_STATE_STI)
1863                 ret |= KVM_X86_SHADOW_INT_STI;
1864         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1865                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1866
1867         return ret & mask;
1868 }
1869
1870 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871 {
1872         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873         u32 interruptibility = interruptibility_old;
1874
1875         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
1877         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1878                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1879         else if (mask & KVM_X86_SHADOW_INT_STI)
1880                 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882         if ((interruptibility != interruptibility_old))
1883                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884 }
1885
1886 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887 {
1888         unsigned long rip;
1889
1890         rip = kvm_rip_read(vcpu);
1891         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1892         kvm_rip_write(vcpu, rip);
1893
1894         /* skipping an emulated instruction also counts */
1895         vmx_set_interrupt_shadow(vcpu, 0);
1896 }
1897
1898 /*
1899  * KVM wants to inject page-faults which it got to the guest. This function
1900  * checks whether in a nested guest, we need to inject them to L1 or L2.
1901  */
1902 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1903 {
1904         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1905
1906         if (!(vmcs12->exception_bitmap & (1u << nr)))
1907                 return 0;
1908
1909         nested_vmx_vmexit(vcpu);
1910         return 1;
1911 }
1912
1913 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1914                                 bool has_error_code, u32 error_code,
1915                                 bool reinject)
1916 {
1917         struct vcpu_vmx *vmx = to_vmx(vcpu);
1918         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1919
1920         if (!reinject && is_guest_mode(vcpu) &&
1921             nested_vmx_check_exception(vcpu, nr))
1922                 return;
1923
1924         if (has_error_code) {
1925                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1926                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927         }
1928
1929         if (vmx->rmode.vm86_active) {
1930                 int inc_eip = 0;
1931                 if (kvm_exception_is_soft(nr))
1932                         inc_eip = vcpu->arch.event_exit_inst_len;
1933                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1934                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1935                 return;
1936         }
1937
1938         if (kvm_exception_is_soft(nr)) {
1939                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940                              vmx->vcpu.arch.event_exit_inst_len);
1941                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942         } else
1943                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1946 }
1947
1948 static bool vmx_rdtscp_supported(void)
1949 {
1950         return cpu_has_vmx_rdtscp();
1951 }
1952
1953 static bool vmx_invpcid_supported(void)
1954 {
1955         return cpu_has_vmx_invpcid() && enable_ept;
1956 }
1957
1958 /*
1959  * Swap MSR entry in host/guest MSR entry array.
1960  */
1961 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1962 {
1963         struct shared_msr_entry tmp;
1964
1965         tmp = vmx->guest_msrs[to];
1966         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967         vmx->guest_msrs[from] = tmp;
1968 }
1969
1970 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971 {
1972         unsigned long *msr_bitmap;
1973
1974         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975                 if (is_long_mode(vcpu))
1976                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977                 else
1978                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979         } else {
1980                 if (is_long_mode(vcpu))
1981                         msr_bitmap = vmx_msr_bitmap_longmode;
1982                 else
1983                         msr_bitmap = vmx_msr_bitmap_legacy;
1984         }
1985
1986         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987 }
1988
1989 /*
1990  * Set up the vmcs to automatically save and restore system
1991  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1992  * mode, as fiddling with msrs is very expensive.
1993  */
1994 static void setup_msrs(struct vcpu_vmx *vmx)
1995 {
1996         int save_nmsrs, index;
1997
1998         save_nmsrs = 0;
1999 #ifdef CONFIG_X86_64
2000         if (is_long_mode(&vmx->vcpu)) {
2001                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2002                 if (index >= 0)
2003                         move_msr_up(vmx, index, save_nmsrs++);
2004                 index = __find_msr_index(vmx, MSR_LSTAR);
2005                 if (index >= 0)
2006                         move_msr_up(vmx, index, save_nmsrs++);
2007                 index = __find_msr_index(vmx, MSR_CSTAR);
2008                 if (index >= 0)
2009                         move_msr_up(vmx, index, save_nmsrs++);
2010                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011                 if (index >= 0 && vmx->rdtscp_enabled)
2012                         move_msr_up(vmx, index, save_nmsrs++);
2013                 /*
2014                  * MSR_STAR is only needed on long mode guests, and only
2015                  * if efer.sce is enabled.
2016                  */
2017                 index = __find_msr_index(vmx, MSR_STAR);
2018                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2019                         move_msr_up(vmx, index, save_nmsrs++);
2020         }
2021 #endif
2022         index = __find_msr_index(vmx, MSR_EFER);
2023         if (index >= 0 && update_transition_efer(vmx, index))
2024                 move_msr_up(vmx, index, save_nmsrs++);
2025
2026         vmx->save_nmsrs = save_nmsrs;
2027
2028         if (cpu_has_vmx_msr_bitmap())
2029                 vmx_set_msr_bitmap(&vmx->vcpu);
2030 }
2031
2032 /*
2033  * reads and returns guest's timestamp counter "register"
2034  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2035  */
2036 static u64 guest_read_tsc(void)
2037 {
2038         u64 host_tsc, tsc_offset;
2039
2040         rdtscll(host_tsc);
2041         tsc_offset = vmcs_read64(TSC_OFFSET);
2042         return host_tsc + tsc_offset;
2043 }
2044
2045 /*
2046  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047  * counter, even if a nested guest (L2) is currently running.
2048  */
2049 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2050 {
2051         u64 tsc_offset;
2052
2053         tsc_offset = is_guest_mode(vcpu) ?
2054                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055                 vmcs_read64(TSC_OFFSET);
2056         return host_tsc + tsc_offset;
2057 }
2058
2059 /*
2060  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2061  * software catchup for faster rates on slower CPUs.
2062  */
2063 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2064 {
2065         if (!scale)
2066                 return;
2067
2068         if (user_tsc_khz > tsc_khz) {
2069                 vcpu->arch.tsc_catchup = 1;
2070                 vcpu->arch.tsc_always_catchup = 1;
2071         } else
2072                 WARN(1, "user requested TSC rate below hardware speed\n");
2073 }
2074
2075 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076 {
2077         return vmcs_read64(TSC_OFFSET);
2078 }
2079
2080 /*
2081  * writes 'offset' into guest's timestamp counter offset register
2082  */
2083 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2084 {
2085         if (is_guest_mode(vcpu)) {
2086                 /*
2087                  * We're here if L1 chose not to trap WRMSR to TSC. According
2088                  * to the spec, this should set L1's TSC; The offset that L1
2089                  * set for L2 remains unchanged, and still needs to be added
2090                  * to the newly set TSC to get L2's TSC.
2091                  */
2092                 struct vmcs12 *vmcs12;
2093                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094                 /* recalculate vmcs02.TSC_OFFSET: */
2095                 vmcs12 = get_vmcs12(vcpu);
2096                 vmcs_write64(TSC_OFFSET, offset +
2097                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098                          vmcs12->tsc_offset : 0));
2099         } else {
2100                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101                                            vmcs_read64(TSC_OFFSET), offset);
2102                 vmcs_write64(TSC_OFFSET, offset);
2103         }
2104 }
2105
2106 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2107 {
2108         u64 offset = vmcs_read64(TSC_OFFSET);
2109
2110         vmcs_write64(TSC_OFFSET, offset + adjustment);
2111         if (is_guest_mode(vcpu)) {
2112                 /* Even when running L2, the adjustment needs to apply to L1 */
2113                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2114         } else
2115                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116                                            offset + adjustment);
2117 }
2118
2119 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120 {
2121         return target_tsc - native_read_tsc();
2122 }
2123
2124 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125 {
2126         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128 }
2129
2130 /*
2131  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133  * all guests if the "nested" module option is off, and can also be disabled
2134  * for a single guest by disabling its VMX cpuid bit.
2135  */
2136 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137 {
2138         return nested && guest_cpuid_has_vmx(vcpu);
2139 }
2140
2141 /*
2142  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143  * returned for the various VMX controls MSRs when nested VMX is enabled.
2144  * The same values should also be used to verify that vmcs12 control fields are
2145  * valid during nested entry from L1 to L2.
2146  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148  * bit in the high half is on if the corresponding bit in the control field
2149  * may be on. See also vmx_control_verify().
2150  * TODO: allow these variables to be modified (downgraded) by module options
2151  * or other means.
2152  */
2153 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2158 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2159 static u32 nested_vmx_ept_caps;
2160 static __init void nested_vmx_setup_ctls_msrs(void)
2161 {
2162         /*
2163          * Note that as a general rule, the high half of the MSRs (bits in
2164          * the control fields which may be 1) should be initialized by the
2165          * intersection of the underlying hardware's MSR (i.e., features which
2166          * can be supported) and the list of features we want to expose -
2167          * because they are known to be properly supported in our code.
2168          * Also, usually, the low half of the MSRs (bits which must be 1) can
2169          * be set to 0, meaning that L1 may turn off any of these bits. The
2170          * reason is that if one of these bits is necessary, it will appear
2171          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2172          * fields of vmcs01 and vmcs02, will turn these bits off - and
2173          * nested_vmx_exit_handled() will not pass related exits to L1.
2174          * These rules have exceptions below.
2175          */
2176
2177         /* pin-based controls */
2178         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2179               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2180         /*
2181          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2182          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2183          */
2184         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2185         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2186                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2187                 PIN_BASED_VMX_PREEMPTION_TIMER;
2188         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189
2190         /*
2191          * Exit controls
2192          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2193          * 17 must be 1.
2194          */
2195         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2196                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2197         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2198         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2199         nested_vmx_exit_ctls_high &=
2200 #ifdef CONFIG_X86_64
2201                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2202 #endif
2203                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2204                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2205         if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2206             !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2207                 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2208                 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2209         }
2210         nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2211                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
2212
2213         /* entry controls */
2214         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2215                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2216         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2217         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2218         nested_vmx_entry_ctls_high &=
2219 #ifdef CONFIG_X86_64
2220                 VM_ENTRY_IA32E_MODE |
2221 #endif
2222                 VM_ENTRY_LOAD_IA32_PAT;
2223         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2224                                        VM_ENTRY_LOAD_IA32_EFER);
2225
2226         /* cpu-based controls */
2227         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2228                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2229         nested_vmx_procbased_ctls_low = 0;
2230         nested_vmx_procbased_ctls_high &=
2231                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2232                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2233                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2234                 CPU_BASED_CR3_STORE_EXITING |
2235 #ifdef CONFIG_X86_64
2236                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2237 #endif
2238                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2239                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2240                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2241                 CPU_BASED_PAUSE_EXITING |
2242                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2243         /*
2244          * We can allow some features even when not supported by the
2245          * hardware. For example, L1 can specify an MSR bitmap - and we
2246          * can use it to avoid exits to L1 - even when L0 runs L2
2247          * without MSR bitmaps.
2248          */
2249         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2250
2251         /* secondary cpu-based controls */
2252         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2253                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2254         nested_vmx_secondary_ctls_low = 0;
2255         nested_vmx_secondary_ctls_high &=
2256                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2257                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2258                 SECONDARY_EXEC_WBINVD_EXITING;
2259
2260         if (enable_ept) {
2261                 /* nested EPT: emulate EPT also to L1 */
2262                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2263                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2264                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2265                 nested_vmx_ept_caps &= vmx_capability.ept;
2266                 /*
2267                  * Since invept is completely emulated we support both global
2268                  * and context invalidation independent of what host cpu
2269                  * supports
2270                  */
2271                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2272                         VMX_EPT_EXTENT_CONTEXT_BIT;
2273         } else
2274                 nested_vmx_ept_caps = 0;
2275
2276         /* miscellaneous data */
2277         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2278         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2279                 VMX_MISC_SAVE_EFER_LMA;
2280         nested_vmx_misc_high = 0;
2281 }
2282
2283 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2284 {
2285         /*
2286          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2287          */
2288         return ((control & high) | low) == control;
2289 }
2290
2291 static inline u64 vmx_control_msr(u32 low, u32 high)
2292 {
2293         return low | ((u64)high << 32);
2294 }
2295
2296 /*
2297  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2298  * also let it use VMX-specific MSRs.
2299  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2300  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2301  * like all other MSRs).
2302  */
2303 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2304 {
2305         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2306                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2307                 /*
2308                  * According to the spec, processors which do not support VMX
2309                  * should throw a #GP(0) when VMX capability MSRs are read.
2310                  */
2311                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2312                 return 1;
2313         }
2314
2315         switch (msr_index) {
2316         case MSR_IA32_FEATURE_CONTROL:
2317                 if (nested_vmx_allowed(vcpu)) {
2318                         *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2319                         break;
2320                 }
2321                 return 0;
2322         case MSR_IA32_VMX_BASIC:
2323                 /*
2324                  * This MSR reports some information about VMX support. We
2325                  * should return information about the VMX we emulate for the
2326                  * guest, and the VMCS structure we give it - not about the
2327                  * VMX support of the underlying hardware.
2328                  */
2329                 *pdata = VMCS12_REVISION |
2330                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2331                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2332                 break;
2333         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2334         case MSR_IA32_VMX_PINBASED_CTLS:
2335                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2336                                         nested_vmx_pinbased_ctls_high);
2337                 break;
2338         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2339         case MSR_IA32_VMX_PROCBASED_CTLS:
2340                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2341                                         nested_vmx_procbased_ctls_high);
2342                 break;
2343         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2344         case MSR_IA32_VMX_EXIT_CTLS:
2345                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2346                                         nested_vmx_exit_ctls_high);
2347                 break;
2348         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2349         case MSR_IA32_VMX_ENTRY_CTLS:
2350                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2351                                         nested_vmx_entry_ctls_high);
2352                 break;
2353         case MSR_IA32_VMX_MISC:
2354                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2355                                          nested_vmx_misc_high);
2356                 break;
2357         /*
2358          * These MSRs specify bits which the guest must keep fixed (on or off)
2359          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2360          * We picked the standard core2 setting.
2361          */
2362 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2363 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2364         case MSR_IA32_VMX_CR0_FIXED0:
2365                 *pdata = VMXON_CR0_ALWAYSON;
2366                 break;
2367         case MSR_IA32_VMX_CR0_FIXED1:
2368                 *pdata = -1ULL;
2369                 break;
2370         case MSR_IA32_VMX_CR4_FIXED0:
2371                 *pdata = VMXON_CR4_ALWAYSON;
2372                 break;
2373         case MSR_IA32_VMX_CR4_FIXED1:
2374                 *pdata = -1ULL;
2375                 break;
2376         case MSR_IA32_VMX_VMCS_ENUM:
2377                 *pdata = 0x1f;
2378                 break;
2379         case MSR_IA32_VMX_PROCBASED_CTLS2:
2380                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2381                                         nested_vmx_secondary_ctls_high);
2382                 break;
2383         case MSR_IA32_VMX_EPT_VPID_CAP:
2384                 /* Currently, no nested vpid support */
2385                 *pdata = nested_vmx_ept_caps;
2386                 break;
2387         default:
2388                 return 0;
2389         }
2390
2391         return 1;
2392 }
2393
2394 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2395 {
2396         u32 msr_index = msr_info->index;
2397         u64 data = msr_info->data;
2398         bool host_initialized = msr_info->host_initiated;
2399
2400         if (!nested_vmx_allowed(vcpu))
2401                 return 0;
2402
2403         if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2404                 if (!host_initialized &&
2405                                 to_vmx(vcpu)->nested.msr_ia32_feature_control
2406                                 & FEATURE_CONTROL_LOCKED)
2407                         return 0;
2408                 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
2409                 return 1;
2410         }
2411
2412         /*
2413          * No need to treat VMX capability MSRs specially: If we don't handle
2414          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2415          */
2416         return 0;
2417 }
2418
2419 /*
2420  * Reads an msr value (of 'msr_index') into 'pdata'.
2421  * Returns 0 on success, non-0 otherwise.
2422  * Assumes vcpu_load() was already called.
2423  */
2424 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2425 {
2426         u64 data;
2427         struct shared_msr_entry *msr;
2428
2429         if (!pdata) {
2430                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2431                 return -EINVAL;
2432         }
2433
2434         switch (msr_index) {
2435 #ifdef CONFIG_X86_64
2436         case MSR_FS_BASE:
2437                 data = vmcs_readl(GUEST_FS_BASE);
2438                 break;
2439         case MSR_GS_BASE:
2440                 data = vmcs_readl(GUEST_GS_BASE);
2441                 break;
2442         case MSR_KERNEL_GS_BASE:
2443                 vmx_load_host_state(to_vmx(vcpu));
2444                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2445                 break;
2446 #endif
2447         case MSR_EFER:
2448                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2449         case MSR_IA32_TSC:
2450                 data = guest_read_tsc();
2451                 break;
2452         case MSR_IA32_SYSENTER_CS:
2453                 data = vmcs_read32(GUEST_SYSENTER_CS);
2454                 break;
2455         case MSR_IA32_SYSENTER_EIP:
2456                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2457                 break;
2458         case MSR_IA32_SYSENTER_ESP:
2459                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2460                 break;
2461         case MSR_TSC_AUX:
2462                 if (!to_vmx(vcpu)->rdtscp_enabled)
2463                         return 1;
2464                 /* Otherwise falls through */
2465         default:
2466                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2467                         return 0;
2468                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2469                 if (msr) {
2470                         data = msr->data;
2471                         break;
2472                 }
2473                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2474         }
2475
2476         *pdata = data;
2477         return 0;
2478 }
2479
2480 /*
2481  * Writes msr value into into the appropriate "register".
2482  * Returns 0 on success, non-0 otherwise.
2483  * Assumes vcpu_load() was already called.
2484  */
2485 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2486 {
2487         struct vcpu_vmx *vmx = to_vmx(vcpu);
2488         struct shared_msr_entry *msr;
2489         int ret = 0;
2490         u32 msr_index = msr_info->index;
2491         u64 data = msr_info->data;
2492
2493         switch (msr_index) {
2494         case MSR_EFER:
2495                 ret = kvm_set_msr_common(vcpu, msr_info);
2496                 break;
2497 #ifdef CONFIG_X86_64
2498         case MSR_FS_BASE:
2499                 vmx_segment_cache_clear(vmx);
2500                 vmcs_writel(GUEST_FS_BASE, data);
2501                 break;
2502         case MSR_GS_BASE:
2503                 vmx_segment_cache_clear(vmx);
2504                 vmcs_writel(GUEST_GS_BASE, data);
2505                 break;
2506         case MSR_KERNEL_GS_BASE:
2507                 vmx_load_host_state(vmx);
2508                 vmx->msr_guest_kernel_gs_base = data;
2509                 break;
2510 #endif
2511         case MSR_IA32_SYSENTER_CS:
2512                 vmcs_write32(GUEST_SYSENTER_CS, data);
2513                 break;
2514         case MSR_IA32_SYSENTER_EIP:
2515                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2516                 break;
2517         case MSR_IA32_SYSENTER_ESP:
2518                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2519                 break;
2520         case MSR_IA32_TSC:
2521                 kvm_write_tsc(vcpu, msr_info);
2522                 break;
2523         case MSR_IA32_CR_PAT:
2524                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2525                         vmcs_write64(GUEST_IA32_PAT, data);
2526                         vcpu->arch.pat = data;
2527                         break;
2528                 }
2529                 ret = kvm_set_msr_common(vcpu, msr_info);
2530                 break;
2531         case MSR_IA32_TSC_ADJUST:
2532                 ret = kvm_set_msr_common(vcpu, msr_info);
2533                 break;
2534         case MSR_TSC_AUX:
2535                 if (!vmx->rdtscp_enabled)
2536                         return 1;
2537                 /* Check reserved bit, higher 32 bits should be zero */
2538                 if ((data >> 32) != 0)
2539                         return 1;
2540                 /* Otherwise falls through */
2541         default:
2542                 if (vmx_set_vmx_msr(vcpu, msr_info))
2543                         break;
2544                 msr = find_msr_entry(vmx, msr_index);
2545                 if (msr) {
2546                         msr->data = data;
2547                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2548                                 preempt_disable();
2549                                 kvm_set_shared_msr(msr->index, msr->data,
2550                                                    msr->mask);
2551                                 preempt_enable();
2552                         }
2553                         break;
2554                 }
2555                 ret = kvm_set_msr_common(vcpu, msr_info);
2556         }
2557
2558         return ret;
2559 }
2560
2561 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2562 {
2563         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2564         switch (reg) {
2565         case VCPU_REGS_RSP:
2566                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2567                 break;
2568         case VCPU_REGS_RIP:
2569                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2570                 break;
2571         case VCPU_EXREG_PDPTR:
2572                 if (enable_ept)
2573                         ept_save_pdptrs(vcpu);
2574                 break;
2575         default:
2576                 break;
2577         }
2578 }
2579
2580 static __init int cpu_has_kvm_support(void)
2581 {
2582         return cpu_has_vmx();
2583 }
2584
2585 static __init int vmx_disabled_by_bios(void)
2586 {
2587         u64 msr;
2588
2589         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2590         if (msr & FEATURE_CONTROL_LOCKED) {
2591                 /* launched w/ TXT and VMX disabled */
2592                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2593                         && tboot_enabled())
2594                         return 1;
2595                 /* launched w/o TXT and VMX only enabled w/ TXT */
2596                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2597                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2598                         && !tboot_enabled()) {
2599                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2600                                 "activate TXT before enabling KVM\n");
2601                         return 1;
2602                 }
2603                 /* launched w/o TXT and VMX disabled */
2604                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2605                         && !tboot_enabled())
2606                         return 1;
2607         }
2608
2609         return 0;
2610 }
2611
2612 static void kvm_cpu_vmxon(u64 addr)
2613 {
2614         asm volatile (ASM_VMX_VMXON_RAX
2615                         : : "a"(&addr), "m"(addr)
2616                         : "memory", "cc");
2617 }
2618
2619 static int hardware_enable(void *garbage)
2620 {
2621         int cpu = raw_smp_processor_id();
2622         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2623         u64 old, test_bits;
2624
2625         if (read_cr4() & X86_CR4_VMXE)
2626                 return -EBUSY;
2627
2628         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2629
2630         /*
2631          * Now we can enable the vmclear operation in kdump
2632          * since the loaded_vmcss_on_cpu list on this cpu
2633          * has been initialized.
2634          *
2635          * Though the cpu is not in VMX operation now, there
2636          * is no problem to enable the vmclear operation
2637          * for the loaded_vmcss_on_cpu list is empty!
2638          */
2639         crash_enable_local_vmclear(cpu);
2640
2641         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2642
2643         test_bits = FEATURE_CONTROL_LOCKED;
2644         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2645         if (tboot_enabled())
2646                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2647
2648         if ((old & test_bits) != test_bits) {
2649                 /* enable and lock */
2650                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2651         }
2652         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2653
2654         if (vmm_exclusive) {
2655                 kvm_cpu_vmxon(phys_addr);
2656                 ept_sync_global();
2657         }
2658
2659         native_store_gdt(&__get_cpu_var(host_gdt));
2660
2661         return 0;
2662 }
2663
2664 static void vmclear_local_loaded_vmcss(void)
2665 {
2666         int cpu = raw_smp_processor_id();
2667         struct loaded_vmcs *v, *n;
2668
2669         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2670                                  loaded_vmcss_on_cpu_link)
2671                 __loaded_vmcs_clear(v);
2672 }
2673
2674
2675 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2676  * tricks.
2677  */
2678 static void kvm_cpu_vmxoff(void)
2679 {
2680         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2681 }
2682
2683 static void hardware_disable(void *garbage)
2684 {
2685         if (vmm_exclusive) {
2686                 vmclear_local_loaded_vmcss();
2687                 kvm_cpu_vmxoff();
2688         }
2689         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2690 }
2691
2692 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2693                                       u32 msr, u32 *result)
2694 {
2695         u32 vmx_msr_low, vmx_msr_high;
2696         u32 ctl = ctl_min | ctl_opt;
2697
2698         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2699
2700         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2701         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2702
2703         /* Ensure minimum (required) set of control bits are supported. */
2704         if (ctl_min & ~ctl)
2705                 return -EIO;
2706
2707         *result = ctl;
2708         return 0;
2709 }
2710
2711 static __init bool allow_1_setting(u32 msr, u32 ctl)
2712 {
2713         u32 vmx_msr_low, vmx_msr_high;
2714
2715         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2716         return vmx_msr_high & ctl;
2717 }
2718
2719 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2720 {
2721         u32 vmx_msr_low, vmx_msr_high;
2722         u32 min, opt, min2, opt2;
2723         u32 _pin_based_exec_control = 0;
2724         u32 _cpu_based_exec_control = 0;
2725         u32 _cpu_based_2nd_exec_control = 0;
2726         u32 _vmexit_control = 0;
2727         u32 _vmentry_control = 0;
2728
2729         min = CPU_BASED_HLT_EXITING |
2730 #ifdef CONFIG_X86_64
2731               CPU_BASED_CR8_LOAD_EXITING |
2732               CPU_BASED_CR8_STORE_EXITING |
2733 #endif
2734               CPU_BASED_CR3_LOAD_EXITING |
2735               CPU_BASED_CR3_STORE_EXITING |
2736               CPU_BASED_USE_IO_BITMAPS |
2737               CPU_BASED_MOV_DR_EXITING |
2738               CPU_BASED_USE_TSC_OFFSETING |
2739               CPU_BASED_MWAIT_EXITING |
2740               CPU_BASED_MONITOR_EXITING |
2741               CPU_BASED_INVLPG_EXITING |
2742               CPU_BASED_RDPMC_EXITING;
2743
2744         opt = CPU_BASED_TPR_SHADOW |
2745               CPU_BASED_USE_MSR_BITMAPS |
2746               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2747         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2748                                 &_cpu_based_exec_control) < 0)
2749                 return -EIO;
2750 #ifdef CONFIG_X86_64
2751         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2752                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2753                                            ~CPU_BASED_CR8_STORE_EXITING;
2754 #endif
2755         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2756                 min2 = 0;
2757                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2758                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2759                         SECONDARY_EXEC_WBINVD_EXITING |
2760                         SECONDARY_EXEC_ENABLE_VPID |
2761                         SECONDARY_EXEC_ENABLE_EPT |
2762                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2763                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2764                         SECONDARY_EXEC_RDTSCP |
2765                         SECONDARY_EXEC_ENABLE_INVPCID |
2766                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2767                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2768                         SECONDARY_EXEC_SHADOW_VMCS;
2769                 if (adjust_vmx_controls(min2, opt2,
2770                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2771                                         &_cpu_based_2nd_exec_control) < 0)
2772                         return -EIO;
2773         }
2774 #ifndef CONFIG_X86_64
2775         if (!(_cpu_based_2nd_exec_control &
2776                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2777                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2778 #endif
2779
2780         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2781                 _cpu_based_2nd_exec_control &= ~(
2782                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2783                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2784                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2785
2786         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2787                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2788                    enabled */
2789                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2790                                              CPU_BASED_CR3_STORE_EXITING |
2791                                              CPU_BASED_INVLPG_EXITING);
2792                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2793                       vmx_capability.ept, vmx_capability.vpid);
2794         }
2795
2796         min = 0;
2797 #ifdef CONFIG_X86_64
2798         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2799 #endif
2800         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2801                 VM_EXIT_ACK_INTR_ON_EXIT;
2802         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2803                                 &_vmexit_control) < 0)
2804                 return -EIO;
2805
2806         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2807         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2808         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2809                                 &_pin_based_exec_control) < 0)
2810                 return -EIO;
2811
2812         if (!(_cpu_based_2nd_exec_control &
2813                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2814                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2815                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2816
2817         min = 0;
2818         opt = VM_ENTRY_LOAD_IA32_PAT;
2819         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2820                                 &_vmentry_control) < 0)
2821                 return -EIO;
2822
2823         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2824
2825         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2826         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2827                 return -EIO;
2828
2829 #ifdef CONFIG_X86_64
2830         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2831         if (vmx_msr_high & (1u<<16))
2832                 return -EIO;
2833 #endif
2834
2835         /* Require Write-Back (WB) memory type for VMCS accesses. */
2836         if (((vmx_msr_high >> 18) & 15) != 6)
2837                 return -EIO;
2838
2839         vmcs_conf->size = vmx_msr_high & 0x1fff;
2840         vmcs_conf->order = get_order(vmcs_config.size);
2841         vmcs_conf->revision_id = vmx_msr_low;
2842
2843         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2844         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2845         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2846         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2847         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2848
2849         cpu_has_load_ia32_efer =
2850                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2851                                 VM_ENTRY_LOAD_IA32_EFER)
2852                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2853                                    VM_EXIT_LOAD_IA32_EFER);
2854
2855         cpu_has_load_perf_global_ctrl =
2856                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2857                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2858                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2859                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2860
2861         /*
2862          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2863          * but due to arrata below it can't be used. Workaround is to use
2864          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2865          *
2866          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2867          *
2868          * AAK155             (model 26)
2869          * AAP115             (model 30)
2870          * AAT100             (model 37)
2871          * BC86,AAY89,BD102   (model 44)
2872          * BA97               (model 46)
2873          *
2874          */
2875         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2876                 switch (boot_cpu_data.x86_model) {
2877                 case 26:
2878                 case 30:
2879                 case 37:
2880                 case 44:
2881                 case 46:
2882                         cpu_has_load_perf_global_ctrl = false;
2883                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2884                                         "does not work properly. Using workaround\n");
2885                         break;
2886                 default:
2887                         break;
2888                 }
2889         }
2890
2891         return 0;
2892 }
2893
2894 static struct vmcs *alloc_vmcs_cpu(int cpu)
2895 {
2896         int node = cpu_to_node(cpu);
2897         struct page *pages;
2898         struct vmcs *vmcs;
2899
2900         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2901         if (!pages)
2902                 return NULL;
2903         vmcs = page_address(pages);
2904         memset(vmcs, 0, vmcs_config.size);
2905         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2906         return vmcs;
2907 }
2908
2909 static struct vmcs *alloc_vmcs(void)
2910 {
2911         return alloc_vmcs_cpu(raw_smp_processor_id());
2912 }
2913
2914 static void free_vmcs(struct vmcs *vmcs)
2915 {
2916         free_pages((unsigned long)vmcs, vmcs_config.order);
2917 }
2918
2919 /*
2920  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2921  */
2922 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2923 {
2924         if (!loaded_vmcs->vmcs)
2925                 return;
2926         loaded_vmcs_clear(loaded_vmcs);
2927         free_vmcs(loaded_vmcs->vmcs);
2928         loaded_vmcs->vmcs = NULL;
2929 }
2930
2931 static void free_kvm_area(void)
2932 {
2933         int cpu;
2934
2935         for_each_possible_cpu(cpu) {
2936                 free_vmcs(per_cpu(vmxarea, cpu));
2937                 per_cpu(vmxarea, cpu) = NULL;
2938         }
2939 }
2940
2941 static __init int alloc_kvm_area(void)
2942 {
2943         int cpu;
2944
2945         for_each_possible_cpu(cpu) {
2946                 struct vmcs *vmcs;
2947
2948                 vmcs = alloc_vmcs_cpu(cpu);
2949                 if (!vmcs) {
2950                         free_kvm_area();
2951                         return -ENOMEM;
2952                 }
2953
2954                 per_cpu(vmxarea, cpu) = vmcs;
2955         }
2956         return 0;
2957 }
2958
2959 static __init int hardware_setup(void)
2960 {
2961         if (setup_vmcs_config(&vmcs_config) < 0)
2962                 return -EIO;
2963
2964         if (boot_cpu_has(X86_FEATURE_NX))
2965                 kvm_enable_efer_bits(EFER_NX);
2966
2967         if (!cpu_has_vmx_vpid())
2968                 enable_vpid = 0;
2969         if (!cpu_has_vmx_shadow_vmcs())
2970                 enable_shadow_vmcs = 0;
2971
2972         if (!cpu_has_vmx_ept() ||
2973             !cpu_has_vmx_ept_4levels()) {
2974                 enable_ept = 0;
2975                 enable_unrestricted_guest = 0;
2976                 enable_ept_ad_bits = 0;
2977         }
2978
2979         if (!cpu_has_vmx_ept_ad_bits())
2980                 enable_ept_ad_bits = 0;
2981
2982         if (!cpu_has_vmx_unrestricted_guest())
2983                 enable_unrestricted_guest = 0;
2984
2985         if (!cpu_has_vmx_flexpriority())
2986                 flexpriority_enabled = 0;
2987
2988         if (!cpu_has_vmx_tpr_shadow())
2989                 kvm_x86_ops->update_cr8_intercept = NULL;
2990
2991         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2992                 kvm_disable_largepages();
2993
2994         if (!cpu_has_vmx_ple())
2995                 ple_gap = 0;
2996
2997         if (!cpu_has_vmx_apicv())
2998                 enable_apicv = 0;
2999
3000         if (enable_apicv)
3001                 kvm_x86_ops->update_cr8_intercept = NULL;
3002         else {
3003                 kvm_x86_ops->hwapic_irr_update = NULL;
3004                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3005                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3006         }
3007
3008         if (nested)
3009                 nested_vmx_setup_ctls_msrs();
3010
3011         return alloc_kvm_area();
3012 }
3013
3014 static __exit void hardware_unsetup(void)
3015 {
3016         free_kvm_area();
3017 }
3018
3019 static bool emulation_required(struct kvm_vcpu *vcpu)
3020 {
3021         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3022 }
3023
3024 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3025                 struct kvm_segment *save)
3026 {
3027         if (!emulate_invalid_guest_state) {
3028                 /*
3029                  * CS and SS RPL should be equal during guest entry according
3030                  * to VMX spec, but in reality it is not always so. Since vcpu
3031                  * is in the middle of the transition from real mode to
3032                  * protected mode it is safe to assume that RPL 0 is a good
3033                  * default value.
3034                  */
3035                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3036                         save->selector &= ~SELECTOR_RPL_MASK;
3037                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3038                 save->s = 1;
3039         }
3040         vmx_set_segment(vcpu, save, seg);
3041 }
3042
3043 static void enter_pmode(struct kvm_vcpu *vcpu)
3044 {
3045         unsigned long flags;
3046         struct vcpu_vmx *vmx = to_vmx(vcpu);
3047
3048         /*
3049          * Update real mode segment cache. It may be not up-to-date if sement
3050          * register was written while vcpu was in a guest mode.
3051          */
3052         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3053         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3054         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3055         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3056         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3057         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3058
3059         vmx->rmode.vm86_active = 0;
3060
3061         vmx_segment_cache_clear(vmx);
3062
3063         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3064
3065         flags = vmcs_readl(GUEST_RFLAGS);
3066         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3067         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3068         vmcs_writel(GUEST_RFLAGS, flags);
3069
3070         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3071                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3072
3073         update_exception_bitmap(vcpu);
3074
3075         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3076         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3077         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3078         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3079         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3080         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3081
3082         /* CPL is always 0 when CPU enters protected mode */
3083         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3084         vmx->cpl = 0;
3085 }
3086
3087 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3088 {
3089         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3090         struct kvm_segment var = *save;
3091
3092         var.dpl = 0x3;
3093         if (seg == VCPU_SREG_CS)
3094                 var.type = 0x3;
3095
3096         if (!emulate_invalid_guest_state) {
3097                 var.selector = var.base >> 4;
3098                 var.base = var.base & 0xffff0;
3099                 var.limit = 0xffff;
3100                 var.g = 0;
3101                 var.db = 0;
3102                 var.present = 1;
3103                 var.s = 1;
3104                 var.l = 0;
3105                 var.unusable = 0;
3106                 var.type = 0x3;
3107                 var.avl = 0;
3108                 if (save->base & 0xf)
3109                         printk_once(KERN_WARNING "kvm: segment base is not "
3110                                         "paragraph aligned when entering "
3111                                         "protected mode (seg=%d)", seg);
3112         }
3113
3114         vmcs_write16(sf->selector, var.selector);
3115         vmcs_write32(sf->base, var.base);
3116         vmcs_write32(sf->limit, var.limit);
3117         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3118 }
3119
3120 static void enter_rmode(struct kvm_vcpu *vcpu)
3121 {
3122         unsigned long flags;
3123         struct vcpu_vmx *vmx = to_vmx(vcpu);
3124
3125         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3126         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3127         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3128         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3129         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3130         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3131         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3132
3133         vmx->rmode.vm86_active = 1;
3134
3135         /*
3136          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3137          * vcpu. Warn the user that an update is overdue.
3138          */
3139         if (!vcpu->kvm->arch.tss_addr)
3140                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3141                              "called before entering vcpu\n");
3142
3143         vmx_segment_cache_clear(vmx);
3144
3145         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3146         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3147         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3148
3149         flags = vmcs_readl(GUEST_RFLAGS);
3150         vmx->rmode.save_rflags = flags;
3151
3152         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3153
3154         vmcs_writel(GUEST_RFLAGS, flags);
3155         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3156         update_exception_bitmap(vcpu);
3157
3158         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3159         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3160         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3161         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3162         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3163         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3164
3165         kvm_mmu_reset_context(vcpu);
3166 }
3167
3168 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3169 {
3170         struct vcpu_vmx *vmx = to_vmx(vcpu);
3171         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3172
3173         if (!msr)
3174                 return;
3175
3176         /*
3177          * Force kernel_gs_base reloading before EFER changes, as control
3178          * of this msr depends on is_long_mode().
3179          */
3180         vmx_load_host_state(to_vmx(vcpu));
3181         vcpu->arch.efer = efer;
3182         if (efer & EFER_LMA) {
3183                 vmcs_write32(VM_ENTRY_CONTROLS,
3184                              vmcs_read32(VM_ENTRY_CONTROLS) |
3185                              VM_ENTRY_IA32E_MODE);
3186                 msr->data = efer;
3187         } else {
3188                 vmcs_write32(VM_ENTRY_CONTROLS,
3189                              vmcs_read32(VM_ENTRY_CONTROLS) &
3190                              ~VM_ENTRY_IA32E_MODE);
3191
3192                 msr->data = efer & ~EFER_LME;
3193         }
3194         setup_msrs(vmx);
3195 }
3196
3197 #ifdef CONFIG_X86_64
3198
3199 static void enter_lmode(struct kvm_vcpu *vcpu)
3200 {
3201         u32 guest_tr_ar;
3202
3203         vmx_segment_cache_clear(to_vmx(vcpu));
3204
3205         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3206         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3207                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3208                                      __func__);
3209                 vmcs_write32(GUEST_TR_AR_BYTES,
3210                              (guest_tr_ar & ~AR_TYPE_MASK)
3211                              | AR_TYPE_BUSY_64_TSS);
3212         }
3213         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3214 }
3215
3216 static void exit_lmode(struct kvm_vcpu *vcpu)
3217 {
3218         vmcs_write32(VM_ENTRY_CONTROLS,
3219                      vmcs_read32(VM_ENTRY_CONTROLS)
3220                      & ~VM_ENTRY_IA32E_MODE);
3221         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3222 }
3223
3224 #endif
3225
3226 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3227 {
3228         vpid_sync_context(to_vmx(vcpu));
3229         if (enable_ept) {
3230                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3231                         return;
3232                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3233         }
3234 }
3235
3236 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3237 {
3238         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3239
3240         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3241         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3242 }
3243
3244 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3245 {
3246         if (enable_ept && is_paging(vcpu))
3247                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3248         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3249 }
3250
3251 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3252 {
3253         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3254
3255         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3256         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3257 }
3258
3259 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3260 {
3261         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3262
3263         if (!test_bit(VCPU_EXREG_PDPTR,
3264                       (unsigned long *)&vcpu->arch.regs_dirty))
3265                 return;
3266
3267         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3268                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3269                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3270                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3271                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3272         }
3273 }
3274
3275 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3276 {
3277         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3278
3279         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3280                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3281                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3282                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3283                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3284         }
3285
3286         __set_bit(VCPU_EXREG_PDPTR,
3287                   (unsigned long *)&vcpu->arch.regs_avail);
3288         __set_bit(VCPU_EXREG_PDPTR,
3289                   (unsigned long *)&vcpu->arch.regs_dirty);
3290 }
3291
3292 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3293
3294 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3295                                         unsigned long cr0,
3296                                         struct kvm_vcpu *vcpu)
3297 {
3298         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3299                 vmx_decache_cr3(vcpu);
3300         if (!(cr0 & X86_CR0_PG)) {
3301                 /* From paging/starting to nonpaging */
3302                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3303                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3304                              (CPU_BASED_CR3_LOAD_EXITING |
3305                               CPU_BASED_CR3_STORE_EXITING));
3306                 vcpu->arch.cr0 = cr0;
3307                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3308         } else if (!is_paging(vcpu)) {
3309                 /* From nonpaging to paging */
3310                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3311                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3312                              ~(CPU_BASED_CR3_LOAD_EXITING |
3313                                CPU_BASED_CR3_STORE_EXITING));
3314                 vcpu->arch.cr0 = cr0;
3315                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3316         }
3317
3318         if (!(cr0 & X86_CR0_WP))
3319                 *hw_cr0 &= ~X86_CR0_WP;
3320 }
3321
3322 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3323 {
3324         struct vcpu_vmx *vmx = to_vmx(vcpu);
3325         unsigned long hw_cr0;
3326
3327         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3328         if (enable_unrestricted_guest)
3329                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3330         else {
3331                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3332
3333                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3334                         enter_pmode(vcpu);
3335
3336                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3337                         enter_rmode(vcpu);
3338         }
3339
3340 #ifdef CONFIG_X86_64
3341         if (vcpu->arch.efer & EFER_LME) {
3342                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3343                         enter_lmode(vcpu);
3344                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3345                         exit_lmode(vcpu);
3346         }
3347 #endif
3348
3349         if (enable_ept)
3350                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3351
3352         if (!vcpu->fpu_active)
3353                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3354
3355         vmcs_writel(CR0_READ_SHADOW, cr0);
3356         vmcs_writel(GUEST_CR0, hw_cr0);
3357         vcpu->arch.cr0 = cr0;
3358
3359         /* depends on vcpu->arch.cr0 to be set to a new value */
3360         vmx->emulation_required = emulation_required(vcpu);
3361 }
3362
3363 static u64 construct_eptp(unsigned long root_hpa)
3364 {
3365         u64 eptp;
3366
3367         /* TODO write the value reading from MSR */
3368         eptp = VMX_EPT_DEFAULT_MT |
3369                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3370         if (enable_ept_ad_bits)
3371                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3372         eptp |= (root_hpa & PAGE_MASK);
3373
3374         return eptp;
3375 }
3376
3377 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3378 {
3379         unsigned long guest_cr3;
3380         u64 eptp;
3381
3382         guest_cr3 = cr3;
3383         if (enable_ept) {
3384                 eptp = construct_eptp(cr3);
3385                 vmcs_write64(EPT_POINTER, eptp);
3386                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3387                         guest_cr3 = kvm_read_cr3(vcpu);
3388                 else
3389                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3390                 ept_load_pdptrs(vcpu);
3391         }
3392
3393         vmx_flush_tlb(vcpu);
3394         vmcs_writel(GUEST_CR3, guest_cr3);
3395 }
3396
3397 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3398 {
3399         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3400                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3401
3402         if (cr4 & X86_CR4_VMXE) {
3403                 /*
3404                  * To use VMXON (and later other VMX instructions), a guest
3405                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3406                  * So basically the check on whether to allow nested VMX
3407                  * is here.
3408                  */
3409                 if (!nested_vmx_allowed(vcpu))
3410                         return 1;
3411         }
3412         if (to_vmx(vcpu)->nested.vmxon &&
3413             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3414                 return 1;
3415
3416         vcpu->arch.cr4 = cr4;
3417         if (enable_ept) {
3418                 if (!is_paging(vcpu)) {
3419                         hw_cr4 &= ~X86_CR4_PAE;
3420                         hw_cr4 |= X86_CR4_PSE;
3421                         /*
3422                          * SMEP is disabled if CPU is in non-paging mode in
3423                          * hardware. However KVM always uses paging mode to
3424                          * emulate guest non-paging mode with TDP.
3425                          * To emulate this behavior, SMEP needs to be manually
3426                          * disabled when guest switches to non-paging mode.
3427                          */
3428                         hw_cr4 &= ~X86_CR4_SMEP;
3429                 } else if (!(cr4 & X86_CR4_PAE)) {
3430                         hw_cr4 &= ~X86_CR4_PAE;
3431                 }
3432         }
3433
3434         vmcs_writel(CR4_READ_SHADOW, cr4);
3435         vmcs_writel(GUEST_CR4, hw_cr4);
3436         return 0;
3437 }
3438
3439 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3440                             struct kvm_segment *var, int seg)
3441 {
3442         struct vcpu_vmx *vmx = to_vmx(vcpu);
3443         u32 ar;
3444
3445         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3446                 *var = vmx->rmode.segs[seg];
3447                 if (seg == VCPU_SREG_TR
3448                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3449                         return;
3450                 var->base = vmx_read_guest_seg_base(vmx, seg);
3451                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3452                 return;
3453         }
3454         var->base = vmx_read_guest_seg_base(vmx, seg);
3455         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3456         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3457         ar = vmx_read_guest_seg_ar(vmx, seg);
3458         var->unusable = (ar >> 16) & 1;
3459         var->type = ar & 15;
3460         var->s = (ar >> 4) & 1;
3461         var->dpl = (ar >> 5) & 3;
3462         /*
3463          * Some userspaces do not preserve unusable property. Since usable
3464          * segment has to be present according to VMX spec we can use present
3465          * property to amend userspace bug by making unusable segment always
3466          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3467          * segment as unusable.
3468          */
3469         var->present = !var->unusable;
3470         var->avl = (ar >> 12) & 1;
3471         var->l = (ar >> 13) & 1;
3472         var->db = (ar >> 14) & 1;
3473         var->g = (ar >> 15) & 1;
3474 }
3475
3476 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3477 {
3478         struct kvm_segment s;
3479
3480         if (to_vmx(vcpu)->rmode.vm86_active) {
3481                 vmx_get_segment(vcpu, &s, seg);
3482                 return s.base;
3483         }
3484         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3485 }
3486
3487 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3488 {
3489         struct vcpu_vmx *vmx = to_vmx(vcpu);
3490
3491         if (!is_protmode(vcpu))
3492                 return 0;
3493
3494         if (!is_long_mode(vcpu)
3495             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3496                 return 3;
3497
3498         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3499                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3500                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3501         }
3502
3503         return vmx->cpl;
3504 }
3505
3506
3507 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3508 {
3509         u32 ar;
3510
3511         if (var->unusable || !var->present)
3512                 ar = 1 << 16;
3513         else {
3514                 ar = var->type & 15;
3515                 ar |= (var->s & 1) << 4;
3516                 ar |= (var->dpl & 3) << 5;
3517                 ar |= (var->present & 1) << 7;
3518                 ar |= (var->avl & 1) << 12;
3519                 ar |= (var->l & 1) << 13;
3520                 ar |= (var->db & 1) << 14;
3521                 ar |= (var->g & 1) << 15;
3522         }
3523
3524         return ar;
3525 }
3526
3527 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3528                             struct kvm_segment *var, int seg)
3529 {
3530         struct vcpu_vmx *vmx = to_vmx(vcpu);
3531         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3532
3533         vmx_segment_cache_clear(vmx);
3534         if (seg == VCPU_SREG_CS)
3535                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3536
3537         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3538                 vmx->rmode.segs[seg] = *var;
3539                 if (seg == VCPU_SREG_TR)
3540                         vmcs_write16(sf->selector, var->selector);
3541                 else if (var->s)
3542                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3543                 goto out;
3544         }
3545
3546         vmcs_writel(sf->base, var->base);
3547         vmcs_write32(sf->limit, var->limit);
3548         vmcs_write16(sf->selector, var->selector);
3549
3550         /*
3551          *   Fix the "Accessed" bit in AR field of segment registers for older
3552          * qemu binaries.
3553          *   IA32 arch specifies that at the time of processor reset the
3554          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3555          * is setting it to 0 in the userland code. This causes invalid guest
3556          * state vmexit when "unrestricted guest" mode is turned on.
3557          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3558          * tree. Newer qemu binaries with that qemu fix would not need this
3559          * kvm hack.
3560          */
3561         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3562                 var->type |= 0x1; /* Accessed */
3563
3564         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3565
3566 out:
3567         vmx->emulation_required |= emulation_required(vcpu);
3568 }
3569
3570 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3571 {
3572         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3573
3574         *db = (ar >> 14) & 1;
3575         *l = (ar >> 13) & 1;
3576 }
3577
3578 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3579 {
3580         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3581         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3582 }
3583
3584 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3585 {
3586         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3587         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3588 }
3589
3590 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3591 {
3592         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3593         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3594 }
3595
3596 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3597 {
3598         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3599         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3600 }
3601
3602 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3603 {
3604         struct kvm_segment var;
3605         u32 ar;
3606
3607         vmx_get_segment(vcpu, &var, seg);
3608         var.dpl = 0x3;
3609         if (seg == VCPU_SREG_CS)
3610                 var.type = 0x3;
3611         ar = vmx_segment_access_rights(&var);
3612
3613         if (var.base != (var.selector << 4))
3614                 return false;
3615         if (var.limit != 0xffff)
3616                 return false;
3617         if (ar != 0xf3)
3618                 return false;
3619
3620         return true;
3621 }
3622
3623 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3624 {
3625         struct kvm_segment cs;
3626         unsigned int cs_rpl;
3627
3628         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3629         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3630
3631         if (cs.unusable)
3632                 return false;
3633         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3634                 return false;
3635         if (!cs.s)
3636                 return false;
3637         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3638                 if (cs.dpl > cs_rpl)
3639                         return false;
3640         } else {
3641                 if (cs.dpl != cs_rpl)
3642                         return false;
3643         }
3644         if (!cs.present)
3645                 return false;
3646
3647         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3648         return true;
3649 }
3650
3651 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3652 {
3653         struct kvm_segment ss;
3654         unsigned int ss_rpl;
3655
3656         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3657         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3658
3659         if (ss.unusable)
3660                 return true;
3661         if (ss.type != 3 && ss.type != 7)
3662                 return false;
3663         if (!ss.s)
3664                 return false;
3665         if (ss.dpl != ss_rpl) /* DPL != RPL */
3666                 return false;
3667         if (!ss.present)
3668                 return false;
3669
3670         return true;
3671 }
3672
3673 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3674 {
3675         struct kvm_segment var;
3676         unsigned int rpl;
3677
3678         vmx_get_segment(vcpu, &var, seg);
3679         rpl = var.selector & SELECTOR_RPL_MASK;
3680
3681         if (var.unusable)
3682                 return true;
3683         if (!var.s)
3684                 return false;
3685         if (!var.present)
3686                 return false;
3687         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3688                 if (var.dpl < rpl) /* DPL < RPL */
3689                         return false;
3690         }
3691
3692         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3693          * rights flags
3694          */
3695         return true;
3696 }
3697
3698 static bool tr_valid(struct kvm_vcpu *vcpu)
3699 {
3700         struct kvm_segment tr;
3701
3702         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3703
3704         if (tr.unusable)
3705                 return false;
3706         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3707                 return false;
3708         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3709                 return false;
3710         if (!tr.present)
3711                 return false;
3712
3713         return true;
3714 }
3715
3716 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3717 {
3718         struct kvm_segment ldtr;
3719
3720         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3721
3722         if (ldtr.unusable)
3723                 return true;
3724         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3725                 return false;
3726         if (ldtr.type != 2)
3727                 return false;
3728         if (!ldtr.present)
3729                 return false;
3730
3731         return true;
3732 }
3733
3734 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3735 {
3736         struct kvm_segment cs, ss;
3737
3738         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3739         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3740
3741         return ((cs.selector & SELECTOR_RPL_MASK) ==
3742                  (ss.selector & SELECTOR_RPL_MASK));
3743 }
3744
3745 /*
3746  * Check if guest state is valid. Returns true if valid, false if
3747  * not.
3748  * We assume that registers are always usable
3749  */
3750 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3751 {
3752         if (enable_unrestricted_guest)
3753                 return true;
3754
3755         /* real mode guest state checks */
3756         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3757                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3758                         return false;
3759                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3760                         return false;
3761                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3762                         return false;
3763                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3764                         return false;
3765                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3766                         return false;
3767                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3768                         return false;
3769         } else {
3770         /* protected mode guest state checks */
3771                 if (!cs_ss_rpl_check(vcpu))
3772                         return false;
3773                 if (!code_segment_valid(vcpu))
3774                         return false;
3775                 if (!stack_segment_valid(vcpu))
3776                         return false;
3777                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3778                         return false;
3779                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3780                         return false;
3781                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3782                         return false;
3783                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3784                         return false;
3785                 if (!tr_valid(vcpu))
3786                         return false;
3787                 if (!ldtr_valid(vcpu))
3788                         return false;
3789         }
3790         /* TODO:
3791          * - Add checks on RIP
3792          * - Add checks on RFLAGS
3793          */
3794
3795         return true;
3796 }
3797
3798 static int init_rmode_tss(struct kvm *kvm)
3799 {
3800         gfn_t fn;
3801         u16 data = 0;
3802         int r, idx, ret = 0;
3803
3804         idx = srcu_read_lock(&kvm->srcu);
3805         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3806         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3807         if (r < 0)
3808                 goto out;
3809         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3810         r = kvm_write_guest_page(kvm, fn++, &data,
3811                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3812         if (r < 0)
3813                 goto out;
3814         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3815         if (r < 0)
3816                 goto out;
3817         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3818         if (r < 0)
3819                 goto out;
3820         data = ~0;
3821         r = kvm_write_guest_page(kvm, fn, &data,
3822                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3823                                  sizeof(u8));
3824         if (r < 0)
3825                 goto out;
3826
3827         ret = 1;
3828 out:
3829         srcu_read_unlock(&kvm->srcu, idx);
3830         return ret;
3831 }
3832
3833 static int init_rmode_identity_map(struct kvm *kvm)
3834 {
3835         int i, idx, r, ret;
3836         pfn_t identity_map_pfn;
3837         u32 tmp;
3838
3839         if (!enable_ept)
3840                 return 1;
3841         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3842                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3843                         "haven't been allocated!\n");
3844                 return 0;
3845         }
3846         if (likely(kvm->arch.ept_identity_pagetable_done))
3847                 return 1;
3848         ret = 0;
3849         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3850         idx = srcu_read_lock(&kvm->srcu);
3851         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3852         if (r < 0)
3853                 goto out;
3854         /* Set up identity-mapping pagetable for EPT in real mode */
3855         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3856                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3857                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3858                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3859                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3860                 if (r < 0)
3861                         goto out;
3862         }
3863         kvm->arch.ept_identity_pagetable_done = true;
3864         ret = 1;
3865 out:
3866         srcu_read_unlock(&kvm->srcu, idx);
3867         return ret;
3868 }
3869
3870 static void seg_setup(int seg)
3871 {
3872         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3873         unsigned int ar;
3874
3875         vmcs_write16(sf->selector, 0);
3876         vmcs_writel(sf->base, 0);
3877         vmcs_write32(sf->limit, 0xffff);
3878         ar = 0x93;
3879         if (seg == VCPU_SREG_CS)
3880                 ar |= 0x08; /* code segment */
3881
3882         vmcs_write32(sf->ar_bytes, ar);
3883 }
3884
3885 static int alloc_apic_access_page(struct kvm *kvm)
3886 {
3887         struct page *page;
3888         struct kvm_userspace_memory_region kvm_userspace_mem;
3889         int r = 0;
3890
3891         mutex_lock(&kvm->slots_lock);
3892         if (kvm->arch.apic_access_page)
3893                 goto out;
3894         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3895         kvm_userspace_mem.flags = 0;
3896         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3897         kvm_userspace_mem.memory_size = PAGE_SIZE;
3898         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3899         if (r)
3900                 goto out;
3901
3902         page = gfn_to_page(kvm, 0xfee00);
3903         if (is_error_page(page)) {
3904                 r = -EFAULT;
3905                 goto out;
3906         }
3907
3908         kvm->arch.apic_access_page = page;
3909 out:
3910         mutex_unlock(&kvm->slots_lock);
3911         return r;
3912 }
3913
3914 static int alloc_identity_pagetable(struct kvm *kvm)
3915 {
3916         struct page *page;
3917         struct kvm_userspace_memory_region kvm_userspace_mem;
3918         int r = 0;
3919
3920         mutex_lock(&kvm->slots_lock);
3921         if (kvm->arch.ept_identity_pagetable)
3922                 goto out;
3923         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3924         kvm_userspace_mem.flags = 0;
3925         kvm_userspace_mem.guest_phys_addr =
3926                 kvm->arch.ept_identity_map_addr;
3927         kvm_userspace_mem.memory_size = PAGE_SIZE;
3928         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3929         if (r)
3930                 goto out;
3931
3932         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3933         if (is_error_page(page)) {
3934                 r = -EFAULT;
3935                 goto out;
3936         }
3937
3938         kvm->arch.ept_identity_pagetable = page;
3939 out:
3940         mutex_unlock(&kvm->slots_lock);
3941         return r;
3942 }
3943
3944 static void allocate_vpid(struct vcpu_vmx *vmx)
3945 {
3946         int vpid;
3947
3948         vmx->vpid = 0;
3949         if (!enable_vpid)
3950                 return;
3951         spin_lock(&vmx_vpid_lock);
3952         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3953         if (vpid < VMX_NR_VPIDS) {
3954                 vmx->vpid = vpid;
3955                 __set_bit(vpid, vmx_vpid_bitmap);
3956         }
3957         spin_unlock(&vmx_vpid_lock);
3958 }
3959
3960 static void free_vpid(struct vcpu_vmx *vmx)
3961 {
3962         if (!enable_vpid)
3963                 return;
3964         spin_lock(&vmx_vpid_lock);
3965         if (vmx->vpid != 0)
3966                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3967         spin_unlock(&vmx_vpid_lock);
3968 }
3969
3970 #define MSR_TYPE_R      1
3971 #define MSR_TYPE_W      2
3972 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3973                                                 u32 msr, int type)
3974 {
3975         int f = sizeof(unsigned long);
3976
3977         if (!cpu_has_vmx_msr_bitmap())
3978                 return;
3979
3980         /*
3981          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3982          * have the write-low and read-high bitmap offsets the wrong way round.
3983          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3984          */
3985         if (msr <= 0x1fff) {
3986                 if (type & MSR_TYPE_R)
3987                         /* read-low */
3988                         __clear_bit(msr, msr_bitmap + 0x000 / f);
3989
3990                 if (type & MSR_TYPE_W)
3991                         /* write-low */
3992                         __clear_bit(msr, msr_bitmap + 0x800 / f);
3993
3994         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3995                 msr &= 0x1fff;
3996                 if (type & MSR_TYPE_R)
3997                         /* read-high */
3998                         __clear_bit(msr, msr_bitmap + 0x400 / f);
3999
4000                 if (type & MSR_TYPE_W)
4001                         /* write-high */
4002                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4003
4004         }
4005 }
4006
4007 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4008                                                 u32 msr, int type)
4009 {
4010         int f = sizeof(unsigned long);
4011
4012         if (!cpu_has_vmx_msr_bitmap())
4013                 return;
4014
4015         /*
4016          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4017          * have the write-low and read-high bitmap offsets the wrong way round.
4018          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4019          */
4020         if (msr <= 0x1fff) {
4021                 if (type & MSR_TYPE_R)
4022                         /* read-low */
4023                         __set_bit(msr, msr_bitmap + 0x000 / f);
4024
4025                 if (type & MSR_TYPE_W)
4026                         /* write-low */
4027                         __set_bit(msr, msr_bitmap + 0x800 / f);
4028
4029         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4030                 msr &= 0x1fff;
4031                 if (type & MSR_TYPE_R)
4032                         /* read-high */
4033                         __set_bit(msr, msr_bitmap + 0x400 / f);
4034
4035                 if (type & MSR_TYPE_W)
4036                         /* write-high */
4037                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4038
4039         }
4040 }
4041
4042 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4043 {
4044         if (!longmode_only)
4045                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4046                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4047         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4048                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4049 }
4050
4051 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4052 {
4053         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4054                         msr, MSR_TYPE_R);
4055         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4056                         msr, MSR_TYPE_R);
4057 }
4058
4059 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4060 {
4061         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4062                         msr, MSR_TYPE_R);
4063         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4064                         msr, MSR_TYPE_R);
4065 }
4066
4067 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4068 {
4069         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4070                         msr, MSR_TYPE_W);
4071         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4072                         msr, MSR_TYPE_W);
4073 }
4074
4075 static int vmx_vm_has_apicv(struct kvm *kvm)
4076 {
4077         return enable_apicv && irqchip_in_kernel(kvm);
4078 }
4079
4080 /*
4081  * Send interrupt to vcpu via posted interrupt way.
4082  * 1. If target vcpu is running(non-root mode), send posted interrupt
4083  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4084  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4085  * interrupt from PIR in next vmentry.
4086  */
4087 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4088 {
4089         struct vcpu_vmx *vmx = to_vmx(vcpu);
4090         int r;
4091
4092         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4093                 return;
4094
4095         r = pi_test_and_set_on(&vmx->pi_desc);
4096         kvm_make_request(KVM_REQ_EVENT, vcpu);
4097 #ifdef CONFIG_SMP
4098         if (!r && (vcpu->mode == IN_GUEST_MODE))
4099                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4100                                 POSTED_INTR_VECTOR);
4101         else
4102 #endif
4103                 kvm_vcpu_kick(vcpu);
4104 }
4105
4106 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4107 {
4108         struct vcpu_vmx *vmx = to_vmx(vcpu);
4109
4110         if (!pi_test_and_clear_on(&vmx->pi_desc))
4111                 return;
4112
4113         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4114 }
4115
4116 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4117 {
4118         return;
4119 }
4120
4121 /*
4122  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4123  * will not change in the lifetime of the guest.
4124  * Note that host-state that does change is set elsewhere. E.g., host-state
4125  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4126  */
4127 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4128 {
4129         u32 low32, high32;
4130         unsigned long tmpl;
4131         struct desc_ptr dt;
4132
4133         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4134         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4135         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4136
4137         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4138 #ifdef CONFIG_X86_64
4139         /*
4140          * Load null selectors, so we can avoid reloading them in
4141          * __vmx_load_host_state(), in case userspace uses the null selectors
4142          * too (the expected case).
4143          */
4144         vmcs_write16(HOST_DS_SELECTOR, 0);
4145         vmcs_write16(HOST_ES_SELECTOR, 0);
4146 #else
4147         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4148         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4149 #endif
4150         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4151         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4152
4153         native_store_idt(&dt);
4154         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4155         vmx->host_idt_base = dt.address;
4156
4157         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4158
4159         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4160         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4161         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4162         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4163
4164         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4165                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4166                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4167         }
4168 }
4169
4170 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4171 {
4172         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4173         if (enable_ept)
4174                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4175         if (is_guest_mode(&vmx->vcpu))
4176                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4177                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4178         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4179 }
4180
4181 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4182 {
4183         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4184
4185         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4186                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4187         return pin_based_exec_ctrl;
4188 }
4189
4190 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4191 {
4192         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4193         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4194                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4195 #ifdef CONFIG_X86_64
4196                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4197                                 CPU_BASED_CR8_LOAD_EXITING;
4198 #endif
4199         }
4200         if (!enable_ept)
4201                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4202                                 CPU_BASED_CR3_LOAD_EXITING  |
4203                                 CPU_BASED_INVLPG_EXITING;
4204         return exec_control;
4205 }
4206
4207 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4208 {
4209         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4210         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4211                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4212         if (vmx->vpid == 0)
4213                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4214         if (!enable_ept) {
4215                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4216                 enable_unrestricted_guest = 0;
4217                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4218                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4219         }
4220         if (!enable_unrestricted_guest)
4221                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4222         if (!ple_gap)
4223                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4224         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4225                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4226                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4227         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4228         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4229            (handle_vmptrld).
4230            We can NOT enable shadow_vmcs here because we don't have yet
4231            a current VMCS12
4232         */
4233         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4234         return exec_control;
4235 }
4236
4237 static void ept_set_mmio_spte_mask(void)
4238 {
4239         /*
4240          * EPT Misconfigurations can be generated if the value of bits 2:0
4241          * of an EPT paging-structure entry is 110b (write/execute).
4242          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4243          * spte.
4244          */
4245         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4246 }
4247
4248 /*
4249  * Sets up the vmcs for emulated real mode.
4250  */
4251 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4252 {
4253 #ifdef CONFIG_X86_64
4254         unsigned long a;
4255 #endif
4256         int i;
4257
4258         /* I/O */
4259         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4260         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4261
4262         if (enable_shadow_vmcs) {
4263                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4264                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4265         }
4266         if (cpu_has_vmx_msr_bitmap())
4267                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4268
4269         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4270
4271         /* Control */
4272         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4273
4274         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4275
4276         if (cpu_has_secondary_exec_ctrls()) {
4277                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4278                                 vmx_secondary_exec_control(vmx));
4279         }
4280
4281         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4282                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4283                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4284                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4285                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4286
4287                 vmcs_write16(GUEST_INTR_STATUS, 0);
4288
4289                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4290                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4291         }
4292
4293         if (ple_gap) {
4294                 vmcs_write32(PLE_GAP, ple_gap);
4295                 vmcs_write32(PLE_WINDOW, ple_window);
4296         }
4297
4298         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4299         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4300         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4301
4302         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4303         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4304         vmx_set_constant_host_state(vmx);
4305 #ifdef CONFIG_X86_64
4306         rdmsrl(MSR_FS_BASE, a);
4307         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4308         rdmsrl(MSR_GS_BASE, a);
4309         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4310 #else
4311         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4312         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4313 #endif
4314
4315         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4316         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4317         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4318         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4319         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4320
4321         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4322                 u32 msr_low, msr_high;
4323                 u64 host_pat;
4324                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4325                 host_pat = msr_low | ((u64) msr_high << 32);
4326                 /* Write the default value follow host pat */
4327                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4328                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4329                 vmx->vcpu.arch.pat = host_pat;
4330         }
4331
4332         for (i = 0; i < NR_VMX_MSR; ++i) {
4333                 u32 index = vmx_msr_index[i];
4334                 u32 data_low, data_high;
4335                 int j = vmx->nmsrs;
4336
4337                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4338                         continue;
4339                 if (wrmsr_safe(index, data_low, data_high) < 0)
4340                         continue;
4341                 vmx->guest_msrs[j].index = i;
4342                 vmx->guest_msrs[j].data = 0;
4343                 vmx->guest_msrs[j].mask = -1ull;
4344                 ++vmx->nmsrs;
4345         }
4346
4347         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4348
4349         /* 22.2.1, 20.8.1 */
4350         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4351
4352         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4353         set_cr4_guest_host_mask(vmx);
4354
4355         return 0;
4356 }
4357
4358 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4359 {
4360         struct vcpu_vmx *vmx = to_vmx(vcpu);
4361         u64 msr;
4362
4363         vmx->rmode.vm86_active = 0;
4364
4365         vmx->soft_vnmi_blocked = 0;
4366
4367         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4368         kvm_set_cr8(&vmx->vcpu, 0);
4369         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4370         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4371                 msr |= MSR_IA32_APICBASE_BSP;
4372         kvm_set_apic_base(&vmx->vcpu, msr);
4373
4374         vmx_segment_cache_clear(vmx);
4375
4376         seg_setup(VCPU_SREG_CS);
4377         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4378         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4379
4380         seg_setup(VCPU_SREG_DS);
4381         seg_setup(VCPU_SREG_ES);
4382         seg_setup(VCPU_SREG_FS);
4383         seg_setup(VCPU_SREG_GS);
4384         seg_setup(VCPU_SREG_SS);
4385
4386         vmcs_write16(GUEST_TR_SELECTOR, 0);
4387         vmcs_writel(GUEST_TR_BASE, 0);
4388         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4389         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4390
4391         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4392         vmcs_writel(GUEST_LDTR_BASE, 0);
4393         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4394         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4395
4396         vmcs_write32(GUEST_SYSENTER_CS, 0);
4397         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4398         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4399
4400         vmcs_writel(GUEST_RFLAGS, 0x02);
4401         kvm_rip_write(vcpu, 0xfff0);
4402
4403         vmcs_writel(GUEST_GDTR_BASE, 0);
4404         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4405
4406         vmcs_writel(GUEST_IDTR_BASE, 0);
4407         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4408
4409         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4410         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4411         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4412
4413         /* Special registers */
4414         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4415
4416         setup_msrs(vmx);
4417
4418         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4419
4420         if (cpu_has_vmx_tpr_shadow()) {
4421                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4422                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4423                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4424                                      __pa(vmx->vcpu.arch.apic->regs));
4425                 vmcs_write32(TPR_THRESHOLD, 0);
4426         }
4427
4428         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4429                 vmcs_write64(APIC_ACCESS_ADDR,
4430                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4431
4432         if (vmx_vm_has_apicv(vcpu->kvm))
4433                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4434
4435         if (vmx->vpid != 0)
4436                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4437
4438         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4439         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4440         vmx_set_cr4(&vmx->vcpu, 0);
4441         vmx_set_efer(&vmx->vcpu, 0);
4442         vmx_fpu_activate(&vmx->vcpu);
4443         update_exception_bitmap(&vmx->vcpu);
4444
4445         vpid_sync_context(vmx);
4446 }
4447
4448 /*
4449  * In nested virtualization, check if L1 asked to exit on external interrupts.
4450  * For most existing hypervisors, this will always return true.
4451  */
4452 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4453 {
4454         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4455                 PIN_BASED_EXT_INTR_MASK;
4456 }
4457
4458 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4459 {
4460         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4461                 PIN_BASED_NMI_EXITING;
4462 }
4463
4464 static int enable_irq_window(struct kvm_vcpu *vcpu)
4465 {
4466         u32 cpu_based_vm_exec_control;
4467
4468         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4469                 /*
4470                  * We get here if vmx_interrupt_allowed() said we can't
4471                  * inject to L1 now because L2 must run. The caller will have
4472                  * to make L2 exit right after entry, so we can inject to L1
4473                  * more promptly.
4474                  */
4475                 return -EBUSY;
4476
4477         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4478         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4479         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4480         return 0;
4481 }
4482
4483 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4484 {
4485         u32 cpu_based_vm_exec_control;
4486
4487         if (!cpu_has_virtual_nmis())
4488                 return enable_irq_window(vcpu);
4489
4490         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4491                 return enable_irq_window(vcpu);
4492
4493         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4494         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4495         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4496         return 0;
4497 }
4498
4499 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4500 {
4501         struct vcpu_vmx *vmx = to_vmx(vcpu);
4502         uint32_t intr;
4503         int irq = vcpu->arch.interrupt.nr;
4504
4505         trace_kvm_inj_virq(irq);
4506
4507         ++vcpu->stat.irq_injections;
4508         if (vmx->rmode.vm86_active) {
4509                 int inc_eip = 0;
4510                 if (vcpu->arch.interrupt.soft)
4511                         inc_eip = vcpu->arch.event_exit_inst_len;
4512                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4513                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4514                 return;
4515         }
4516         intr = irq | INTR_INFO_VALID_MASK;
4517         if (vcpu->arch.interrupt.soft) {
4518                 intr |= INTR_TYPE_SOFT_INTR;
4519                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4520                              vmx->vcpu.arch.event_exit_inst_len);
4521         } else
4522                 intr |= INTR_TYPE_EXT_INTR;
4523         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4524 }
4525
4526 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4527 {
4528         struct vcpu_vmx *vmx = to_vmx(vcpu);
4529
4530         if (is_guest_mode(vcpu))
4531                 return;
4532
4533         if (!cpu_has_virtual_nmis()) {
4534                 /*
4535                  * Tracking the NMI-blocked state in software is built upon
4536                  * finding the next open IRQ window. This, in turn, depends on
4537                  * well-behaving guests: They have to keep IRQs disabled at
4538                  * least as long as the NMI handler runs. Otherwise we may
4539                  * cause NMI nesting, maybe breaking the guest. But as this is
4540                  * highly unlikely, we can live with the residual risk.
4541                  */
4542                 vmx->soft_vnmi_blocked = 1;
4543                 vmx->vnmi_blocked_time = 0;
4544         }
4545
4546         ++vcpu->stat.nmi_injections;
4547         vmx->nmi_known_unmasked = false;
4548         if (vmx->rmode.vm86_active) {
4549                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4550                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4551                 return;
4552         }
4553         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4554                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4555 }
4556
4557 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4558 {
4559         if (!cpu_has_virtual_nmis())
4560                 return to_vmx(vcpu)->soft_vnmi_blocked;
4561         if (to_vmx(vcpu)->nmi_known_unmasked)
4562                 return false;
4563         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4564 }
4565
4566 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4567 {
4568         struct vcpu_vmx *vmx = to_vmx(vcpu);
4569
4570         if (!cpu_has_virtual_nmis()) {
4571                 if (vmx->soft_vnmi_blocked != masked) {
4572                         vmx->soft_vnmi_blocked = masked;
4573                         vmx->vnmi_blocked_time = 0;
4574                 }
4575         } else {
4576                 vmx->nmi_known_unmasked = !masked;
4577                 if (masked)
4578                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4579                                       GUEST_INTR_STATE_NMI);
4580                 else
4581                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4582                                         GUEST_INTR_STATE_NMI);
4583         }
4584 }
4585
4586 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4587 {
4588         if (is_guest_mode(vcpu)) {
4589                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4590
4591                 if (to_vmx(vcpu)->nested.nested_run_pending)
4592                         return 0;
4593                 if (nested_exit_on_nmi(vcpu)) {
4594                         nested_vmx_vmexit(vcpu);
4595                         vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4596                         vmcs12->vm_exit_intr_info = NMI_VECTOR |
4597                                 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4598                         /*
4599                          * The NMI-triggered VM exit counts as injection:
4600                          * clear this one and block further NMIs.
4601                          */
4602                         vcpu->arch.nmi_pending = 0;
4603                         vmx_set_nmi_mask(vcpu, true);
4604                         return 0;
4605                 }
4606         }
4607
4608         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4609                 return 0;
4610
4611         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4612                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4613                    | GUEST_INTR_STATE_NMI));
4614 }
4615
4616 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4617 {
4618         if (is_guest_mode(vcpu)) {
4619                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4620
4621                 if (to_vmx(vcpu)->nested.nested_run_pending)
4622                         return 0;
4623                 if (nested_exit_on_intr(vcpu)) {
4624                         nested_vmx_vmexit(vcpu);
4625                         vmcs12->vm_exit_reason =
4626                                 EXIT_REASON_EXTERNAL_INTERRUPT;
4627                         vmcs12->vm_exit_intr_info = 0;
4628                         /*
4629                          * fall through to normal code, but now in L1, not L2
4630                          */
4631                 }
4632         }
4633
4634         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4635                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4636                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4637 }
4638
4639 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4640 {
4641         int ret;
4642         struct kvm_userspace_memory_region tss_mem = {
4643                 .slot = TSS_PRIVATE_MEMSLOT,
4644                 .guest_phys_addr = addr,
4645                 .memory_size = PAGE_SIZE * 3,
4646                 .flags = 0,
4647         };
4648
4649         ret = kvm_set_memory_region(kvm, &tss_mem);
4650         if (ret)
4651                 return ret;
4652         kvm->arch.tss_addr = addr;
4653         if (!init_rmode_tss(kvm))
4654                 return  -ENOMEM;
4655
4656         return 0;
4657 }
4658
4659 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4660 {
4661         switch (vec) {
4662         case BP_VECTOR:
4663                 /*
4664                  * Update instruction length as we may reinject the exception
4665                  * from user space while in guest debugging mode.
4666                  */
4667                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4668                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4669                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4670                         return false;
4671                 /* fall through */
4672         case DB_VECTOR:
4673                 if (vcpu->guest_debug &
4674                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4675                         return false;
4676                 /* fall through */
4677         case DE_VECTOR:
4678         case OF_VECTOR:
4679         case BR_VECTOR:
4680         case UD_VECTOR:
4681         case DF_VECTOR:
4682         case SS_VECTOR:
4683         case GP_VECTOR:
4684         case MF_VECTOR:
4685                 return true;
4686         break;
4687         }
4688         return false;
4689 }
4690
4691 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4692                                   int vec, u32 err_code)
4693 {
4694         /*
4695          * Instruction with address size override prefix opcode 0x67
4696          * Cause the #SS fault with 0 error code in VM86 mode.
4697          */
4698         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4699                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4700                         if (vcpu->arch.halt_request) {
4701                                 vcpu->arch.halt_request = 0;
4702                                 return kvm_emulate_halt(vcpu);
4703                         }
4704                         return 1;
4705                 }
4706                 return 0;
4707         }
4708
4709         /*
4710          * Forward all other exceptions that are valid in real mode.
4711          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4712          *        the required debugging infrastructure rework.
4713          */
4714         kvm_queue_exception(vcpu, vec);
4715         return 1;
4716 }
4717
4718 /*
4719  * Trigger machine check on the host. We assume all the MSRs are already set up
4720  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4721  * We pass a fake environment to the machine check handler because we want
4722  * the guest to be always treated like user space, no matter what context
4723  * it used internally.
4724  */
4725 static void kvm_machine_check(void)
4726 {
4727 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4728         struct pt_regs regs = {
4729                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4730                 .flags = X86_EFLAGS_IF,
4731         };
4732
4733         do_machine_check(&regs, 0);
4734 #endif
4735 }
4736
4737 static int handle_machine_check(struct kvm_vcpu *vcpu)
4738 {
4739         /* already handled by vcpu_run */
4740         return 1;
4741 }
4742
4743 static int handle_exception(struct kvm_vcpu *vcpu)
4744 {
4745         struct vcpu_vmx *vmx = to_vmx(vcpu);
4746         struct kvm_run *kvm_run = vcpu->run;
4747         u32 intr_info, ex_no, error_code;
4748         unsigned long cr2, rip, dr6;
4749         u32 vect_info;
4750         enum emulation_result er;
4751
4752         vect_info = vmx->idt_vectoring_info;
4753         intr_info = vmx->exit_intr_info;
4754
4755         if (is_machine_check(intr_info))
4756                 return handle_machine_check(vcpu);
4757
4758         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4759                 return 1;  /* already handled by vmx_vcpu_run() */
4760
4761         if (is_no_device(intr_info)) {
4762                 vmx_fpu_activate(vcpu);
4763                 return 1;
4764         }
4765
4766         if (is_invalid_opcode(intr_info)) {
4767                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4768                 if (er != EMULATE_DONE)
4769                         kvm_queue_exception(vcpu, UD_VECTOR);
4770                 return 1;
4771         }
4772
4773         error_code = 0;
4774         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4775                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4776
4777         /*
4778          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4779          * MMIO, it is better to report an internal error.
4780          * See the comments in vmx_handle_exit.
4781          */
4782         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4783             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4784                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4785                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4786                 vcpu->run->internal.ndata = 2;
4787                 vcpu->run->internal.data[0] = vect_info;
4788                 vcpu->run->internal.data[1] = intr_info;
4789                 return 0;
4790         }
4791
4792         if (is_page_fault(intr_info)) {
4793                 /* EPT won't cause page fault directly */
4794                 BUG_ON(enable_ept);
4795                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4796                 trace_kvm_page_fault(cr2, error_code);
4797
4798                 if (kvm_event_needs_reinjection(vcpu))
4799                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4800                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4801         }
4802
4803         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4804
4805         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4806                 return handle_rmode_exception(vcpu, ex_no, error_code);
4807
4808         switch (ex_no) {
4809         case DB_VECTOR:
4810                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4811                 if (!(vcpu->guest_debug &
4812                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4813                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4814                         kvm_queue_exception(vcpu, DB_VECTOR);
4815                         return 1;
4816                 }
4817                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4818                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4819                 /* fall through */
4820         case BP_VECTOR:
4821                 /*
4822                  * Update instruction length as we may reinject #BP from
4823                  * user space while in guest debugging mode. Reading it for
4824                  * #DB as well causes no harm, it is not used in that case.
4825                  */
4826                 vmx->vcpu.arch.event_exit_inst_len =
4827                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4828                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4829                 rip = kvm_rip_read(vcpu);
4830                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4831                 kvm_run->debug.arch.exception = ex_no;
4832                 break;
4833         default:
4834                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4835                 kvm_run->ex.exception = ex_no;
4836                 kvm_run->ex.error_code = error_code;
4837                 break;
4838         }
4839         return 0;
4840 }
4841
4842 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4843 {
4844         ++vcpu->stat.irq_exits;
4845         return 1;
4846 }
4847
4848 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4849 {
4850         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4851         return 0;
4852 }
4853
4854 static int handle_io(struct kvm_vcpu *vcpu)
4855 {
4856         unsigned long exit_qualification;
4857         int size, in, string;
4858         unsigned port;
4859
4860         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4861         string = (exit_qualification & 16) != 0;
4862         in = (exit_qualification & 8) != 0;
4863
4864         ++vcpu->stat.io_exits;
4865
4866         if (string || in)
4867                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4868
4869         port = exit_qualification >> 16;
4870         size = (exit_qualification & 7) + 1;
4871         skip_emulated_instruction(vcpu);
4872
4873         return kvm_fast_pio_out(vcpu, size, port);
4874 }
4875
4876 static void
4877 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4878 {
4879         /*
4880          * Patch in the VMCALL instruction:
4881          */
4882         hypercall[0] = 0x0f;
4883         hypercall[1] = 0x01;
4884         hypercall[2] = 0xc1;
4885 }
4886
4887 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4888 {
4889         unsigned long always_on = VMXON_CR0_ALWAYSON;
4890
4891         if (nested_vmx_secondary_ctls_high &
4892                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4893             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4894                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4895         return (val & always_on) == always_on;
4896 }
4897
4898 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4899 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4900 {
4901         if (is_guest_mode(vcpu)) {
4902                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4903                 unsigned long orig_val = val;
4904
4905                 /*
4906                  * We get here when L2 changed cr0 in a way that did not change
4907                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4908                  * but did change L0 shadowed bits. So we first calculate the
4909                  * effective cr0 value that L1 would like to write into the
4910                  * hardware. It consists of the L2-owned bits from the new
4911                  * value combined with the L1-owned bits from L1's guest_cr0.
4912                  */
4913                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4914                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4915
4916                 if (!nested_cr0_valid(vmcs12, val))
4917                         return 1;
4918
4919                 if (kvm_set_cr0(vcpu, val))
4920                         return 1;
4921                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4922                 return 0;
4923         } else {
4924                 if (to_vmx(vcpu)->nested.vmxon &&
4925                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4926                         return 1;
4927                 return kvm_set_cr0(vcpu, val);
4928         }
4929 }
4930
4931 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4932 {
4933         if (is_guest_mode(vcpu)) {
4934                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4935                 unsigned long orig_val = val;
4936
4937                 /* analogously to handle_set_cr0 */
4938                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4939                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4940                 if (kvm_set_cr4(vcpu, val))
4941                         return 1;
4942                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4943                 return 0;
4944         } else
4945                 return kvm_set_cr4(vcpu, val);
4946 }
4947
4948 /* called to set cr0 as approriate for clts instruction exit. */
4949 static void handle_clts(struct kvm_vcpu *vcpu)
4950 {
4951         if (is_guest_mode(vcpu)) {
4952                 /*
4953                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4954                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4955                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4956                  */
4957                 vmcs_writel(CR0_READ_SHADOW,
4958                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4959                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4960         } else
4961                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4962 }
4963
4964 static int handle_cr(struct kvm_vcpu *vcpu)
4965 {
4966         unsigned long exit_qualification, val;
4967         int cr;
4968         int reg;
4969         int err;
4970
4971         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4972         cr = exit_qualification & 15;
4973         reg = (exit_qualification >> 8) & 15;
4974         switch ((exit_qualification >> 4) & 3) {
4975         case 0: /* mov to cr */
4976                 val = kvm_register_read(vcpu, reg);
4977                 trace_kvm_cr_write(cr, val);
4978                 switch (cr) {
4979                 case 0:
4980                         err = handle_set_cr0(vcpu, val);
4981                         kvm_complete_insn_gp(vcpu, err);
4982                         return 1;
4983                 case 3:
4984                         err = kvm_set_cr3(vcpu, val);
4985                         kvm_complete_insn_gp(vcpu, err);
4986                         return 1;
4987                 case 4:
4988                         err = handle_set_cr4(vcpu, val);
4989                         kvm_complete_insn_gp(vcpu, err);
4990                         return 1;
4991                 case 8: {
4992                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4993                                 u8 cr8 = kvm_register_read(vcpu, reg);
4994                                 err = kvm_set_cr8(vcpu, cr8);
4995                                 kvm_complete_insn_gp(vcpu, err);
4996                                 if (irqchip_in_kernel(vcpu->kvm))
4997                                         return 1;
4998                                 if (cr8_prev <= cr8)
4999                                         return 1;
5000                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5001                                 return 0;
5002                         }
5003                 }
5004                 break;
5005         case 2: /* clts */
5006                 handle_clts(vcpu);
5007                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5008                 skip_emulated_instruction(vcpu);
5009                 vmx_fpu_activate(vcpu);
5010                 return 1;
5011         case 1: /*mov from cr*/
5012                 switch (cr) {
5013                 case 3:
5014                         val = kvm_read_cr3(vcpu);
5015                         kvm_register_write(vcpu, reg, val);
5016                         trace_kvm_cr_read(cr, val);
5017                         skip_emulated_instruction(vcpu);
5018                         return 1;
5019                 case 8:
5020                         val = kvm_get_cr8(vcpu);
5021                         kvm_register_write(vcpu, reg, val);
5022                         trace_kvm_cr_read(cr, val);
5023                         skip_emulated_instruction(vcpu);
5024                         return 1;
5025                 }
5026                 break;
5027         case 3: /* lmsw */
5028                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5029                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5030                 kvm_lmsw(vcpu, val);
5031
5032                 skip_emulated_instruction(vcpu);
5033                 return 1;
5034         default:
5035                 break;
5036         }
5037         vcpu->run->exit_reason = 0;
5038         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5039                (int)(exit_qualification >> 4) & 3, cr);
5040         return 0;
5041 }
5042
5043 static int handle_dr(struct kvm_vcpu *vcpu)
5044 {
5045         unsigned long exit_qualification;
5046         int dr, reg;
5047
5048         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5049         if (!kvm_require_cpl(vcpu, 0))
5050                 return 1;
5051         dr = vmcs_readl(GUEST_DR7);
5052         if (dr & DR7_GD) {
5053                 /*
5054                  * As the vm-exit takes precedence over the debug trap, we
5055                  * need to emulate the latter, either for the host or the
5056                  * guest debugging itself.
5057                  */
5058                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5059                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5060                         vcpu->run->debug.arch.dr7 = dr;
5061                         vcpu->run->debug.arch.pc =
5062                                 vmcs_readl(GUEST_CS_BASE) +
5063                                 vmcs_readl(GUEST_RIP);
5064                         vcpu->run->debug.arch.exception = DB_VECTOR;
5065                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5066                         return 0;
5067                 } else {
5068                         vcpu->arch.dr7 &= ~DR7_GD;
5069                         vcpu->arch.dr6 |= DR6_BD;
5070                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5071                         kvm_queue_exception(vcpu, DB_VECTOR);
5072                         return 1;
5073                 }
5074         }
5075
5076         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5077         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5078         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5079         if (exit_qualification & TYPE_MOV_FROM_DR) {
5080                 unsigned long val;
5081                 if (!kvm_get_dr(vcpu, dr, &val))
5082                         kvm_register_write(vcpu, reg, val);
5083         } else
5084                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
5085         skip_emulated_instruction(vcpu);
5086         return 1;
5087 }
5088
5089 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5090 {
5091         vmcs_writel(GUEST_DR7, val);
5092 }
5093
5094 static int handle_cpuid(struct kvm_vcpu *vcpu)
5095 {
5096         kvm_emulate_cpuid(vcpu);
5097         return 1;
5098 }
5099
5100 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5101 {
5102         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5103         u64 data;
5104
5105         if (vmx_get_msr(vcpu, ecx, &data)) {
5106                 trace_kvm_msr_read_ex(ecx);
5107                 kvm_inject_gp(vcpu, 0);
5108                 return 1;
5109         }
5110
5111         trace_kvm_msr_read(ecx, data);
5112
5113         /* FIXME: handling of bits 32:63 of rax, rdx */
5114         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5115         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5116         skip_emulated_instruction(vcpu);
5117         return 1;
5118 }
5119
5120 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5121 {
5122         struct msr_data msr;
5123         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5124         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5125                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5126
5127         msr.data = data;
5128         msr.index = ecx;
5129         msr.host_initiated = false;
5130         if (vmx_set_msr(vcpu, &msr) != 0) {
5131                 trace_kvm_msr_write_ex(ecx, data);
5132                 kvm_inject_gp(vcpu, 0);
5133                 return 1;
5134         }
5135
5136         trace_kvm_msr_write(ecx, data);
5137         skip_emulated_instruction(vcpu);
5138         return 1;
5139 }
5140
5141 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5142 {
5143         kvm_make_request(KVM_REQ_EVENT, vcpu);
5144         return 1;
5145 }
5146
5147 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5148 {
5149         u32 cpu_based_vm_exec_control;
5150
5151         /* clear pending irq */
5152         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5153         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5154         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5155
5156         kvm_make_request(KVM_REQ_EVENT, vcpu);
5157
5158         ++vcpu->stat.irq_window_exits;
5159
5160         /*
5161          * If the user space waits to inject interrupts, exit as soon as
5162          * possible
5163          */
5164         if (!irqchip_in_kernel(vcpu->kvm) &&
5165             vcpu->run->request_interrupt_window &&
5166             !kvm_cpu_has_interrupt(vcpu)) {
5167                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5168                 return 0;
5169         }
5170         return 1;
5171 }
5172
5173 static int handle_halt(struct kvm_vcpu *vcpu)
5174 {
5175         skip_emulated_instruction(vcpu);
5176         return kvm_emulate_halt(vcpu);
5177 }
5178
5179 static int handle_vmcall(struct kvm_vcpu *vcpu)
5180 {
5181         skip_emulated_instruction(vcpu);
5182         kvm_emulate_hypercall(vcpu);
5183         return 1;
5184 }
5185
5186 static int handle_invd(struct kvm_vcpu *vcpu)
5187 {
5188         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5189 }
5190
5191 static int handle_invlpg(struct kvm_vcpu *vcpu)
5192 {
5193         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5194
5195         kvm_mmu_invlpg(vcpu, exit_qualification);
5196         skip_emulated_instruction(vcpu);
5197         return 1;
5198 }
5199
5200 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5201 {
5202         int err;
5203
5204         err = kvm_rdpmc(vcpu);
5205         kvm_complete_insn_gp(vcpu, err);
5206
5207         return 1;
5208 }
5209
5210 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5211 {
5212         skip_emulated_instruction(vcpu);
5213         kvm_emulate_wbinvd(vcpu);
5214         return 1;
5215 }
5216
5217 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5218 {
5219         u64 new_bv = kvm_read_edx_eax(vcpu);
5220         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5221
5222         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5223                 skip_emulated_instruction(vcpu);
5224         return 1;
5225 }
5226
5227 static int handle_apic_access(struct kvm_vcpu *vcpu)
5228 {
5229         if (likely(fasteoi)) {
5230                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5231                 int access_type, offset;
5232
5233                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5234                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5235                 /*
5236                  * Sane guest uses MOV to write EOI, with written value
5237                  * not cared. So make a short-circuit here by avoiding
5238                  * heavy instruction emulation.
5239                  */
5240                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5241                     (offset == APIC_EOI)) {
5242                         kvm_lapic_set_eoi(vcpu);
5243                         skip_emulated_instruction(vcpu);
5244                         return 1;
5245                 }
5246         }
5247         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5248 }
5249
5250 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5251 {
5252         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5253         int vector = exit_qualification & 0xff;
5254
5255         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5256         kvm_apic_set_eoi_accelerated(vcpu, vector);
5257         return 1;
5258 }
5259
5260 static int handle_apic_write(struct kvm_vcpu *vcpu)
5261 {
5262         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5263         u32 offset = exit_qualification & 0xfff;
5264
5265         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5266         kvm_apic_write_nodecode(vcpu, offset);
5267         return 1;
5268 }
5269
5270 static int handle_task_switch(struct kvm_vcpu *vcpu)
5271 {
5272         struct vcpu_vmx *vmx = to_vmx(vcpu);
5273         unsigned long exit_qualification;
5274         bool has_error_code = false;
5275         u32 error_code = 0;
5276         u16 tss_selector;
5277         int reason, type, idt_v, idt_index;
5278
5279         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5280         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5281         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5282
5283         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5284
5285         reason = (u32)exit_qualification >> 30;
5286         if (reason == TASK_SWITCH_GATE && idt_v) {
5287                 switch (type) {
5288                 case INTR_TYPE_NMI_INTR:
5289                         vcpu->arch.nmi_injected = false;
5290                         vmx_set_nmi_mask(vcpu, true);
5291                         break;
5292                 case INTR_TYPE_EXT_INTR:
5293                 case INTR_TYPE_SOFT_INTR:
5294                         kvm_clear_interrupt_queue(vcpu);
5295                         break;
5296                 case INTR_TYPE_HARD_EXCEPTION:
5297                         if (vmx->idt_vectoring_info &
5298                             VECTORING_INFO_DELIVER_CODE_MASK) {
5299                                 has_error_code = true;
5300                                 error_code =
5301                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5302                         }
5303                         /* fall through */
5304                 case INTR_TYPE_SOFT_EXCEPTION:
5305                         kvm_clear_exception_queue(vcpu);
5306                         break;
5307                 default:
5308                         break;
5309                 }
5310         }
5311         tss_selector = exit_qualification;
5312
5313         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5314                        type != INTR_TYPE_EXT_INTR &&
5315                        type != INTR_TYPE_NMI_INTR))
5316                 skip_emulated_instruction(vcpu);
5317
5318         if (kvm_task_switch(vcpu, tss_selector,
5319                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5320                             has_error_code, error_code) == EMULATE_FAIL) {
5321                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5322                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5323                 vcpu->run->internal.ndata = 0;
5324                 return 0;
5325         }
5326
5327         /* clear all local breakpoint enable flags */
5328         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5329
5330         /*
5331          * TODO: What about debug traps on tss switch?
5332          *       Are we supposed to inject them and update dr6?
5333          */
5334
5335         return 1;
5336 }
5337
5338 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5339 {
5340         unsigned long exit_qualification;
5341         gpa_t gpa;
5342         u32 error_code;
5343         int gla_validity;
5344
5345         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5346
5347         gla_validity = (exit_qualification >> 7) & 0x3;
5348         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5349                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5350                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5351                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5352                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5353                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5354                         (long unsigned int)exit_qualification);
5355                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5356                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5357                 return 0;
5358         }
5359
5360         /*
5361          * EPT violation happened while executing iret from NMI,
5362          * "blocked by NMI" bit has to be set before next VM entry.
5363          * There are errata that may cause this bit to not be set:
5364          * AAK134, BY25.
5365          */
5366         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5367                         cpu_has_virtual_nmis() &&
5368                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5369                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5370
5371         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5372         trace_kvm_page_fault(gpa, exit_qualification);
5373
5374         /* It is a write fault? */
5375         error_code = exit_qualification & (1U << 1);
5376         /* It is a fetch fault? */
5377         error_code |= (exit_qualification & (1U << 2)) << 2;
5378         /* ept page table is present? */
5379         error_code |= (exit_qualification >> 3) & 0x1;
5380
5381         vcpu->arch.exit_qualification = exit_qualification;
5382
5383         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5384 }
5385
5386 static u64 ept_rsvd_mask(u64 spte, int level)
5387 {
5388         int i;
5389         u64 mask = 0;
5390
5391         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5392                 mask |= (1ULL << i);
5393
5394         if (level > 2)
5395                 /* bits 7:3 reserved */
5396                 mask |= 0xf8;
5397         else if (level == 2) {
5398                 if (spte & (1ULL << 7))
5399                         /* 2MB ref, bits 20:12 reserved */
5400                         mask |= 0x1ff000;
5401                 else
5402                         /* bits 6:3 reserved */
5403                         mask |= 0x78;
5404         }
5405
5406         return mask;
5407 }
5408
5409 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5410                                        int level)
5411 {
5412         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5413
5414         /* 010b (write-only) */
5415         WARN_ON((spte & 0x7) == 0x2);
5416
5417         /* 110b (write/execute) */
5418         WARN_ON((spte & 0x7) == 0x6);
5419
5420         /* 100b (execute-only) and value not supported by logical processor */
5421         if (!cpu_has_vmx_ept_execute_only())
5422                 WARN_ON((spte & 0x7) == 0x4);
5423
5424         /* not 000b */
5425         if ((spte & 0x7)) {
5426                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5427
5428                 if (rsvd_bits != 0) {
5429                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5430                                          __func__, rsvd_bits);
5431                         WARN_ON(1);
5432                 }
5433
5434                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5435                         u64 ept_mem_type = (spte & 0x38) >> 3;
5436
5437                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5438                             ept_mem_type == 7) {
5439                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5440                                                 __func__, ept_mem_type);
5441                                 WARN_ON(1);
5442                         }
5443                 }
5444         }
5445 }
5446
5447 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5448 {
5449         u64 sptes[4];
5450         int nr_sptes, i, ret;
5451         gpa_t gpa;
5452
5453         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5454
5455         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5456         if (likely(ret == RET_MMIO_PF_EMULATE))
5457                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5458                                               EMULATE_DONE;
5459
5460         if (unlikely(ret == RET_MMIO_PF_INVALID))
5461                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5462
5463         if (unlikely(ret == RET_MMIO_PF_RETRY))
5464                 return 1;
5465
5466         /* It is the real ept misconfig */
5467         printk(KERN_ERR "EPT: Misconfiguration.\n");
5468         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5469
5470         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5471
5472         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5473                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5474
5475         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5476         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5477
5478         return 0;
5479 }
5480
5481 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5482 {
5483         u32 cpu_based_vm_exec_control;
5484
5485         /* clear pending NMI */
5486         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5487         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5488         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5489         ++vcpu->stat.nmi_window_exits;
5490         kvm_make_request(KVM_REQ_EVENT, vcpu);
5491
5492         return 1;
5493 }
5494
5495 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5496 {
5497         struct vcpu_vmx *vmx = to_vmx(vcpu);
5498         enum emulation_result err = EMULATE_DONE;
5499         int ret = 1;
5500         u32 cpu_exec_ctrl;
5501         bool intr_window_requested;
5502         unsigned count = 130;
5503
5504         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5505         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5506
5507         while (!guest_state_valid(vcpu) && count-- != 0) {
5508                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5509                         return handle_interrupt_window(&vmx->vcpu);
5510
5511                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5512                         return 1;
5513
5514                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5515
5516                 if (err == EMULATE_USER_EXIT) {
5517                         ++vcpu->stat.mmio_exits;
5518                         ret = 0;
5519                         goto out;
5520                 }
5521
5522                 if (err != EMULATE_DONE) {
5523                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5524                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5525                         vcpu->run->internal.ndata = 0;
5526                         return 0;
5527                 }
5528
5529                 if (vcpu->arch.halt_request) {
5530                         vcpu->arch.halt_request = 0;
5531                         ret = kvm_emulate_halt(vcpu);
5532                         goto out;
5533                 }
5534
5535                 if (signal_pending(current))
5536                         goto out;
5537                 if (need_resched())
5538                         schedule();
5539         }
5540
5541         vmx->emulation_required = emulation_required(vcpu);
5542 out:
5543         return ret;
5544 }
5545
5546 /*
5547  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5548  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5549  */
5550 static int handle_pause(struct kvm_vcpu *vcpu)
5551 {
5552         skip_emulated_instruction(vcpu);
5553         kvm_vcpu_on_spin(vcpu);
5554
5555         return 1;
5556 }
5557
5558 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5559 {
5560         kvm_queue_exception(vcpu, UD_VECTOR);
5561         return 1;
5562 }
5563
5564 /*
5565  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5566  * We could reuse a single VMCS for all the L2 guests, but we also want the
5567  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5568  * allows keeping them loaded on the processor, and in the future will allow
5569  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5570  * every entry if they never change.
5571  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5572  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5573  *
5574  * The following functions allocate and free a vmcs02 in this pool.
5575  */
5576
5577 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5578 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5579 {
5580         struct vmcs02_list *item;
5581         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5582                 if (item->vmptr == vmx->nested.current_vmptr) {
5583                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5584                         return &item->vmcs02;
5585                 }
5586
5587         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5588                 /* Recycle the least recently used VMCS. */
5589                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5590                         struct vmcs02_list, list);
5591                 item->vmptr = vmx->nested.current_vmptr;
5592                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5593                 return &item->vmcs02;
5594         }
5595
5596         /* Create a new VMCS */
5597         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5598         if (!item)
5599                 return NULL;
5600         item->vmcs02.vmcs = alloc_vmcs();
5601         if (!item->vmcs02.vmcs) {
5602                 kfree(item);
5603                 return NULL;
5604         }
5605         loaded_vmcs_init(&item->vmcs02);
5606         item->vmptr = vmx->nested.current_vmptr;
5607         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5608         vmx->nested.vmcs02_num++;
5609         return &item->vmcs02;
5610 }
5611
5612 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5613 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5614 {
5615         struct vmcs02_list *item;
5616         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5617                 if (item->vmptr == vmptr) {
5618                         free_loaded_vmcs(&item->vmcs02);
5619                         list_del(&item->list);
5620                         kfree(item);
5621                         vmx->nested.vmcs02_num--;
5622                         return;
5623                 }
5624 }
5625
5626 /*
5627  * Free all VMCSs saved for this vcpu, except the one pointed by
5628  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5629  * currently used, if running L2), and vmcs01 when running L2.
5630  */
5631 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5632 {
5633         struct vmcs02_list *item, *n;
5634         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5635                 if (vmx->loaded_vmcs != &item->vmcs02)
5636                         free_loaded_vmcs(&item->vmcs02);
5637                 list_del(&item->list);
5638                 kfree(item);
5639         }
5640         vmx->nested.vmcs02_num = 0;
5641
5642         if (vmx->loaded_vmcs != &vmx->vmcs01)
5643                 free_loaded_vmcs(&vmx->vmcs01);
5644 }
5645
5646 /*
5647  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5648  * set the success or error code of an emulated VMX instruction, as specified
5649  * by Vol 2B, VMX Instruction Reference, "Conventions".
5650  */
5651 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5652 {
5653         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5654                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5655                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5656 }
5657
5658 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5659 {
5660         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5661                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5662                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5663                         | X86_EFLAGS_CF);
5664 }
5665
5666 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5667                                         u32 vm_instruction_error)
5668 {
5669         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5670                 /*
5671                  * failValid writes the error number to the current VMCS, which
5672                  * can't be done there isn't a current VMCS.
5673                  */
5674                 nested_vmx_failInvalid(vcpu);
5675                 return;
5676         }
5677         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5678                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5679                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5680                         | X86_EFLAGS_ZF);
5681         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5682         /*
5683          * We don't need to force a shadow sync because
5684          * VM_INSTRUCTION_ERROR is not shadowed
5685          */
5686 }
5687
5688 /*
5689  * Emulate the VMXON instruction.
5690  * Currently, we just remember that VMX is active, and do not save or even
5691  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5692  * do not currently need to store anything in that guest-allocated memory
5693  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5694  * argument is different from the VMXON pointer (which the spec says they do).
5695  */
5696 static int handle_vmon(struct kvm_vcpu *vcpu)
5697 {
5698         struct kvm_segment cs;
5699         struct vcpu_vmx *vmx = to_vmx(vcpu);
5700         struct vmcs *shadow_vmcs;
5701         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5702                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5703
5704         /* The Intel VMX Instruction Reference lists a bunch of bits that
5705          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5706          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5707          * Otherwise, we should fail with #UD. We test these now:
5708          */
5709         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5710             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5711             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5712                 kvm_queue_exception(vcpu, UD_VECTOR);
5713                 return 1;
5714         }
5715
5716         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5717         if (is_long_mode(vcpu) && !cs.l) {
5718                 kvm_queue_exception(vcpu, UD_VECTOR);
5719                 return 1;
5720         }
5721
5722         if (vmx_get_cpl(vcpu)) {
5723                 kvm_inject_gp(vcpu, 0);
5724                 return 1;
5725         }
5726         if (vmx->nested.vmxon) {
5727                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5728                 skip_emulated_instruction(vcpu);
5729                 return 1;
5730         }
5731
5732         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5733                         != VMXON_NEEDED_FEATURES) {
5734                 kvm_inject_gp(vcpu, 0);
5735                 return 1;
5736         }
5737
5738         if (enable_shadow_vmcs) {
5739                 shadow_vmcs = alloc_vmcs();
5740                 if (!shadow_vmcs)
5741                         return -ENOMEM;
5742                 /* mark vmcs as shadow */
5743                 shadow_vmcs->revision_id |= (1u << 31);
5744                 /* init shadow vmcs */
5745                 vmcs_clear(shadow_vmcs);
5746                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5747         }
5748
5749         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5750         vmx->nested.vmcs02_num = 0;
5751
5752         vmx->nested.vmxon = true;
5753
5754         skip_emulated_instruction(vcpu);
5755         nested_vmx_succeed(vcpu);
5756         return 1;
5757 }
5758
5759 /*
5760  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5761  * for running VMX instructions (except VMXON, whose prerequisites are
5762  * slightly different). It also specifies what exception to inject otherwise.
5763  */
5764 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5765 {
5766         struct kvm_segment cs;
5767         struct vcpu_vmx *vmx = to_vmx(vcpu);
5768
5769         if (!vmx->nested.vmxon) {
5770                 kvm_queue_exception(vcpu, UD_VECTOR);
5771                 return 0;
5772         }
5773
5774         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5775         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5776             (is_long_mode(vcpu) && !cs.l)) {
5777                 kvm_queue_exception(vcpu, UD_VECTOR);
5778                 return 0;
5779         }
5780
5781         if (vmx_get_cpl(vcpu)) {
5782                 kvm_inject_gp(vcpu, 0);
5783                 return 0;
5784         }
5785
5786         return 1;
5787 }
5788
5789 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5790 {
5791         u32 exec_control;
5792         if (enable_shadow_vmcs) {
5793                 if (vmx->nested.current_vmcs12 != NULL) {
5794                         /* copy to memory all shadowed fields in case
5795                            they were modified */
5796                         copy_shadow_to_vmcs12(vmx);
5797                         vmx->nested.sync_shadow_vmcs = false;
5798                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5799                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5800                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5801                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5802                 }
5803         }
5804         kunmap(vmx->nested.current_vmcs12_page);
5805         nested_release_page(vmx->nested.current_vmcs12_page);
5806 }
5807
5808 /*
5809  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5810  * just stops using VMX.
5811  */
5812 static void free_nested(struct vcpu_vmx *vmx)
5813 {
5814         if (!vmx->nested.vmxon)
5815                 return;
5816         vmx->nested.vmxon = false;
5817         if (vmx->nested.current_vmptr != -1ull) {
5818                 nested_release_vmcs12(vmx);
5819                 vmx->nested.current_vmptr = -1ull;
5820                 vmx->nested.current_vmcs12 = NULL;
5821         }
5822         if (enable_shadow_vmcs)
5823                 free_vmcs(vmx->nested.current_shadow_vmcs);
5824         /* Unpin physical memory we referred to in current vmcs02 */
5825         if (vmx->nested.apic_access_page) {
5826                 nested_release_page(vmx->nested.apic_access_page);
5827                 vmx->nested.apic_access_page = 0;
5828         }
5829
5830         nested_free_all_saved_vmcss(vmx);
5831 }
5832
5833 /* Emulate the VMXOFF instruction */
5834 static int handle_vmoff(struct kvm_vcpu *vcpu)
5835 {
5836         if (!nested_vmx_check_permission(vcpu))
5837                 return 1;
5838         free_nested(to_vmx(vcpu));
5839         skip_emulated_instruction(vcpu);
5840         nested_vmx_succeed(vcpu);
5841         return 1;
5842 }
5843
5844 /*
5845  * Decode the memory-address operand of a vmx instruction, as recorded on an
5846  * exit caused by such an instruction (run by a guest hypervisor).
5847  * On success, returns 0. When the operand is invalid, returns 1 and throws
5848  * #UD or #GP.
5849  */
5850 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5851                                  unsigned long exit_qualification,
5852                                  u32 vmx_instruction_info, gva_t *ret)
5853 {
5854         /*
5855          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5856          * Execution", on an exit, vmx_instruction_info holds most of the
5857          * addressing components of the operand. Only the displacement part
5858          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5859          * For how an actual address is calculated from all these components,
5860          * refer to Vol. 1, "Operand Addressing".
5861          */
5862         int  scaling = vmx_instruction_info & 3;
5863         int  addr_size = (vmx_instruction_info >> 7) & 7;
5864         bool is_reg = vmx_instruction_info & (1u << 10);
5865         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5866         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5867         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5868         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5869         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5870
5871         if (is_reg) {
5872                 kvm_queue_exception(vcpu, UD_VECTOR);
5873                 return 1;
5874         }
5875
5876         /* Addr = segment_base + offset */
5877         /* offset = base + [index * scale] + displacement */
5878         *ret = vmx_get_segment_base(vcpu, seg_reg);
5879         if (base_is_valid)
5880                 *ret += kvm_register_read(vcpu, base_reg);
5881         if (index_is_valid)
5882                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5883         *ret += exit_qualification; /* holds the displacement */
5884
5885         if (addr_size == 1) /* 32 bit */
5886                 *ret &= 0xffffffff;
5887
5888         /*
5889          * TODO: throw #GP (and return 1) in various cases that the VM*
5890          * instructions require it - e.g., offset beyond segment limit,
5891          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5892          * address, and so on. Currently these are not checked.
5893          */
5894         return 0;
5895 }
5896
5897 /* Emulate the VMCLEAR instruction */
5898 static int handle_vmclear(struct kvm_vcpu *vcpu)
5899 {
5900         struct vcpu_vmx *vmx = to_vmx(vcpu);
5901         gva_t gva;
5902         gpa_t vmptr;
5903         struct vmcs12 *vmcs12;
5904         struct page *page;
5905         struct x86_exception e;
5906
5907         if (!nested_vmx_check_permission(vcpu))
5908                 return 1;
5909
5910         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5911                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5912                 return 1;
5913
5914         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5915                                 sizeof(vmptr), &e)) {
5916                 kvm_inject_page_fault(vcpu, &e);
5917                 return 1;
5918         }
5919
5920         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5921                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5922                 skip_emulated_instruction(vcpu);
5923                 return 1;
5924         }
5925
5926         if (vmptr == vmx->nested.current_vmptr) {
5927                 nested_release_vmcs12(vmx);
5928                 vmx->nested.current_vmptr = -1ull;
5929                 vmx->nested.current_vmcs12 = NULL;
5930         }
5931
5932         page = nested_get_page(vcpu, vmptr);
5933         if (page == NULL) {
5934                 /*
5935                  * For accurate processor emulation, VMCLEAR beyond available
5936                  * physical memory should do nothing at all. However, it is
5937                  * possible that a nested vmx bug, not a guest hypervisor bug,
5938                  * resulted in this case, so let's shut down before doing any
5939                  * more damage:
5940                  */
5941                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5942                 return 1;
5943         }
5944         vmcs12 = kmap(page);
5945         vmcs12->launch_state = 0;
5946         kunmap(page);
5947         nested_release_page(page);
5948
5949         nested_free_vmcs02(vmx, vmptr);
5950
5951         skip_emulated_instruction(vcpu);
5952         nested_vmx_succeed(vcpu);
5953         return 1;
5954 }
5955
5956 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5957
5958 /* Emulate the VMLAUNCH instruction */
5959 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5960 {
5961         return nested_vmx_run(vcpu, true);
5962 }
5963
5964 /* Emulate the VMRESUME instruction */
5965 static int handle_vmresume(struct kvm_vcpu *vcpu)
5966 {
5967
5968         return nested_vmx_run(vcpu, false);
5969 }
5970
5971 enum vmcs_field_type {
5972         VMCS_FIELD_TYPE_U16 = 0,
5973         VMCS_FIELD_TYPE_U64 = 1,
5974         VMCS_FIELD_TYPE_U32 = 2,
5975         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5976 };
5977
5978 static inline int vmcs_field_type(unsigned long field)
5979 {
5980         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5981                 return VMCS_FIELD_TYPE_U32;
5982         return (field >> 13) & 0x3 ;
5983 }
5984
5985 static inline int vmcs_field_readonly(unsigned long field)
5986 {
5987         return (((field >> 10) & 0x3) == 1);
5988 }
5989
5990 /*
5991  * Read a vmcs12 field. Since these can have varying lengths and we return
5992  * one type, we chose the biggest type (u64) and zero-extend the return value
5993  * to that size. Note that the caller, handle_vmread, might need to use only
5994  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5995  * 64-bit fields are to be returned).
5996  */
5997 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5998                                         unsigned long field, u64 *ret)
5999 {
6000         short offset = vmcs_field_to_offset(field);
6001         char *p;
6002
6003         if (offset < 0)
6004                 return 0;
6005
6006         p = ((char *)(get_vmcs12(vcpu))) + offset;
6007
6008         switch (vmcs_field_type(field)) {
6009         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6010                 *ret = *((natural_width *)p);
6011                 return 1;
6012         case VMCS_FIELD_TYPE_U16:
6013                 *ret = *((u16 *)p);
6014                 return 1;
6015         case VMCS_FIELD_TYPE_U32:
6016                 *ret = *((u32 *)p);
6017                 return 1;
6018         case VMCS_FIELD_TYPE_U64:
6019                 *ret = *((u64 *)p);
6020                 return 1;
6021         default:
6022                 return 0; /* can never happen. */
6023         }
6024 }
6025
6026
6027 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6028                                     unsigned long field, u64 field_value){
6029         short offset = vmcs_field_to_offset(field);
6030         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6031         if (offset < 0)
6032                 return false;
6033
6034         switch (vmcs_field_type(field)) {
6035         case VMCS_FIELD_TYPE_U16:
6036                 *(u16 *)p = field_value;
6037                 return true;
6038         case VMCS_FIELD_TYPE_U32:
6039                 *(u32 *)p = field_value;
6040                 return true;
6041         case VMCS_FIELD_TYPE_U64:
6042                 *(u64 *)p = field_value;
6043                 return true;
6044         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6045                 *(natural_width *)p = field_value;
6046                 return true;
6047         default:
6048                 return false; /* can never happen. */
6049         }
6050
6051 }
6052
6053 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6054 {
6055         int i;
6056         unsigned long field;
6057         u64 field_value;
6058         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6059         const unsigned long *fields = shadow_read_write_fields;
6060         const int num_fields = max_shadow_read_write_fields;
6061
6062         vmcs_load(shadow_vmcs);
6063
6064         for (i = 0; i < num_fields; i++) {
6065                 field = fields[i];
6066                 switch (vmcs_field_type(field)) {
6067                 case VMCS_FIELD_TYPE_U16:
6068                         field_value = vmcs_read16(field);
6069                         break;
6070                 case VMCS_FIELD_TYPE_U32:
6071                         field_value = vmcs_read32(field);
6072                         break;
6073                 case VMCS_FIELD_TYPE_U64:
6074                         field_value = vmcs_read64(field);
6075                         break;
6076                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6077                         field_value = vmcs_readl(field);
6078                         break;
6079                 }
6080                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6081         }
6082
6083         vmcs_clear(shadow_vmcs);
6084         vmcs_load(vmx->loaded_vmcs->vmcs);
6085 }
6086
6087 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6088 {
6089         const unsigned long *fields[] = {
6090                 shadow_read_write_fields,
6091                 shadow_read_only_fields
6092         };
6093         const int max_fields[] = {
6094                 max_shadow_read_write_fields,
6095                 max_shadow_read_only_fields
6096         };
6097         int i, q;
6098         unsigned long field;
6099         u64 field_value = 0;
6100         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6101
6102         vmcs_load(shadow_vmcs);
6103
6104         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6105                 for (i = 0; i < max_fields[q]; i++) {
6106                         field = fields[q][i];
6107                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6108
6109                         switch (vmcs_field_type(field)) {
6110                         case VMCS_FIELD_TYPE_U16:
6111                                 vmcs_write16(field, (u16)field_value);
6112                                 break;
6113                         case VMCS_FIELD_TYPE_U32:
6114                                 vmcs_write32(field, (u32)field_value);
6115                                 break;
6116                         case VMCS_FIELD_TYPE_U64:
6117                                 vmcs_write64(field, (u64)field_value);
6118                                 break;
6119                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6120                                 vmcs_writel(field, (long)field_value);
6121                                 break;
6122                         }
6123                 }
6124         }
6125
6126         vmcs_clear(shadow_vmcs);
6127         vmcs_load(vmx->loaded_vmcs->vmcs);
6128 }
6129
6130 /*
6131  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6132  * used before) all generate the same failure when it is missing.
6133  */
6134 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6135 {
6136         struct vcpu_vmx *vmx = to_vmx(vcpu);
6137         if (vmx->nested.current_vmptr == -1ull) {
6138                 nested_vmx_failInvalid(vcpu);
6139                 skip_emulated_instruction(vcpu);
6140                 return 0;
6141         }
6142         return 1;
6143 }
6144
6145 static int handle_vmread(struct kvm_vcpu *vcpu)
6146 {
6147         unsigned long field;
6148         u64 field_value;
6149         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6150         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6151         gva_t gva = 0;
6152
6153         if (!nested_vmx_check_permission(vcpu) ||
6154             !nested_vmx_check_vmcs12(vcpu))
6155                 return 1;
6156
6157         /* Decode instruction info and find the field to read */
6158         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6159         /* Read the field, zero-extended to a u64 field_value */
6160         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6161                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6162                 skip_emulated_instruction(vcpu);
6163                 return 1;
6164         }
6165         /*
6166          * Now copy part of this value to register or memory, as requested.
6167          * Note that the number of bits actually copied is 32 or 64 depending
6168          * on the guest's mode (32 or 64 bit), not on the given field's length.
6169          */
6170         if (vmx_instruction_info & (1u << 10)) {
6171                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6172                         field_value);
6173         } else {
6174                 if (get_vmx_mem_address(vcpu, exit_qualification,
6175                                 vmx_instruction_info, &gva))
6176                         return 1;
6177                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6178                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6179                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6180         }
6181
6182         nested_vmx_succeed(vcpu);
6183         skip_emulated_instruction(vcpu);
6184         return 1;
6185 }
6186
6187
6188 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6189 {
6190         unsigned long field;
6191         gva_t gva;
6192         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6193         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6194         /* The value to write might be 32 or 64 bits, depending on L1's long
6195          * mode, and eventually we need to write that into a field of several
6196          * possible lengths. The code below first zero-extends the value to 64
6197          * bit (field_value), and then copies only the approriate number of
6198          * bits into the vmcs12 field.
6199          */
6200         u64 field_value = 0;
6201         struct x86_exception e;
6202
6203         if (!nested_vmx_check_permission(vcpu) ||
6204             !nested_vmx_check_vmcs12(vcpu))
6205                 return 1;
6206
6207         if (vmx_instruction_info & (1u << 10))
6208                 field_value = kvm_register_read(vcpu,
6209                         (((vmx_instruction_info) >> 3) & 0xf));
6210         else {
6211                 if (get_vmx_mem_address(vcpu, exit_qualification,
6212                                 vmx_instruction_info, &gva))
6213                         return 1;
6214                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6215                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6216                         kvm_inject_page_fault(vcpu, &e);
6217                         return 1;
6218                 }
6219         }
6220
6221
6222         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6223         if (vmcs_field_readonly(field)) {
6224                 nested_vmx_failValid(vcpu,
6225                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6226                 skip_emulated_instruction(vcpu);
6227                 return 1;
6228         }
6229
6230         if (!vmcs12_write_any(vcpu, field, field_value)) {
6231                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6232                 skip_emulated_instruction(vcpu);
6233                 return 1;
6234         }
6235
6236         nested_vmx_succeed(vcpu);
6237         skip_emulated_instruction(vcpu);
6238         return 1;
6239 }
6240
6241 /* Emulate the VMPTRLD instruction */
6242 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6243 {
6244         struct vcpu_vmx *vmx = to_vmx(vcpu);
6245         gva_t gva;
6246         gpa_t vmptr;
6247         struct x86_exception e;
6248         u32 exec_control;
6249
6250         if (!nested_vmx_check_permission(vcpu))
6251                 return 1;
6252
6253         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6254                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6255                 return 1;
6256
6257         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6258                                 sizeof(vmptr), &e)) {
6259                 kvm_inject_page_fault(vcpu, &e);
6260                 return 1;
6261         }
6262
6263         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6264                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6265                 skip_emulated_instruction(vcpu);
6266                 return 1;
6267         }
6268
6269         if (vmx->nested.current_vmptr != vmptr) {
6270                 struct vmcs12 *new_vmcs12;
6271                 struct page *page;
6272                 page = nested_get_page(vcpu, vmptr);
6273                 if (page == NULL) {
6274                         nested_vmx_failInvalid(vcpu);
6275                         skip_emulated_instruction(vcpu);
6276                         return 1;
6277                 }
6278                 new_vmcs12 = kmap(page);
6279                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6280                         kunmap(page);
6281                         nested_release_page_clean(page);
6282                         nested_vmx_failValid(vcpu,
6283                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6284                         skip_emulated_instruction(vcpu);
6285                         return 1;
6286                 }
6287                 if (vmx->nested.current_vmptr != -1ull)
6288                         nested_release_vmcs12(vmx);
6289
6290                 vmx->nested.current_vmptr = vmptr;
6291                 vmx->nested.current_vmcs12 = new_vmcs12;
6292                 vmx->nested.current_vmcs12_page = page;
6293                 if (enable_shadow_vmcs) {
6294                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6295                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6296                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6297                         vmcs_write64(VMCS_LINK_POINTER,
6298                                      __pa(vmx->nested.current_shadow_vmcs));
6299                         vmx->nested.sync_shadow_vmcs = true;
6300                 }
6301         }
6302
6303         nested_vmx_succeed(vcpu);
6304         skip_emulated_instruction(vcpu);
6305         return 1;
6306 }
6307
6308 /* Emulate the VMPTRST instruction */
6309 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6310 {
6311         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6312         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6313         gva_t vmcs_gva;
6314         struct x86_exception e;
6315
6316         if (!nested_vmx_check_permission(vcpu))
6317                 return 1;
6318
6319         if (get_vmx_mem_address(vcpu, exit_qualification,
6320                         vmx_instruction_info, &vmcs_gva))
6321                 return 1;
6322         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6323         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6324                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6325                                  sizeof(u64), &e)) {
6326                 kvm_inject_page_fault(vcpu, &e);
6327                 return 1;
6328         }
6329         nested_vmx_succeed(vcpu);
6330         skip_emulated_instruction(vcpu);
6331         return 1;
6332 }
6333
6334 /* Emulate the INVEPT instruction */
6335 static int handle_invept(struct kvm_vcpu *vcpu)
6336 {
6337         u32 vmx_instruction_info, types;
6338         unsigned long type;
6339         gva_t gva;
6340         struct x86_exception e;
6341         struct {
6342                 u64 eptp, gpa;
6343         } operand;
6344         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6345
6346         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6347             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6348                 kvm_queue_exception(vcpu, UD_VECTOR);
6349                 return 1;
6350         }
6351
6352         if (!nested_vmx_check_permission(vcpu))
6353                 return 1;
6354
6355         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6356                 kvm_queue_exception(vcpu, UD_VECTOR);
6357                 return 1;
6358         }
6359
6360         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6361         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6362
6363         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6364
6365         if (!(types & (1UL << type))) {
6366                 nested_vmx_failValid(vcpu,
6367                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6368                 return 1;
6369         }
6370
6371         /* According to the Intel VMX instruction reference, the memory
6372          * operand is read even if it isn't needed (e.g., for type==global)
6373          */
6374         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6375                         vmx_instruction_info, &gva))
6376                 return 1;
6377         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6378                                 sizeof(operand), &e)) {
6379                 kvm_inject_page_fault(vcpu, &e);
6380                 return 1;
6381         }
6382
6383         switch (type) {
6384         case VMX_EPT_EXTENT_CONTEXT:
6385                 if ((operand.eptp & eptp_mask) !=
6386                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6387                         break;
6388         case VMX_EPT_EXTENT_GLOBAL:
6389                 kvm_mmu_sync_roots(vcpu);
6390                 kvm_mmu_flush_tlb(vcpu);
6391                 nested_vmx_succeed(vcpu);
6392                 break;
6393         default:
6394                 BUG_ON(1);
6395                 break;
6396         }
6397
6398         skip_emulated_instruction(vcpu);
6399         return 1;
6400 }
6401
6402 /*
6403  * The exit handlers return 1 if the exit was handled fully and guest execution
6404  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6405  * to be done to userspace and return 0.
6406  */
6407 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6408         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6409         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6410         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6411         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6412         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6413         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6414         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6415         [EXIT_REASON_CPUID]                   = handle_cpuid,
6416         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6417         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6418         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6419         [EXIT_REASON_HLT]                     = handle_halt,
6420         [EXIT_REASON_INVD]                    = handle_invd,
6421         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6422         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6423         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6424         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6425         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6426         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6427         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6428         [EXIT_REASON_VMREAD]                  = handle_vmread,
6429         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6430         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6431         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6432         [EXIT_REASON_VMON]                    = handle_vmon,
6433         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6434         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6435         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6436         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6437         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6438         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6439         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6440         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6441         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6442         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6443         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6444         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6445         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6446         [EXIT_REASON_INVEPT]                  = handle_invept,
6447 };
6448
6449 static const int kvm_vmx_max_exit_handlers =
6450         ARRAY_SIZE(kvm_vmx_exit_handlers);
6451
6452 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6453                                        struct vmcs12 *vmcs12)
6454 {
6455         unsigned long exit_qualification;
6456         gpa_t bitmap, last_bitmap;
6457         unsigned int port;
6458         int size;
6459         u8 b;
6460
6461         if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6462                 return 1;
6463
6464         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6465                 return 0;
6466
6467         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6468
6469         port = exit_qualification >> 16;
6470         size = (exit_qualification & 7) + 1;
6471
6472         last_bitmap = (gpa_t)-1;
6473         b = -1;
6474
6475         while (size > 0) {
6476                 if (port < 0x8000)
6477                         bitmap = vmcs12->io_bitmap_a;
6478                 else if (port < 0x10000)
6479                         bitmap = vmcs12->io_bitmap_b;
6480                 else
6481                         return 1;
6482                 bitmap += (port & 0x7fff) / 8;
6483
6484                 if (last_bitmap != bitmap)
6485                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6486                                 return 1;
6487                 if (b & (1 << (port & 7)))
6488                         return 1;
6489
6490                 port++;
6491                 size--;
6492                 last_bitmap = bitmap;
6493         }
6494
6495         return 0;
6496 }
6497
6498 /*
6499  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6500  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6501  * disinterest in the current event (read or write a specific MSR) by using an
6502  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6503  */
6504 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6505         struct vmcs12 *vmcs12, u32 exit_reason)
6506 {
6507         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6508         gpa_t bitmap;
6509
6510         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6511                 return 1;
6512
6513         /*
6514          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6515          * for the four combinations of read/write and low/high MSR numbers.
6516          * First we need to figure out which of the four to use:
6517          */
6518         bitmap = vmcs12->msr_bitmap;
6519         if (exit_reason == EXIT_REASON_MSR_WRITE)
6520                 bitmap += 2048;
6521         if (msr_index >= 0xc0000000) {
6522                 msr_index -= 0xc0000000;
6523                 bitmap += 1024;
6524         }
6525
6526         /* Then read the msr_index'th bit from this bitmap: */
6527         if (msr_index < 1024*8) {
6528                 unsigned char b;
6529                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6530                         return 1;
6531                 return 1 & (b >> (msr_index & 7));
6532         } else
6533                 return 1; /* let L1 handle the wrong parameter */
6534 }
6535
6536 /*
6537  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6538  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6539  * intercept (via guest_host_mask etc.) the current event.
6540  */
6541 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6542         struct vmcs12 *vmcs12)
6543 {
6544         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6545         int cr = exit_qualification & 15;
6546         int reg = (exit_qualification >> 8) & 15;
6547         unsigned long val = kvm_register_read(vcpu, reg);
6548
6549         switch ((exit_qualification >> 4) & 3) {
6550         case 0: /* mov to cr */
6551                 switch (cr) {
6552                 case 0:
6553                         if (vmcs12->cr0_guest_host_mask &
6554                             (val ^ vmcs12->cr0_read_shadow))
6555                                 return 1;
6556                         break;
6557                 case 3:
6558                         if ((vmcs12->cr3_target_count >= 1 &&
6559                                         vmcs12->cr3_target_value0 == val) ||
6560                                 (vmcs12->cr3_target_count >= 2 &&
6561                                         vmcs12->cr3_target_value1 == val) ||
6562                                 (vmcs12->cr3_target_count >= 3 &&
6563                                         vmcs12->cr3_target_value2 == val) ||
6564                                 (vmcs12->cr3_target_count >= 4 &&
6565                                         vmcs12->cr3_target_value3 == val))
6566                                 return 0;
6567                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6568                                 return 1;
6569                         break;
6570                 case 4:
6571                         if (vmcs12->cr4_guest_host_mask &
6572                             (vmcs12->cr4_read_shadow ^ val))
6573                                 return 1;
6574                         break;
6575                 case 8:
6576                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6577                                 return 1;
6578                         break;
6579                 }
6580                 break;
6581         case 2: /* clts */
6582                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6583                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6584                         return 1;
6585                 break;
6586         case 1: /* mov from cr */
6587                 switch (cr) {
6588                 case 3:
6589                         if (vmcs12->cpu_based_vm_exec_control &
6590                             CPU_BASED_CR3_STORE_EXITING)
6591                                 return 1;
6592                         break;
6593                 case 8:
6594                         if (vmcs12->cpu_based_vm_exec_control &
6595                             CPU_BASED_CR8_STORE_EXITING)
6596                                 return 1;
6597                         break;
6598                 }
6599                 break;
6600         case 3: /* lmsw */
6601                 /*
6602                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6603                  * cr0. Other attempted changes are ignored, with no exit.
6604                  */
6605                 if (vmcs12->cr0_guest_host_mask & 0xe &
6606                     (val ^ vmcs12->cr0_read_shadow))
6607                         return 1;
6608                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6609                     !(vmcs12->cr0_read_shadow & 0x1) &&
6610                     (val & 0x1))
6611                         return 1;
6612                 break;
6613         }
6614         return 0;
6615 }
6616
6617 /*
6618  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6619  * should handle it ourselves in L0 (and then continue L2). Only call this
6620  * when in is_guest_mode (L2).
6621  */
6622 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6623 {
6624         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6625         struct vcpu_vmx *vmx = to_vmx(vcpu);
6626         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6627         u32 exit_reason = vmx->exit_reason;
6628
6629         if (vmx->nested.nested_run_pending)
6630                 return 0;
6631
6632         if (unlikely(vmx->fail)) {
6633                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6634                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6635                 return 1;
6636         }
6637
6638         switch (exit_reason) {
6639         case EXIT_REASON_EXCEPTION_NMI:
6640                 if (!is_exception(intr_info))
6641                         return 0;
6642                 else if (is_page_fault(intr_info))
6643                         return enable_ept;
6644                 return vmcs12->exception_bitmap &
6645                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6646         case EXIT_REASON_EXTERNAL_INTERRUPT:
6647                 return 0;
6648         case EXIT_REASON_TRIPLE_FAULT:
6649                 return 1;
6650         case EXIT_REASON_PENDING_INTERRUPT:
6651                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6652         case EXIT_REASON_NMI_WINDOW:
6653                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6654         case EXIT_REASON_TASK_SWITCH:
6655                 return 1;
6656         case EXIT_REASON_CPUID:
6657                 return 1;
6658         case EXIT_REASON_HLT:
6659                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6660         case EXIT_REASON_INVD:
6661                 return 1;
6662         case EXIT_REASON_INVLPG:
6663                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6664         case EXIT_REASON_RDPMC:
6665                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6666         case EXIT_REASON_RDTSC:
6667                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6668         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6669         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6670         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6671         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6672         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6673         case EXIT_REASON_INVEPT:
6674                 /*
6675                  * VMX instructions trap unconditionally. This allows L1 to
6676                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6677                  */
6678                 return 1;
6679         case EXIT_REASON_CR_ACCESS:
6680                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6681         case EXIT_REASON_DR_ACCESS:
6682                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6683         case EXIT_REASON_IO_INSTRUCTION:
6684                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6685         case EXIT_REASON_MSR_READ:
6686         case EXIT_REASON_MSR_WRITE:
6687                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6688         case EXIT_REASON_INVALID_STATE:
6689                 return 1;
6690         case EXIT_REASON_MWAIT_INSTRUCTION:
6691                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6692         case EXIT_REASON_MONITOR_INSTRUCTION:
6693                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6694         case EXIT_REASON_PAUSE_INSTRUCTION:
6695                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6696                         nested_cpu_has2(vmcs12,
6697                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6698         case EXIT_REASON_MCE_DURING_VMENTRY:
6699                 return 0;
6700         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6701                 return 1;
6702         case EXIT_REASON_APIC_ACCESS:
6703                 return nested_cpu_has2(vmcs12,
6704                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6705         case EXIT_REASON_EPT_VIOLATION:
6706                 /*
6707                  * L0 always deals with the EPT violation. If nested EPT is
6708                  * used, and the nested mmu code discovers that the address is
6709                  * missing in the guest EPT table (EPT12), the EPT violation
6710                  * will be injected with nested_ept_inject_page_fault()
6711                  */
6712                 return 0;
6713         case EXIT_REASON_EPT_MISCONFIG:
6714                 /*
6715                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6716                  * table (shadow on EPT) or a merged EPT table that L0 built
6717                  * (EPT on EPT). So any problems with the structure of the
6718                  * table is L0's fault.
6719                  */
6720                 return 0;
6721         case EXIT_REASON_PREEMPTION_TIMER:
6722                 return vmcs12->pin_based_vm_exec_control &
6723                         PIN_BASED_VMX_PREEMPTION_TIMER;
6724         case EXIT_REASON_WBINVD:
6725                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6726         case EXIT_REASON_XSETBV:
6727                 return 1;
6728         default:
6729                 return 1;
6730         }
6731 }
6732
6733 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6734 {
6735         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6736         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6737 }
6738
6739 static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6740 {
6741         u64 delta_tsc_l1;
6742         u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6743
6744         if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6745                         PIN_BASED_VMX_PREEMPTION_TIMER))
6746                 return;
6747         preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6748                         MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6749         preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6750         delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6751                 - vcpu->arch.last_guest_tsc;
6752         preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6753         if (preempt_val_l2 <= preempt_val_l1)
6754                 preempt_val_l2 = 0;
6755         else
6756                 preempt_val_l2 -= preempt_val_l1;
6757         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6758 }
6759
6760 /*
6761  * The guest has exited.  See if we can fix it or if we need userspace
6762  * assistance.
6763  */
6764 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6765 {
6766         struct vcpu_vmx *vmx = to_vmx(vcpu);
6767         u32 exit_reason = vmx->exit_reason;
6768         u32 vectoring_info = vmx->idt_vectoring_info;
6769
6770         /* If guest state is invalid, start emulating */
6771         if (vmx->emulation_required)
6772                 return handle_invalid_guest_state(vcpu);
6773
6774         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6775                 nested_vmx_vmexit(vcpu);
6776                 return 1;
6777         }
6778
6779         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6780                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6781                 vcpu->run->fail_entry.hardware_entry_failure_reason
6782                         = exit_reason;
6783                 return 0;
6784         }
6785
6786         if (unlikely(vmx->fail)) {
6787                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6788                 vcpu->run->fail_entry.hardware_entry_failure_reason
6789                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6790                 return 0;
6791         }
6792
6793         /*
6794          * Note:
6795          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6796          * delivery event since it indicates guest is accessing MMIO.
6797          * The vm-exit can be triggered again after return to guest that
6798          * will cause infinite loop.
6799          */
6800         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6801                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6802                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6803                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6804                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6805                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6806                 vcpu->run->internal.ndata = 2;
6807                 vcpu->run->internal.data[0] = vectoring_info;
6808                 vcpu->run->internal.data[1] = exit_reason;
6809                 return 0;
6810         }
6811
6812         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6813             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6814                                         get_vmcs12(vcpu))))) {
6815                 if (vmx_interrupt_allowed(vcpu)) {
6816                         vmx->soft_vnmi_blocked = 0;
6817                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6818                            vcpu->arch.nmi_pending) {
6819                         /*
6820                          * This CPU don't support us in finding the end of an
6821                          * NMI-blocked window if the guest runs with IRQs
6822                          * disabled. So we pull the trigger after 1 s of
6823                          * futile waiting, but inform the user about this.
6824                          */
6825                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6826                                "state on VCPU %d after 1 s timeout\n",
6827                                __func__, vcpu->vcpu_id);
6828                         vmx->soft_vnmi_blocked = 0;
6829                 }
6830         }
6831
6832         if (exit_reason < kvm_vmx_max_exit_handlers
6833             && kvm_vmx_exit_handlers[exit_reason])
6834                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6835         else {
6836                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6837                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6838         }
6839         return 0;
6840 }
6841
6842 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6843 {
6844         if (irr == -1 || tpr < irr) {
6845                 vmcs_write32(TPR_THRESHOLD, 0);
6846                 return;
6847         }
6848
6849         vmcs_write32(TPR_THRESHOLD, irr);
6850 }
6851
6852 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6853 {
6854         u32 sec_exec_control;
6855
6856         /*
6857          * There is not point to enable virtualize x2apic without enable
6858          * apicv
6859          */
6860         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6861                                 !vmx_vm_has_apicv(vcpu->kvm))
6862                 return;
6863
6864         if (!vm_need_tpr_shadow(vcpu->kvm))
6865                 return;
6866
6867         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6868
6869         if (set) {
6870                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6871                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6872         } else {
6873                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6874                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6875         }
6876         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6877
6878         vmx_set_msr_bitmap(vcpu);
6879 }
6880
6881 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6882 {
6883         u16 status;
6884         u8 old;
6885
6886         if (!vmx_vm_has_apicv(kvm))
6887                 return;
6888
6889         if (isr == -1)
6890                 isr = 0;
6891
6892         status = vmcs_read16(GUEST_INTR_STATUS);
6893         old = status >> 8;
6894         if (isr != old) {
6895                 status &= 0xff;
6896                 status |= isr << 8;
6897                 vmcs_write16(GUEST_INTR_STATUS, status);
6898         }
6899 }
6900
6901 static void vmx_set_rvi(int vector)
6902 {
6903         u16 status;
6904         u8 old;
6905
6906         status = vmcs_read16(GUEST_INTR_STATUS);
6907         old = (u8)status & 0xff;
6908         if ((u8)vector != old) {
6909                 status &= ~0xff;
6910                 status |= (u8)vector;
6911                 vmcs_write16(GUEST_INTR_STATUS, status);
6912         }
6913 }
6914
6915 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6916 {
6917         if (max_irr == -1)
6918                 return;
6919
6920         vmx_set_rvi(max_irr);
6921 }
6922
6923 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6924 {
6925         if (!vmx_vm_has_apicv(vcpu->kvm))
6926                 return;
6927
6928         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6929         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6930         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6931         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6932 }
6933
6934 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6935 {
6936         u32 exit_intr_info;
6937
6938         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6939               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6940                 return;
6941
6942         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6943         exit_intr_info = vmx->exit_intr_info;
6944
6945         /* Handle machine checks before interrupts are enabled */
6946         if (is_machine_check(exit_intr_info))
6947                 kvm_machine_check();
6948
6949         /* We need to handle NMIs before interrupts are enabled */
6950         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6951             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6952                 kvm_before_handle_nmi(&vmx->vcpu);
6953                 asm("int $2");
6954                 kvm_after_handle_nmi(&vmx->vcpu);
6955         }
6956 }
6957
6958 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6959 {
6960         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6961
6962         /*
6963          * If external interrupt exists, IF bit is set in rflags/eflags on the
6964          * interrupt stack frame, and interrupt will be enabled on a return
6965          * from interrupt handler.
6966          */
6967         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6968                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6969                 unsigned int vector;
6970                 unsigned long entry;
6971                 gate_desc *desc;
6972                 struct vcpu_vmx *vmx = to_vmx(vcpu);
6973 #ifdef CONFIG_X86_64
6974                 unsigned long tmp;
6975 #endif
6976
6977                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
6978                 desc = (gate_desc *)vmx->host_idt_base + vector;
6979                 entry = gate_offset(*desc);
6980                 asm volatile(
6981 #ifdef CONFIG_X86_64
6982                         "mov %%" _ASM_SP ", %[sp]\n\t"
6983                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6984                         "push $%c[ss]\n\t"
6985                         "push %[sp]\n\t"
6986 #endif
6987                         "pushf\n\t"
6988                         "orl $0x200, (%%" _ASM_SP ")\n\t"
6989                         __ASM_SIZE(push) " $%c[cs]\n\t"
6990                         "call *%[entry]\n\t"
6991                         :
6992 #ifdef CONFIG_X86_64
6993                         [sp]"=&r"(tmp)
6994 #endif
6995                         :
6996                         [entry]"r"(entry),
6997                         [ss]"i"(__KERNEL_DS),
6998                         [cs]"i"(__KERNEL_CS)
6999                         );
7000         } else
7001                 local_irq_enable();
7002 }
7003
7004 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7005 {
7006         u32 exit_intr_info;
7007         bool unblock_nmi;
7008         u8 vector;
7009         bool idtv_info_valid;
7010
7011         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7012
7013         if (cpu_has_virtual_nmis()) {
7014                 if (vmx->nmi_known_unmasked)
7015                         return;
7016                 /*
7017                  * Can't use vmx->exit_intr_info since we're not sure what
7018                  * the exit reason is.
7019                  */
7020                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7021                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7022                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7023                 /*
7024                  * SDM 3: 27.7.1.2 (September 2008)
7025                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7026                  * a guest IRET fault.
7027                  * SDM 3: 23.2.2 (September 2008)
7028                  * Bit 12 is undefined in any of the following cases:
7029                  *  If the VM exit sets the valid bit in the IDT-vectoring
7030                  *   information field.
7031                  *  If the VM exit is due to a double fault.
7032                  */
7033                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7034                     vector != DF_VECTOR && !idtv_info_valid)
7035                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7036                                       GUEST_INTR_STATE_NMI);
7037                 else
7038                         vmx->nmi_known_unmasked =
7039                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7040                                   & GUEST_INTR_STATE_NMI);
7041         } else if (unlikely(vmx->soft_vnmi_blocked))
7042                 vmx->vnmi_blocked_time +=
7043                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7044 }
7045
7046 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7047                                       u32 idt_vectoring_info,
7048                                       int instr_len_field,
7049                                       int error_code_field)
7050 {
7051         u8 vector;
7052         int type;
7053         bool idtv_info_valid;
7054
7055         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7056
7057         vcpu->arch.nmi_injected = false;
7058         kvm_clear_exception_queue(vcpu);
7059         kvm_clear_interrupt_queue(vcpu);
7060
7061         if (!idtv_info_valid)
7062                 return;
7063
7064         kvm_make_request(KVM_REQ_EVENT, vcpu);
7065
7066         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7067         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7068
7069         switch (type) {
7070         case INTR_TYPE_NMI_INTR:
7071                 vcpu->arch.nmi_injected = true;
7072                 /*
7073                  * SDM 3: 27.7.1.2 (September 2008)
7074                  * Clear bit "block by NMI" before VM entry if a NMI
7075                  * delivery faulted.
7076                  */
7077                 vmx_set_nmi_mask(vcpu, false);
7078                 break;
7079         case INTR_TYPE_SOFT_EXCEPTION:
7080                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7081                 /* fall through */
7082         case INTR_TYPE_HARD_EXCEPTION:
7083                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7084                         u32 err = vmcs_read32(error_code_field);
7085                         kvm_requeue_exception_e(vcpu, vector, err);
7086                 } else
7087                         kvm_requeue_exception(vcpu, vector);
7088                 break;
7089         case INTR_TYPE_SOFT_INTR:
7090                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7091                 /* fall through */
7092         case INTR_TYPE_EXT_INTR:
7093                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7094                 break;
7095         default:
7096                 break;
7097         }
7098 }
7099
7100 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7101 {
7102         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7103                                   VM_EXIT_INSTRUCTION_LEN,
7104                                   IDT_VECTORING_ERROR_CODE);
7105 }
7106
7107 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7108 {
7109         __vmx_complete_interrupts(vcpu,
7110                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7111                                   VM_ENTRY_INSTRUCTION_LEN,
7112                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7113
7114         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7115 }
7116
7117 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7118 {
7119         int i, nr_msrs;
7120         struct perf_guest_switch_msr *msrs;
7121
7122         msrs = perf_guest_get_msrs(&nr_msrs);
7123
7124         if (!msrs)
7125                 return;
7126
7127         for (i = 0; i < nr_msrs; i++)
7128                 if (msrs[i].host == msrs[i].guest)
7129                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7130                 else
7131                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7132                                         msrs[i].host);
7133 }
7134
7135 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7136 {
7137         struct vcpu_vmx *vmx = to_vmx(vcpu);
7138         unsigned long debugctlmsr;
7139
7140         /* Record the guest's net vcpu time for enforced NMI injections. */
7141         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7142                 vmx->entry_time = ktime_get();
7143
7144         /* Don't enter VMX if guest state is invalid, let the exit handler
7145            start emulation until we arrive back to a valid state */
7146         if (vmx->emulation_required)
7147                 return;
7148
7149         if (vmx->nested.sync_shadow_vmcs) {
7150                 copy_vmcs12_to_shadow(vmx);
7151                 vmx->nested.sync_shadow_vmcs = false;
7152         }
7153
7154         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7155                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7156         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7157                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7158
7159         /* When single-stepping over STI and MOV SS, we must clear the
7160          * corresponding interruptibility bits in the guest state. Otherwise
7161          * vmentry fails as it then expects bit 14 (BS) in pending debug
7162          * exceptions being set, but that's not correct for the guest debugging
7163          * case. */
7164         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7165                 vmx_set_interrupt_shadow(vcpu, 0);
7166
7167         atomic_switch_perf_msrs(vmx);
7168         debugctlmsr = get_debugctlmsr();
7169
7170         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7171                 nested_adjust_preemption_timer(vcpu);
7172         vmx->__launched = vmx->loaded_vmcs->launched;
7173         asm(
7174                 /* Store host registers */
7175                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7176                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7177                 "push %%" _ASM_CX " \n\t"
7178                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7179                 "je 1f \n\t"
7180                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7181                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7182                 "1: \n\t"
7183                 /* Reload cr2 if changed */
7184                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7185                 "mov %%cr2, %%" _ASM_DX " \n\t"
7186                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7187                 "je 2f \n\t"
7188                 "mov %%" _ASM_AX", %%cr2 \n\t"
7189                 "2: \n\t"
7190                 /* Check if vmlaunch of vmresume is needed */
7191                 "cmpl $0, %c[launched](%0) \n\t"
7192                 /* Load guest registers.  Don't clobber flags. */
7193                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7194                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7195                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7196                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7197                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7198                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7199 #ifdef CONFIG_X86_64
7200                 "mov %c[r8](%0),  %%r8  \n\t"
7201                 "mov %c[r9](%0),  %%r9  \n\t"
7202                 "mov %c[r10](%0), %%r10 \n\t"
7203                 "mov %c[r11](%0), %%r11 \n\t"
7204                 "mov %c[r12](%0), %%r12 \n\t"
7205                 "mov %c[r13](%0), %%r13 \n\t"
7206                 "mov %c[r14](%0), %%r14 \n\t"
7207                 "mov %c[r15](%0), %%r15 \n\t"
7208 #endif
7209                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7210
7211                 /* Enter guest mode */
7212                 "jne 1f \n\t"
7213                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7214                 "jmp 2f \n\t"
7215                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7216                 "2: "
7217                 /* Save guest registers, load host registers, keep flags */
7218                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7219                 "pop %0 \n\t"
7220                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7221                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7222                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7223                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7224                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7225                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7226                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7227 #ifdef CONFIG_X86_64
7228                 "mov %%r8,  %c[r8](%0) \n\t"
7229                 "mov %%r9,  %c[r9](%0) \n\t"
7230                 "mov %%r10, %c[r10](%0) \n\t"
7231                 "mov %%r11, %c[r11](%0) \n\t"
7232                 "mov %%r12, %c[r12](%0) \n\t"
7233                 "mov %%r13, %c[r13](%0) \n\t"
7234                 "mov %%r14, %c[r14](%0) \n\t"
7235                 "mov %%r15, %c[r15](%0) \n\t"
7236 #endif
7237                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7238                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7239
7240                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7241                 "setbe %c[fail](%0) \n\t"
7242                 ".pushsection .rodata \n\t"
7243                 ".global vmx_return \n\t"
7244                 "vmx_return: " _ASM_PTR " 2b \n\t"
7245                 ".popsection"
7246               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7247                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7248                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7249                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7250                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7251                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7252                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7253                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7254                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7255                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7256                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7257 #ifdef CONFIG_X86_64
7258                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7259                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7260                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7261                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7262                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7263                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7264                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7265                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7266 #endif
7267                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7268                 [wordsize]"i"(sizeof(ulong))
7269               : "cc", "memory"
7270 #ifdef CONFIG_X86_64
7271                 , "rax", "rbx", "rdi", "rsi"
7272                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7273 #else
7274                 , "eax", "ebx", "edi", "esi"
7275 #endif
7276               );
7277
7278         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7279         if (debugctlmsr)
7280                 update_debugctlmsr(debugctlmsr);
7281
7282 #ifndef CONFIG_X86_64
7283         /*
7284          * The sysexit path does not restore ds/es, so we must set them to
7285          * a reasonable value ourselves.
7286          *
7287          * We can't defer this to vmx_load_host_state() since that function
7288          * may be executed in interrupt context, which saves and restore segments
7289          * around it, nullifying its effect.
7290          */
7291         loadsegment(ds, __USER_DS);
7292         loadsegment(es, __USER_DS);
7293 #endif
7294
7295         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7296                                   | (1 << VCPU_EXREG_RFLAGS)
7297                                   | (1 << VCPU_EXREG_CPL)
7298                                   | (1 << VCPU_EXREG_PDPTR)
7299                                   | (1 << VCPU_EXREG_SEGMENTS)
7300                                   | (1 << VCPU_EXREG_CR3));
7301         vcpu->arch.regs_dirty = 0;
7302
7303         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7304
7305         vmx->loaded_vmcs->launched = 1;
7306
7307         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7308         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7309
7310         /*
7311          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7312          * we did not inject a still-pending event to L1 now because of
7313          * nested_run_pending, we need to re-enable this bit.
7314          */
7315         if (vmx->nested.nested_run_pending)
7316                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7317
7318         vmx->nested.nested_run_pending = 0;
7319
7320         vmx_complete_atomic_exit(vmx);
7321         vmx_recover_nmi_blocking(vmx);
7322         vmx_complete_interrupts(vmx);
7323 }
7324
7325 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7326 {
7327         struct vcpu_vmx *vmx = to_vmx(vcpu);
7328
7329         free_vpid(vmx);
7330         free_nested(vmx);
7331         free_loaded_vmcs(vmx->loaded_vmcs);
7332         kfree(vmx->guest_msrs);
7333         kvm_vcpu_uninit(vcpu);
7334         kmem_cache_free(kvm_vcpu_cache, vmx);
7335 }
7336
7337 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7338 {
7339         int err;
7340         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7341         int cpu;
7342
7343         if (!vmx)
7344                 return ERR_PTR(-ENOMEM);
7345
7346         allocate_vpid(vmx);
7347
7348         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7349         if (err)
7350                 goto free_vcpu;
7351
7352         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7353         err = -ENOMEM;
7354         if (!vmx->guest_msrs) {
7355                 goto uninit_vcpu;
7356         }
7357
7358         vmx->loaded_vmcs = &vmx->vmcs01;
7359         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7360         if (!vmx->loaded_vmcs->vmcs)
7361                 goto free_msrs;
7362         if (!vmm_exclusive)
7363                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7364         loaded_vmcs_init(vmx->loaded_vmcs);
7365         if (!vmm_exclusive)
7366                 kvm_cpu_vmxoff();
7367
7368         cpu = get_cpu();
7369         vmx_vcpu_load(&vmx->vcpu, cpu);
7370         vmx->vcpu.cpu = cpu;
7371         err = vmx_vcpu_setup(vmx);
7372         vmx_vcpu_put(&vmx->vcpu);
7373         put_cpu();
7374         if (err)
7375                 goto free_vmcs;
7376         if (vm_need_virtualize_apic_accesses(kvm)) {
7377                 err = alloc_apic_access_page(kvm);
7378                 if (err)
7379                         goto free_vmcs;
7380         }
7381
7382         if (enable_ept) {
7383                 if (!kvm->arch.ept_identity_map_addr)
7384                         kvm->arch.ept_identity_map_addr =
7385                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7386                 err = -ENOMEM;
7387                 if (alloc_identity_pagetable(kvm) != 0)
7388                         goto free_vmcs;
7389                 if (!init_rmode_identity_map(kvm))
7390                         goto free_vmcs;
7391         }
7392
7393         vmx->nested.current_vmptr = -1ull;
7394         vmx->nested.current_vmcs12 = NULL;
7395
7396         return &vmx->vcpu;
7397
7398 free_vmcs:
7399         free_loaded_vmcs(vmx->loaded_vmcs);
7400 free_msrs:
7401         kfree(vmx->guest_msrs);
7402 uninit_vcpu:
7403         kvm_vcpu_uninit(&vmx->vcpu);
7404 free_vcpu:
7405         free_vpid(vmx);
7406         kmem_cache_free(kvm_vcpu_cache, vmx);
7407         return ERR_PTR(err);
7408 }
7409
7410 static void __init vmx_check_processor_compat(void *rtn)
7411 {
7412         struct vmcs_config vmcs_conf;
7413
7414         *(int *)rtn = 0;
7415         if (setup_vmcs_config(&vmcs_conf) < 0)
7416                 *(int *)rtn = -EIO;
7417         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7418                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7419                                 smp_processor_id());
7420                 *(int *)rtn = -EIO;
7421         }
7422 }
7423
7424 static int get_ept_level(void)
7425 {
7426         return VMX_EPT_DEFAULT_GAW + 1;
7427 }
7428
7429 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7430 {
7431         u64 ret;
7432
7433         /* For VT-d and EPT combination
7434          * 1. MMIO: always map as UC
7435          * 2. EPT with VT-d:
7436          *   a. VT-d without snooping control feature: can't guarantee the
7437          *      result, try to trust guest.
7438          *   b. VT-d with snooping control feature: snooping control feature of
7439          *      VT-d engine can guarantee the cache correctness. Just set it
7440          *      to WB to keep consistent with host. So the same as item 3.
7441          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7442          *    consistent with host MTRR
7443          */
7444         if (is_mmio)
7445                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7446         else if (vcpu->kvm->arch.iommu_domain &&
7447                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7448                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7449                       VMX_EPT_MT_EPTE_SHIFT;
7450         else
7451                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7452                         | VMX_EPT_IPAT_BIT;
7453
7454         return ret;
7455 }
7456
7457 static int vmx_get_lpage_level(void)
7458 {
7459         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7460                 return PT_DIRECTORY_LEVEL;
7461         else
7462                 /* For shadow and EPT supported 1GB page */
7463                 return PT_PDPE_LEVEL;
7464 }
7465
7466 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7467 {
7468         struct kvm_cpuid_entry2 *best;
7469         struct vcpu_vmx *vmx = to_vmx(vcpu);
7470         u32 exec_control;
7471
7472         vmx->rdtscp_enabled = false;
7473         if (vmx_rdtscp_supported()) {
7474                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7475                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7476                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7477                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7478                                 vmx->rdtscp_enabled = true;
7479                         else {
7480                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7481                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7482                                                 exec_control);
7483                         }
7484                 }
7485         }
7486
7487         /* Exposing INVPCID only when PCID is exposed */
7488         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7489         if (vmx_invpcid_supported() &&
7490             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7491             guest_cpuid_has_pcid(vcpu)) {
7492                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7493                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7494                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7495                              exec_control);
7496         } else {
7497                 if (cpu_has_secondary_exec_ctrls()) {
7498                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7499                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7500                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7501                                      exec_control);
7502                 }
7503                 if (best)
7504                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7505         }
7506 }
7507
7508 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7509 {
7510         if (func == 1 && nested)
7511                 entry->ecx |= bit(X86_FEATURE_VMX);
7512 }
7513
7514 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7515                 struct x86_exception *fault)
7516 {
7517         struct vmcs12 *vmcs12;
7518         nested_vmx_vmexit(vcpu);
7519         vmcs12 = get_vmcs12(vcpu);
7520
7521         if (fault->error_code & PFERR_RSVD_MASK)
7522                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7523         else
7524                 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7525         vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7526         vmcs12->guest_physical_address = fault->address;
7527 }
7528
7529 /* Callbacks for nested_ept_init_mmu_context: */
7530
7531 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7532 {
7533         /* return the page table to be shadowed - in our case, EPT12 */
7534         return get_vmcs12(vcpu)->ept_pointer;
7535 }
7536
7537 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7538 {
7539         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7540                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7541
7542         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7543         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7544         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7545
7546         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7547 }
7548
7549 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7550 {
7551         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7552 }
7553
7554 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7555                 struct x86_exception *fault)
7556 {
7557         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7558
7559         WARN_ON(!is_guest_mode(vcpu));
7560
7561         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7562         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7563                 nested_vmx_vmexit(vcpu);
7564         else
7565                 kvm_inject_page_fault(vcpu, fault);
7566 }
7567
7568 /*
7569  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7570  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7571  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7572  * guest in a way that will both be appropriate to L1's requests, and our
7573  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7574  * function also has additional necessary side-effects, like setting various
7575  * vcpu->arch fields.
7576  */
7577 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7578 {
7579         struct vcpu_vmx *vmx = to_vmx(vcpu);
7580         u32 exec_control;
7581         u32 exit_control;
7582
7583         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7584         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7585         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7586         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7587         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7588         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7589         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7590         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7591         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7592         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7593         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7594         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7595         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7596         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7597         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7598         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7599         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7600         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7601         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7602         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7603         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7604         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7605         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7606         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7607         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7608         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7609         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7610         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7611         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7612         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7613         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7614         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7615         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7616         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7617         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7618         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7619
7620         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7621         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7622                 vmcs12->vm_entry_intr_info_field);
7623         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7624                 vmcs12->vm_entry_exception_error_code);
7625         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7626                 vmcs12->vm_entry_instruction_len);
7627         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7628                 vmcs12->guest_interruptibility_info);
7629         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7630         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7631         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7632         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7633                 vmcs12->guest_pending_dbg_exceptions);
7634         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7635         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7636
7637         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7638
7639         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7640                 (vmcs_config.pin_based_exec_ctrl |
7641                  vmcs12->pin_based_vm_exec_control));
7642
7643         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7644                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7645                              vmcs12->vmx_preemption_timer_value);
7646
7647         /*
7648          * Whether page-faults are trapped is determined by a combination of
7649          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7650          * If enable_ept, L0 doesn't care about page faults and we should
7651          * set all of these to L1's desires. However, if !enable_ept, L0 does
7652          * care about (at least some) page faults, and because it is not easy
7653          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7654          * to exit on each and every L2 page fault. This is done by setting
7655          * MASK=MATCH=0 and (see below) EB.PF=1.
7656          * Note that below we don't need special code to set EB.PF beyond the
7657          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7658          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7659          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7660          *
7661          * A problem with this approach (when !enable_ept) is that L1 may be
7662          * injected with more page faults than it asked for. This could have
7663          * caused problems, but in practice existing hypervisors don't care.
7664          * To fix this, we will need to emulate the PFEC checking (on the L1
7665          * page tables), using walk_addr(), when injecting PFs to L1.
7666          */
7667         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7668                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7669         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7670                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7671
7672         if (cpu_has_secondary_exec_ctrls()) {
7673                 u32 exec_control = vmx_secondary_exec_control(vmx);
7674                 if (!vmx->rdtscp_enabled)
7675                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7676                 /* Take the following fields only from vmcs12 */
7677                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7678                 if (nested_cpu_has(vmcs12,
7679                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7680                         exec_control |= vmcs12->secondary_vm_exec_control;
7681
7682                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7683                         /*
7684                          * Translate L1 physical address to host physical
7685                          * address for vmcs02. Keep the page pinned, so this
7686                          * physical address remains valid. We keep a reference
7687                          * to it so we can release it later.
7688                          */
7689                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7690                                 nested_release_page(vmx->nested.apic_access_page);
7691                         vmx->nested.apic_access_page =
7692                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7693                         /*
7694                          * If translation failed, no matter: This feature asks
7695                          * to exit when accessing the given address, and if it
7696                          * can never be accessed, this feature won't do
7697                          * anything anyway.
7698                          */
7699                         if (!vmx->nested.apic_access_page)
7700                                 exec_control &=
7701                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7702                         else
7703                                 vmcs_write64(APIC_ACCESS_ADDR,
7704                                   page_to_phys(vmx->nested.apic_access_page));
7705                 }
7706
7707                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7708         }
7709
7710
7711         /*
7712          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7713          * Some constant fields are set here by vmx_set_constant_host_state().
7714          * Other fields are different per CPU, and will be set later when
7715          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7716          */
7717         vmx_set_constant_host_state(vmx);
7718
7719         /*
7720          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7721          * entry, but only if the current (host) sp changed from the value
7722          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7723          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7724          * here we just force the write to happen on entry.
7725          */
7726         vmx->host_rsp = 0;
7727
7728         exec_control = vmx_exec_control(vmx); /* L0's desires */
7729         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7730         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7731         exec_control &= ~CPU_BASED_TPR_SHADOW;
7732         exec_control |= vmcs12->cpu_based_vm_exec_control;
7733         /*
7734          * Merging of IO and MSR bitmaps not currently supported.
7735          * Rather, exit every time.
7736          */
7737         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7738         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7739         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7740
7741         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7742
7743         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7744          * bitwise-or of what L1 wants to trap for L2, and what we want to
7745          * trap. Note that CR0.TS also needs updating - we do this later.
7746          */
7747         update_exception_bitmap(vcpu);
7748         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7749         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7750
7751         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7752          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7753          * bits are further modified by vmx_set_efer() below.
7754          */
7755         exit_control = vmcs_config.vmexit_ctrl;
7756         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7757                 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
7758         vmcs_write32(VM_EXIT_CONTROLS, exit_control);
7759
7760         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7761          * emulated by vmx_set_efer(), below.
7762          */
7763         vmcs_write32(VM_ENTRY_CONTROLS,
7764                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7765                         ~VM_ENTRY_IA32E_MODE) |
7766                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7767
7768         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7769                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7770                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7771         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7772                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7773
7774
7775         set_cr4_guest_host_mask(vmx);
7776
7777         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7778                 vmcs_write64(TSC_OFFSET,
7779                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7780         else
7781                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7782
7783         if (enable_vpid) {
7784                 /*
7785                  * Trivially support vpid by letting L2s share their parent
7786                  * L1's vpid. TODO: move to a more elaborate solution, giving
7787                  * each L2 its own vpid and exposing the vpid feature to L1.
7788                  */
7789                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7790                 vmx_flush_tlb(vcpu);
7791         }
7792
7793         if (nested_cpu_has_ept(vmcs12)) {
7794                 kvm_mmu_unload(vcpu);
7795                 nested_ept_init_mmu_context(vcpu);
7796         }
7797
7798         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7799                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7800         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7801                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7802         else
7803                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7804         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7805         vmx_set_efer(vcpu, vcpu->arch.efer);
7806
7807         /*
7808          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7809          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7810          * The CR0_READ_SHADOW is what L2 should have expected to read given
7811          * the specifications by L1; It's not enough to take
7812          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7813          * have more bits than L1 expected.
7814          */
7815         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7816         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7817
7818         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7819         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7820
7821         /* shadow page tables on either EPT or shadow page tables */
7822         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7823         kvm_mmu_reset_context(vcpu);
7824
7825         if (!enable_ept)
7826                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7827
7828         /*
7829          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7830          */
7831         if (enable_ept) {
7832                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7833                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7834                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7835                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7836         }
7837
7838         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7839         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7840 }
7841
7842 /*
7843  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7844  * for running an L2 nested guest.
7845  */
7846 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7847 {
7848         struct vmcs12 *vmcs12;
7849         struct vcpu_vmx *vmx = to_vmx(vcpu);
7850         int cpu;
7851         struct loaded_vmcs *vmcs02;
7852         bool ia32e;
7853
7854         if (!nested_vmx_check_permission(vcpu) ||
7855             !nested_vmx_check_vmcs12(vcpu))
7856                 return 1;
7857
7858         skip_emulated_instruction(vcpu);
7859         vmcs12 = get_vmcs12(vcpu);
7860
7861         if (enable_shadow_vmcs)
7862                 copy_shadow_to_vmcs12(vmx);
7863
7864         /*
7865          * The nested entry process starts with enforcing various prerequisites
7866          * on vmcs12 as required by the Intel SDM, and act appropriately when
7867          * they fail: As the SDM explains, some conditions should cause the
7868          * instruction to fail, while others will cause the instruction to seem
7869          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7870          * To speed up the normal (success) code path, we should avoid checking
7871          * for misconfigurations which will anyway be caught by the processor
7872          * when using the merged vmcs02.
7873          */
7874         if (vmcs12->launch_state == launch) {
7875                 nested_vmx_failValid(vcpu,
7876                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7877                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7878                 return 1;
7879         }
7880
7881         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7882                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7883                 return 1;
7884         }
7885
7886         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7887                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7888                 /*TODO: Also verify bits beyond physical address width are 0*/
7889                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7890                 return 1;
7891         }
7892
7893         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7894                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7895                 /*TODO: Also verify bits beyond physical address width are 0*/
7896                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7897                 return 1;
7898         }
7899
7900         if (vmcs12->vm_entry_msr_load_count > 0 ||
7901             vmcs12->vm_exit_msr_load_count > 0 ||
7902             vmcs12->vm_exit_msr_store_count > 0) {
7903                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7904                                     __func__);
7905                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7906                 return 1;
7907         }
7908
7909         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7910               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7911             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7912               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7913             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7914               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7915             !vmx_control_verify(vmcs12->vm_exit_controls,
7916               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7917             !vmx_control_verify(vmcs12->vm_entry_controls,
7918               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7919         {
7920                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7921                 return 1;
7922         }
7923
7924         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7925             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7926                 nested_vmx_failValid(vcpu,
7927                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7928                 return 1;
7929         }
7930
7931         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7932             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7933                 nested_vmx_entry_failure(vcpu, vmcs12,
7934                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7935                 return 1;
7936         }
7937         if (vmcs12->vmcs_link_pointer != -1ull) {
7938                 nested_vmx_entry_failure(vcpu, vmcs12,
7939                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7940                 return 1;
7941         }
7942
7943         /*
7944          * If the load IA32_EFER VM-entry control is 1, the following checks
7945          * are performed on the field for the IA32_EFER MSR:
7946          * - Bits reserved in the IA32_EFER MSR must be 0.
7947          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7948          *   the IA-32e mode guest VM-exit control. It must also be identical
7949          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7950          *   CR0.PG) is 1.
7951          */
7952         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7953                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7954                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7955                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7956                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7957                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7958                         nested_vmx_entry_failure(vcpu, vmcs12,
7959                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7960                         return 1;
7961                 }
7962         }
7963
7964         /*
7965          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7966          * IA32_EFER MSR must be 0 in the field for that register. In addition,
7967          * the values of the LMA and LME bits in the field must each be that of
7968          * the host address-space size VM-exit control.
7969          */
7970         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7971                 ia32e = (vmcs12->vm_exit_controls &
7972                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7973                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7974                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7975                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7976                         nested_vmx_entry_failure(vcpu, vmcs12,
7977                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7978                         return 1;
7979                 }
7980         }
7981
7982         /*
7983          * We're finally done with prerequisite checking, and can start with
7984          * the nested entry.
7985          */
7986
7987         vmcs02 = nested_get_current_vmcs02(vmx);
7988         if (!vmcs02)
7989                 return -ENOMEM;
7990
7991         enter_guest_mode(vcpu);
7992
7993         vmx->nested.nested_run_pending = 1;
7994
7995         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7996
7997         cpu = get_cpu();
7998         vmx->loaded_vmcs = vmcs02;
7999         vmx_vcpu_put(vcpu);
8000         vmx_vcpu_load(vcpu, cpu);
8001         vcpu->cpu = cpu;
8002         put_cpu();
8003
8004         vmx_segment_cache_clear(vmx);
8005
8006         vmcs12->launch_state = 1;
8007
8008         prepare_vmcs02(vcpu, vmcs12);
8009
8010         /*
8011          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8012          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8013          * returned as far as L1 is concerned. It will only return (and set
8014          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8015          */
8016         return 1;
8017 }
8018
8019 /*
8020  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8021  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8022  * This function returns the new value we should put in vmcs12.guest_cr0.
8023  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8024  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8025  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8026  *     didn't trap the bit, because if L1 did, so would L0).
8027  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8028  *     been modified by L2, and L1 knows it. So just leave the old value of
8029  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8030  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8031  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8032  *     changed these bits, and therefore they need to be updated, but L0
8033  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8034  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8035  */
8036 static inline unsigned long
8037 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8038 {
8039         return
8040         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8041         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8042         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8043                         vcpu->arch.cr0_guest_owned_bits));
8044 }
8045
8046 static inline unsigned long
8047 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8048 {
8049         return
8050         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8051         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8052         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8053                         vcpu->arch.cr4_guest_owned_bits));
8054 }
8055
8056 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8057                                        struct vmcs12 *vmcs12)
8058 {
8059         u32 idt_vectoring;
8060         unsigned int nr;
8061
8062         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8063                 nr = vcpu->arch.exception.nr;
8064                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8065
8066                 if (kvm_exception_is_soft(nr)) {
8067                         vmcs12->vm_exit_instruction_len =
8068                                 vcpu->arch.event_exit_inst_len;
8069                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8070                 } else
8071                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8072
8073                 if (vcpu->arch.exception.has_error_code) {
8074                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8075                         vmcs12->idt_vectoring_error_code =
8076                                 vcpu->arch.exception.error_code;
8077                 }
8078
8079                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8080         } else if (vcpu->arch.nmi_pending) {
8081                 vmcs12->idt_vectoring_info_field =
8082                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8083         } else if (vcpu->arch.interrupt.pending) {
8084                 nr = vcpu->arch.interrupt.nr;
8085                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8086
8087                 if (vcpu->arch.interrupt.soft) {
8088                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8089                         vmcs12->vm_entry_instruction_len =
8090                                 vcpu->arch.event_exit_inst_len;
8091                 } else
8092                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8093
8094                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8095         }
8096 }
8097
8098 /*
8099  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8100  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8101  * and this function updates it to reflect the changes to the guest state while
8102  * L2 was running (and perhaps made some exits which were handled directly by L0
8103  * without going back to L1), and to reflect the exit reason.
8104  * Note that we do not have to copy here all VMCS fields, just those that
8105  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8106  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8107  * which already writes to vmcs12 directly.
8108  */
8109 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8110 {
8111         /* update guest state fields: */
8112         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8113         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8114
8115         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8116         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8117         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8118         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8119
8120         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8121         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8122         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8123         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8124         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8125         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8126         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8127         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8128         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8129         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8130         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8131         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8132         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8133         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8134         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8135         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8136         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8137         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8138         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8139         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8140         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8141         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8142         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8143         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8144         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8145         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8146         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8147         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8148         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8149         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8150         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8151         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8152         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8153         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8154         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8155         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8156
8157         vmcs12->guest_interruptibility_info =
8158                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8159         vmcs12->guest_pending_dbg_exceptions =
8160                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8161
8162         if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8163             (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8164                 vmcs12->vmx_preemption_timer_value =
8165                         vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8166
8167         /*
8168          * In some cases (usually, nested EPT), L2 is allowed to change its
8169          * own CR3 without exiting. If it has changed it, we must keep it.
8170          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8171          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8172          *
8173          * Additionally, restore L2's PDPTR to vmcs12.
8174          */
8175         if (enable_ept) {
8176                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8177                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8178                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8179                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8180                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8181         }
8182
8183         vmcs12->vm_entry_controls =
8184                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8185                 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8186
8187         /* TODO: These cannot have changed unless we have MSR bitmaps and
8188          * the relevant bit asks not to trap the change */
8189         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8190         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8191                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8192         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8193                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8194         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8195         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8196         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8197
8198         /* update exit information fields: */
8199
8200         vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
8201         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8202
8203         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8204         if ((vmcs12->vm_exit_intr_info &
8205              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8206             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8207                 vmcs12->vm_exit_intr_error_code =
8208                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8209         vmcs12->idt_vectoring_info_field = 0;
8210         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8211         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8212
8213         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8214                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8215                  * instead of reading the real value. */
8216                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8217
8218                 /*
8219                  * Transfer the event that L0 or L1 may wanted to inject into
8220                  * L2 to IDT_VECTORING_INFO_FIELD.
8221                  */
8222                 vmcs12_save_pending_event(vcpu, vmcs12);
8223         }
8224
8225         /*
8226          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8227          * preserved above and would only end up incorrectly in L1.
8228          */
8229         vcpu->arch.nmi_injected = false;
8230         kvm_clear_exception_queue(vcpu);
8231         kvm_clear_interrupt_queue(vcpu);
8232 }
8233
8234 /*
8235  * A part of what we need to when the nested L2 guest exits and we want to
8236  * run its L1 parent, is to reset L1's guest state to the host state specified
8237  * in vmcs12.
8238  * This function is to be called not only on normal nested exit, but also on
8239  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8240  * Failures During or After Loading Guest State").
8241  * This function should be called when the active VMCS is L1's (vmcs01).
8242  */
8243 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8244                                    struct vmcs12 *vmcs12)
8245 {
8246         struct kvm_segment seg;
8247
8248         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8249                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8250         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8251                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8252         else
8253                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8254         vmx_set_efer(vcpu, vcpu->arch.efer);
8255
8256         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8257         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8258         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8259         /*
8260          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8261          * actually changed, because it depends on the current state of
8262          * fpu_active (which may have changed).
8263          * Note that vmx_set_cr0 refers to efer set above.
8264          */
8265         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8266         /*
8267          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8268          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8269          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8270          */
8271         update_exception_bitmap(vcpu);
8272         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8273         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8274
8275         /*
8276          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8277          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8278          */
8279         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8280         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8281
8282         if (nested_cpu_has_ept(vmcs12))
8283                 nested_ept_uninit_mmu_context(vcpu);
8284
8285         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8286         kvm_mmu_reset_context(vcpu);
8287
8288         if (!enable_ept)
8289                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8290
8291         if (enable_vpid) {
8292                 /*
8293                  * Trivially support vpid by letting L2s share their parent
8294                  * L1's vpid. TODO: move to a more elaborate solution, giving
8295                  * each L2 its own vpid and exposing the vpid feature to L1.
8296                  */
8297                 vmx_flush_tlb(vcpu);
8298         }
8299
8300
8301         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8302         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8303         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8304         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8305         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8306
8307         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8308                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8309                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8310         }
8311         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8312                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8313                         vmcs12->host_ia32_perf_global_ctrl);
8314
8315         /* Set L1 segment info according to Intel SDM
8316             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8317         seg = (struct kvm_segment) {
8318                 .base = 0,
8319                 .limit = 0xFFFFFFFF,
8320                 .selector = vmcs12->host_cs_selector,
8321                 .type = 11,
8322                 .present = 1,
8323                 .s = 1,
8324                 .g = 1
8325         };
8326         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8327                 seg.l = 1;
8328         else
8329                 seg.db = 1;
8330         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8331         seg = (struct kvm_segment) {
8332                 .base = 0,
8333                 .limit = 0xFFFFFFFF,
8334                 .type = 3,
8335                 .present = 1,
8336                 .s = 1,
8337                 .db = 1,
8338                 .g = 1
8339         };
8340         seg.selector = vmcs12->host_ds_selector;
8341         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8342         seg.selector = vmcs12->host_es_selector;
8343         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8344         seg.selector = vmcs12->host_ss_selector;
8345         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8346         seg.selector = vmcs12->host_fs_selector;
8347         seg.base = vmcs12->host_fs_base;
8348         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8349         seg.selector = vmcs12->host_gs_selector;
8350         seg.base = vmcs12->host_gs_base;
8351         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8352         seg = (struct kvm_segment) {
8353                 .base = vmcs12->host_tr_base,
8354                 .limit = 0x67,
8355                 .selector = vmcs12->host_tr_selector,
8356                 .type = 11,
8357                 .present = 1
8358         };
8359         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8360
8361         kvm_set_dr(vcpu, 7, 0x400);
8362         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8363 }
8364
8365 /*
8366  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8367  * and modify vmcs12 to make it see what it would expect to see there if
8368  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8369  */
8370 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8371 {
8372         struct vcpu_vmx *vmx = to_vmx(vcpu);
8373         int cpu;
8374         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8375
8376         /* trying to cancel vmlaunch/vmresume is a bug */
8377         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8378
8379         leave_guest_mode(vcpu);
8380         prepare_vmcs12(vcpu, vmcs12);
8381
8382         cpu = get_cpu();
8383         vmx->loaded_vmcs = &vmx->vmcs01;
8384         vmx_vcpu_put(vcpu);
8385         vmx_vcpu_load(vcpu, cpu);
8386         vcpu->cpu = cpu;
8387         put_cpu();
8388
8389         vmx_segment_cache_clear(vmx);
8390
8391         /* if no vmcs02 cache requested, remove the one we used */
8392         if (VMCS02_POOL_SIZE == 0)
8393                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8394
8395         load_vmcs12_host_state(vcpu, vmcs12);
8396
8397         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8398         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8399
8400         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8401         vmx->host_rsp = 0;
8402
8403         /* Unpin physical memory we referred to in vmcs02 */
8404         if (vmx->nested.apic_access_page) {
8405                 nested_release_page(vmx->nested.apic_access_page);
8406                 vmx->nested.apic_access_page = 0;
8407         }
8408
8409         /*
8410          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8411          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8412          * success or failure flag accordingly.
8413          */
8414         if (unlikely(vmx->fail)) {
8415                 vmx->fail = 0;
8416                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8417         } else
8418                 nested_vmx_succeed(vcpu);
8419         if (enable_shadow_vmcs)
8420                 vmx->nested.sync_shadow_vmcs = true;
8421 }
8422
8423 /*
8424  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8425  * 23.7 "VM-entry failures during or after loading guest state" (this also
8426  * lists the acceptable exit-reason and exit-qualification parameters).
8427  * It should only be called before L2 actually succeeded to run, and when
8428  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8429  */
8430 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8431                         struct vmcs12 *vmcs12,
8432                         u32 reason, unsigned long qualification)
8433 {
8434         load_vmcs12_host_state(vcpu, vmcs12);
8435         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8436         vmcs12->exit_qualification = qualification;
8437         nested_vmx_succeed(vcpu);
8438         if (enable_shadow_vmcs)
8439                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8440 }
8441
8442 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8443                                struct x86_instruction_info *info,
8444                                enum x86_intercept_stage stage)
8445 {
8446         return X86EMUL_CONTINUE;
8447 }
8448
8449 static struct kvm_x86_ops vmx_x86_ops = {
8450         .cpu_has_kvm_support = cpu_has_kvm_support,
8451         .disabled_by_bios = vmx_disabled_by_bios,
8452         .hardware_setup = hardware_setup,
8453         .hardware_unsetup = hardware_unsetup,
8454         .check_processor_compatibility = vmx_check_processor_compat,
8455         .hardware_enable = hardware_enable,
8456         .hardware_disable = hardware_disable,
8457         .cpu_has_accelerated_tpr = report_flexpriority,
8458
8459         .vcpu_create = vmx_create_vcpu,
8460         .vcpu_free = vmx_free_vcpu,
8461         .vcpu_reset = vmx_vcpu_reset,
8462
8463         .prepare_guest_switch = vmx_save_host_state,
8464         .vcpu_load = vmx_vcpu_load,
8465         .vcpu_put = vmx_vcpu_put,
8466
8467         .update_db_bp_intercept = update_exception_bitmap,
8468         .get_msr = vmx_get_msr,
8469         .set_msr = vmx_set_msr,
8470         .get_segment_base = vmx_get_segment_base,
8471         .get_segment = vmx_get_segment,
8472         .set_segment = vmx_set_segment,
8473         .get_cpl = vmx_get_cpl,
8474         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8475         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8476         .decache_cr3 = vmx_decache_cr3,
8477         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8478         .set_cr0 = vmx_set_cr0,
8479         .set_cr3 = vmx_set_cr3,
8480         .set_cr4 = vmx_set_cr4,
8481         .set_efer = vmx_set_efer,
8482         .get_idt = vmx_get_idt,
8483         .set_idt = vmx_set_idt,
8484         .get_gdt = vmx_get_gdt,
8485         .set_gdt = vmx_set_gdt,
8486         .set_dr7 = vmx_set_dr7,
8487         .cache_reg = vmx_cache_reg,
8488         .get_rflags = vmx_get_rflags,
8489         .set_rflags = vmx_set_rflags,
8490         .fpu_activate = vmx_fpu_activate,
8491         .fpu_deactivate = vmx_fpu_deactivate,
8492
8493         .tlb_flush = vmx_flush_tlb,
8494
8495         .run = vmx_vcpu_run,
8496         .handle_exit = vmx_handle_exit,
8497         .skip_emulated_instruction = skip_emulated_instruction,
8498         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8499         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8500         .patch_hypercall = vmx_patch_hypercall,
8501         .set_irq = vmx_inject_irq,
8502         .set_nmi = vmx_inject_nmi,
8503         .queue_exception = vmx_queue_exception,
8504         .cancel_injection = vmx_cancel_injection,
8505         .interrupt_allowed = vmx_interrupt_allowed,
8506         .nmi_allowed = vmx_nmi_allowed,
8507         .get_nmi_mask = vmx_get_nmi_mask,
8508         .set_nmi_mask = vmx_set_nmi_mask,
8509         .enable_nmi_window = enable_nmi_window,
8510         .enable_irq_window = enable_irq_window,
8511         .update_cr8_intercept = update_cr8_intercept,
8512         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8513         .vm_has_apicv = vmx_vm_has_apicv,
8514         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8515         .hwapic_irr_update = vmx_hwapic_irr_update,
8516         .hwapic_isr_update = vmx_hwapic_isr_update,
8517         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8518         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8519
8520         .set_tss_addr = vmx_set_tss_addr,
8521         .get_tdp_level = get_ept_level,
8522         .get_mt_mask = vmx_get_mt_mask,
8523
8524         .get_exit_info = vmx_get_exit_info,
8525
8526         .get_lpage_level = vmx_get_lpage_level,
8527
8528         .cpuid_update = vmx_cpuid_update,
8529
8530         .rdtscp_supported = vmx_rdtscp_supported,
8531         .invpcid_supported = vmx_invpcid_supported,
8532
8533         .set_supported_cpuid = vmx_set_supported_cpuid,
8534
8535         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8536
8537         .set_tsc_khz = vmx_set_tsc_khz,
8538         .read_tsc_offset = vmx_read_tsc_offset,
8539         .write_tsc_offset = vmx_write_tsc_offset,
8540         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8541         .compute_tsc_offset = vmx_compute_tsc_offset,
8542         .read_l1_tsc = vmx_read_l1_tsc,
8543
8544         .set_tdp_cr3 = vmx_set_cr3,
8545
8546         .check_intercept = vmx_check_intercept,
8547         .handle_external_intr = vmx_handle_external_intr,
8548 };
8549
8550 static int __init vmx_init(void)
8551 {
8552         int r, i, msr;
8553
8554         rdmsrl_safe(MSR_EFER, &host_efer);
8555
8556         for (i = 0; i < NR_VMX_MSR; ++i)
8557                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8558
8559         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8560         if (!vmx_io_bitmap_a)
8561                 return -ENOMEM;
8562
8563         r = -ENOMEM;
8564
8565         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8566         if (!vmx_io_bitmap_b)
8567                 goto out;
8568
8569         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8570         if (!vmx_msr_bitmap_legacy)
8571                 goto out1;
8572
8573         vmx_msr_bitmap_legacy_x2apic =
8574                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8575         if (!vmx_msr_bitmap_legacy_x2apic)
8576                 goto out2;
8577
8578         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8579         if (!vmx_msr_bitmap_longmode)
8580                 goto out3;
8581
8582         vmx_msr_bitmap_longmode_x2apic =
8583                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8584         if (!vmx_msr_bitmap_longmode_x2apic)
8585                 goto out4;
8586         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8587         if (!vmx_vmread_bitmap)
8588                 goto out5;
8589
8590         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8591         if (!vmx_vmwrite_bitmap)
8592                 goto out6;
8593
8594         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8595         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8596         /* shadowed read/write fields */
8597         for (i = 0; i < max_shadow_read_write_fields; i++) {
8598                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8599                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8600         }
8601         /* shadowed read only fields */
8602         for (i = 0; i < max_shadow_read_only_fields; i++)
8603                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8604
8605         /*
8606          * Allow direct access to the PC debug port (it is often used for I/O
8607          * delays, but the vmexits simply slow things down).
8608          */
8609         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8610         clear_bit(0x80, vmx_io_bitmap_a);
8611
8612         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8613
8614         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8615         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8616
8617         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8618
8619         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8620                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8621         if (r)
8622                 goto out7;
8623
8624 #ifdef CONFIG_KEXEC
8625         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8626                            crash_vmclear_local_loaded_vmcss);
8627 #endif
8628
8629         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8630         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8631         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8632         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8633         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8634         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8635         memcpy(vmx_msr_bitmap_legacy_x2apic,
8636                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8637         memcpy(vmx_msr_bitmap_longmode_x2apic,
8638                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8639
8640         if (enable_apicv) {
8641                 for (msr = 0x800; msr <= 0x8ff; msr++)
8642                         vmx_disable_intercept_msr_read_x2apic(msr);
8643
8644                 /* According SDM, in x2apic mode, the whole id reg is used.
8645                  * But in KVM, it only use the highest eight bits. Need to
8646                  * intercept it */
8647                 vmx_enable_intercept_msr_read_x2apic(0x802);
8648                 /* TMCCT */
8649                 vmx_enable_intercept_msr_read_x2apic(0x839);
8650                 /* TPR */
8651                 vmx_disable_intercept_msr_write_x2apic(0x808);
8652                 /* EOI */
8653                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8654                 /* SELF-IPI */
8655                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8656         }
8657
8658         if (enable_ept) {
8659                 kvm_mmu_set_mask_ptes(0ull,
8660                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8661                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8662                         0ull, VMX_EPT_EXECUTABLE_MASK);
8663                 ept_set_mmio_spte_mask();
8664                 kvm_enable_tdp();
8665         } else
8666                 kvm_disable_tdp();
8667
8668         return 0;
8669
8670 out7:
8671         free_page((unsigned long)vmx_vmwrite_bitmap);
8672 out6:
8673         free_page((unsigned long)vmx_vmread_bitmap);
8674 out5:
8675         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8676 out4:
8677         free_page((unsigned long)vmx_msr_bitmap_longmode);
8678 out3:
8679         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8680 out2:
8681         free_page((unsigned long)vmx_msr_bitmap_legacy);
8682 out1:
8683         free_page((unsigned long)vmx_io_bitmap_b);
8684 out:
8685         free_page((unsigned long)vmx_io_bitmap_a);
8686         return r;
8687 }
8688
8689 static void __exit vmx_exit(void)
8690 {
8691         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8692         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8693         free_page((unsigned long)vmx_msr_bitmap_legacy);
8694         free_page((unsigned long)vmx_msr_bitmap_longmode);
8695         free_page((unsigned long)vmx_io_bitmap_b);
8696         free_page((unsigned long)vmx_io_bitmap_a);
8697         free_page((unsigned long)vmx_vmwrite_bitmap);
8698         free_page((unsigned long)vmx_vmread_bitmap);
8699
8700 #ifdef CONFIG_KEXEC
8701         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8702         synchronize_rcu();
8703 #endif
8704
8705         kvm_exit();
8706 }
8707
8708 module_init(vmx_init)
8709 module_exit(vmx_exit)