2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/init.h>
53 #include <linux/mbus.h>
55 #include <linux/ioport.h>
57 #include <linux/of_address.h>
58 #include <linux/debugfs.h>
59 #include <linux/log2.h>
60 #include <linux/syscore_ops.h>
61 #include <linux/memblock.h>
64 * DDR target is the same on all platforms.
69 * CPU Address Decode Windows registers
71 #define WIN_CTRL_OFF 0x0000
72 #define WIN_CTRL_ENABLE BIT(0)
73 /* Only on HW I/O coherency capable platforms */
74 #define WIN_CTRL_SYNCBARRIER BIT(1)
75 #define WIN_CTRL_TGT_MASK 0xf0
76 #define WIN_CTRL_TGT_SHIFT 4
77 #define WIN_CTRL_ATTR_MASK 0xff00
78 #define WIN_CTRL_ATTR_SHIFT 8
79 #define WIN_CTRL_SIZE_MASK 0xffff0000
80 #define WIN_CTRL_SIZE_SHIFT 16
81 #define WIN_BASE_OFF 0x0004
82 #define WIN_BASE_LOW 0xffff0000
83 #define WIN_BASE_HIGH 0xf
84 #define WIN_REMAP_LO_OFF 0x0008
85 #define WIN_REMAP_LOW 0xffff0000
86 #define WIN_REMAP_HI_OFF 0x000c
88 #define UNIT_SYNC_BARRIER_OFF 0x84
89 #define UNIT_SYNC_BARRIER_ALL 0xFFFF
91 #define ATTR_HW_COHERENCY (0x1 << 4)
93 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
94 #define DDR_BASE_CS_HIGH_MASK 0xf
95 #define DDR_BASE_CS_LOW_MASK 0xff000000
96 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
97 #define DDR_SIZE_ENABLED BIT(0)
98 #define DDR_SIZE_CS_MASK 0x1c
99 #define DDR_SIZE_CS_SHIFT 2
100 #define DDR_SIZE_MASK 0xff000000
102 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
104 /* Relative to mbusbridge_base */
105 #define MBUS_BRIDGE_CTRL_OFF 0x0
106 #define MBUS_BRIDGE_SIZE_MASK 0xffff0000
107 #define MBUS_BRIDGE_BASE_OFF 0x4
108 #define MBUS_BRIDGE_BASE_MASK 0xffff0000
110 /* Maximum number of windows, for all known platforms */
111 #define MBUS_WINS_MAX 20
113 struct mvebu_mbus_state;
115 struct mvebu_mbus_soc_data {
116 unsigned int num_wins;
117 bool has_mbus_bridge;
118 unsigned int (*win_cfg_offset)(const int win);
119 unsigned int (*win_remap_offset)(const int win);
120 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
121 int (*save_cpu_target)(struct mvebu_mbus_state *s,
123 int (*show_cpu_target)(struct mvebu_mbus_state *s,
124 struct seq_file *seq, void *v);
128 * Used to store the state of one MBus window accross suspend/resume.
130 struct mvebu_mbus_win_data {
137 struct mvebu_mbus_state {
138 void __iomem *mbuswins_base;
139 void __iomem *sdramwins_base;
140 void __iomem *mbusbridge_base;
141 phys_addr_t sdramwins_phys_base;
142 struct dentry *debugfs_root;
143 struct dentry *debugfs_sdram;
144 struct dentry *debugfs_devs;
145 struct resource pcie_mem_aperture;
146 struct resource pcie_io_aperture;
147 const struct mvebu_mbus_soc_data *soc;
150 /* Used during suspend/resume */
151 u32 mbus_bridge_ctrl;
152 u32 mbus_bridge_base;
153 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
156 static struct mvebu_mbus_state mbus_state;
158 static struct mbus_dram_target_info mvebu_mbus_dram_info;
159 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
161 return &mvebu_mbus_dram_info;
163 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
165 /* Checks whether the given window has remap capability */
166 static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
169 return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
173 * Functions to manipulate the address decoding windows
176 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
177 int win, int *enabled, u64 *base,
178 u32 *size, u8 *target, u8 *attr,
181 void __iomem *addr = mbus->mbuswins_base +
182 mbus->soc->win_cfg_offset(win);
183 u32 basereg = readl(addr + WIN_BASE_OFF);
184 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
186 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
192 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
193 *base |= (basereg & WIN_BASE_LOW);
194 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
197 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
200 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
203 if (mvebu_mbus_window_is_remappable(mbus, win)) {
204 u32 remap_low, remap_hi;
205 void __iomem *addr_rmp = mbus->mbuswins_base +
206 mbus->soc->win_remap_offset(win);
207 remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
208 remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
209 *remap = ((u64)remap_hi << 32) | remap_low;
215 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
220 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
221 writel(0, addr + WIN_BASE_OFF);
222 writel(0, addr + WIN_CTRL_OFF);
224 if (mvebu_mbus_window_is_remappable(mbus, win)) {
225 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
226 writel(0, addr + WIN_REMAP_LO_OFF);
227 writel(0, addr + WIN_REMAP_HI_OFF);
231 /* Checks whether the given window number is available */
233 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
236 void __iomem *addr = mbus->mbuswins_base +
237 mbus->soc->win_cfg_offset(win);
238 u32 ctrl = readl(addr + WIN_CTRL_OFF);
240 return !(ctrl & WIN_CTRL_ENABLE);
244 * Checks whether the given (base, base+size) area doesn't overlap an
247 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
248 phys_addr_t base, size_t size,
251 u64 end = (u64)base + size;
254 for (win = 0; win < mbus->soc->num_wins; win++) {
260 mvebu_mbus_read_window(mbus, win,
261 &enabled, &wbase, &wsize,
262 &wtarget, &wattr, NULL);
267 wend = wbase + wsize;
270 * Check if the current window overlaps with the
271 * proposed physical range
273 if ((u64)base < wend && end > wbase)
280 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
281 phys_addr_t base, size_t size)
285 for (win = 0; win < mbus->soc->num_wins; win++) {
290 mvebu_mbus_read_window(mbus, win,
291 &enabled, &wbase, &wsize,
297 if (base == wbase && size == wsize)
304 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
305 int win, phys_addr_t base, size_t size,
306 phys_addr_t remap, u8 target,
309 void __iomem *addr = mbus->mbuswins_base +
310 mbus->soc->win_cfg_offset(win);
311 u32 ctrl, remap_addr;
313 if (!is_power_of_2(size)) {
314 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
318 if ((base & (phys_addr_t)(size - 1)) != 0) {
319 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
324 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
325 (attr << WIN_CTRL_ATTR_SHIFT) |
326 (target << WIN_CTRL_TGT_SHIFT) |
328 if (mbus->hw_io_coherency)
329 ctrl |= WIN_CTRL_SYNCBARRIER;
331 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
332 writel(ctrl, addr + WIN_CTRL_OFF);
334 if (mvebu_mbus_window_is_remappable(mbus, win)) {
335 void __iomem *addr_rmp = mbus->mbuswins_base +
336 mbus->soc->win_remap_offset(win);
338 if (remap == MVEBU_MBUS_NO_REMAP)
342 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
343 writel(0, addr_rmp + WIN_REMAP_HI_OFF);
349 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
350 phys_addr_t base, size_t size,
351 phys_addr_t remap, u8 target,
356 if (remap == MVEBU_MBUS_NO_REMAP) {
357 for (win = 0; win < mbus->soc->num_wins; win++) {
358 if (mvebu_mbus_window_is_remappable(mbus, win))
361 if (mvebu_mbus_window_is_free(mbus, win))
362 return mvebu_mbus_setup_window(mbus, win, base,
368 for (win = 0; win < mbus->soc->num_wins; win++) {
369 /* Skip window if need remap but is not supported */
370 if ((remap != MVEBU_MBUS_NO_REMAP) &&
371 !mvebu_mbus_window_is_remappable(mbus, win))
374 if (mvebu_mbus_window_is_free(mbus, win))
375 return mvebu_mbus_setup_window(mbus, win, base, size,
376 remap, target, attr);
386 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
387 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
388 struct seq_file *seq, void *v)
392 for (i = 0; i < 4; i++) {
393 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
394 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
398 if (!(sizereg & DDR_SIZE_ENABLED)) {
399 seq_printf(seq, "[%d] disabled\n", i);
403 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
404 base |= basereg & DDR_BASE_CS_LOW_MASK;
405 size = (sizereg | ~DDR_SIZE_MASK);
407 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
408 i, (unsigned long long)base,
409 (unsigned long long)base + size + 1,
410 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
416 /* Special function for Dove */
417 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
418 struct seq_file *seq, void *v)
422 for (i = 0; i < 2; i++) {
423 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
428 seq_printf(seq, "[%d] disabled\n", i);
432 base = map & 0xff800000;
433 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
435 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
436 i, (unsigned long long)base,
437 (unsigned long long)base + size, i);
443 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
445 struct mvebu_mbus_state *mbus = &mbus_state;
446 return mbus->soc->show_cpu_target(mbus, seq, v);
449 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
451 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
454 static const struct file_operations mvebu_sdram_debug_fops = {
455 .open = mvebu_sdram_debug_open,
458 .release = single_release,
461 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
463 struct mvebu_mbus_state *mbus = &mbus_state;
466 for (win = 0; win < mbus->soc->num_wins; win++) {
472 mvebu_mbus_read_window(mbus, win,
473 &enabled, &wbase, &wsize,
474 &wtarget, &wattr, &wremap);
477 seq_printf(seq, "[%02d] disabled\n", win);
481 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
482 win, (unsigned long long)wbase,
483 (unsigned long long)(wbase + wsize), wtarget, wattr);
485 if (!is_power_of_2(wsize) ||
486 ((wbase & (u64)(wsize - 1)) != 0))
487 seq_puts(seq, " (Invalid base/size!!)");
489 if (mvebu_mbus_window_is_remappable(mbus, win)) {
490 seq_printf(seq, " (remap %016llx)\n",
491 (unsigned long long)wremap);
493 seq_printf(seq, "\n");
499 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
501 return single_open(file, mvebu_devs_debug_show, inode->i_private);
504 static const struct file_operations mvebu_devs_debug_fops = {
505 .open = mvebu_devs_debug_open,
508 .release = single_release,
512 * SoC-specific functions and definitions
515 static unsigned int generic_mbus_win_cfg_offset(int win)
520 static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
522 /* The register layout is a bit annoying and the below code
523 * tries to cope with it.
524 * - At offset 0x0, there are the registers for the first 8
525 * windows, with 4 registers of 32 bits per window (ctrl,
526 * base, remap low, remap high)
527 * - Then at offset 0x80, there is a hole of 0x10 bytes for
528 * the internal registers base address and internal units
529 * sync barrier register.
530 * - Then at offset 0x90, there the registers for 12
531 * windows, with only 2 registers of 32 bits per window
537 return 0x90 + ((win - 8) << 3);
540 static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
545 return 0x900 + ((win - 8) << 4);
548 static unsigned int generic_mbus_win_remap_2_offset(int win)
551 return generic_mbus_win_cfg_offset(win);
553 return MVEBU_MBUS_NO_REMAP;
556 static unsigned int generic_mbus_win_remap_4_offset(int win)
559 return generic_mbus_win_cfg_offset(win);
561 return MVEBU_MBUS_NO_REMAP;
564 static unsigned int generic_mbus_win_remap_8_offset(int win)
567 return generic_mbus_win_cfg_offset(win);
569 return MVEBU_MBUS_NO_REMAP;
572 static unsigned int armada_xp_mbus_win_remap_offset(int win)
575 return generic_mbus_win_cfg_offset(win);
577 return 0xF0 - WIN_REMAP_LO_OFF;
579 return MVEBU_MBUS_NO_REMAP;
583 * Use the memblock information to find the MBus bridge hole in the
584 * physical address space.
587 mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
589 struct memblock_region *r;
592 for_each_memblock(memory, r) {
594 * This part of the memory is above 4 GB, so we don't
595 * care for the MBus bridge hole.
597 if (r->base >= 0x100000000)
601 * The MBus bridge hole is at the end of the RAM under
604 if (r->base + r->size > s)
605 s = r->base + r->size;
613 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
617 uint64_t mbus_bridge_base, mbus_bridge_end;
619 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
621 mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
623 for (i = 0, cs = 0; i < 4; i++) {
624 u64 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
625 u64 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
627 struct mbus_dram_window *w;
629 /* Ignore entries that are not enabled */
630 if (!(size & DDR_SIZE_ENABLED))
634 * Ignore entries whose base address is above 2^32,
635 * since devices cannot DMA to such high addresses
637 if (base & DDR_BASE_CS_HIGH_MASK)
640 base = base & DDR_BASE_CS_LOW_MASK;
641 size = (size | ~DDR_SIZE_MASK) + 1;
645 * Adjust base/size of the current CS to make sure it
646 * doesn't overlap with the MBus bridge hole. This is
647 * particularly important for devices that do DMA from
648 * DRAM to a SRAM mapped in a MBus window, such as the
649 * CESA cryptographic engine.
653 * The CS is fully enclosed inside the MBus bridge
654 * area, so ignore it.
656 if (base >= mbus_bridge_base && end <= mbus_bridge_end)
660 * Beginning of CS overlaps with end of MBus, raise CS
661 * base address, and shrink its size.
663 if (base >= mbus_bridge_base && end > mbus_bridge_end) {
664 size -= mbus_bridge_end - base;
665 base = mbus_bridge_end;
669 * End of CS overlaps with beginning of MBus, shrink
672 if (base < mbus_bridge_base && end > mbus_bridge_base)
673 size -= end - mbus_bridge_base;
675 w = &mvebu_mbus_dram_info.cs[cs++];
677 w->mbus_attr = 0xf & ~(1 << i);
678 if (mbus->hw_io_coherency)
679 w->mbus_attr |= ATTR_HW_COHERENCY;
683 mvebu_mbus_dram_info.num_cs = cs;
687 mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
692 for (i = 0; i < 4; i++) {
693 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
694 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
696 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
698 writel(base, store_addr++);
699 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
701 writel(size, store_addr++);
704 /* We've written 16 words to the store address */
709 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
714 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
716 for (i = 0, cs = 0; i < 2; i++) {
717 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
720 * Chip select enabled?
723 struct mbus_dram_window *w;
725 w = &mvebu_mbus_dram_info.cs[cs++];
727 w->mbus_attr = 0; /* CS address decoding done inside */
728 /* the DDR controller, no need to */
729 /* provide attributes */
730 w->base = map & 0xff800000;
731 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
735 mvebu_mbus_dram_info.num_cs = cs;
739 mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
744 for (i = 0; i < 2; i++) {
745 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
747 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
749 writel(map, store_addr++);
752 /* We've written 4 words to the store address */
756 int mvebu_mbus_save_cpu_target(u32 *store_addr)
758 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
761 static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
763 .has_mbus_bridge = true,
764 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
765 .win_remap_offset = generic_mbus_win_remap_8_offset,
766 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
767 .show_cpu_target = mvebu_sdram_debug_show_orion,
768 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
771 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
773 .has_mbus_bridge = true,
774 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
775 .win_remap_offset = armada_xp_mbus_win_remap_offset,
776 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
777 .show_cpu_target = mvebu_sdram_debug_show_orion,
778 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
781 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
783 .win_cfg_offset = generic_mbus_win_cfg_offset,
784 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
785 .win_remap_offset = generic_mbus_win_remap_4_offset,
786 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
787 .show_cpu_target = mvebu_sdram_debug_show_orion,
790 static const struct mvebu_mbus_soc_data dove_mbus_data = {
792 .win_cfg_offset = generic_mbus_win_cfg_offset,
793 .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
794 .win_remap_offset = generic_mbus_win_remap_4_offset,
795 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
796 .show_cpu_target = mvebu_sdram_debug_show_dove,
800 * Some variants of Orion5x have 4 remappable windows, some other have
803 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
805 .win_cfg_offset = generic_mbus_win_cfg_offset,
806 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
807 .win_remap_offset = generic_mbus_win_remap_4_offset,
808 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
809 .show_cpu_target = mvebu_sdram_debug_show_orion,
812 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
814 .win_cfg_offset = generic_mbus_win_cfg_offset,
815 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
816 .win_remap_offset = generic_mbus_win_remap_2_offset,
817 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
818 .show_cpu_target = mvebu_sdram_debug_show_orion,
821 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
823 .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
824 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
825 .win_remap_offset = generic_mbus_win_remap_8_offset,
826 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
827 .show_cpu_target = mvebu_sdram_debug_show_orion,
830 static const struct of_device_id of_mvebu_mbus_ids[] = {
831 { .compatible = "marvell,armada370-mbus",
832 .data = &armada_370_mbus_data, },
833 { .compatible = "marvell,armada375-mbus",
834 .data = &armada_xp_mbus_data, },
835 { .compatible = "marvell,armada380-mbus",
836 .data = &armada_xp_mbus_data, },
837 { .compatible = "marvell,armadaxp-mbus",
838 .data = &armada_xp_mbus_data, },
839 { .compatible = "marvell,kirkwood-mbus",
840 .data = &kirkwood_mbus_data, },
841 { .compatible = "marvell,dove-mbus",
842 .data = &dove_mbus_data, },
843 { .compatible = "marvell,orion5x-88f5281-mbus",
844 .data = &orion5x_4win_mbus_data, },
845 { .compatible = "marvell,orion5x-88f5182-mbus",
846 .data = &orion5x_2win_mbus_data, },
847 { .compatible = "marvell,orion5x-88f5181-mbus",
848 .data = &orion5x_2win_mbus_data, },
849 { .compatible = "marvell,orion5x-88f6183-mbus",
850 .data = &orion5x_4win_mbus_data, },
851 { .compatible = "marvell,mv78xx0-mbus",
852 .data = &mv78xx0_mbus_data, },
857 * Public API of the driver
859 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
860 unsigned int attribute,
861 phys_addr_t base, size_t size,
864 struct mvebu_mbus_state *s = &mbus_state;
866 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
867 pr_err("cannot add window '%x:%x', conflicts with another window\n",
872 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
875 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
876 phys_addr_t base, size_t size)
878 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
879 size, MVEBU_MBUS_NO_REMAP);
882 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
886 win = mvebu_mbus_find_window(&mbus_state, base, size);
890 mvebu_mbus_disable_window(&mbus_state, win);
894 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
898 *res = mbus_state.pcie_mem_aperture;
901 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
905 *res = mbus_state.pcie_io_aperture;
908 static __init int mvebu_mbus_debugfs_init(void)
910 struct mvebu_mbus_state *s = &mbus_state;
913 * If no base has been initialized, doesn't make sense to
914 * register the debugfs entries. We may be on a multiplatform
915 * kernel that isn't running a Marvell EBU SoC.
917 if (!s->mbuswins_base)
920 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
921 if (s->debugfs_root) {
922 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
923 s->debugfs_root, NULL,
924 &mvebu_sdram_debug_fops);
925 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
926 s->debugfs_root, NULL,
927 &mvebu_devs_debug_fops);
932 fs_initcall(mvebu_mbus_debugfs_init);
934 static int mvebu_mbus_suspend(void)
936 struct mvebu_mbus_state *s = &mbus_state;
939 if (!s->mbusbridge_base)
942 for (win = 0; win < s->soc->num_wins; win++) {
943 void __iomem *addr = s->mbuswins_base +
944 s->soc->win_cfg_offset(win);
945 void __iomem *addr_rmp;
947 s->wins[win].base = readl(addr + WIN_BASE_OFF);
948 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
950 if (!mvebu_mbus_window_is_remappable(s, win))
953 addr_rmp = s->mbuswins_base +
954 s->soc->win_remap_offset(win);
956 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
957 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
960 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
961 MBUS_BRIDGE_CTRL_OFF);
962 s->mbus_bridge_base = readl(s->mbusbridge_base +
963 MBUS_BRIDGE_BASE_OFF);
968 static void mvebu_mbus_resume(void)
970 struct mvebu_mbus_state *s = &mbus_state;
973 writel(s->mbus_bridge_ctrl,
974 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
975 writel(s->mbus_bridge_base,
976 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
978 for (win = 0; win < s->soc->num_wins; win++) {
979 void __iomem *addr = s->mbuswins_base +
980 s->soc->win_cfg_offset(win);
981 void __iomem *addr_rmp;
983 writel(s->wins[win].base, addr + WIN_BASE_OFF);
984 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
986 if (!mvebu_mbus_window_is_remappable(s, win))
989 addr_rmp = s->mbuswins_base +
990 s->soc->win_remap_offset(win);
992 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
993 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
997 struct syscore_ops mvebu_mbus_syscore_ops = {
998 .suspend = mvebu_mbus_suspend,
999 .resume = mvebu_mbus_resume,
1002 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
1003 phys_addr_t mbuswins_phys_base,
1004 size_t mbuswins_size,
1005 phys_addr_t sdramwins_phys_base,
1006 size_t sdramwins_size,
1007 phys_addr_t mbusbridge_phys_base,
1008 size_t mbusbridge_size,
1013 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
1014 if (!mbus->mbuswins_base)
1017 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
1018 if (!mbus->sdramwins_base) {
1019 iounmap(mbus_state.mbuswins_base);
1023 mbus->sdramwins_phys_base = sdramwins_phys_base;
1025 if (mbusbridge_phys_base) {
1026 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
1028 if (!mbus->mbusbridge_base) {
1029 iounmap(mbus->sdramwins_base);
1030 iounmap(mbus->mbuswins_base);
1034 mbus->mbusbridge_base = NULL;
1036 for (win = 0; win < mbus->soc->num_wins; win++)
1037 mvebu_mbus_disable_window(mbus, win);
1039 mbus->soc->setup_cpu_target(mbus);
1042 writel(UNIT_SYNC_BARRIER_ALL,
1043 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
1045 register_syscore_ops(&mvebu_mbus_syscore_ops);
1050 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
1051 size_t mbuswins_size,
1052 phys_addr_t sdramwins_phys_base,
1053 size_t sdramwins_size)
1055 const struct of_device_id *of_id;
1057 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
1058 if (!strcmp(of_id->compatible, soc))
1061 if (!of_id->compatible[0]) {
1062 pr_err("could not find a matching SoC family\n");
1066 mbus_state.soc = of_id->data;
1068 return mvebu_mbus_common_init(&mbus_state,
1071 sdramwins_phys_base,
1072 sdramwins_size, 0, 0, false);
1077 * The window IDs in the ranges DT property have the following format:
1078 * - bits 28 to 31: MBus custom field
1079 * - bits 24 to 27: window target ID
1080 * - bits 16 to 23: window attribute ID
1081 * - bits 0 to 15: unused
1083 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
1084 #define TARGET(id) (((id) & 0x0F000000) >> 24)
1085 #define ATTR(id) (((id) & 0x00FF0000) >> 16)
1087 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
1091 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
1092 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
1097 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1099 pr_err("cannot add window '%04x:%04x', too many windows\n",
1107 mbus_parse_ranges(struct device_node *node,
1108 int *addr_cells, int *c_addr_cells, int *c_size_cells,
1109 int *cell_count, const __be32 **ranges_start,
1110 const __be32 **ranges_end)
1113 int ranges_len, tuple_len;
1115 /* Allow a node with no 'ranges' property */
1116 *ranges_start = of_get_property(node, "ranges", &ranges_len);
1117 if (*ranges_start == NULL) {
1118 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
1119 *ranges_start = *ranges_end = NULL;
1122 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
1124 *addr_cells = of_n_addr_cells(node);
1126 prop = of_get_property(node, "#address-cells", NULL);
1127 *c_addr_cells = be32_to_cpup(prop);
1129 prop = of_get_property(node, "#size-cells", NULL);
1130 *c_size_cells = be32_to_cpup(prop);
1132 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
1133 tuple_len = (*cell_count) * sizeof(__be32);
1135 if (ranges_len % tuple_len) {
1136 pr_warn("malformed ranges entry '%s'\n", node->name);
1142 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1143 struct device_node *np)
1145 int addr_cells, c_addr_cells, c_size_cells;
1146 int i, ret, cell_count;
1147 const __be32 *r, *ranges_start, *ranges_end;
1149 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
1150 &c_size_cells, &cell_count,
1151 &ranges_start, &ranges_end);
1155 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
1156 u32 windowid, base, size;
1160 * An entry with a non-zero custom field do not
1161 * correspond to a static window, so skip it.
1163 windowid = of_read_number(r, 1);
1164 if (CUSTOM(windowid))
1167 target = TARGET(windowid);
1168 attr = ATTR(windowid);
1170 base = of_read_number(r + c_addr_cells, addr_cells);
1171 size = of_read_number(r + c_addr_cells + addr_cells,
1173 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
1180 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1181 struct resource *mem,
1182 struct resource *io)
1188 * These are optional, so we make sure that resource_size(x) will
1191 memset(mem, 0, sizeof(struct resource));
1193 memset(io, 0, sizeof(struct resource));
1196 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1198 mem->start = reg[0];
1199 mem->end = mem->start + reg[1] - 1;
1200 mem->flags = IORESOURCE_MEM;
1203 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1206 io->end = io->start + reg[1] - 1;
1207 io->flags = IORESOURCE_IO;
1211 int __init mvebu_mbus_dt_init(bool is_coherent)
1213 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
1214 struct device_node *np, *controller;
1215 const struct of_device_id *of_id;
1219 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
1221 pr_err("could not find a matching SoC family\n");
1225 mbus_state.soc = of_id->data;
1227 prop = of_get_property(np, "controller", NULL);
1229 pr_err("required 'controller' property missing\n");
1233 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1235 pr_err("could not find an 'mbus-controller' node\n");
1239 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1240 pr_err("cannot get MBUS register address\n");
1244 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1245 pr_err("cannot get SDRAM register address\n");
1250 * Set the resource to 0 so that it can be left unmapped by
1251 * mvebu_mbus_common_init() if the DT doesn't carry the
1252 * necessary information. This is needed to preserve backward
1255 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1257 if (mbus_state.soc->has_mbus_bridge) {
1258 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1259 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1262 mbus_state.hw_io_coherency = is_coherent;
1264 /* Get optional pcie-{mem,io}-aperture properties */
1265 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1266 &mbus_state.pcie_io_aperture);
1268 ret = mvebu_mbus_common_init(&mbus_state,
1270 resource_size(&mbuswins_res),
1271 sdramwins_res.start,
1272 resource_size(&sdramwins_res),
1273 mbusbridge_res.start,
1274 resource_size(&mbusbridge_res),
1279 /* Setup statically declared windows in the DT */
1280 return mbus_dt_setup(&mbus_state, np);