drivers/dma/xgene-dma.c

   1 /*
   2  * Applied Micro X-Gene SoC DMA engine Driver
   3  *
   4  * Copyright (c) 2015, Applied Micro Circuits Corporation
   5  * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
   6  *          Loc Ho <lho@apm.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  *
  21  * NOTE: PM support is currently not available.
  22  */
  23
  24 #include <linux/acpi.h>
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/module.h>
  33 #include <linux/of_device.h>
  34
  35 #include "dmaengine.h"
  36
  37 /* X-Gene DMA ring csr registers and bit definations */
  38 #define XGENE_DMA_RING_CONFIG                   0x04
  39 #define XGENE_DMA_RING_ENABLE                   BIT(31)
  40 #define XGENE_DMA_RING_ID                       0x08
  41 #define XGENE_DMA_RING_ID_SETUP(v)              ((v) | BIT(31))
  42 #define XGENE_DMA_RING_ID_BUF                   0x0C
  43 #define XGENE_DMA_RING_ID_BUF_SETUP(v)          (((v) << 9) | BIT(21))
  44 #define XGENE_DMA_RING_THRESLD0_SET1            0x30
  45 #define XGENE_DMA_RING_THRESLD0_SET1_VAL        0X64
  46 #define XGENE_DMA_RING_THRESLD1_SET1            0x34
  47 #define XGENE_DMA_RING_THRESLD1_SET1_VAL        0xC8
  48 #define XGENE_DMA_RING_HYSTERESIS               0x68
  49 #define XGENE_DMA_RING_HYSTERESIS_VAL           0xFFFFFFFF
  50 #define XGENE_DMA_RING_STATE                    0x6C
  51 #define XGENE_DMA_RING_STATE_WR_BASE            0x70
  52 #define XGENE_DMA_RING_NE_INT_MODE              0x017C
  53 #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v)    \
  54         ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
  55 #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v)  \
  56         ((m) &= (~BIT(31 - (v))))
  57 #define XGENE_DMA_RING_CLKEN                    0xC208
  58 #define XGENE_DMA_RING_SRST                     0xC200
  59 #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN         0xD070
  60 #define XGENE_DMA_RING_BLK_MEM_RDY              0xD074
  61 #define XGENE_DMA_RING_BLK_MEM_RDY_VAL          0xFFFFFFFF
  62 #define XGENE_DMA_RING_DESC_CNT(v)              (((v) & 0x0001FFFE) >> 1)
  63 #define XGENE_DMA_RING_ID_GET(owner, num)       (((owner) << 6) | (num))
  64 #define XGENE_DMA_RING_DST_ID(v)                ((1 << 10) | (v))
  65 #define XGENE_DMA_RING_CMD_OFFSET               0x2C
  66 #define XGENE_DMA_RING_CMD_BASE_OFFSET(v)       ((v) << 6)
  67 #define XGENE_DMA_RING_COHERENT_SET(m)          \
  68         (((u32 *)(m))[2] |= BIT(4))
  69 #define XGENE_DMA_RING_ADDRL_SET(m, v)          \
  70         (((u32 *)(m))[2] |= (((v) >> 8) << 5))
  71 #define XGENE_DMA_RING_ADDRH_SET(m, v)          \
  72         (((u32 *)(m))[3] |= ((v) >> 35))
  73 #define XGENE_DMA_RING_ACCEPTLERR_SET(m)        \
  74         (((u32 *)(m))[3] |= BIT(19))
  75 #define XGENE_DMA_RING_SIZE_SET(m, v)           \
  76         (((u32 *)(m))[3] |= ((v) << 23))
  77 #define XGENE_DMA_RING_RECOMBBUF_SET(m)         \
  78         (((u32 *)(m))[3] |= BIT(27))
  79 #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m)     \
  80         (((u32 *)(m))[3] |= (0x7 << 28))
  81 #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m)     \
  82         (((u32 *)(m))[4] |= 0x3)
  83 #define XGENE_DMA_RING_SELTHRSH_SET(m)          \
  84         (((u32 *)(m))[4] |= BIT(3))
  85 #define XGENE_DMA_RING_TYPE_SET(m, v)           \
  86         (((u32 *)(m))[4] |= ((v) << 19))
  87
  88 /* X-Gene DMA device csr registers and bit definitions */
  89 #define XGENE_DMA_IPBRR                         0x0
  90 #define XGENE_DMA_DEV_ID_RD(v)                  ((v) & 0x00000FFF)
  91 #define XGENE_DMA_BUS_ID_RD(v)                  (((v) >> 12) & 3)
  92 #define XGENE_DMA_REV_NO_RD(v)                  (((v) >> 14) & 3)
  93 #define XGENE_DMA_GCR                           0x10
  94 #define XGENE_DMA_CH_SETUP(v)                   \
  95         ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
  96 #define XGENE_DMA_ENABLE(v)                     ((v) |= BIT(31))
  97 #define XGENE_DMA_DISABLE(v)                    ((v) &= ~BIT(31))
  98 #define XGENE_DMA_RAID6_CONT                    0x14
  99 #define XGENE_DMA_RAID6_MULTI_CTRL(v)           ((v) << 24)
 100 #define XGENE_DMA_INT                           0x70
 101 #define XGENE_DMA_INT_MASK                      0x74
 102 #define XGENE_DMA_INT_ALL_MASK                  0xFFFFFFFF
 103 #define XGENE_DMA_INT_ALL_UNMASK                0x0
 104 #define XGENE_DMA_INT_MASK_SHIFT                0x14
 105 #define XGENE_DMA_RING_INT0_MASK                0x90A0
 106 #define XGENE_DMA_RING_INT1_MASK                0x90A8
 107 #define XGENE_DMA_RING_INT2_MASK                0x90B0
 108 #define XGENE_DMA_RING_INT3_MASK                0x90B8
 109 #define XGENE_DMA_RING_INT4_MASK                0x90C0
 110 #define XGENE_DMA_CFG_RING_WQ_ASSOC             0x90E0
 111 #define XGENE_DMA_ASSOC_RING_MNGR1              0xFFFFFFFF
 112 #define XGENE_DMA_MEM_RAM_SHUTDOWN              0xD070
 113 #define XGENE_DMA_BLK_MEM_RDY                   0xD074
 114 #define XGENE_DMA_BLK_MEM_RDY_VAL               0xFFFFFFFF
 115 #define XGENE_DMA_RING_CMD_SM_OFFSET            0x8000
 116
 117 /* X-Gene SoC EFUSE csr register and bit defination */
 118 #define XGENE_SOC_JTAG1_SHADOW                  0x18
 119 #define XGENE_DMA_PQ_DISABLE_MASK               BIT(13)
 120
 121 /* X-Gene DMA Descriptor format */
 122 #define XGENE_DMA_DESC_NV_BIT                   BIT_ULL(50)
 123 #define XGENE_DMA_DESC_IN_BIT                   BIT_ULL(55)
 124 #define XGENE_DMA_DESC_C_BIT                    BIT_ULL(63)
 125 #define XGENE_DMA_DESC_DR_BIT                   BIT_ULL(61)
 126 #define XGENE_DMA_DESC_ELERR_POS                46
 127 #define XGENE_DMA_DESC_RTYPE_POS                56
 128 #define XGENE_DMA_DESC_LERR_POS                 60
 129 #define XGENE_DMA_DESC_BUFLEN_POS               48
 130 #define XGENE_DMA_DESC_HOENQ_NUM_POS            48
 131 #define XGENE_DMA_DESC_ELERR_RD(m)              \
 132         (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
 133 #define XGENE_DMA_DESC_LERR_RD(m)               \
 134         (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
 135 #define XGENE_DMA_DESC_STATUS(elerr, lerr)      \
 136         (((elerr) << 4) | (lerr))
 137
 138 /* X-Gene DMA descriptor empty s/w signature */
 139 #define XGENE_DMA_DESC_EMPTY_SIGNATURE          ~0ULL
 140
 141 /* X-Gene DMA configurable parameters defines */
 142 #define XGENE_DMA_RING_NUM              512
 143 #define XGENE_DMA_BUFNUM                0x0
 144 #define XGENE_DMA_CPU_BUFNUM            0x18
 145 #define XGENE_DMA_RING_OWNER_DMA        0x03
 146 #define XGENE_DMA_RING_OWNER_CPU        0x0F
 147 #define XGENE_DMA_RING_TYPE_REGULAR     0x01
 148 #define XGENE_DMA_RING_WQ_DESC_SIZE     32      /* 32 Bytes */
 149 #define XGENE_DMA_RING_NUM_CONFIG       5
 150 #define XGENE_DMA_MAX_CHANNEL           4
 151 #define XGENE_DMA_XOR_CHANNEL           0
 152 #define XGENE_DMA_PQ_CHANNEL            1
 153 #define XGENE_DMA_MAX_BYTE_CNT          0x4000  /* 16 KB */
 154 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
 155 #define XGENE_DMA_MAX_XOR_SRC           5
 156 #define XGENE_DMA_16K_BUFFER_LEN_CODE   0x0
 157 #define XGENE_DMA_INVALID_LEN_CODE      0x7800000000000000ULL
 158
 159 /* X-Gene DMA descriptor error codes */
 160 #define ERR_DESC_AXI                    0x01
 161 #define ERR_BAD_DESC                    0x02
 162 #define ERR_READ_DATA_AXI               0x03
 163 #define ERR_WRITE_DATA_AXI              0x04
 164 #define ERR_FBP_TIMEOUT                 0x05
 165 #define ERR_ECC                         0x06
 166 #define ERR_DIFF_SIZE                   0x08
 167 #define ERR_SCT_GAT_LEN                 0x09
 168 #define ERR_CRC_ERR                     0x11
 169 #define ERR_CHKSUM                      0x12
 170 #define ERR_DIF                         0x13
 171
 172 /* X-Gene DMA error interrupt codes */
 173 #define ERR_DIF_SIZE_INT                0x0
 174 #define ERR_GS_ERR_INT                  0x1
 175 #define ERR_FPB_TIMEO_INT               0x2
 176 #define ERR_WFIFO_OVF_INT               0x3
 177 #define ERR_RFIFO_OVF_INT               0x4
 178 #define ERR_WR_TIMEO_INT                0x5
 179 #define ERR_RD_TIMEO_INT                0x6
 180 #define ERR_WR_ERR_INT                  0x7
 181 #define ERR_RD_ERR_INT                  0x8
 182 #define ERR_BAD_DESC_INT                0x9
 183 #define ERR_DESC_DST_INT                0xA
 184 #define ERR_DESC_SRC_INT                0xB
 185
 186 /* X-Gene DMA flyby operation code */
 187 #define FLYBY_2SRC_XOR                  0x80
 188 #define FLYBY_3SRC_XOR                  0x90
 189 #define FLYBY_4SRC_XOR                  0xA0
 190 #define FLYBY_5SRC_XOR                  0xB0
 191
 192 /* X-Gene DMA SW descriptor flags */
 193 #define XGENE_DMA_FLAG_64B_DESC         BIT(0)
 194
 195 /* Define to dump X-Gene DMA descriptor */
 196 #define XGENE_DMA_DESC_DUMP(desc, m)    \
 197         print_hex_dump(KERN_ERR, (m),   \
 198                         DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
 199
 200 #define to_dma_desc_sw(tx)              \
 201         container_of(tx, struct xgene_dma_desc_sw, tx)
 202 #define to_dma_chan(dchan)              \
 203         container_of(dchan, struct xgene_dma_chan, dma_chan)
 204
 205 #define chan_dbg(chan, fmt, arg...)     \
 206         dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
 207 #define chan_err(chan, fmt, arg...)     \
 208         dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
 209
 210 struct xgene_dma_desc_hw {
 211         __le64 m0;
 212         __le64 m1;
 213         __le64 m2;
 214         __le64 m3;
 215 };
 216
 217 enum xgene_dma_ring_cfgsize {
 218         XGENE_DMA_RING_CFG_SIZE_512B,
 219         XGENE_DMA_RING_CFG_SIZE_2KB,
 220         XGENE_DMA_RING_CFG_SIZE_16KB,
 221         XGENE_DMA_RING_CFG_SIZE_64KB,
 222         XGENE_DMA_RING_CFG_SIZE_512KB,
 223         XGENE_DMA_RING_CFG_SIZE_INVALID
 224 };
 225
 226 struct xgene_dma_ring {
 227         struct xgene_dma *pdma;
 228         u8 buf_num;
 229         u16 id;
 230         u16 num;
 231         u16 head;
 232         u16 owner;
 233         u16 slots;
 234         u16 dst_ring_num;
 235         u32 size;
 236         void __iomem *cmd;
 237         void __iomem *cmd_base;
 238         dma_addr_t desc_paddr;
 239         u32 state[XGENE_DMA_RING_NUM_CONFIG];
 240         enum xgene_dma_ring_cfgsize cfgsize;
 241         union {
 242                 void *desc_vaddr;
 243                 struct xgene_dma_desc_hw *desc_hw;
 244         };
 245 };
 246
 247 struct xgene_dma_desc_sw {
 248         struct xgene_dma_desc_hw desc1;
 249         struct xgene_dma_desc_hw desc2;
 250         u32 flags;
 251         struct list_head node;
 252         struct list_head tx_list;
 253         struct dma_async_tx_descriptor tx;
 254 };
 255
 256 /**
 257  * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
 258  * @dma_chan: dmaengine channel object member
 259  * @pdma: X-Gene DMA device structure reference
 260  * @dev: struct device reference for dma mapping api
 261  * @id: raw id of this channel
 262  * @rx_irq: channel IRQ
 263  * @name: name of X-Gene DMA channel
 264  * @lock: serializes enqueue/dequeue operations to the descriptor pool
 265  * @pending: number of transaction request pushed to DMA controller for
 266  *      execution, but still waiting for completion,
 267  * @max_outstanding: max number of outstanding request we can push to channel
 268  * @ld_pending: descriptors which are queued to run, but have not yet been
 269  *      submitted to the hardware for execution
 270  * @ld_running: descriptors which are currently being executing by the hardware
 271  * @ld_completed: descriptors which have finished execution by the hardware.
 272  *      These descriptors have already had their cleanup actions run. They
 273  *      are waiting for the ACK bit to be set by the async tx API.
 274  * @desc_pool: descriptor pool for DMA operations
 275  * @tasklet: bottom half where all completed descriptors cleans
 276  * @tx_ring: transmit ring descriptor that we use to prepare actual
 277  *      descriptors for further executions
 278  * @rx_ring: receive ring descriptor that we use to get completed DMA
 279  *      descriptors during cleanup time
 280  */
 281 struct xgene_dma_chan {
 282         struct dma_chan dma_chan;
 283         struct xgene_dma *pdma;
 284         struct device *dev;
 285         int id;
 286         int rx_irq;
 287         char name[10];
 288         spinlock_t lock;
 289         int pending;
 290         int max_outstanding;
 291         struct list_head ld_pending;
 292         struct list_head ld_running;
 293         struct list_head ld_completed;
 294         struct dma_pool *desc_pool;
 295         struct tasklet_struct tasklet;
 296         struct xgene_dma_ring tx_ring;
 297         struct xgene_dma_ring rx_ring;
 298 };
 299
 300 /**
 301  * struct xgene_dma - internal representation of an X-Gene DMA device
 302  * @err_irq: DMA error irq number
 303  * @ring_num: start id number for DMA ring
 304  * @csr_dma: base for DMA register access
 305  * @csr_ring: base for DMA ring register access
 306  * @csr_ring_cmd: base for DMA ring command register access
 307  * @csr_efuse: base for efuse register access
 308  * @dma_dev: embedded struct dma_device
 309  * @chan: reference to X-Gene DMA channels
 310  */
 311 struct xgene_dma {
 312         struct device *dev;
 313         struct clk *clk;
 314         int err_irq;
 315         int ring_num;
 316         void __iomem *csr_dma;
 317         void __iomem *csr_ring;
 318         void __iomem *csr_ring_cmd;
 319         void __iomem *csr_efuse;
 320         struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];
 321         struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL];
 322 };
 323
 324 static const char * const xgene_dma_desc_err[] = {
 325         [ERR_DESC_AXI] = "AXI error when reading src/dst link list",
 326         [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc",
 327         [ERR_READ_DATA_AXI] = "AXI error when reading data",
 328         [ERR_WRITE_DATA_AXI] = "AXI error when writing data",
 329         [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch",
 330         [ERR_ECC] = "ECC double bit error",
 331         [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result",
 332         [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same",
 333         [ERR_CRC_ERR] = "CRC error",
 334         [ERR_CHKSUM] = "Checksum error",
 335         [ERR_DIF] = "DIF error",
 336 };
 337
 338 static const char * const xgene_dma_err[] = {
 339         [ERR_DIF_SIZE_INT] = "DIF size error",
 340         [ERR_GS_ERR_INT] = "Gather scatter not same size error",
 341         [ERR_FPB_TIMEO_INT] = "Free pool time out error",
 342         [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error",
 343         [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error",
 344         [ERR_WR_TIMEO_INT] = "Write time out error",
 345         [ERR_RD_TIMEO_INT] = "Read time out error",
 346         [ERR_WR_ERR_INT] = "HBF bus write error",
 347         [ERR_RD_ERR_INT] = "HBF bus read error",
 348         [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error",
 349         [ERR_DESC_DST_INT] = "HFB reading dst link address error",
 350         [ERR_DESC_SRC_INT] = "HFB reading src link address error",
 351 };
 352
 353 static bool is_pq_enabled(struct xgene_dma *pdma)
 354 {
 355         u32 val;
 356
 357         val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
 358         return !(val & XGENE_DMA_PQ_DISABLE_MASK);
 359 }
 360
 361 static u64 xgene_dma_encode_len(size_t len)
 362 {
 363         return (len < XGENE_DMA_MAX_BYTE_CNT) ?
 364                 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
 365                 XGENE_DMA_16K_BUFFER_LEN_CODE;
 366 }
 367
 368 static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
 369 {
 370         static u8 flyby_type[] = {
 371                 FLYBY_2SRC_XOR, /* Dummy */
 372                 FLYBY_2SRC_XOR, /* Dummy */
 373                 FLYBY_2SRC_XOR,
 374                 FLYBY_3SRC_XOR,
 375                 FLYBY_4SRC_XOR,
 376                 FLYBY_5SRC_XOR
 377         };
 378
 379         return flyby_type[src_cnt];
 380 }
 381
 382 static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring *ring)
 383 {
 384         u32 __iomem *cmd_base = ring->cmd_base;
 385         u32 ring_state = ioread32(&cmd_base[1]);
 386
 387         return XGENE_DMA_RING_DESC_CNT(ring_state);
 388 }
 389
 390 static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
 391                                      dma_addr_t *paddr)
 392 {
 393         size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
 394                         *len : XGENE_DMA_MAX_BYTE_CNT;
 395
 396         *ext8 |= cpu_to_le64(*paddr);
 397         *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes));
 398         *len -= nbytes;
 399         *paddr += nbytes;
 400 }
 401
 402 static void xgene_dma_invalidate_buffer(__le64 *ext8)
 403 {
 404         *ext8 |= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE);
 405 }
 406
 407 static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx)
 408 {
 409         switch (idx) {
 410         case 0:
 411                 return &desc->m1;
 412         case 1:
 413                 return &desc->m0;
 414         case 2:
 415                 return &desc->m3;
 416         case 3:
 417                 return &desc->m2;
 418         default:
 419                 pr_err("Invalid dma descriptor index\n");
 420         }
 421
 422         return NULL;
 423 }
 424
 425 static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc,
 426                                 u16 dst_ring_num)
 427 {
 428         desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT);
 429         desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA <<
 430                                 XGENE_DMA_DESC_RTYPE_POS);
 431         desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT);
 432         desc->m3 |= cpu_to_le64((u64)dst_ring_num <<
 433                                 XGENE_DMA_DESC_HOENQ_NUM_POS);
 434 }
 435
 436 static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan *chan,
 437                                     struct xgene_dma_desc_sw *desc_sw,
 438                                     dma_addr_t dst, dma_addr_t src,
 439                                     size_t len)
 440 {
 441         struct xgene_dma_desc_hw *desc1, *desc2;
 442         int i;
 443
 444         /* Get 1st descriptor */
 445         desc1 = &desc_sw->desc1;
 446         xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
 447
 448         /* Set destination address */
 449         desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
 450         desc1->m3 |= cpu_to_le64(dst);
 451
 452         /* Set 1st source address */
 453         xgene_dma_set_src_buffer(&desc1->m1, &len, &src);
 454
 455         if (!len)
 456                 return;
 457
 458         /*
 459          * We need to split this source buffer,
 460          * and need to use 2nd descriptor
 461          */
 462         desc2 = &desc_sw->desc2;
 463         desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
 464
 465         /* Set 2nd to 5th source address */
 466         for (i = 0; i < 4 && len; i++)
 467                 xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2, i),
 468                                          &len, &src);
 469
 470         /* Invalidate unused source address field */
 471         for (; i < 4; i++)
 472                 xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
 473
 474         /* Updated flag that we have prepared 64B descriptor */
 475         desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
 476 }
 477
 478 static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
 479                                     struct xgene_dma_desc_sw *desc_sw,
 480                                     dma_addr_t *dst, dma_addr_t *src,
 481                                     u32 src_cnt, size_t *nbytes,
 482                                     const u8 *scf)
 483 {
 484         struct xgene_dma_desc_hw *desc1, *desc2;
 485         size_t len = *nbytes;
 486         int i;
 487
 488         desc1 = &desc_sw->desc1;
 489         desc2 = &desc_sw->desc2;
 490
 491         /* Initialize DMA descriptor */
 492         xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
 493
 494         /* Set destination address */
 495         desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
 496         desc1->m3 |= cpu_to_le64(*dst);
 497
 498         /* We have multiple source addresses, so need to set NV bit*/
 499         desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
 500
 501         /* Set flyby opcode */
 502         desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt));
 503
 504         /* Set 1st to 5th source addresses */
 505         for (i = 0; i < src_cnt; i++) {
 506                 len = *nbytes;
 507                 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 :
 508                                          xgene_dma_lookup_ext8(desc2, i - 1),
 509                                          &len, &src[i]);
 510                 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8)));
 511         }
 512
 513         /* Update meta data */
 514         *nbytes = len;
 515         *dst += XGENE_DMA_MAX_BYTE_CNT;
 516
 517         /* We need always 64B descriptor to perform xor or pq operations */
 518         desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
 519 }
 520
 521 static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 522 {
 523         struct xgene_dma_desc_sw *desc;
 524         struct xgene_dma_chan *chan;
 525         dma_cookie_t cookie;
 526
 527         if (unlikely(!tx))
 528                 return -EINVAL;
 529
 530         chan = to_dma_chan(tx->chan);
 531         desc = to_dma_desc_sw(tx);
 532
 533         spin_lock_bh(&chan->lock);
 534
 535         cookie = dma_cookie_assign(tx);
 536
 537         /* Add this transaction list onto the tail of the pending queue */
 538         list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
 539
 540         spin_unlock_bh(&chan->lock);
 541
 542         return cookie;
 543 }
 544
 545 static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan,
 546                                        struct xgene_dma_desc_sw *desc)
 547 {
 548         list_del(&desc->node);
 549         chan_dbg(chan, "LD %p free\n", desc);
 550         dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
 551 }
 552
 553 static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
 554                                  struct xgene_dma_chan *chan)
 555 {
 556         struct xgene_dma_desc_sw *desc;
 557         dma_addr_t phys;
 558
 559         desc = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &phys);
 560         if (!desc) {
 561                 chan_err(chan, "Failed to allocate LDs\n");
 562                 return NULL;
 563         }
 564
 565         memset(desc, 0, sizeof(*desc));
 566
 567         INIT_LIST_HEAD(&desc->tx_list);
 568         desc->tx.phys = phys;
 569         desc->tx.tx_submit = xgene_dma_tx_submit;
 570         dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan);
 571
 572         chan_dbg(chan, "LD %p allocated\n", desc);
 573
 574         return desc;
 575 }
 576
 577 /**
 578  * xgene_dma_clean_completed_descriptor - free all descriptors which
 579  * has been completed and acked
 580  * @chan: X-Gene DMA channel
 581  *
 582  * This function is used on all completed and acked descriptors.
 583  */
 584 static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan)
 585 {
 586         struct xgene_dma_desc_sw *desc, *_desc;
 587
 588         /* Run the callback for each descriptor, in order */
 589         list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
 590                 if (async_tx_test_ack(&desc->tx))
 591                         xgene_dma_clean_descriptor(chan, desc);
 592         }
 593 }
 594
 595 /**
 596  * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
 597  * @chan: X-Gene DMA channel
 598  * @desc: descriptor to cleanup and free
 599  *
 600  * This function is used on a descriptor which has been executed by the DMA
 601  * controller. It will run any callbacks, submit any dependencies.
 602  */
 603 static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan,
 604                                               struct xgene_dma_desc_sw *desc)
 605 {
 606         struct dma_async_tx_descriptor *tx = &desc->tx;
 607
 608         /*
 609          * If this is not the last transaction in the group,
 610          * then no need to complete cookie and run any callback as
 611          * this is not the tx_descriptor which had been sent to caller
 612          * of this DMA request
 613          */
 614
 615         if (tx->cookie == 0)
 616                 return;
 617
 618         dma_cookie_complete(tx);
 619
 620         /* Run the link descriptor callback function */
 621         if (tx->callback)
 622                 tx->callback(tx->callback_param);
 623
 624         dma_descriptor_unmap(tx);
 625
 626         /* Run any dependencies */
 627         dma_run_dependencies(tx);
 628 }
 629
 630 /**
 631  * xgene_dma_clean_running_descriptor - move the completed descriptor from
 632  * ld_running to ld_completed
 633  * @chan: X-Gene DMA channel
 634  * @desc: the descriptor which is completed
 635  *
 636  * Free the descriptor directly if acked by async_tx api,
 637  * else move it to queue ld_completed.
 638  */
 639 static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan,
 640                                                struct xgene_dma_desc_sw *desc)
 641 {
 642         /* Remove from the list of running transactions */
 643         list_del(&desc->node);
 644
 645         /*
 646          * the client is allowed to attach dependent operations
 647          * until 'ack' is set
 648          */
 649         if (!async_tx_test_ack(&desc->tx)) {
 650                 /*
 651                  * Move this descriptor to the list of descriptors which is
 652                  * completed, but still awaiting the 'ack' bit to be set.
 653                  */
 654                 list_add_tail(&desc->node, &chan->ld_completed);
 655                 return;
 656         }
 657
 658         chan_dbg(chan, "LD %p free\n", desc);
 659         dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
 660 }
 661
 662 static int xgene_chan_xfer_request(struct xgene_dma_ring *ring,
 663                                    struct xgene_dma_desc_sw *desc_sw)
 664 {
 665         struct xgene_dma_desc_hw *desc_hw;
 666
 667         /* Check if can push more descriptor to hw for execution */
 668         if (xgene_dma_ring_desc_cnt(ring) > (ring->slots - 2))
 669                 return -EBUSY;
 670
 671         /* Get hw descriptor from DMA tx ring */
 672         desc_hw = &ring->desc_hw[ring->head];
 673
 674         /*
 675          * Increment the head count to point next
 676          * descriptor for next time
 677          */
 678         if (++ring->head == ring->slots)
 679                 ring->head = 0;
 680
 681         /* Copy prepared sw descriptor data to hw descriptor */
 682         memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw));
 683
 684         /*
 685          * Check if we have prepared 64B descriptor,
 686          * in this case we need one more hw descriptor
 687          */
 688         if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) {
 689                 desc_hw = &ring->desc_hw[ring->head];
 690
 691                 if (++ring->head == ring->slots)
 692                         ring->head = 0;
 693
 694                 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
 695         }
 696
 697         /* Notify the hw that we have descriptor ready for execution */
 698         iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
 699                   2 : 1, ring->cmd);
 700
 701         return 0;
 702 }
 703
 704 /**
 705  * xgene_chan_xfer_ld_pending - push any pending transactions to hw
 706  * @chan : X-Gene DMA channel
 707  *
 708  * LOCKING: must hold chan->lock
 709  */
 710 static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
 711 {
 712         struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
 713         int ret;
 714
 715         /*
 716          * If the list of pending descriptors is empty, then we
 717          * don't need to do any work at all
 718          */
 719         if (list_empty(&chan->ld_pending)) {
 720                 chan_dbg(chan, "No pending LDs\n");
 721                 return;
 722         }
 723
 724         /*
 725          * Move elements from the queue of pending transactions onto the list
 726          * of running transactions and push it to hw for further executions
 727          */
 728         list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) {
 729                 /*
 730                  * Check if have pushed max number of transactions to hw
 731                  * as capable, so let's stop here and will push remaining
 732                  * elements from pening ld queue after completing some
 733                  * descriptors that we have already pushed
 734                  */
 735                 if (chan->pending >= chan->max_outstanding)
 736                         return;
 737
 738                 ret = xgene_chan_xfer_request(&chan->tx_ring, desc_sw);
 739                 if (ret)
 740                         return;
 741
 742                 /*
 743                  * Delete this element from ld pending queue and append it to
 744                  * ld running queue
 745                  */
 746                 list_move_tail(&desc_sw->node, &chan->ld_running);
 747
 748                 /* Increment the pending transaction count */
 749                 chan->pending++;
 750         }
 751 }
 752
 753 /**
 754  * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
 755  * and move them to ld_completed to free until flag 'ack' is set
 756  * @chan: X-Gene DMA channel
 757  *
 758  * This function is used on descriptors which have been executed by the DMA
 759  * controller. It will run any callbacks, submit any dependencies, then
 760  * free these descriptors if flag 'ack' is set.
 761  */
 762 static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan)
 763 {
 764         struct xgene_dma_ring *ring = &chan->rx_ring;
 765         struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
 766         struct xgene_dma_desc_hw *desc_hw;
 767         struct list_head ld_completed;
 768         u8 status;
 769
 770         INIT_LIST_HEAD(&ld_completed);
 771
 772         spin_lock_bh(&chan->lock);
 773
 774         /* Clean already completed and acked descriptors */
 775         xgene_dma_clean_completed_descriptor(chan);
 776
 777         /* Move all completed descriptors to ld completed queue, in order */
 778         list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
 779                 /* Get subsequent hw descriptor from DMA rx ring */
 780                 desc_hw = &ring->desc_hw[ring->head];
 781
 782                 /* Check if this descriptor has been completed */
 783                 if (unlikely(le64_to_cpu(desc_hw->m0) ==
 784                              XGENE_DMA_DESC_EMPTY_SIGNATURE))
 785                         break;
 786
 787                 if (++ring->head == ring->slots)
 788                         ring->head = 0;
 789
 790                 /* Check if we have any error with DMA transactions */
 791                 status = XGENE_DMA_DESC_STATUS(
 792                                 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
 793                                                         desc_hw->m0)),
 794                                 XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
 795                                                        desc_hw->m0)));
 796                 if (status) {
 797                         /* Print the DMA error type */
 798                         chan_err(chan, "%s\n", xgene_dma_desc_err[status]);
 799
 800                         /*
 801                          * We have DMA transactions error here. Dump DMA Tx
 802                          * and Rx descriptors for this request */
 803                         XGENE_DMA_DESC_DUMP(&desc_sw->desc1,
 804                                             "X-Gene DMA TX DESC1: ");
 805
 806                         if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC)
 807                                 XGENE_DMA_DESC_DUMP(&desc_sw->desc2,
 808                                                     "X-Gene DMA TX DESC2: ");
 809
 810                         XGENE_DMA_DESC_DUMP(desc_hw,
 811                                             "X-Gene DMA RX ERR DESC: ");
 812                 }
 813
 814                 /* Notify the hw about this completed descriptor */
 815                 iowrite32(-1, ring->cmd);
 816
 817                 /* Mark this hw descriptor as processed */
 818                 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
 819
 820                 /*
 821                  * Decrement the pending transaction count
 822                  * as we have processed one
 823                  */
 824                 chan->pending--;
 825
 826                 /*
 827                  * Delete this node from ld running queue and append it to
 828                  * ld completed queue for further processing
 829                  */
 830                 list_move_tail(&desc_sw->node, &ld_completed);
 831         }
 832
 833         /*
 834          * Start any pending transactions automatically
 835          * In the ideal case, we keep the DMA controller busy while we go
 836          * ahead and free the descriptors below.
 837          */
 838         xgene_chan_xfer_ld_pending(chan);
 839
 840         spin_unlock_bh(&chan->lock);
 841
 842         /* Run the callback for each descriptor, in order */
 843         list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
 844                 xgene_dma_run_tx_complete_actions(chan, desc_sw);
 845                 xgene_dma_clean_running_descriptor(chan, desc_sw);
 846         }
 847 }
 848
 849 static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
 850 {
 851         struct xgene_dma_chan *chan = to_dma_chan(dchan);
 852
 853         /* Has this channel already been allocated? */
 854         if (chan->desc_pool)
 855                 return 1;
 856
 857         chan->desc_pool = dma_pool_create(chan->name, chan->dev,
 858                                           sizeof(struct xgene_dma_desc_sw),
 859                                           0, 0);
 860         if (!chan->desc_pool) {
 861                 chan_err(chan, "Failed to allocate descriptor pool\n");
 862                 return -ENOMEM;
 863         }
 864
 865         chan_dbg(chan, "Allocate descripto pool\n");
 866
 867         return 1;
 868 }
 869
 870 /**
 871  * xgene_dma_free_desc_list - Free all descriptors in a queue
 872  * @chan: X-Gene DMA channel
 873  * @list: the list to free
 874  *
 875  * LOCKING: must hold chan->lock
 876  */
 877 static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan,
 878                                      struct list_head *list)
 879 {
 880         struct xgene_dma_desc_sw *desc, *_desc;
 881
 882         list_for_each_entry_safe(desc, _desc, list, node)
 883                 xgene_dma_clean_descriptor(chan, desc);
 884 }
 885
 886 static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
 887 {
 888         struct xgene_dma_chan *chan = to_dma_chan(dchan);
 889
 890         chan_dbg(chan, "Free all resources\n");
 891
 892         if (!chan->desc_pool)
 893                 return;
 894
 895         /* Process all running descriptor */
 896         xgene_dma_cleanup_descriptors(chan);
 897
 898         spin_lock_bh(&chan->lock);
 899
 900         /* Clean all link descriptor queues */
 901         xgene_dma_free_desc_list(chan, &chan->ld_pending);
 902         xgene_dma_free_desc_list(chan, &chan->ld_running);
 903         xgene_dma_free_desc_list(chan, &chan->ld_completed);
 904
 905         spin_unlock_bh(&chan->lock);
 906
 907         /* Delete this channel DMA pool */
 908         dma_pool_destroy(chan->desc_pool);
 909         chan->desc_pool = NULL;
 910 }
 911
 912 static struct dma_async_tx_descriptor *xgene_dma_prep_memcpy(
 913         struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
 914         size_t len, unsigned long flags)
 915 {
 916         struct xgene_dma_desc_sw *first = NULL, *new;
 917         struct xgene_dma_chan *chan;
 918         size_t copy;
 919
 920         if (unlikely(!dchan || !len))
 921                 return NULL;
 922
 923         chan = to_dma_chan(dchan);
 924
 925         do {
 926                 /* Allocate the link descriptor from DMA pool */
 927                 new = xgene_dma_alloc_descriptor(chan);
 928                 if (!new)
 929                         goto fail;
 930
 931                 /* Create the largest transaction possible */
 932                 copy = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
 933
 934                 /* Prepare DMA descriptor */
 935                 xgene_dma_prep_cpy_desc(chan, new, dst, src, copy);
 936
 937                 if (!first)
 938                         first = new;
 939
 940                 new->tx.cookie = 0;
 941                 async_tx_ack(&new->tx);
 942
 943                 /* Update metadata */
 944                 len -= copy;
 945                 dst += copy;
 946                 src += copy;
 947
 948                 /* Insert the link descriptor to the LD ring */
 949                 list_add_tail(&new->node, &first->tx_list);
 950         } while (len);
 951
 952         new->tx.flags = flags; /* client is in control of this ack */
 953         new->tx.cookie = -EBUSY;
 954         list_splice(&first->tx_list, &new->tx_list);
 955
 956         return &new->tx;
 957
 958 fail:
 959         if (!first)
 960                 return NULL;
 961
 962         xgene_dma_free_desc_list(chan, &first->tx_list);
 963         return NULL;
 964 }
 965
 966 static struct dma_async_tx_descriptor *xgene_dma_prep_sg(
 967         struct dma_chan *dchan, struct scatterlist *dst_sg,
 968         u32 dst_nents, struct scatterlist *src_sg,
 969         u32 src_nents, unsigned long flags)
 970 {
 971         struct xgene_dma_desc_sw *first = NULL, *new = NULL;
 972         struct xgene_dma_chan *chan;
 973         size_t dst_avail, src_avail;
 974         dma_addr_t dst, src;
 975         size_t len;
 976
 977         if (unlikely(!dchan))
 978                 return NULL;
 979
 980         if (unlikely(!dst_nents || !src_nents))
 981                 return NULL;
 982
 983         if (unlikely(!dst_sg || !src_sg))
 984                 return NULL;
 985
 986         chan = to_dma_chan(dchan);
 987
 988         /* Get prepared for the loop */
 989         dst_avail = sg_dma_len(dst_sg);
 990         src_avail = sg_dma_len(src_sg);
 991         dst_nents--;
 992         src_nents--;
 993
 994         /* Run until we are out of scatterlist entries */
 995         while (true) {
 996                 /* Create the largest transaction possible */
 997                 len = min_t(size_t, src_avail, dst_avail);
 998                 len = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
 999                 if (len == 0)
1000                         goto fetch;
1001
1002                 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
1003                 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
1004
1005                 /* Allocate the link descriptor from DMA pool */
1006                 new = xgene_dma_alloc_descriptor(chan);
1007                 if (!new)
1008                         goto fail;
1009
1010                 /* Prepare DMA descriptor */
1011                 xgene_dma_prep_cpy_desc(chan, new, dst, src, len);
1012
1013                 if (!first)
1014                         first = new;
1015
1016                 new->tx.cookie = 0;
1017                 async_tx_ack(&new->tx);
1018
1019                 /* update metadata */
1020                 dst_avail -= len;
1021                 src_avail -= len;
1022
1023                 /* Insert the link descriptor to the LD ring */
1024                 list_add_tail(&new->node, &first->tx_list);
1025
1026 fetch:
1027                 /* fetch the next dst scatterlist entry */
1028                 if (dst_avail == 0) {
1029                         /* no more entries: we're done */
1030                         if (dst_nents == 0)
1031                                 break;
1032
1033                         /* fetch the next entry: if there are no more: done */
1034                         dst_sg = sg_next(dst_sg);
1035                         if (!dst_sg)
1036                                 break;
1037
1038                         dst_nents--;
1039                         dst_avail = sg_dma_len(dst_sg);
1040                 }
1041
1042                 /* fetch the next src scatterlist entry */
1043                 if (src_avail == 0) {
1044                         /* no more entries: we're done */
1045                         if (src_nents == 0)
1046                                 break;
1047
1048                         /* fetch the next entry: if there are no more: done */
1049                         src_sg = sg_next(src_sg);
1050                         if (!src_sg)
1051                                 break;
1052
1053                         src_nents--;
1054                         src_avail = sg_dma_len(src_sg);
1055                 }
1056         }
1057
1058         if (!new)
1059                 return NULL;
1060
1061         new->tx.flags = flags; /* client is in control of this ack */
1062         new->tx.cookie = -EBUSY;
1063         list_splice(&first->tx_list, &new->tx_list);
1064
1065         return &new->tx;
1066 fail:
1067         if (!first)
1068                 return NULL;
1069
1070         xgene_dma_free_desc_list(chan, &first->tx_list);
1071         return NULL;
1072 }
1073
1074 static struct dma_async_tx_descriptor *xgene_dma_prep_xor(
1075         struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
1076         u32 src_cnt, size_t len, unsigned long flags)
1077 {
1078         struct xgene_dma_desc_sw *first = NULL, *new;
1079         struct xgene_dma_chan *chan;
1080         static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {
1081                                 0x01, 0x01, 0x01, 0x01, 0x01};
1082
1083         if (unlikely(!dchan || !len))
1084                 return NULL;
1085
1086         chan = to_dma_chan(dchan);
1087
1088         do {
1089                 /* Allocate the link descriptor from DMA pool */
1090                 new = xgene_dma_alloc_descriptor(chan);
1091                 if (!new)
1092                         goto fail;
1093
1094                 /* Prepare xor DMA descriptor */
1095                 xgene_dma_prep_xor_desc(chan, new, &dst, src,
1096                                         src_cnt, &len, multi);
1097
1098                 if (!first)
1099                         first = new;
1100
1101                 new->tx.cookie = 0;
1102                 async_tx_ack(&new->tx);
1103
1104                 /* Insert the link descriptor to the LD ring */
1105                 list_add_tail(&new->node, &first->tx_list);
1106         } while (len);
1107
1108         new->tx.flags = flags; /* client is in control of this ack */
1109         new->tx.cookie = -EBUSY;
1110         list_splice(&first->tx_list, &new->tx_list);
1111
1112         return &new->tx;
1113
1114 fail:
1115         if (!first)
1116                 return NULL;
1117
1118         xgene_dma_free_desc_list(chan, &first->tx_list);
1119         return NULL;
1120 }
1121
1122 static struct dma_async_tx_descriptor *xgene_dma_prep_pq(
1123         struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
1124         u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1125 {
1126         struct xgene_dma_desc_sw *first = NULL, *new;
1127         struct xgene_dma_chan *chan;
1128         size_t _len = len;
1129         dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC];
1130         static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01};
1131
1132         if (unlikely(!dchan || !len))
1133                 return NULL;
1134
1135         chan = to_dma_chan(dchan);
1136
1137         /*
1138          * Save source addresses on local variable, may be we have to
1139          * prepare two descriptor to generate P and Q if both enabled
1140          * in the flags by client
1141          */
1142         memcpy(_src, src, sizeof(*src) * src_cnt);
1143
1144         if (flags & DMA_PREP_PQ_DISABLE_P)
1145                 len = 0;
1146
1147         if (flags & DMA_PREP_PQ_DISABLE_Q)
1148                 _len = 0;
1149
1150         do {
1151                 /* Allocate the link descriptor from DMA pool */
1152                 new = xgene_dma_alloc_descriptor(chan);
1153                 if (!new)
1154                         goto fail;
1155
1156                 if (!first)
1157                         first = new;
1158
1159                 new->tx.cookie = 0;
1160                 async_tx_ack(&new->tx);
1161
1162                 /* Insert the link descriptor to the LD ring */
1163                 list_add_tail(&new->node, &first->tx_list);
1164
1165                 /*
1166                  * Prepare DMA descriptor to generate P,
1167                  * if DMA_PREP_PQ_DISABLE_P flag is not set
1168                  */
1169                 if (len) {
1170                         xgene_dma_prep_xor_desc(chan, new, &dst[0], src,
1171                                                 src_cnt, &len, multi);
1172                         continue;
1173                 }
1174
1175                 /*
1176                  * Prepare DMA descriptor to generate Q,
1177                  * if DMA_PREP_PQ_DISABLE_Q flag is not set
1178                  */
1179                 if (_len) {
1180                         xgene_dma_prep_xor_desc(chan, new, &dst[1], _src,
1181                                                 src_cnt, &_len, scf);
1182                 }
1183         } while (len || _len);
1184
1185         new->tx.flags = flags; /* client is in control of this ack */
1186         new->tx.cookie = -EBUSY;
1187         list_splice(&first->tx_list, &new->tx_list);
1188
1189         return &new->tx;
1190
1191 fail:
1192         if (!first)
1193                 return NULL;
1194
1195         xgene_dma_free_desc_list(chan, &first->tx_list);
1196         return NULL;
1197 }
1198
1199 static void xgene_dma_issue_pending(struct dma_chan *dchan)
1200 {
1201         struct xgene_dma_chan *chan = to_dma_chan(dchan);
1202
1203         spin_lock_bh(&chan->lock);
1204         xgene_chan_xfer_ld_pending(chan);
1205         spin_unlock_bh(&chan->lock);
1206 }
1207
1208 static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan,
1209                                            dma_cookie_t cookie,
1210                                            struct dma_tx_state *txstate)
1211 {
1212         return dma_cookie_status(dchan, cookie, txstate);
1213 }
1214
1215 static void xgene_dma_tasklet_cb(unsigned long data)
1216 {
1217         struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data;
1218
1219         /* Run all cleanup for descriptors which have been completed */
1220         xgene_dma_cleanup_descriptors(chan);
1221
1222         /* Re-enable DMA channel IRQ */
1223         enable_irq(chan->rx_irq);
1224 }
1225
1226 static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
1227 {
1228         struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id;
1229
1230         BUG_ON(!chan);
1231
1232         /*
1233          * Disable DMA channel IRQ until we process completed
1234          * descriptors
1235          */
1236         disable_irq_nosync(chan->rx_irq);
1237
1238         /*
1239          * Schedule the tasklet to handle all cleanup of the current
1240          * transaction. It will start a new transaction if there is
1241          * one pending.
1242          */
1243         tasklet_schedule(&chan->tasklet);
1244
1245         return IRQ_HANDLED;
1246 }
1247
1248 static irqreturn_t xgene_dma_err_isr(int irq, void *id)
1249 {
1250         struct xgene_dma *pdma = (struct xgene_dma *)id;
1251         unsigned long int_mask;
1252         u32 val, i;
1253
1254         val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1255
1256         /* Clear DMA interrupts */
1257         iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1258
1259         /* Print DMA error info */
1260         int_mask = val >> XGENE_DMA_INT_MASK_SHIFT;
1261         for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err))
1262                 dev_err(pdma->dev,
1263                         "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]);
1264
1265         return IRQ_HANDLED;
1266 }
1267
1268 static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring)
1269 {
1270         int i;
1271
1272         iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1273
1274         for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++)
1275                 iowrite32(ring->state[i], ring->pdma->csr_ring +
1276                           XGENE_DMA_RING_STATE_WR_BASE + (i * 4));
1277 }
1278
1279 static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring)
1280 {
1281         memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG);
1282         xgene_dma_wr_ring_state(ring);
1283 }
1284
1285 static void xgene_dma_setup_ring(struct xgene_dma_ring *ring)
1286 {
1287         void *ring_cfg = ring->state;
1288         u64 addr = ring->desc_paddr;
1289         u32 i, val;
1290
1291         ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE;
1292
1293         /* Clear DMA ring state */
1294         xgene_dma_clr_ring_state(ring);
1295
1296         /* Set DMA ring type */
1297         XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR);
1298
1299         if (ring->owner == XGENE_DMA_RING_OWNER_DMA) {
1300                 /* Set recombination buffer and timeout */
1301                 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg);
1302                 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg);
1303                 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg);
1304         }
1305
1306         /* Initialize DMA ring state */
1307         XGENE_DMA_RING_SELTHRSH_SET(ring_cfg);
1308         XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg);
1309         XGENE_DMA_RING_COHERENT_SET(ring_cfg);
1310         XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr);
1311         XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr);
1312         XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize);
1313
1314         /* Write DMA ring configurations */
1315         xgene_dma_wr_ring_state(ring);
1316
1317         /* Set DMA ring id */
1318         iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id),
1319                   ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1320
1321         /* Set DMA ring buffer */
1322         iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num),
1323                   ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1324
1325         if (ring->owner != XGENE_DMA_RING_OWNER_CPU)
1326                 return;
1327
1328         /* Set empty signature to DMA Rx ring descriptors */
1329         for (i = 0; i < ring->slots; i++) {
1330                 struct xgene_dma_desc_hw *desc;
1331
1332                 desc = &ring->desc_hw[i];
1333                 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
1334         }
1335
1336         /* Enable DMA Rx ring interrupt */
1337         val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1338         XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num);
1339         iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1340 }
1341
1342 static void xgene_dma_clear_ring(struct xgene_dma_ring *ring)
1343 {
1344         u32 ring_id, val;
1345
1346         if (ring->owner == XGENE_DMA_RING_OWNER_CPU) {
1347                 /* Disable DMA Rx ring interrupt */
1348                 val = ioread32(ring->pdma->csr_ring +
1349                                XGENE_DMA_RING_NE_INT_MODE);
1350                 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num);
1351                 iowrite32(val, ring->pdma->csr_ring +
1352                           XGENE_DMA_RING_NE_INT_MODE);
1353         }
1354
1355         /* Clear DMA ring state */
1356         ring_id = XGENE_DMA_RING_ID_SETUP(ring->id);
1357         iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1358
1359         iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1360         xgene_dma_clr_ring_state(ring);
1361 }
1362
1363 static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring)
1364 {
1365         ring->cmd_base = ring->pdma->csr_ring_cmd +
1366                                 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num -
1367                                                           XGENE_DMA_RING_NUM));
1368
1369         ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET;
1370 }
1371
1372 static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan,
1373                                    enum xgene_dma_ring_cfgsize cfgsize)
1374 {
1375         int size;
1376
1377         switch (cfgsize) {
1378         case XGENE_DMA_RING_CFG_SIZE_512B:
1379                 size = 0x200;
1380                 break;
1381         case XGENE_DMA_RING_CFG_SIZE_2KB:
1382                 size = 0x800;
1383                 break;
1384         case XGENE_DMA_RING_CFG_SIZE_16KB:
1385                 size = 0x4000;
1386                 break;
1387         case XGENE_DMA_RING_CFG_SIZE_64KB:
1388                 size = 0x10000;
1389                 break;
1390         case XGENE_DMA_RING_CFG_SIZE_512KB:
1391                 size = 0x80000;
1392                 break;
1393         default:
1394                 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize);
1395                 return -EINVAL;
1396         }
1397
1398         return size;
1399 }
1400
1401 static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring)
1402 {
1403         /* Clear DMA ring configurations */
1404         xgene_dma_clear_ring(ring);
1405
1406         /* De-allocate DMA ring descriptor */
1407         if (ring->desc_vaddr) {
1408                 dma_free_coherent(ring->pdma->dev, ring->size,
1409                                   ring->desc_vaddr, ring->desc_paddr);
1410                 ring->desc_vaddr = NULL;
1411         }
1412 }
1413
1414 static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan)
1415 {
1416         xgene_dma_delete_ring_one(&chan->rx_ring);
1417         xgene_dma_delete_ring_one(&chan->tx_ring);
1418 }
1419
1420 static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan,
1421                                      struct xgene_dma_ring *ring,
1422                                      enum xgene_dma_ring_cfgsize cfgsize)
1423 {
1424         /* Setup DMA ring descriptor variables */
1425         ring->pdma = chan->pdma;
1426         ring->cfgsize = cfgsize;
1427         ring->num = chan->pdma->ring_num++;
1428         ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num);
1429
1430         ring->size = xgene_dma_get_ring_size(chan, cfgsize);
1431         if (ring->size <= 0)
1432                 return ring->size;
1433
1434         /* Allocate memory for DMA ring descriptor */
1435         ring->desc_vaddr = dma_zalloc_coherent(chan->dev, ring->size,
1436                                                &ring->desc_paddr, GFP_KERNEL);
1437         if (!ring->desc_vaddr) {
1438                 chan_err(chan, "Failed to allocate ring desc\n");
1439                 return -ENOMEM;
1440         }
1441
1442         /* Configure and enable DMA ring */
1443         xgene_dma_set_ring_cmd(ring);
1444         xgene_dma_setup_ring(ring);
1445
1446         return 0;
1447 }
1448
1449 static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan)
1450 {
1451         struct xgene_dma_ring *rx_ring = &chan->rx_ring;
1452         struct xgene_dma_ring *tx_ring = &chan->tx_ring;
1453         int ret;
1454
1455         /* Create DMA Rx ring descriptor */
1456         rx_ring->owner = XGENE_DMA_RING_OWNER_CPU;
1457         rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id;
1458
1459         ret = xgene_dma_create_ring_one(chan, rx_ring,
1460                                         XGENE_DMA_RING_CFG_SIZE_64KB);
1461         if (ret)
1462                 return ret;
1463
1464         chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n",
1465                  rx_ring->id, rx_ring->num, rx_ring->desc_vaddr);
1466
1467         /* Create DMA Tx ring descriptor */
1468         tx_ring->owner = XGENE_DMA_RING_OWNER_DMA;
1469         tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id;
1470
1471         ret = xgene_dma_create_ring_one(chan, tx_ring,
1472                                         XGENE_DMA_RING_CFG_SIZE_64KB);
1473         if (ret) {
1474                 xgene_dma_delete_ring_one(rx_ring);
1475                 return ret;
1476         }
1477
1478         tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num);
1479
1480         chan_dbg(chan,
1481                  "Tx ring id 0x%X num %d desc 0x%p\n",
1482                  tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
1483
1484         /* Set the max outstanding request possible to this channel */
1485         chan->max_outstanding = rx_ring->slots;
1486
1487         return ret;
1488 }
1489
1490 static int xgene_dma_init_rings(struct xgene_dma *pdma)
1491 {
1492         int ret, i, j;
1493
1494         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1495                 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1496                 if (ret) {
1497                         for (j = 0; j < i; j++)
1498                                 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1499                         return ret;
1500                 }
1501         }
1502
1503         return ret;
1504 }
1505
1506 static void xgene_dma_enable(struct xgene_dma *pdma)
1507 {
1508         u32 val;
1509
1510         /* Configure and enable DMA engine */
1511         val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1512         XGENE_DMA_CH_SETUP(val);
1513         XGENE_DMA_ENABLE(val);
1514         iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1515 }
1516
1517 static void xgene_dma_disable(struct xgene_dma *pdma)
1518 {
1519         u32 val;
1520
1521         val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1522         XGENE_DMA_DISABLE(val);
1523         iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1524 }
1525
1526 static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1527 {
1528         /*
1529          * Mask DMA ring overflow, underflow and
1530          * AXI write/read error interrupts
1531          */
1532         iowrite32(XGENE_DMA_INT_ALL_MASK,
1533                   pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1534         iowrite32(XGENE_DMA_INT_ALL_MASK,
1535                   pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1536         iowrite32(XGENE_DMA_INT_ALL_MASK,
1537                   pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1538         iowrite32(XGENE_DMA_INT_ALL_MASK,
1539                   pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1540         iowrite32(XGENE_DMA_INT_ALL_MASK,
1541                   pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1542
1543         /* Mask DMA error interrupts */
1544         iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1545 }
1546
1547 static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1548 {
1549         /*
1550          * Unmask DMA ring overflow, underflow and
1551          * AXI write/read error interrupts
1552          */
1553         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1554                   pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1555         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1556                   pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1557         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1558                   pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1559         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1560                   pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1561         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1562                   pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1563
1564         /* Unmask DMA error interrupts */
1565         iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1566                   pdma->csr_dma + XGENE_DMA_INT_MASK);
1567 }
1568
1569 static void xgene_dma_init_hw(struct xgene_dma *pdma)
1570 {
1571         u32 val;
1572
1573         /* Associate DMA ring to corresponding ring HW */
1574         iowrite32(XGENE_DMA_ASSOC_RING_MNGR1,
1575                   pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1576
1577         /* Configure RAID6 polynomial control setting */
1578         if (is_pq_enabled(pdma))
1579                 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
1580                           pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1581         else
1582                 dev_info(pdma->dev, "PQ is disabled in HW\n");
1583
1584         xgene_dma_enable(pdma);
1585         xgene_dma_unmask_interrupts(pdma);
1586
1587         /* Get DMA id and version info */
1588         val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1589
1590         /* DMA device info */
1591         dev_info(pdma->dev,
1592                  "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1593                  XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val),
1594                  XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL);
1595 }
1596
1597 static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
1598 {
1599         if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1600             (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1601                 return 0;
1602
1603         iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1604         iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1605
1606         /* Bring up memory */
1607         iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1608
1609         /* Force a barrier */
1610         ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1611
1612         /* reset may take up to 1ms */
1613         usleep_range(1000, 1100);
1614
1615         if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1616                 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) {
1617                 dev_err(pdma->dev,
1618                         "Failed to release ring mngr memory from shutdown\n");
1619                 return -ENODEV;
1620         }
1621
1622         /* program threshold set 1 and all hysteresis */
1623         iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL,
1624                   pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1625         iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL,
1626                   pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1627         iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL,
1628                   pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1629
1630         /* Enable QPcore and assign error queue */
1631         iowrite32(XGENE_DMA_RING_ENABLE,
1632                   pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1633
1634         return 0;
1635 }
1636
1637 static int xgene_dma_init_mem(struct xgene_dma *pdma)
1638 {
1639         int ret;
1640
1641         ret = xgene_dma_init_ring_mngr(pdma);
1642         if (ret)
1643                 return ret;
1644
1645         /* Bring up memory */
1646         iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1647
1648         /* Force a barrier */
1649         ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1650
1651         /* reset may take up to 1ms */
1652         usleep_range(1000, 1100);
1653
1654         if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1655                 != XGENE_DMA_BLK_MEM_RDY_VAL) {
1656                 dev_err(pdma->dev,
1657                         "Failed to release DMA memory from shutdown\n");
1658                 return -ENODEV;
1659         }
1660
1661         return 0;
1662 }
1663
1664 static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1665 {
1666         struct xgene_dma_chan *chan;
1667         int ret, i, j;
1668
1669         /* Register DMA error irq */
1670         ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1671                                0, "dma_error", pdma);
1672         if (ret) {
1673                 dev_err(pdma->dev,
1674                         "Failed to register error IRQ %d\n", pdma->err_irq);
1675                 return ret;
1676         }
1677
1678         /* Register DMA channel rx irq */
1679         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1680                 chan = &pdma->chan[i];
1681                 ret = devm_request_irq(chan->dev, chan->rx_irq,
1682                                        xgene_dma_chan_ring_isr,
1683                                        0, chan->name, chan);
1684                 if (ret) {
1685                         chan_err(chan, "Failed to register Rx IRQ %d\n",
1686                                  chan->rx_irq);
1687                         devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1688
1689                         for (j = 0; j < i; j++) {
1690                                 chan = &pdma->chan[i];
1691                                 devm_free_irq(chan->dev, chan->rx_irq, chan);
1692                         }
1693
1694                         return ret;
1695                 }
1696         }
1697
1698         return 0;
1699 }
1700
1701 static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1702 {
1703         struct xgene_dma_chan *chan;
1704         int i;
1705
1706         /* Free DMA device error irq */
1707         devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1708
1709         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1710                 chan = &pdma->chan[i];
1711                 devm_free_irq(chan->dev, chan->rx_irq, chan);
1712         }
1713 }
1714
1715 static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
1716                                struct dma_device *dma_dev)
1717 {
1718         /* Initialize DMA device capability mask */
1719         dma_cap_zero(dma_dev->cap_mask);
1720
1721         /* Set DMA device capability */
1722         dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1723         dma_cap_set(DMA_SG, dma_dev->cap_mask);
1724
1725         /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
1726          * and channel 1 supports XOR, PQ both. First thing here is we have
1727          * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
1728          * we can make sure this by reading SoC Efuse register.
1729          * Second thing, we have hw errata that if we run channel 0 and
1730          * channel 1 simultaneously with executing XOR and PQ request,
1731          * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
1732          * if XOR and PQ supports on channel 1 is disabled.
1733          */
1734         if ((chan->id == XGENE_DMA_PQ_CHANNEL) &&
1735             is_pq_enabled(chan->pdma)) {
1736                 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1737                 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1738         } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) &&
1739                    !is_pq_enabled(chan->pdma)) {
1740                 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1741         }
1742
1743         /* Set base and prep routines */
1744         dma_dev->dev = chan->dev;
1745         dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;
1746         dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
1747         dma_dev->device_issue_pending = xgene_dma_issue_pending;
1748         dma_dev->device_tx_status = xgene_dma_tx_status;
1749         dma_dev->device_prep_dma_memcpy = xgene_dma_prep_memcpy;
1750         dma_dev->device_prep_dma_sg = xgene_dma_prep_sg;
1751
1752         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1753                 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;
1754                 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;
1755                 dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES;
1756         }
1757
1758         if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1759                 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;
1760                 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;
1761                 dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES;
1762         }
1763 }
1764
1765 static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1766 {
1767         struct xgene_dma_chan *chan = &pdma->chan[id];
1768         struct dma_device *dma_dev = &pdma->dma_dev[id];
1769         int ret;
1770
1771         chan->dma_chan.device = dma_dev;
1772
1773         spin_lock_init(&chan->lock);
1774         INIT_LIST_HEAD(&chan->ld_pending);
1775         INIT_LIST_HEAD(&chan->ld_running);
1776         INIT_LIST_HEAD(&chan->ld_completed);
1777         tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb,
1778                      (unsigned long)chan);
1779
1780         chan->pending = 0;
1781         chan->desc_pool = NULL;
1782         dma_cookie_init(&chan->dma_chan);
1783
1784         /* Setup dma device capabilities and prep routines */
1785         xgene_dma_set_caps(chan, dma_dev);
1786
1787         /* Initialize DMA device list head */
1788         INIT_LIST_HEAD(&dma_dev->channels);
1789         list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
1790
1791         /* Register with Linux async DMA framework*/
1792         ret = dma_async_device_register(dma_dev);
1793         if (ret) {
1794                 chan_err(chan, "Failed to register async device %d", ret);
1795                 tasklet_kill(&chan->tasklet);
1796
1797                 return ret;
1798         }
1799
1800         /* DMA capability info */
1801         dev_info(pdma->dev,
1802                  "%s: CAPABILITY ( %s%s%s%s)\n", dma_chan_name(&chan->dma_chan),
1803                  dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "MEMCPY " : "",
1804                  dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "",
1805                  dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
1806                  dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
1807
1808         return 0;
1809 }
1810
1811 static int xgene_dma_init_async(struct xgene_dma *pdma)
1812 {
1813         int ret, i, j;
1814
1815         for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) {
1816                 ret = xgene_dma_async_register(pdma, i);
1817                 if (ret) {
1818                         for (j = 0; j < i; j++) {
1819                                 dma_async_device_unregister(&pdma->dma_dev[j]);
1820                                 tasklet_kill(&pdma->chan[j].tasklet);
1821                         }
1822
1823                         return ret;
1824                 }
1825         }
1826
1827         return ret;
1828 }
1829
1830 static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1831 {
1832         int i;
1833
1834         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1835                 dma_async_device_unregister(&pdma->dma_dev[i]);
1836 }
1837
1838 static void xgene_dma_init_channels(struct xgene_dma *pdma)
1839 {
1840         struct xgene_dma_chan *chan;
1841         int i;
1842
1843         pdma->ring_num = XGENE_DMA_RING_NUM;
1844
1845         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1846                 chan = &pdma->chan[i];
1847                 chan->dev = pdma->dev;
1848                 chan->pdma = pdma;
1849                 chan->id = i;
1850                 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id);
1851         }
1852 }
1853
1854 static int xgene_dma_get_resources(struct platform_device *pdev,
1855                                    struct xgene_dma *pdma)
1856 {
1857         struct resource *res;
1858         int irq, i;
1859
1860         /* Get DMA csr region */
1861         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1862         if (!res) {
1863                 dev_err(&pdev->dev, "Failed to get csr region\n");
1864                 return -ENXIO;
1865         }
1866
1867         pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1868                                      resource_size(res));
1869         if (!pdma->csr_dma) {
1870                 dev_err(&pdev->dev, "Failed to ioremap csr region");
1871                 return -ENOMEM;
1872         }
1873
1874         /* Get DMA ring csr region */
1875         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1876         if (!res) {
1877                 dev_err(&pdev->dev, "Failed to get ring csr region\n");
1878                 return -ENXIO;
1879         }
1880
1881         pdma->csr_ring =  devm_ioremap(&pdev->dev, res->start,
1882                                        resource_size(res));
1883         if (!pdma->csr_ring) {
1884                 dev_err(&pdev->dev, "Failed to ioremap ring csr region");
1885                 return -ENOMEM;
1886         }
1887
1888         /* Get DMA ring cmd csr region */
1889         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1890         if (!res) {
1891                 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n");
1892                 return -ENXIO;
1893         }
1894
1895         pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1896                                           resource_size(res));
1897         if (!pdma->csr_ring_cmd) {
1898                 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
1899                 return -ENOMEM;
1900         }
1901
1902         pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
1903
1904         /* Get efuse csr region */
1905         res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1906         if (!res) {
1907                 dev_err(&pdev->dev, "Failed to get efuse csr region\n");
1908                 return -ENXIO;
1909         }
1910
1911         pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1912                                        resource_size(res));
1913         if (!pdma->csr_efuse) {
1914                 dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
1915                 return -ENOMEM;
1916         }
1917
1918         /* Get DMA error interrupt */
1919         irq = platform_get_irq(pdev, 0);
1920         if (irq <= 0) {
1921                 dev_err(&pdev->dev, "Failed to get Error IRQ\n");
1922                 return -ENXIO;
1923         }
1924
1925         pdma->err_irq = irq;
1926
1927         /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1928         for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
1929                 irq = platform_get_irq(pdev, i);
1930                 if (irq <= 0) {
1931                         dev_err(&pdev->dev, "Failed to get Rx IRQ\n");
1932                         return -ENXIO;
1933                 }
1934
1935                 pdma->chan[i - 1].rx_irq = irq;
1936         }
1937
1938         return 0;
1939 }
1940
1941 static int xgene_dma_probe(struct platform_device *pdev)
1942 {
1943         struct xgene_dma *pdma;
1944         int ret, i;
1945
1946         pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1947         if (!pdma)
1948                 return -ENOMEM;
1949
1950         pdma->dev = &pdev->dev;
1951         platform_set_drvdata(pdev, pdma);
1952
1953         ret = xgene_dma_get_resources(pdev, pdma);
1954         if (ret)
1955                 return ret;
1956
1957         pdma->clk = devm_clk_get(&pdev->dev, NULL);
1958         if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
1959                 dev_err(&pdev->dev, "Failed to get clk\n");
1960                 return PTR_ERR(pdma->clk);
1961         }
1962
1963         /* Enable clk before accessing registers */
1964         if (!IS_ERR(pdma->clk)) {
1965                 ret = clk_prepare_enable(pdma->clk);
1966                 if (ret) {
1967                         dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
1968                         return ret;
1969                 }
1970         }
1971
1972         /* Remove DMA RAM out of shutdown */
1973         ret = xgene_dma_init_mem(pdma);
1974         if (ret)
1975                 goto err_clk_enable;
1976
1977         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42));
1978         if (ret) {
1979                 dev_err(&pdev->dev, "No usable DMA configuration\n");
1980                 goto err_dma_mask;
1981         }
1982
1983         /* Initialize DMA channels software state */
1984         xgene_dma_init_channels(pdma);
1985
1986         /* Configue DMA rings */
1987         ret = xgene_dma_init_rings(pdma);
1988         if (ret)
1989                 goto err_clk_enable;
1990
1991         ret = xgene_dma_request_irqs(pdma);
1992         if (ret)
1993                 goto err_request_irq;
1994
1995         /* Configure and enable DMA engine */
1996         xgene_dma_init_hw(pdma);
1997
1998         /* Register DMA device with linux async framework */
1999         ret = xgene_dma_init_async(pdma);
2000         if (ret)
2001                 goto err_async_init;
2002
2003         return 0;
2004
2005 err_async_init:
2006         xgene_dma_free_irqs(pdma);
2007
2008 err_request_irq:
2009         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
2010                 xgene_dma_delete_chan_rings(&pdma->chan[i]);
2011
2012 err_dma_mask:
2013 err_clk_enable:
2014         if (!IS_ERR(pdma->clk))
2015                 clk_disable_unprepare(pdma->clk);
2016
2017         return ret;
2018 }
2019
2020 static int xgene_dma_remove(struct platform_device *pdev)
2021 {
2022         struct xgene_dma *pdma = platform_get_drvdata(pdev);
2023         struct xgene_dma_chan *chan;
2024         int i;
2025
2026         xgene_dma_async_unregister(pdma);
2027
2028         /* Mask interrupts and disable DMA engine */
2029         xgene_dma_mask_interrupts(pdma);
2030         xgene_dma_disable(pdma);
2031         xgene_dma_free_irqs(pdma);
2032
2033         for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
2034                 chan = &pdma->chan[i];
2035                 tasklet_kill(&chan->tasklet);
2036                 xgene_dma_delete_chan_rings(chan);
2037         }
2038
2039         if (!IS_ERR(pdma->clk))
2040                 clk_disable_unprepare(pdma->clk);
2041
2042         return 0;
2043 }
2044
2045 #ifdef CONFIG_ACPI
2046 static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = {
2047         {"APMC0D43", 0},
2048         {},
2049 };
2050 MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr);
2051 #endif
2052
2053 static const struct of_device_id xgene_dma_of_match_ptr[] = {
2054         {.compatible = "apm,xgene-storm-dma",},
2055         {},
2056 };
2057 MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr);
2058
2059 static struct platform_driver xgene_dma_driver = {
2060         .probe = xgene_dma_probe,
2061         .remove = xgene_dma_remove,
2062         .driver = {
2063                 .name = "X-Gene-DMA",
2064                 .of_match_table = xgene_dma_of_match_ptr,
2065                 .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr),
2066         },
2067 };
2068
2069 module_platform_driver(xgene_dma_driver);
2070
2071 MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
2072 MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
2073 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
2074 MODULE_LICENSE("GPL");
2075 MODULE_VERSION("1.0");