drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fbdev.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_plane.h"
  35 #include "exynos_drm_iommu.h"
  36
  37 /*
  38  * FIMD stands for Fully Interactive Mobile Display and
  39  * as a display controller, it transfers contents drawn on memory
  40  * to a LCD Panel through Display Interfaces such as RGB or
  41  * CPU Interface.
  42  */
  43
  44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  45
  46 /* position control register for hardware window 0, 2 ~ 4.*/
  47 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  48 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  49 /*
  50  * size control register for hardware windows 0 and alpha control register
  51  * for hardware windows 1 ~ 4
  52  */
  53 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  54 /* size control register for hardware windows 1 ~ 2. */
  55 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  56
  57 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  58 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  59
  60 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  61 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  62 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  63 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  64
  65 /* color key control register for hardware window 1 ~ 4. */
  66 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  67 /* color key value register for hardware window 1 ~ 4. */
  68 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  69
  70 /* I80 / RGB trigger control register */
  71 #define TRIGCON                         0x1A4
  72 #define TRGMODE_I80_RGB_ENABLE_I80      (1 << 0)
  73 #define SWTRGCMD_I80_RGB_ENABLE         (1 << 1)
  74
  75 /* display mode change control register except exynos4 */
  76 #define VIDOUT_CON                      0x000
  77 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  78
  79 /* I80 interface control for main LDI register */
  80 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  81 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  82 #define LCD_CS_SETUP(x)                 ((x) << 16)
  83 #define LCD_WR_SETUP(x)                 ((x) << 12)
  84 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  85 #define LCD_WR_HOLD(x)                  ((x) << 4)
  86 #define I80IFEN_ENABLE                  (1 << 0)
  87
  88 /* FIMD has totally five hardware windows. */
  89 #define WINDOWS_NR      5
  90
  91 struct fimd_driver_data {
  92         unsigned int timing_base;
  93         unsigned int lcdblk_offset;
  94         unsigned int lcdblk_vt_shift;
  95         unsigned int lcdblk_bypass_shift;
  96
  97         unsigned int has_shadowcon:1;
  98         unsigned int has_clksel:1;
  99         unsigned int has_limited_fmt:1;
 100         unsigned int has_vidoutcon:1;
 101         unsigned int has_vtsel:1;
 102 };
 103
 104 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 105         .timing_base = 0x0,
 106         .has_clksel = 1,
 107         .has_limited_fmt = 1,
 108 };
 109
 110 static struct fimd_driver_data exynos3_fimd_driver_data = {
 111         .timing_base = 0x20000,
 112         .lcdblk_offset = 0x210,
 113         .lcdblk_bypass_shift = 1,
 114         .has_shadowcon = 1,
 115         .has_vidoutcon = 1,
 116 };
 117
 118 static struct fimd_driver_data exynos4_fimd_driver_data = {
 119         .timing_base = 0x0,
 120         .lcdblk_offset = 0x210,
 121         .lcdblk_vt_shift = 10,
 122         .lcdblk_bypass_shift = 1,
 123         .has_shadowcon = 1,
 124         .has_vtsel = 1,
 125 };
 126
 127 static struct fimd_driver_data exynos4415_fimd_driver_data = {
 128         .timing_base = 0x20000,
 129         .lcdblk_offset = 0x210,
 130         .lcdblk_vt_shift = 10,
 131         .lcdblk_bypass_shift = 1,
 132         .has_shadowcon = 1,
 133         .has_vidoutcon = 1,
 134         .has_vtsel = 1,
 135 };
 136
 137 static struct fimd_driver_data exynos5_fimd_driver_data = {
 138         .timing_base = 0x20000,
 139         .lcdblk_offset = 0x214,
 140         .lcdblk_vt_shift = 24,
 141         .lcdblk_bypass_shift = 15,
 142         .has_shadowcon = 1,
 143         .has_vidoutcon = 1,
 144         .has_vtsel = 1,
 145 };
 146
 147 struct fimd_context {
 148         struct device                   *dev;
 149         struct drm_device               *drm_dev;
 150         struct exynos_drm_crtc          *crtc;
 151         struct exynos_drm_plane         planes[WINDOWS_NR];
 152         struct clk                      *bus_clk;
 153         struct clk                      *lcd_clk;
 154         void __iomem                    *regs;
 155         struct regmap                   *sysreg;
 156         unsigned int                    default_win;
 157         unsigned long                   irq_flags;
 158         u32                             vidcon0;
 159         u32                             vidcon1;
 160         u32                             vidout_con;
 161         u32                             i80ifcon;
 162         bool                            i80_if;
 163         bool                            suspended;
 164         int                             pipe;
 165         wait_queue_head_t               wait_vsync_queue;
 166         atomic_t                        wait_vsync_event;
 167         atomic_t                        win_updated;
 168         atomic_t                        triggering;
 169
 170         struct exynos_drm_panel_info panel;
 171         struct fimd_driver_data *driver_data;
 172         struct drm_encoder *encoder;
 173 };
 174
 175 static const struct of_device_id fimd_driver_dt_match[] = {
 176         { .compatible = "samsung,s3c6400-fimd",
 177           .data = &s3c64xx_fimd_driver_data },
 178         { .compatible = "samsung,exynos3250-fimd",
 179           .data = &exynos3_fimd_driver_data },
 180         { .compatible = "samsung,exynos4210-fimd",
 181           .data = &exynos4_fimd_driver_data },
 182         { .compatible = "samsung,exynos4415-fimd",
 183           .data = &exynos4415_fimd_driver_data },
 184         { .compatible = "samsung,exynos5250-fimd",
 185           .data = &exynos5_fimd_driver_data },
 186         {},
 187 };
 188 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 189
 190 static const uint32_t fimd_formats[] = {
 191         DRM_FORMAT_C8,
 192         DRM_FORMAT_XRGB1555,
 193         DRM_FORMAT_RGB565,
 194         DRM_FORMAT_XRGB8888,
 195         DRM_FORMAT_ARGB8888,
 196 };
 197
 198 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
 199         struct platform_device *pdev)
 200 {
 201         const struct of_device_id *of_id =
 202                         of_match_device(fimd_driver_dt_match, &pdev->dev);
 203
 204         return (struct fimd_driver_data *)of_id->data;
 205 }
 206
 207 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 208 {
 209         struct fimd_context *ctx = crtc->ctx;
 210         u32 val;
 211
 212         if (ctx->suspended)
 213                 return -EPERM;
 214
 215         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 216                 val = readl(ctx->regs + VIDINTCON0);
 217
 218                 val |= VIDINTCON0_INT_ENABLE;
 219
 220                 if (ctx->i80_if) {
 221                         val |= VIDINTCON0_INT_I80IFDONE;
 222                         val |= VIDINTCON0_INT_SYSMAINCON;
 223                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 224                 } else {
 225                         val |= VIDINTCON0_INT_FRAME;
 226
 227                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 228                         val |= VIDINTCON0_FRAMESEL0_VSYNC;
 229                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 230                         val |= VIDINTCON0_FRAMESEL1_NONE;
 231                 }
 232
 233                 writel(val, ctx->regs + VIDINTCON0);
 234         }
 235
 236         return 0;
 237 }
 238
 239 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 240 {
 241         struct fimd_context *ctx = crtc->ctx;
 242         u32 val;
 243
 244         if (ctx->suspended)
 245                 return;
 246
 247         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 248                 val = readl(ctx->regs + VIDINTCON0);
 249
 250                 val &= ~VIDINTCON0_INT_ENABLE;
 251
 252                 if (ctx->i80_if) {
 253                         val &= ~VIDINTCON0_INT_I80IFDONE;
 254                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 255                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 256                 } else
 257                         val &= ~VIDINTCON0_INT_FRAME;
 258
 259                 writel(val, ctx->regs + VIDINTCON0);
 260         }
 261 }
 262
 263 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 264 {
 265         struct fimd_context *ctx = crtc->ctx;
 266
 267         if (ctx->suspended)
 268                 return;
 269
 270         atomic_set(&ctx->wait_vsync_event, 1);
 271
 272         /*
 273          * wait for FIMD to signal VSYNC interrupt or return after
 274          * timeout which is set to 50ms (refresh rate of 20).
 275          */
 276         if (!wait_event_timeout(ctx->wait_vsync_queue,
 277                                 !atomic_read(&ctx->wait_vsync_event),
 278                                 HZ/20))
 279                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 280 }
 281
 282 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 283                                         bool enable)
 284 {
 285         u32 val = readl(ctx->regs + WINCON(win));
 286
 287         if (enable)
 288                 val |= WINCONx_ENWIN;
 289         else
 290                 val &= ~WINCONx_ENWIN;
 291
 292         writel(val, ctx->regs + WINCON(win));
 293 }
 294
 295 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 296                                                 unsigned int win,
 297                                                 bool enable)
 298 {
 299         u32 val = readl(ctx->regs + SHADOWCON);
 300
 301         if (enable)
 302                 val |= SHADOWCON_CHx_ENABLE(win);
 303         else
 304                 val &= ~SHADOWCON_CHx_ENABLE(win);
 305
 306         writel(val, ctx->regs + SHADOWCON);
 307 }
 308
 309 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 310 {
 311         struct fimd_context *ctx = crtc->ctx;
 312         unsigned int win, ch_enabled = 0;
 313
 314         DRM_DEBUG_KMS("%s\n", __FILE__);
 315
 316         /* Hardware is in unknown state, so ensure it gets enabled properly */
 317         pm_runtime_get_sync(ctx->dev);
 318
 319         clk_prepare_enable(ctx->bus_clk);
 320         clk_prepare_enable(ctx->lcd_clk);
 321
 322         /* Check if any channel is enabled. */
 323         for (win = 0; win < WINDOWS_NR; win++) {
 324                 u32 val = readl(ctx->regs + WINCON(win));
 325
 326                 if (val & WINCONx_ENWIN) {
 327                         fimd_enable_video_output(ctx, win, false);
 328
 329                         if (ctx->driver_data->has_shadowcon)
 330                                 fimd_enable_shadow_channel_path(ctx, win,
 331                                                                 false);
 332
 333                         ch_enabled = 1;
 334                 }
 335         }
 336
 337         /* Wait for vsync, as disable channel takes effect at next vsync */
 338         if (ch_enabled) {
 339                 int pipe = ctx->pipe;
 340
 341                 /* ensure that vblank interrupt won't be reported to core */
 342                 ctx->suspended = false;
 343                 ctx->pipe = -1;
 344
 345                 fimd_enable_vblank(ctx->crtc);
 346                 fimd_wait_for_vblank(ctx->crtc);
 347                 fimd_disable_vblank(ctx->crtc);
 348
 349                 ctx->suspended = true;
 350                 ctx->pipe = pipe;
 351         }
 352
 353         clk_disable_unprepare(ctx->lcd_clk);
 354         clk_disable_unprepare(ctx->bus_clk);
 355
 356         pm_runtime_put(ctx->dev);
 357 }
 358
 359 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
 360                 const struct drm_display_mode *mode)
 361 {
 362         unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
 363         u32 clkdiv;
 364
 365         if (ctx->i80_if) {
 366                 /*
 367                  * The frame done interrupt should be occurred prior to the
 368                  * next TE signal.
 369                  */
 370                 ideal_clk *= 2;
 371         }
 372
 373         /* Find the clock divider value that gets us closest to ideal_clk */
 374         clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
 375
 376         return (clkdiv < 0x100) ? clkdiv : 0xff;
 377 }
 378
 379 static void fimd_commit(struct exynos_drm_crtc *crtc)
 380 {
 381         struct fimd_context *ctx = crtc->ctx;
 382         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 383         struct fimd_driver_data *driver_data = ctx->driver_data;
 384         void *timing_base = ctx->regs + driver_data->timing_base;
 385         u32 val, clkdiv;
 386
 387         if (ctx->suspended)
 388                 return;
 389
 390         /* nothing to do if we haven't set the mode yet */
 391         if (mode->htotal == 0 || mode->vtotal == 0)
 392                 return;
 393
 394         if (ctx->i80_if) {
 395                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 396                 writel(val, timing_base + I80IFCONFAx(0));
 397
 398                 /* disable auto frame rate */
 399                 writel(0, timing_base + I80IFCONFBx(0));
 400
 401                 /* set video type selection to I80 interface */
 402                 if (driver_data->has_vtsel && ctx->sysreg &&
 403                                 regmap_update_bits(ctx->sysreg,
 404                                         driver_data->lcdblk_offset,
 405                                         0x3 << driver_data->lcdblk_vt_shift,
 406                                         0x1 << driver_data->lcdblk_vt_shift)) {
 407                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 408                         return;
 409                 }
 410         } else {
 411                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 412                 u32 vidcon1;
 413
 414                 /* setup polarity values */
 415                 vidcon1 = ctx->vidcon1;
 416                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 417                         vidcon1 |= VIDCON1_INV_VSYNC;
 418                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 419                         vidcon1 |= VIDCON1_INV_HSYNC;
 420                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 421
 422                 /* setup vertical timing values. */
 423                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 424                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 425                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 426
 427                 val = VIDTCON0_VBPD(vbpd - 1) |
 428                         VIDTCON0_VFPD(vfpd - 1) |
 429                         VIDTCON0_VSPW(vsync_len - 1);
 430                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 431
 432                 /* setup horizontal timing values.  */
 433                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 434                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 435                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 436
 437                 val = VIDTCON1_HBPD(hbpd - 1) |
 438                         VIDTCON1_HFPD(hfpd - 1) |
 439                         VIDTCON1_HSPW(hsync_len - 1);
 440                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 441         }
 442
 443         if (driver_data->has_vidoutcon)
 444                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 445
 446         /* set bypass selection */
 447         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 448                                 driver_data->lcdblk_offset,
 449                                 0x1 << driver_data->lcdblk_bypass_shift,
 450                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 451                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 452                 return;
 453         }
 454
 455         /* setup horizontal and vertical display size. */
 456         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 457                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 458                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 459                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 460         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 461
 462         /*
 463          * fields of register with prefix '_F' would be updated
 464          * at vsync(same as dma start)
 465          */
 466         val = ctx->vidcon0;
 467         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 468
 469         if (ctx->driver_data->has_clksel)
 470                 val |= VIDCON0_CLKSEL_LCD;
 471
 472         clkdiv = fimd_calc_clkdiv(ctx, mode);
 473         if (clkdiv > 1)
 474                 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
 475
 476         writel(val, ctx->regs + VIDCON0);
 477 }
 478
 479
 480 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 481                                 struct drm_framebuffer *fb)
 482 {
 483         unsigned long val;
 484
 485         val = WINCONx_ENWIN;
 486
 487         /*
 488          * In case of s3c64xx, window 0 doesn't support alpha channel.
 489          * So the request format is ARGB8888 then change it to XRGB8888.
 490          */
 491         if (ctx->driver_data->has_limited_fmt && !win) {
 492                 if (fb->pixel_format == DRM_FORMAT_ARGB8888)
 493                         fb->pixel_format = DRM_FORMAT_XRGB8888;
 494         }
 495
 496         switch (fb->pixel_format) {
 497         case DRM_FORMAT_C8:
 498                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 499                 val |= WINCONx_BURSTLEN_8WORD;
 500                 val |= WINCONx_BYTSWP;
 501                 break;
 502         case DRM_FORMAT_XRGB1555:
 503                 val |= WINCON0_BPPMODE_16BPP_1555;
 504                 val |= WINCONx_HAWSWP;
 505                 val |= WINCONx_BURSTLEN_16WORD;
 506                 break;
 507         case DRM_FORMAT_RGB565:
 508                 val |= WINCON0_BPPMODE_16BPP_565;
 509                 val |= WINCONx_HAWSWP;
 510                 val |= WINCONx_BURSTLEN_16WORD;
 511                 break;
 512         case DRM_FORMAT_XRGB8888:
 513                 val |= WINCON0_BPPMODE_24BPP_888;
 514                 val |= WINCONx_WSWP;
 515                 val |= WINCONx_BURSTLEN_16WORD;
 516                 break;
 517         case DRM_FORMAT_ARGB8888:
 518                 val |= WINCON1_BPPMODE_25BPP_A1888
 519                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 520                 val |= WINCONx_WSWP;
 521                 val |= WINCONx_BURSTLEN_16WORD;
 522                 break;
 523         default:
 524                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 525
 526                 val |= WINCON0_BPPMODE_24BPP_888;
 527                 val |= WINCONx_WSWP;
 528                 val |= WINCONx_BURSTLEN_16WORD;
 529                 break;
 530         }
 531
 532         DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
 533
 534         /*
 535          * In case of exynos, setting dma-burst to 16Word causes permanent
 536          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 537          * switching which is based on plane size is not recommended as
 538          * plane size varies alot towards the end of the screen and rapid
 539          * movement causes unstable DMA which results into iommu crash/tear.
 540          */
 541
 542         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 543                 val &= ~WINCONx_BURSTLEN_MASK;
 544                 val |= WINCONx_BURSTLEN_4WORD;
 545         }
 546
 547         writel(val, ctx->regs + WINCON(win));
 548
 549         /* hardware window 0 doesn't support alpha channel. */
 550         if (win != 0) {
 551                 /* OSD alpha */
 552                 val = VIDISD14C_ALPHA0_R(0xf) |
 553                         VIDISD14C_ALPHA0_G(0xf) |
 554                         VIDISD14C_ALPHA0_B(0xf) |
 555                         VIDISD14C_ALPHA1_R(0xf) |
 556                         VIDISD14C_ALPHA1_G(0xf) |
 557                         VIDISD14C_ALPHA1_B(0xf);
 558
 559                 writel(val, ctx->regs + VIDOSD_C(win));
 560
 561                 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
 562                         VIDW_ALPHA_G(0xf);
 563                 writel(val, ctx->regs + VIDWnALPHA0(win));
 564                 writel(val, ctx->regs + VIDWnALPHA1(win));
 565         }
 566 }
 567
 568 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 569 {
 570         unsigned int keycon0 = 0, keycon1 = 0;
 571
 572         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 573                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 574
 575         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 576
 577         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 578         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 579 }
 580
 581 /**
 582  * shadow_protect_win() - disable updating values from shadow registers at vsync
 583  *
 584  * @win: window to protect registers for
 585  * @protect: 1 to protect (disable updates)
 586  */
 587 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 588                                     unsigned int win, bool protect)
 589 {
 590         u32 reg, bits, val;
 591
 592         /*
 593          * SHADOWCON/PRTCON register is used for enabling timing.
 594          *
 595          * for example, once only width value of a register is set,
 596          * if the dma is started then fimd hardware could malfunction so
 597          * with protect window setting, the register fields with prefix '_F'
 598          * wouldn't be updated at vsync also but updated once unprotect window
 599          * is set.
 600          */
 601
 602         if (ctx->driver_data->has_shadowcon) {
 603                 reg = SHADOWCON;
 604                 bits = SHADOWCON_WINx_PROTECT(win);
 605         } else {
 606                 reg = PRTCON;
 607                 bits = PRTCON_PROTECT;
 608         }
 609
 610         val = readl(ctx->regs + reg);
 611         if (protect)
 612                 val |= bits;
 613         else
 614                 val &= ~bits;
 615         writel(val, ctx->regs + reg);
 616 }
 617
 618 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc,
 619                                struct exynos_drm_plane *plane)
 620 {
 621         struct fimd_context *ctx = crtc->ctx;
 622
 623         if (ctx->suspended)
 624                 return;
 625
 626         fimd_shadow_protect_win(ctx, plane->zpos, true);
 627 }
 628
 629 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc,
 630                                struct exynos_drm_plane *plane)
 631 {
 632         struct fimd_context *ctx = crtc->ctx;
 633
 634         if (ctx->suspended)
 635                 return;
 636
 637         fimd_shadow_protect_win(ctx, plane->zpos, false);
 638 }
 639
 640 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 641                               struct exynos_drm_plane *plane)
 642 {
 643         struct fimd_context *ctx = crtc->ctx;
 644         struct drm_plane_state *state = plane->base.state;
 645         dma_addr_t dma_addr;
 646         unsigned long val, size, offset;
 647         unsigned int last_x, last_y, buf_offsize, line_size;
 648         unsigned int win = plane->zpos;
 649         unsigned int bpp = state->fb->bits_per_pixel >> 3;
 650         unsigned int pitch = state->fb->pitches[0];
 651
 652         if (ctx->suspended)
 653                 return;
 654
 655         offset = plane->src_x * bpp;
 656         offset += plane->src_y * pitch;
 657
 658         /* buffer start address */
 659         dma_addr = plane->dma_addr[0] + offset;
 660         val = (unsigned long)dma_addr;
 661         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 662
 663         /* buffer end address */
 664         size = pitch * plane->crtc_h;
 665         val = (unsigned long)(dma_addr + size);
 666         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 667
 668         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 669                         (unsigned long)dma_addr, val, size);
 670         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 671                         plane->crtc_w, plane->crtc_h);
 672
 673         /* buffer size */
 674         buf_offsize = pitch - (plane->crtc_w * bpp);
 675         line_size = plane->crtc_w * bpp;
 676         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 677                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 678                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 679                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 680         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 681
 682         /* OSD position */
 683         val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
 684                 VIDOSDxA_TOPLEFT_Y(plane->crtc_y) |
 685                 VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) |
 686                 VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y);
 687         writel(val, ctx->regs + VIDOSD_A(win));
 688
 689         last_x = plane->crtc_x + plane->crtc_w;
 690         if (last_x)
 691                 last_x--;
 692         last_y = plane->crtc_y + plane->crtc_h;
 693         if (last_y)
 694                 last_y--;
 695
 696         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 697                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 698
 699         writel(val, ctx->regs + VIDOSD_B(win));
 700
 701         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 702                         plane->crtc_x, plane->crtc_y, last_x, last_y);
 703
 704         /* OSD size */
 705         if (win != 3 && win != 4) {
 706                 u32 offset = VIDOSD_D(win);
 707                 if (win == 0)
 708                         offset = VIDOSD_C(win);
 709                 val = plane->crtc_w * plane->crtc_h;
 710                 writel(val, ctx->regs + offset);
 711
 712                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 713         }
 714
 715         fimd_win_set_pixfmt(ctx, win, state->fb);
 716
 717         /* hardware window 0 doesn't support color key. */
 718         if (win != 0)
 719                 fimd_win_set_colkey(ctx, win);
 720
 721         fimd_enable_video_output(ctx, win, true);
 722
 723         if (ctx->driver_data->has_shadowcon)
 724                 fimd_enable_shadow_channel_path(ctx, win, true);
 725
 726         if (ctx->i80_if)
 727                 atomic_set(&ctx->win_updated, 1);
 728 }
 729
 730 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 731                                struct exynos_drm_plane *plane)
 732 {
 733         struct fimd_context *ctx = crtc->ctx;
 734         unsigned int win = plane->zpos;
 735
 736         if (ctx->suspended)
 737                 return;
 738
 739         fimd_enable_video_output(ctx, win, false);
 740
 741         if (ctx->driver_data->has_shadowcon)
 742                 fimd_enable_shadow_channel_path(ctx, win, false);
 743 }
 744
 745 static void fimd_enable(struct exynos_drm_crtc *crtc)
 746 {
 747         struct fimd_context *ctx = crtc->ctx;
 748         int ret;
 749
 750         if (!ctx->suspended)
 751                 return;
 752
 753         ctx->suspended = false;
 754
 755         pm_runtime_get_sync(ctx->dev);
 756
 757         ret = clk_prepare_enable(ctx->bus_clk);
 758         if (ret < 0) {
 759                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
 760                 return;
 761         }
 762
 763         ret = clk_prepare_enable(ctx->lcd_clk);
 764         if  (ret < 0) {
 765                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
 766                 return;
 767         }
 768
 769         /* if vblank was enabled status, enable it again. */
 770         if (test_and_clear_bit(0, &ctx->irq_flags))
 771                 fimd_enable_vblank(ctx->crtc);
 772
 773         fimd_commit(ctx->crtc);
 774 }
 775
 776 static void fimd_disable(struct exynos_drm_crtc *crtc)
 777 {
 778         struct fimd_context *ctx = crtc->ctx;
 779         int i;
 780
 781         if (ctx->suspended)
 782                 return;
 783
 784         /*
 785          * We need to make sure that all windows are disabled before we
 786          * suspend that connector. Otherwise we might try to scan from
 787          * a destroyed buffer later.
 788          */
 789         for (i = 0; i < WINDOWS_NR; i++)
 790                 fimd_disable_plane(crtc, &ctx->planes[i]);
 791
 792         fimd_enable_vblank(crtc);
 793         fimd_wait_for_vblank(crtc);
 794         fimd_disable_vblank(crtc);
 795
 796         writel(0, ctx->regs + VIDCON0);
 797
 798         clk_disable_unprepare(ctx->lcd_clk);
 799         clk_disable_unprepare(ctx->bus_clk);
 800
 801         pm_runtime_put_sync(ctx->dev);
 802
 803         ctx->suspended = true;
 804 }
 805
 806 static void fimd_trigger(struct device *dev)
 807 {
 808         struct fimd_context *ctx = dev_get_drvdata(dev);
 809         struct fimd_driver_data *driver_data = ctx->driver_data;
 810         void *timing_base = ctx->regs + driver_data->timing_base;
 811         u32 reg;
 812
 813          /*
 814           * Skips triggering if in triggering state, because multiple triggering
 815           * requests can cause panel reset.
 816           */
 817         if (atomic_read(&ctx->triggering))
 818                 return;
 819
 820         /* Enters triggering mode */
 821         atomic_set(&ctx->triggering, 1);
 822
 823         reg = readl(timing_base + TRIGCON);
 824         reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
 825         writel(reg, timing_base + TRIGCON);
 826
 827         /*
 828          * Exits triggering mode if vblank is not enabled yet, because when the
 829          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 830          */
 831         if (!test_bit(0, &ctx->irq_flags))
 832                 atomic_set(&ctx->triggering, 0);
 833 }
 834
 835 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 836 {
 837         struct fimd_context *ctx = crtc->ctx;
 838
 839         /* Checks the crtc is detached already from encoder */
 840         if (ctx->pipe < 0 || !ctx->drm_dev)
 841                 return;
 842
 843         /*
 844          * If there is a page flip request, triggers and handles the page flip
 845          * event so that current fb can be updated into panel GRAM.
 846          */
 847         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 848                 fimd_trigger(ctx->dev);
 849
 850         /* Wakes up vsync event queue */
 851         if (atomic_read(&ctx->wait_vsync_event)) {
 852                 atomic_set(&ctx->wait_vsync_event, 0);
 853                 wake_up(&ctx->wait_vsync_queue);
 854         }
 855
 856         if (test_bit(0, &ctx->irq_flags))
 857                 drm_crtc_handle_vblank(&ctx->crtc->base);
 858 }
 859
 860 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
 861 {
 862         struct fimd_context *ctx = crtc->ctx;
 863         u32 val;
 864
 865         /*
 866          * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
 867          * clock. On these SoCs the bootloader may enable it but any
 868          * power domain off/on will reset it to disable state.
 869          */
 870         if (ctx->driver_data != &exynos5_fimd_driver_data)
 871                 return;
 872
 873         val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
 874         writel(val, ctx->regs + DP_MIE_CLKCON);
 875 }
 876
 877 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
 878         .enable = fimd_enable,
 879         .disable = fimd_disable,
 880         .commit = fimd_commit,
 881         .enable_vblank = fimd_enable_vblank,
 882         .disable_vblank = fimd_disable_vblank,
 883         .wait_for_vblank = fimd_wait_for_vblank,
 884         .atomic_begin = fimd_atomic_begin,
 885         .update_plane = fimd_update_plane,
 886         .disable_plane = fimd_disable_plane,
 887         .atomic_flush = fimd_atomic_flush,
 888         .te_handler = fimd_te_handler,
 889         .clock_enable = fimd_dp_clock_enable,
 890 };
 891
 892 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 893 {
 894         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 895         u32 val, clear_bit, start, start_s;
 896         int win;
 897
 898         val = readl(ctx->regs + VIDINTCON1);
 899
 900         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
 901         if (val & clear_bit)
 902                 writel(clear_bit, ctx->regs + VIDINTCON1);
 903
 904         /* check the crtc is detached already from encoder */
 905         if (ctx->pipe < 0 || !ctx->drm_dev)
 906                 goto out;
 907
 908         if (!ctx->i80_if)
 909                 drm_crtc_handle_vblank(&ctx->crtc->base);
 910
 911         for (win = 0 ; win < WINDOWS_NR ; win++) {
 912                 struct exynos_drm_plane *plane = &ctx->planes[win];
 913
 914                 if (!plane->pending_fb)
 915                         continue;
 916
 917                 start = readl(ctx->regs + VIDWx_BUF_START(win, 0));
 918                 start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0));
 919                 if (start == start_s)
 920                         exynos_drm_crtc_finish_update(ctx->crtc, plane);
 921         }
 922
 923         if (ctx->i80_if) {
 924                 /* Exits triggering mode */
 925                 atomic_set(&ctx->triggering, 0);
 926         } else {
 927                 /* set wait vsync event to zero and wake up queue. */
 928                 if (atomic_read(&ctx->wait_vsync_event)) {
 929                         atomic_set(&ctx->wait_vsync_event, 0);
 930                         wake_up(&ctx->wait_vsync_queue);
 931                 }
 932         }
 933
 934 out:
 935         return IRQ_HANDLED;
 936 }
 937
 938 static int fimd_bind(struct device *dev, struct device *master, void *data)
 939 {
 940         struct fimd_context *ctx = dev_get_drvdata(dev);
 941         struct drm_device *drm_dev = data;
 942         struct exynos_drm_private *priv = drm_dev->dev_private;
 943         struct exynos_drm_plane *exynos_plane;
 944         enum drm_plane_type type;
 945         unsigned int zpos;
 946         int ret;
 947
 948         ctx->drm_dev = drm_dev;
 949         ctx->pipe = priv->pipe++;
 950
 951         for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
 952                 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
 953                                                 DRM_PLANE_TYPE_OVERLAY;
 954                 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
 955                                         1 << ctx->pipe, type, fimd_formats,
 956                                         ARRAY_SIZE(fimd_formats), zpos);
 957                 if (ret)
 958                         return ret;
 959         }
 960
 961         exynos_plane = &ctx->planes[ctx->default_win];
 962         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 963                                            ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
 964                                            &fimd_crtc_ops, ctx);
 965         if (IS_ERR(ctx->crtc))
 966                 return PTR_ERR(ctx->crtc);
 967
 968         if (ctx->encoder)
 969                 exynos_dpi_bind(drm_dev, ctx->encoder);
 970
 971         if (is_drm_iommu_supported(drm_dev))
 972                 fimd_clear_channels(ctx->crtc);
 973
 974         ret = drm_iommu_attach_device(drm_dev, dev);
 975         if (ret)
 976                 priv->pipe--;
 977
 978         return ret;
 979 }
 980
 981 static void fimd_unbind(struct device *dev, struct device *master,
 982                         void *data)
 983 {
 984         struct fimd_context *ctx = dev_get_drvdata(dev);
 985
 986         fimd_disable(ctx->crtc);
 987
 988         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 989
 990         if (ctx->encoder)
 991                 exynos_dpi_remove(ctx->encoder);
 992 }
 993
 994 static const struct component_ops fimd_component_ops = {
 995         .bind   = fimd_bind,
 996         .unbind = fimd_unbind,
 997 };
 998
 999 static int fimd_probe(struct platform_device *pdev)
1000 {
1001         struct device *dev = &pdev->dev;
1002         struct fimd_context *ctx;
1003         struct device_node *i80_if_timings;
1004         struct resource *res;
1005         int ret;
1006
1007         if (!dev->of_node)
1008                 return -ENODEV;
1009
1010         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1011         if (!ctx)
1012                 return -ENOMEM;
1013
1014         ctx->dev = dev;
1015         ctx->suspended = true;
1016         ctx->driver_data = drm_fimd_get_driver_data(pdev);
1017
1018         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1019                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1020         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1021                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1022
1023         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1024         if (i80_if_timings) {
1025                 u32 val;
1026
1027                 ctx->i80_if = true;
1028
1029                 if (ctx->driver_data->has_vidoutcon)
1030                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1031                 else
1032                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1033                 /*
1034                  * The user manual describes that this "DSI_EN" bit is required
1035                  * to enable I80 24-bit data interface.
1036                  */
1037                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1038
1039                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1040                         val = 0;
1041                 ctx->i80ifcon = LCD_CS_SETUP(val);
1042                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1043                         val = 0;
1044                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1045                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1046                         val = 1;
1047                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1048                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1049                         val = 0;
1050                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1051         }
1052         of_node_put(i80_if_timings);
1053
1054         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1055                                                         "samsung,sysreg");
1056         if (IS_ERR(ctx->sysreg)) {
1057                 dev_warn(dev, "failed to get system register.\n");
1058                 ctx->sysreg = NULL;
1059         }
1060
1061         ctx->bus_clk = devm_clk_get(dev, "fimd");
1062         if (IS_ERR(ctx->bus_clk)) {
1063                 dev_err(dev, "failed to get bus clock\n");
1064                 return PTR_ERR(ctx->bus_clk);
1065         }
1066
1067         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1068         if (IS_ERR(ctx->lcd_clk)) {
1069                 dev_err(dev, "failed to get lcd clock\n");
1070                 return PTR_ERR(ctx->lcd_clk);
1071         }
1072
1073         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1074
1075         ctx->regs = devm_ioremap_resource(dev, res);
1076         if (IS_ERR(ctx->regs))
1077                 return PTR_ERR(ctx->regs);
1078
1079         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1080                                            ctx->i80_if ? "lcd_sys" : "vsync");
1081         if (!res) {
1082                 dev_err(dev, "irq request failed.\n");
1083                 return -ENXIO;
1084         }
1085
1086         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1087                                                         0, "drm_fimd", ctx);
1088         if (ret) {
1089                 dev_err(dev, "irq request failed.\n");
1090                 return ret;
1091         }
1092
1093         init_waitqueue_head(&ctx->wait_vsync_queue);
1094         atomic_set(&ctx->wait_vsync_event, 0);
1095
1096         platform_set_drvdata(pdev, ctx);
1097
1098         ctx->encoder = exynos_dpi_probe(dev);
1099         if (IS_ERR(ctx->encoder))
1100                 return PTR_ERR(ctx->encoder);
1101
1102         pm_runtime_enable(dev);
1103
1104         ret = component_add(dev, &fimd_component_ops);
1105         if (ret)
1106                 goto err_disable_pm_runtime;
1107
1108         return ret;
1109
1110 err_disable_pm_runtime:
1111         pm_runtime_disable(dev);
1112
1113         return ret;
1114 }
1115
1116 static int fimd_remove(struct platform_device *pdev)
1117 {
1118         pm_runtime_disable(&pdev->dev);
1119
1120         component_del(&pdev->dev, &fimd_component_ops);
1121
1122         return 0;
1123 }
1124
1125 struct platform_driver fimd_driver = {
1126         .probe          = fimd_probe,
1127         .remove         = fimd_remove,
1128         .driver         = {
1129                 .name   = "exynos4-fb",
1130                 .owner  = THIS_MODULE,
1131                 .of_match_table = fimd_driver_dt_match,
1132         },
1133 };