drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include "drmP.h"
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <drm/exynos_drm.h>
  23 #include <plat/regs-fb-v4.h>
  24
  25 #include "exynos_drm_drv.h"
  26 #include "exynos_drm_fbdev.h"
  27 #include "exynos_drm_crtc.h"
  28
  29 /*
  30  * FIMD is stand for Fully Interactive Mobile Display and
  31  * as a display controller, it transfers contents drawn on memory
  32  * to a LCD Panel through Display Interfaces such as RGB or
  33  * CPU Interface.
  34  */
  35
  36 /* position control register for hardware window 0, 2 ~ 4.*/
  37 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  38 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  39 /* size control register for hardware window 0. */
  40 #define VIDOSD_C_SIZE_W0        (VIDOSD_BASE + 0x08)
  41 /* alpha control register for hardware window 1 ~ 4. */
  42 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x18 + (win) * 16)
  43 /* size control register for hardware window 1 ~ 4. */
  44 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  45
  46 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  47 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  48 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  49
  50 /* color key control register for hardware window 1 ~ 4. */
  51 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + (x * 8))
  52 /* color key value register for hardware window 1 ~ 4. */
  53 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + (x * 8))
  54
  55 /* FIMD has totally five hardware windows. */
  56 #define WINDOWS_NR      5
  57
  58 #define get_fimd_context(dev)   platform_get_drvdata(to_platform_device(dev))
  59
  60 struct fimd_win_data {
  61         unsigned int            offset_x;
  62         unsigned int            offset_y;
  63         unsigned int            ovl_width;
  64         unsigned int            ovl_height;
  65         unsigned int            fb_width;
  66         unsigned int            fb_height;
  67         unsigned int            bpp;
  68         dma_addr_t              dma_addr;
  69         void __iomem            *vaddr;
  70         unsigned int            buf_offsize;
  71         unsigned int            line_size;      /* bytes */
  72         bool                    enabled;
  73 };
  74
  75 struct fimd_context {
  76         struct exynos_drm_subdrv        subdrv;
  77         int                             irq;
  78         struct drm_crtc                 *crtc;
  79         struct clk                      *bus_clk;
  80         struct clk                      *lcd_clk;
  81         struct resource                 *regs_res;
  82         void __iomem                    *regs;
  83         struct fimd_win_data            win_data[WINDOWS_NR];
  84         unsigned int                    clkdiv;
  85         unsigned int                    default_win;
  86         unsigned long                   irq_flags;
  87         u32                             vidcon0;
  88         u32                             vidcon1;
  89         bool                            suspended;
  90         struct mutex                    lock;
  91
  92         struct fb_videomode             *timing;
  93 };
  94
  95 static bool fimd_display_is_connected(struct device *dev)
  96 {
  97         DRM_DEBUG_KMS("%s\n", __FILE__);
  98
  99         /* TODO. */
 100
 101         return true;
 102 }
 103
 104 static void *fimd_get_timing(struct device *dev)
 105 {
 106         struct fimd_context *ctx = get_fimd_context(dev);
 107
 108         DRM_DEBUG_KMS("%s\n", __FILE__);
 109
 110         return ctx->timing;
 111 }
 112
 113 static int fimd_check_timing(struct device *dev, void *timing)
 114 {
 115         DRM_DEBUG_KMS("%s\n", __FILE__);
 116
 117         /* TODO. */
 118
 119         return 0;
 120 }
 121
 122 static int fimd_display_power_on(struct device *dev, int mode)
 123 {
 124         DRM_DEBUG_KMS("%s\n", __FILE__);
 125
 126         /* TODO */
 127
 128         return 0;
 129 }
 130
 131 static struct exynos_drm_display_ops fimd_display_ops = {
 132         .type = EXYNOS_DISPLAY_TYPE_LCD,
 133         .is_connected = fimd_display_is_connected,
 134         .get_timing = fimd_get_timing,
 135         .check_timing = fimd_check_timing,
 136         .power_on = fimd_display_power_on,
 137 };
 138
 139 static void fimd_dpms(struct device *subdrv_dev, int mode)
 140 {
 141         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 142
 143         DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
 144
 145         mutex_lock(&ctx->lock);
 146
 147         switch (mode) {
 148         case DRM_MODE_DPMS_ON:
 149                 /*
 150                  * enable fimd hardware only if suspended status.
 151                  *
 152                  * P.S. fimd_dpms function would be called at booting time so
 153                  * clk_enable could be called double time.
 154                  */
 155                 if (ctx->suspended)
 156                         pm_runtime_get_sync(subdrv_dev);
 157                 break;
 158         case DRM_MODE_DPMS_STANDBY:
 159         case DRM_MODE_DPMS_SUSPEND:
 160         case DRM_MODE_DPMS_OFF:
 161                 if (!ctx->suspended)
 162                         pm_runtime_put_sync(subdrv_dev);
 163                 break;
 164         default:
 165                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 166                 break;
 167         }
 168
 169         mutex_unlock(&ctx->lock);
 170 }
 171
 172 static void fimd_apply(struct device *subdrv_dev)
 173 {
 174         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 175         struct exynos_drm_manager *mgr = &ctx->subdrv.manager;
 176         struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
 177         struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
 178         struct fimd_win_data *win_data;
 179         int i;
 180
 181         DRM_DEBUG_KMS("%s\n", __FILE__);
 182
 183         for (i = 0; i < WINDOWS_NR; i++) {
 184                 win_data = &ctx->win_data[i];
 185                 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
 186                         ovl_ops->commit(subdrv_dev, i);
 187         }
 188
 189         if (mgr_ops && mgr_ops->commit)
 190                 mgr_ops->commit(subdrv_dev);
 191 }
 192
 193 static void fimd_commit(struct device *dev)
 194 {
 195         struct fimd_context *ctx = get_fimd_context(dev);
 196         struct fb_videomode *timing = ctx->timing;
 197         u32 val;
 198
 199         if (ctx->suspended)
 200                 return;
 201
 202         DRM_DEBUG_KMS("%s\n", __FILE__);
 203
 204         /* setup polarity values from machine code. */
 205         writel(ctx->vidcon1, ctx->regs + VIDCON1);
 206
 207         /* setup vertical timing values. */
 208         val = VIDTCON0_VBPD(timing->upper_margin - 1) |
 209                VIDTCON0_VFPD(timing->lower_margin - 1) |
 210                VIDTCON0_VSPW(timing->vsync_len - 1);
 211         writel(val, ctx->regs + VIDTCON0);
 212
 213         /* setup horizontal timing values.  */
 214         val = VIDTCON1_HBPD(timing->left_margin - 1) |
 215                VIDTCON1_HFPD(timing->right_margin - 1) |
 216                VIDTCON1_HSPW(timing->hsync_len - 1);
 217         writel(val, ctx->regs + VIDTCON1);
 218
 219         /* setup horizontal and vertical display size. */
 220         val = VIDTCON2_LINEVAL(timing->yres - 1) |
 221                VIDTCON2_HOZVAL(timing->xres - 1);
 222         writel(val, ctx->regs + VIDTCON2);
 223
 224         /* setup clock source, clock divider, enable dma. */
 225         val = ctx->vidcon0;
 226         val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
 227
 228         if (ctx->clkdiv > 1)
 229                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 230         else
 231                 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
 232
 233         /*
 234          * fields of register with prefix '_F' would be updated
 235          * at vsync(same as dma start)
 236          */
 237         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 238         writel(val, ctx->regs + VIDCON0);
 239 }
 240
 241 static int fimd_enable_vblank(struct device *dev)
 242 {
 243         struct fimd_context *ctx = get_fimd_context(dev);
 244         u32 val;
 245
 246         DRM_DEBUG_KMS("%s\n", __FILE__);
 247
 248         if (ctx->suspended)
 249                 return -EPERM;
 250
 251         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 252                 val = readl(ctx->regs + VIDINTCON0);
 253
 254                 val |= VIDINTCON0_INT_ENABLE;
 255                 val |= VIDINTCON0_INT_FRAME;
 256
 257                 val &= ~VIDINTCON0_FRAMESEL0_MASK;
 258                 val |= VIDINTCON0_FRAMESEL0_VSYNC;
 259                 val &= ~VIDINTCON0_FRAMESEL1_MASK;
 260                 val |= VIDINTCON0_FRAMESEL1_NONE;
 261
 262                 writel(val, ctx->regs + VIDINTCON0);
 263         }
 264
 265         return 0;
 266 }
 267
 268 static void fimd_disable_vblank(struct device *dev)
 269 {
 270         struct fimd_context *ctx = get_fimd_context(dev);
 271         u32 val;
 272
 273         DRM_DEBUG_KMS("%s\n", __FILE__);
 274
 275         if (ctx->suspended)
 276                 return;
 277
 278         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 279                 val = readl(ctx->regs + VIDINTCON0);
 280
 281                 val &= ~VIDINTCON0_INT_FRAME;
 282                 val &= ~VIDINTCON0_INT_ENABLE;
 283
 284                 writel(val, ctx->regs + VIDINTCON0);
 285         }
 286 }
 287
 288 static struct exynos_drm_manager_ops fimd_manager_ops = {
 289         .dpms = fimd_dpms,
 290         .apply = fimd_apply,
 291         .commit = fimd_commit,
 292         .enable_vblank = fimd_enable_vblank,
 293         .disable_vblank = fimd_disable_vblank,
 294 };
 295
 296 static void fimd_win_mode_set(struct device *dev,
 297                               struct exynos_drm_overlay *overlay)
 298 {
 299         struct fimd_context *ctx = get_fimd_context(dev);
 300         struct fimd_win_data *win_data;
 301         int win;
 302         unsigned long offset;
 303
 304         DRM_DEBUG_KMS("%s\n", __FILE__);
 305
 306         if (!overlay) {
 307                 dev_err(dev, "overlay is NULL\n");
 308                 return;
 309         }
 310
 311         win = overlay->zpos;
 312         if (win == DEFAULT_ZPOS)
 313                 win = ctx->default_win;
 314
 315         if (win < 0 || win > WINDOWS_NR)
 316                 return;
 317
 318         offset = overlay->fb_x * (overlay->bpp >> 3);
 319         offset += overlay->fb_y * overlay->pitch;
 320
 321         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
 322
 323         win_data = &ctx->win_data[win];
 324
 325         win_data->offset_x = overlay->crtc_x;
 326         win_data->offset_y = overlay->crtc_y;
 327         win_data->ovl_width = overlay->crtc_width;
 328         win_data->ovl_height = overlay->crtc_height;
 329         win_data->fb_width = overlay->fb_width;
 330         win_data->fb_height = overlay->fb_height;
 331         win_data->dma_addr = overlay->dma_addr[0] + offset;
 332         win_data->vaddr = overlay->vaddr[0] + offset;
 333         win_data->bpp = overlay->bpp;
 334         win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
 335                                 (overlay->bpp >> 3);
 336         win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
 337
 338         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 339                         win_data->offset_x, win_data->offset_y);
 340         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 341                         win_data->ovl_width, win_data->ovl_height);
 342         DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
 343                         (unsigned long)win_data->dma_addr,
 344                         (unsigned long)win_data->vaddr);
 345         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 346                         overlay->fb_width, overlay->crtc_width);
 347 }
 348
 349 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
 350 {
 351         struct fimd_context *ctx = get_fimd_context(dev);
 352         struct fimd_win_data *win_data = &ctx->win_data[win];
 353         unsigned long val;
 354
 355         DRM_DEBUG_KMS("%s\n", __FILE__);
 356
 357         val = WINCONx_ENWIN;
 358
 359         switch (win_data->bpp) {
 360         case 1:
 361                 val |= WINCON0_BPPMODE_1BPP;
 362                 val |= WINCONx_BITSWP;
 363                 val |= WINCONx_BURSTLEN_4WORD;
 364                 break;
 365         case 2:
 366                 val |= WINCON0_BPPMODE_2BPP;
 367                 val |= WINCONx_BITSWP;
 368                 val |= WINCONx_BURSTLEN_8WORD;
 369                 break;
 370         case 4:
 371                 val |= WINCON0_BPPMODE_4BPP;
 372                 val |= WINCONx_BITSWP;
 373                 val |= WINCONx_BURSTLEN_8WORD;
 374                 break;
 375         case 8:
 376                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 377                 val |= WINCONx_BURSTLEN_8WORD;
 378                 val |= WINCONx_BYTSWP;
 379                 break;
 380         case 16:
 381                 val |= WINCON0_BPPMODE_16BPP_565;
 382                 val |= WINCONx_HAWSWP;
 383                 val |= WINCONx_BURSTLEN_16WORD;
 384                 break;
 385         case 24:
 386                 val |= WINCON0_BPPMODE_24BPP_888;
 387                 val |= WINCONx_WSWP;
 388                 val |= WINCONx_BURSTLEN_16WORD;
 389                 break;
 390         case 32:
 391                 val |= WINCON1_BPPMODE_28BPP_A4888
 392                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 393                 val |= WINCONx_WSWP;
 394                 val |= WINCONx_BURSTLEN_16WORD;
 395                 break;
 396         default:
 397                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 398
 399                 val |= WINCON0_BPPMODE_24BPP_888;
 400                 val |= WINCONx_WSWP;
 401                 val |= WINCONx_BURSTLEN_16WORD;
 402                 break;
 403         }
 404
 405         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 406
 407         writel(val, ctx->regs + WINCON(win));
 408 }
 409
 410 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
 411 {
 412         struct fimd_context *ctx = get_fimd_context(dev);
 413         unsigned int keycon0 = 0, keycon1 = 0;
 414
 415         DRM_DEBUG_KMS("%s\n", __FILE__);
 416
 417         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 418                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 419
 420         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 421
 422         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 423         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 424 }
 425
 426 static void fimd_win_commit(struct device *dev, int zpos)
 427 {
 428         struct fimd_context *ctx = get_fimd_context(dev);
 429         struct fimd_win_data *win_data;
 430         int win = zpos;
 431         unsigned long val, alpha, size;
 432
 433         DRM_DEBUG_KMS("%s\n", __FILE__);
 434
 435         if (ctx->suspended)
 436                 return;
 437
 438         if (win == DEFAULT_ZPOS)
 439                 win = ctx->default_win;
 440
 441         if (win < 0 || win > WINDOWS_NR)
 442                 return;
 443
 444         win_data = &ctx->win_data[win];
 445
 446         /*
 447          * SHADOWCON register is used for enabling timing.
 448          *
 449          * for example, once only width value of a register is set,
 450          * if the dma is started then fimd hardware could malfunction so
 451          * with protect window setting, the register fields with prefix '_F'
 452          * wouldn't be updated at vsync also but updated once unprotect window
 453          * is set.
 454          */
 455
 456         /* protect windows */
 457         val = readl(ctx->regs + SHADOWCON);
 458         val |= SHADOWCON_WINx_PROTECT(win);
 459         writel(val, ctx->regs + SHADOWCON);
 460
 461         /* buffer start address */
 462         val = (unsigned long)win_data->dma_addr;
 463         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 464
 465         /* buffer end address */
 466         size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
 467         val = (unsigned long)(win_data->dma_addr + size);
 468         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 469
 470         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 471                         (unsigned long)win_data->dma_addr, val, size);
 472         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 473                         win_data->ovl_width, win_data->ovl_height);
 474
 475         /* buffer size */
 476         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 477                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
 478         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 479
 480         /* OSD position */
 481         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 482                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
 483         writel(val, ctx->regs + VIDOSD_A(win));
 484
 485         val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
 486                                         win_data->ovl_width - 1) |
 487                 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
 488                                         win_data->ovl_height - 1);
 489         writel(val, ctx->regs + VIDOSD_B(win));
 490
 491         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 492                         win_data->offset_x, win_data->offset_y,
 493                         win_data->offset_x + win_data->ovl_width - 1,
 494                         win_data->offset_y + win_data->ovl_height - 1);
 495
 496         /* hardware window 0 doesn't support alpha channel. */
 497         if (win != 0) {
 498                 /* OSD alpha */
 499                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 500                         VIDISD14C_ALPHA1_G(0xf) |
 501                         VIDISD14C_ALPHA1_B(0xf);
 502
 503                 writel(alpha, ctx->regs + VIDOSD_C(win));
 504         }
 505
 506         /* OSD size */
 507         if (win != 3 && win != 4) {
 508                 u32 offset = VIDOSD_D(win);
 509                 if (win == 0)
 510                         offset = VIDOSD_C_SIZE_W0;
 511                 val = win_data->ovl_width * win_data->ovl_height;
 512                 writel(val, ctx->regs + offset);
 513
 514                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 515         }
 516
 517         fimd_win_set_pixfmt(dev, win);
 518
 519         /* hardware window 0 doesn't support color key. */
 520         if (win != 0)
 521                 fimd_win_set_colkey(dev, win);
 522
 523         /* wincon */
 524         val = readl(ctx->regs + WINCON(win));
 525         val |= WINCONx_ENWIN;
 526         writel(val, ctx->regs + WINCON(win));
 527
 528         /* Enable DMA channel and unprotect windows */
 529         val = readl(ctx->regs + SHADOWCON);
 530         val |= SHADOWCON_CHx_ENABLE(win);
 531         val &= ~SHADOWCON_WINx_PROTECT(win);
 532         writel(val, ctx->regs + SHADOWCON);
 533
 534         win_data->enabled = true;
 535 }
 536
 537 static void fimd_win_disable(struct device *dev, int zpos)
 538 {
 539         struct fimd_context *ctx = get_fimd_context(dev);
 540         struct fimd_win_data *win_data;
 541         int win = zpos;
 542         u32 val;
 543
 544         DRM_DEBUG_KMS("%s\n", __FILE__);
 545
 546         if (win == DEFAULT_ZPOS)
 547                 win = ctx->default_win;
 548
 549         if (win < 0 || win > WINDOWS_NR)
 550                 return;
 551
 552         win_data = &ctx->win_data[win];
 553
 554         /* protect windows */
 555         val = readl(ctx->regs + SHADOWCON);
 556         val |= SHADOWCON_WINx_PROTECT(win);
 557         writel(val, ctx->regs + SHADOWCON);
 558
 559         /* wincon */
 560         val = readl(ctx->regs + WINCON(win));
 561         val &= ~WINCONx_ENWIN;
 562         writel(val, ctx->regs + WINCON(win));
 563
 564         /* unprotect windows */
 565         val = readl(ctx->regs + SHADOWCON);
 566         val &= ~SHADOWCON_CHx_ENABLE(win);
 567         val &= ~SHADOWCON_WINx_PROTECT(win);
 568         writel(val, ctx->regs + SHADOWCON);
 569
 570         win_data->enabled = false;
 571 }
 572
 573 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
 574         .mode_set = fimd_win_mode_set,
 575         .commit = fimd_win_commit,
 576         .disable = fimd_win_disable,
 577 };
 578
 579 static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
 580 {
 581         struct exynos_drm_private *dev_priv = drm_dev->dev_private;
 582         struct drm_pending_vblank_event *e, *t;
 583         struct timeval now;
 584         unsigned long flags;
 585         bool is_checked = false;
 586
 587         spin_lock_irqsave(&drm_dev->event_lock, flags);
 588
 589         list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
 590                         base.link) {
 591                 /* if event's pipe isn't same as crtc then ignore it. */
 592                 if (crtc != e->pipe)
 593                         continue;
 594
 595                 is_checked = true;
 596
 597                 do_gettimeofday(&now);
 598                 e->event.sequence = 0;
 599                 e->event.tv_sec = now.tv_sec;
 600                 e->event.tv_usec = now.tv_usec;
 601
 602                 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
 603                 wake_up_interruptible(&e->base.file_priv->event_wait);
 604         }
 605
 606         if (is_checked) {
 607                 drm_vblank_put(drm_dev, crtc);
 608
 609                 /*
 610                  * don't off vblank if vblank_disable_allowed is 1,
 611                  * because vblank would be off by timer handler.
 612                  */
 613                 if (!drm_dev->vblank_disable_allowed)
 614                         drm_vblank_off(drm_dev, crtc);
 615         }
 616
 617         spin_unlock_irqrestore(&drm_dev->event_lock, flags);
 618 }
 619
 620 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 621 {
 622         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 623         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 624         struct drm_device *drm_dev = subdrv->drm_dev;
 625         struct exynos_drm_manager *manager = &subdrv->manager;
 626         u32 val;
 627
 628         val = readl(ctx->regs + VIDINTCON1);
 629
 630         if (val & VIDINTCON1_INT_FRAME)
 631                 /* VSYNC interrupt */
 632                 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
 633
 634         /* check the crtc is detached already from encoder */
 635         if (manager->pipe < 0)
 636                 goto out;
 637
 638         drm_handle_vblank(drm_dev, manager->pipe);
 639         fimd_finish_pageflip(drm_dev, manager->pipe);
 640
 641 out:
 642         return IRQ_HANDLED;
 643 }
 644
 645 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 646 {
 647         DRM_DEBUG_KMS("%s\n", __FILE__);
 648
 649         /*
 650          * enable drm irq mode.
 651          * - with irq_enabled = 1, we can use the vblank feature.
 652          *
 653          * P.S. note that we wouldn't use drm irq handler but
 654          *      just specific driver own one instead because
 655          *      drm framework supports only one irq handler.
 656          */
 657         drm_dev->irq_enabled = 1;
 658
 659         /*
 660          * with vblank_disable_allowed = 1, vblank interrupt will be disabled
 661          * by drm timer once a current process gives up ownership of
 662          * vblank event.(after drm_vblank_put function is called)
 663          */
 664         drm_dev->vblank_disable_allowed = 1;
 665
 666         return 0;
 667 }
 668
 669 static void fimd_subdrv_remove(struct drm_device *drm_dev)
 670 {
 671         DRM_DEBUG_KMS("%s\n", __FILE__);
 672
 673         /* TODO. */
 674 }
 675
 676 static int fimd_calc_clkdiv(struct fimd_context *ctx,
 677                             struct fb_videomode *timing)
 678 {
 679         unsigned long clk = clk_get_rate(ctx->lcd_clk);
 680         u32 retrace;
 681         u32 clkdiv;
 682         u32 best_framerate = 0;
 683         u32 framerate;
 684
 685         DRM_DEBUG_KMS("%s\n", __FILE__);
 686
 687         retrace = timing->left_margin + timing->hsync_len +
 688                                 timing->right_margin + timing->xres;
 689         retrace *= timing->upper_margin + timing->vsync_len +
 690                                 timing->lower_margin + timing->yres;
 691
 692         /* default framerate is 60Hz */
 693         if (!timing->refresh)
 694                 timing->refresh = 60;
 695
 696         clk /= retrace;
 697
 698         for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
 699                 int tmp;
 700
 701                 /* get best framerate */
 702                 framerate = clk / clkdiv;
 703                 tmp = timing->refresh - framerate;
 704                 if (tmp < 0) {
 705                         best_framerate = framerate;
 706                         continue;
 707                 } else {
 708                         if (!best_framerate)
 709                                 best_framerate = framerate;
 710                         else if (tmp < (best_framerate - framerate))
 711                                 best_framerate = framerate;
 712                         break;
 713                 }
 714         }
 715
 716         return clkdiv;
 717 }
 718
 719 static void fimd_clear_win(struct fimd_context *ctx, int win)
 720 {
 721         u32 val;
 722
 723         DRM_DEBUG_KMS("%s\n", __FILE__);
 724
 725         writel(0, ctx->regs + WINCON(win));
 726         writel(0, ctx->regs + VIDOSD_A(win));
 727         writel(0, ctx->regs + VIDOSD_B(win));
 728         writel(0, ctx->regs + VIDOSD_C(win));
 729
 730         if (win == 1 || win == 2)
 731                 writel(0, ctx->regs + VIDOSD_D(win));
 732
 733         val = readl(ctx->regs + SHADOWCON);
 734         val &= ~SHADOWCON_WINx_PROTECT(win);
 735         writel(val, ctx->regs + SHADOWCON);
 736 }
 737
 738 static int fimd_power_on(struct fimd_context *ctx, bool enable)
 739 {
 740         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 741         struct device *dev = subdrv->manager.dev;
 742
 743         DRM_DEBUG_KMS("%s\n", __FILE__);
 744
 745         if (enable != false && enable != true)
 746                 return -EINVAL;
 747
 748         if (enable) {
 749                 int ret;
 750
 751                 ret = clk_enable(ctx->bus_clk);
 752                 if (ret < 0)
 753                         return ret;
 754
 755                 ret = clk_enable(ctx->lcd_clk);
 756                 if  (ret < 0) {
 757                         clk_disable(ctx->bus_clk);
 758                         return ret;
 759                 }
 760
 761                 ctx->suspended = false;
 762
 763                 /* if vblank was enabled status, enable it again. */
 764                 if (test_and_clear_bit(0, &ctx->irq_flags))
 765                         fimd_enable_vblank(dev);
 766
 767                 fimd_apply(dev);
 768         } else {
 769                 clk_disable(ctx->lcd_clk);
 770                 clk_disable(ctx->bus_clk);
 771
 772                 ctx->suspended = true;
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int __devinit fimd_probe(struct platform_device *pdev)
 779 {
 780         struct device *dev = &pdev->dev;
 781         struct fimd_context *ctx;
 782         struct exynos_drm_subdrv *subdrv;
 783         struct exynos_drm_fimd_pdata *pdata;
 784         struct fb_videomode *timing;
 785         struct resource *res;
 786         int win;
 787         int ret = -EINVAL;
 788
 789         DRM_DEBUG_KMS("%s\n", __FILE__);
 790
 791         pdata = pdev->dev.platform_data;
 792         if (!pdata) {
 793                 dev_err(dev, "no platform data specified\n");
 794                 return -EINVAL;
 795         }
 796
 797         timing = &pdata->timing;
 798         if (!timing) {
 799                 dev_err(dev, "timing is null.\n");
 800                 return -EINVAL;
 801         }
 802
 803         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 804         if (!ctx)
 805                 return -ENOMEM;
 806
 807         ctx->bus_clk = clk_get(dev, "fimd");
 808         if (IS_ERR(ctx->bus_clk)) {
 809                 dev_err(dev, "failed to get bus clock\n");
 810                 ret = PTR_ERR(ctx->bus_clk);
 811                 goto err_clk_get;
 812         }
 813
 814         clk_enable(ctx->bus_clk);
 815
 816         ctx->lcd_clk = clk_get(dev, "sclk_fimd");
 817         if (IS_ERR(ctx->lcd_clk)) {
 818                 dev_err(dev, "failed to get lcd clock\n");
 819                 ret = PTR_ERR(ctx->lcd_clk);
 820                 goto err_bus_clk;
 821         }
 822
 823         clk_enable(ctx->lcd_clk);
 824
 825         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 826         if (!res) {
 827                 dev_err(dev, "failed to find registers\n");
 828                 ret = -ENOENT;
 829                 goto err_clk;
 830         }
 831
 832         ctx->regs_res = request_mem_region(res->start, resource_size(res),
 833                                            dev_name(dev));
 834         if (!ctx->regs_res) {
 835                 dev_err(dev, "failed to claim register region\n");
 836                 ret = -ENOENT;
 837                 goto err_clk;
 838         }
 839
 840         ctx->regs = ioremap(res->start, resource_size(res));
 841         if (!ctx->regs) {
 842                 dev_err(dev, "failed to map registers\n");
 843                 ret = -ENXIO;
 844                 goto err_req_region_io;
 845         }
 846
 847         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 848         if (!res) {
 849                 dev_err(dev, "irq request failed.\n");
 850                 goto err_req_region_irq;
 851         }
 852
 853         ctx->irq = res->start;
 854
 855         ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
 856         if (ret < 0) {
 857                 dev_err(dev, "irq request failed.\n");
 858                 goto err_req_irq;
 859         }
 860
 861         ctx->clkdiv = fimd_calc_clkdiv(ctx, timing);
 862         ctx->vidcon0 = pdata->vidcon0;
 863         ctx->vidcon1 = pdata->vidcon1;
 864         ctx->default_win = pdata->default_win;
 865         ctx->timing = timing;
 866
 867         timing->pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
 868
 869         DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
 870                         timing->pixclock, ctx->clkdiv);
 871
 872         subdrv = &ctx->subdrv;
 873
 874         subdrv->probe = fimd_subdrv_probe;
 875         subdrv->remove = fimd_subdrv_remove;
 876         subdrv->manager.pipe = -1;
 877         subdrv->manager.ops = &fimd_manager_ops;
 878         subdrv->manager.overlay_ops = &fimd_overlay_ops;
 879         subdrv->manager.display_ops = &fimd_display_ops;
 880         subdrv->manager.dev = dev;
 881
 882         mutex_init(&ctx->lock);
 883
 884         platform_set_drvdata(pdev, ctx);
 885
 886         pm_runtime_set_active(dev);
 887         pm_runtime_enable(dev);
 888         pm_runtime_get_sync(dev);
 889
 890         for (win = 0; win < WINDOWS_NR; win++)
 891                 fimd_clear_win(ctx, win);
 892
 893         exynos_drm_subdrv_register(subdrv);
 894
 895         return 0;
 896
 897 err_req_irq:
 898 err_req_region_irq:
 899         iounmap(ctx->regs);
 900
 901 err_req_region_io:
 902         release_resource(ctx->regs_res);
 903         kfree(ctx->regs_res);
 904
 905 err_clk:
 906         clk_disable(ctx->lcd_clk);
 907         clk_put(ctx->lcd_clk);
 908
 909 err_bus_clk:
 910         clk_disable(ctx->bus_clk);
 911         clk_put(ctx->bus_clk);
 912
 913 err_clk_get:
 914         kfree(ctx);
 915         return ret;
 916 }
 917
 918 static int __devexit fimd_remove(struct platform_device *pdev)
 919 {
 920         struct device *dev = &pdev->dev;
 921         struct fimd_context *ctx = platform_get_drvdata(pdev);
 922
 923         DRM_DEBUG_KMS("%s\n", __FILE__);
 924
 925         exynos_drm_subdrv_unregister(&ctx->subdrv);
 926
 927         if (ctx->suspended)
 928                 goto out;
 929
 930         clk_disable(ctx->lcd_clk);
 931         clk_disable(ctx->bus_clk);
 932
 933         pm_runtime_set_suspended(dev);
 934         pm_runtime_put_sync(dev);
 935
 936 out:
 937         pm_runtime_disable(dev);
 938
 939         clk_put(ctx->lcd_clk);
 940         clk_put(ctx->bus_clk);
 941
 942         iounmap(ctx->regs);
 943         release_resource(ctx->regs_res);
 944         kfree(ctx->regs_res);
 945         free_irq(ctx->irq, ctx);
 946
 947         kfree(ctx);
 948
 949         return 0;
 950 }
 951
 952 #ifdef CONFIG_PM_SLEEP
 953 static int fimd_suspend(struct device *dev)
 954 {
 955         struct fimd_context *ctx = get_fimd_context(dev);
 956
 957         if (pm_runtime_suspended(dev))
 958                 return 0;
 959
 960         /*
 961          * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
 962          * called here, an error would be returned by that interface
 963          * because the usage_count of pm runtime is more than 1.
 964          */
 965         return fimd_power_on(ctx, false);
 966 }
 967
 968 static int fimd_resume(struct device *dev)
 969 {
 970         struct fimd_context *ctx = get_fimd_context(dev);
 971
 972         /*
 973          * if entered to sleep when lcd panel was on, the usage_count
 974          * of pm runtime would still be 1 so in this case, fimd driver
 975          * should be on directly not drawing on pm runtime interface.
 976          */
 977         if (!pm_runtime_suspended(dev))
 978                 return fimd_power_on(ctx, true);
 979
 980         return 0;
 981 }
 982 #endif
 983
 984 #ifdef CONFIG_PM_RUNTIME
 985 static int fimd_runtime_suspend(struct device *dev)
 986 {
 987         struct fimd_context *ctx = get_fimd_context(dev);
 988
 989         DRM_DEBUG_KMS("%s\n", __FILE__);
 990
 991         return fimd_power_on(ctx, false);
 992 }
 993
 994 static int fimd_runtime_resume(struct device *dev)
 995 {
 996         struct fimd_context *ctx = get_fimd_context(dev);
 997
 998         DRM_DEBUG_KMS("%s\n", __FILE__);
 999
1000         return fimd_power_on(ctx, true);
1001 }
1002 #endif
1003
1004 static const struct dev_pm_ops fimd_pm_ops = {
1005         SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1006         SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1007 };
1008
1009 static struct platform_driver fimd_driver = {
1010         .probe          = fimd_probe,
1011         .remove         = __devexit_p(fimd_remove),
1012         .driver         = {
1013                 .name   = "exynos4-fb",
1014                 .owner  = THIS_MODULE,
1015                 .pm     = &fimd_pm_ops,
1016         },
1017 };
1018
1019 static int __init fimd_init(void)
1020 {
1021         return platform_driver_register(&fimd_driver);
1022 }
1023
1024 static void __exit fimd_exit(void)
1025 {
1026         platform_driver_unregister(&fimd_driver);
1027 }
1028
1029 module_init(fimd_init);
1030 module_exit(fimd_exit);
1031
1032 MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
1033 MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
1034 MODULE_DESCRIPTION("Samsung DRM FIMD Driver");
1035 MODULE_LICENSE("GPL");