drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .gen = 8, .num_pipes = 3,
 350         .need_gfx_hws = 1, .has_hotplug = 1,
 351         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 352         .is_valleyview = 1,
 353         .display_mmio_offset = VLV_DISPLAY_BASE,
 354         GEN_CHV_PIPEOFFSETS,
 355         CURSOR_OFFSETS,
 356 };
 357
 358 static const struct intel_device_info intel_skylake_info = {
 359         .is_skylake = 1,
 360         .gen = 9, .num_pipes = 3,
 361         .need_gfx_hws = 1, .has_hotplug = 1,
 362         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 363         .has_llc = 1,
 364         .has_ddi = 1,
 365         .has_fpga_dbg = 1,
 366         .has_fbc = 1,
 367         GEN_DEFAULT_PIPEOFFSETS,
 368         IVB_CURSOR_OFFSETS,
 369 };
 370
 371 static const struct intel_device_info intel_skylake_gt3_info = {
 372         .is_skylake = 1,
 373         .gen = 9, .num_pipes = 3,
 374         .need_gfx_hws = 1, .has_hotplug = 1,
 375         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 376         .has_llc = 1,
 377         .has_ddi = 1,
 378         .has_fpga_dbg = 1,
 379         .has_fbc = 1,
 380         GEN_DEFAULT_PIPEOFFSETS,
 381         IVB_CURSOR_OFFSETS,
 382 };
 383
 384 static const struct intel_device_info intel_broxton_info = {
 385         .is_preliminary = 1,
 386         .gen = 9,
 387         .need_gfx_hws = 1, .has_hotplug = 1,
 388         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 389         .num_pipes = 3,
 390         .has_ddi = 1,
 391         .has_fpga_dbg = 1,
 392         .has_fbc = 1,
 393         GEN_DEFAULT_PIPEOFFSETS,
 394         IVB_CURSOR_OFFSETS,
 395 };
 396
 397 /*
 398  * Make sure any device matches here are from most specific to most
 399  * general.  For example, since the Quanta match is based on the subsystem
 400  * and subvendor IDs, we need it to come before the more general IVB
 401  * PCI ID matches, otherwise we'll use the wrong info struct above.
 402  */
 403 #define INTEL_PCI_IDS \
 404         INTEL_I830_IDS(&intel_i830_info),       \
 405         INTEL_I845G_IDS(&intel_845g_info),      \
 406         INTEL_I85X_IDS(&intel_i85x_info),       \
 407         INTEL_I865G_IDS(&intel_i865g_info),     \
 408         INTEL_I915G_IDS(&intel_i915g_info),     \
 409         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 410         INTEL_I945G_IDS(&intel_i945g_info),     \
 411         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 412         INTEL_I965G_IDS(&intel_i965g_info),     \
 413         INTEL_G33_IDS(&intel_g33_info),         \
 414         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 415         INTEL_GM45_IDS(&intel_gm45_info),       \
 416         INTEL_G45_IDS(&intel_g45_info),         \
 417         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 418         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 419         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 420         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 421         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 422         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 423         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 424         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 425         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 426         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 427         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 428         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 429         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 430         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 431         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 432         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 433         INTEL_CHV_IDS(&intel_cherryview_info),  \
 434         INTEL_SKL_GT1_IDS(&intel_skylake_info), \
 435         INTEL_SKL_GT2_IDS(&intel_skylake_info), \
 436         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),     \
 437         INTEL_BXT_IDS(&intel_broxton_info)
 438
 439 static const struct pci_device_id pciidlist[] = {               /* aka */
 440         INTEL_PCI_IDS,
 441         {0, 0, 0}
 442 };
 443
 444 MODULE_DEVICE_TABLE(pci, pciidlist);
 445
 446 void intel_detect_pch(struct drm_device *dev)
 447 {
 448         struct drm_i915_private *dev_priv = dev->dev_private;
 449         struct pci_dev *pch = NULL;
 450
 451         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 452          * (which really amounts to a PCH but no South Display).
 453          */
 454         if (INTEL_INFO(dev)->num_pipes == 0) {
 455                 dev_priv->pch_type = PCH_NOP;
 456                 return;
 457         }
 458
 459         /*
 460          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 461          * make graphics device passthrough work easy for VMM, that only
 462          * need to expose ISA bridge to let driver know the real hardware
 463          * underneath. This is a requirement from virtualization team.
 464          *
 465          * In some virtualized environments (e.g. XEN), there is irrelevant
 466          * ISA bridge in the system. To work reliably, we should scan trhough
 467          * all the ISA bridge devices and check for the first match, instead
 468          * of only checking the first one.
 469          */
 470         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 471                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 472                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 473                         dev_priv->pch_id = id;
 474
 475                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 476                                 dev_priv->pch_type = PCH_IBX;
 477                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 478                                 WARN_ON(!IS_GEN5(dev));
 479                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 480                                 dev_priv->pch_type = PCH_CPT;
 481                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 482                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 483                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 484                                 /* PantherPoint is CPT compatible */
 485                                 dev_priv->pch_type = PCH_CPT;
 486                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 487                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 488                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 489                                 dev_priv->pch_type = PCH_LPT;
 490                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 491                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 492                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 493                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 494                                 dev_priv->pch_type = PCH_LPT;
 495                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 496                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 497                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 498                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 499                                 dev_priv->pch_type = PCH_SPT;
 500                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 501                                 WARN_ON(!IS_SKYLAKE(dev));
 502                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 503                                 dev_priv->pch_type = PCH_SPT;
 504                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 505                                 WARN_ON(!IS_SKYLAKE(dev));
 506                         } else
 507                                 continue;
 508
 509                         break;
 510                 }
 511         }
 512         if (!pch)
 513                 DRM_DEBUG_KMS("No PCH found.\n");
 514
 515         pci_dev_put(pch);
 516 }
 517
 518 bool i915_semaphore_is_enabled(struct drm_device *dev)
 519 {
 520         if (INTEL_INFO(dev)->gen < 6)
 521                 return false;
 522
 523         if (i915.semaphores >= 0)
 524                 return i915.semaphores;
 525
 526         /* TODO: make semaphores and Execlists play nicely together */
 527         if (i915.enable_execlists)
 528                 return false;
 529
 530         /* Until we get further testing... */
 531         if (IS_GEN8(dev))
 532                 return false;
 533
 534 #ifdef CONFIG_INTEL_IOMMU
 535         /* Enable semaphores on SNB when IO remapping is off */
 536         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 537                 return false;
 538 #endif
 539
 540         return true;
 541 }
 542
 543 void i915_firmware_load_error_print(const char *fw_path, int err)
 544 {
 545         DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
 546
 547         /*
 548          * If the reason is not known assume -ENOENT since that's the most
 549          * usual failure mode.
 550          */
 551         if (!err)
 552                 err = -ENOENT;
 553
 554         if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
 555                 return;
 556
 557         DRM_ERROR(
 558           "The driver is built-in, so to load the firmware you need to\n"
 559           "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
 560           "in your initrd/initramfs image.\n");
 561 }
 562
 563 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 564 {
 565         struct drm_device *dev = dev_priv->dev;
 566         struct drm_encoder *encoder;
 567
 568         drm_modeset_lock_all(dev);
 569         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 570                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 571
 572                 if (intel_encoder->suspend)
 573                         intel_encoder->suspend(intel_encoder);
 574         }
 575         drm_modeset_unlock_all(dev);
 576 }
 577
 578 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 579 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 580                               bool rpm_resume);
 581 static int skl_resume_prepare(struct drm_i915_private *dev_priv);
 582 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
 583
 584
 585 static int i915_drm_suspend(struct drm_device *dev)
 586 {
 587         struct drm_i915_private *dev_priv = dev->dev_private;
 588         pci_power_t opregion_target_state;
 589         int error;
 590
 591         /* ignore lid events during suspend */
 592         mutex_lock(&dev_priv->modeset_restore_lock);
 593         dev_priv->modeset_restore = MODESET_SUSPENDED;
 594         mutex_unlock(&dev_priv->modeset_restore_lock);
 595
 596         /* We do a lot of poking in a lot of registers, make sure they work
 597          * properly. */
 598         intel_display_set_init_power(dev_priv, true);
 599
 600         drm_kms_helper_poll_disable(dev);
 601
 602         pci_save_state(dev->pdev);
 603
 604         error = i915_gem_suspend(dev);
 605         if (error) {
 606                 dev_err(&dev->pdev->dev,
 607                         "GEM idle failed, resume might fail\n");
 608                 return error;
 609         }
 610
 611         intel_suspend_gt_powersave(dev);
 612
 613         /*
 614          * Disable CRTCs directly since we want to preserve sw state
 615          * for _thaw. Also, power gate the CRTC power wells.
 616          */
 617         drm_modeset_lock_all(dev);
 618         intel_display_suspend(dev);
 619         drm_modeset_unlock_all(dev);
 620
 621         intel_dp_mst_suspend(dev);
 622
 623         intel_runtime_pm_disable_interrupts(dev_priv);
 624         intel_hpd_cancel_work(dev_priv);
 625
 626         intel_suspend_encoders(dev_priv);
 627
 628         intel_suspend_hw(dev);
 629
 630         i915_gem_suspend_gtt_mappings(dev);
 631
 632         i915_save_state(dev);
 633
 634         opregion_target_state = PCI_D3cold;
 635 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 636         if (acpi_target_system_state() < ACPI_STATE_S3)
 637                 opregion_target_state = PCI_D1;
 638 #endif
 639         intel_opregion_notify_adapter(dev, opregion_target_state);
 640
 641         intel_uncore_forcewake_reset(dev, false);
 642         intel_opregion_fini(dev);
 643
 644         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 645
 646         dev_priv->suspend_count++;
 647
 648         intel_display_set_init_power(dev_priv, false);
 649
 650         return 0;
 651 }
 652
 653 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 654 {
 655         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 656         int ret;
 657
 658         ret = intel_suspend_complete(dev_priv);
 659
 660         if (ret) {
 661                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 662
 663                 return ret;
 664         }
 665
 666         pci_disable_device(drm_dev->pdev);
 667         /*
 668          * During hibernation on some platforms the BIOS may try to access
 669          * the device even though it's already in D3 and hang the machine. So
 670          * leave the device in D0 on those platforms and hope the BIOS will
 671          * power down the device properly. The issue was seen on multiple old
 672          * GENs with different BIOS vendors, so having an explicit blacklist
 673          * is inpractical; apply the workaround on everything pre GEN6. The
 674          * platforms where the issue was seen:
 675          * Lenovo Thinkpad X301, X61s, X60, T60, X41
 676          * Fujitsu FSC S7110
 677          * Acer Aspire 1830T
 678          */
 679         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
 680                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 681
 682         return 0;
 683 }
 684
 685 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
 686 {
 687         int error;
 688
 689         if (!dev || !dev->dev_private) {
 690                 DRM_ERROR("dev: %p\n", dev);
 691                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 692                 return -ENODEV;
 693         }
 694
 695         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 696                          state.event != PM_EVENT_FREEZE))
 697                 return -EINVAL;
 698
 699         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 700                 return 0;
 701
 702         error = i915_drm_suspend(dev);
 703         if (error)
 704                 return error;
 705
 706         return i915_drm_suspend_late(dev, false);
 707 }
 708
 709 static int i915_drm_resume(struct drm_device *dev)
 710 {
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712
 713         mutex_lock(&dev->struct_mutex);
 714         i915_gem_restore_gtt_mappings(dev);
 715         mutex_unlock(&dev->struct_mutex);
 716
 717         i915_restore_state(dev);
 718         intel_opregion_setup(dev);
 719
 720         intel_init_pch_refclk(dev);
 721         drm_mode_config_reset(dev);
 722
 723         /*
 724          * Interrupts have to be enabled before any batches are run. If not the
 725          * GPU will hang. i915_gem_init_hw() will initiate batches to
 726          * update/restore the context.
 727          *
 728          * Modeset enabling in intel_modeset_init_hw() also needs working
 729          * interrupts.
 730          */
 731         intel_runtime_pm_enable_interrupts(dev_priv);
 732
 733         mutex_lock(&dev->struct_mutex);
 734         if (i915_gem_init_hw(dev)) {
 735                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 736                         atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 737         }
 738         mutex_unlock(&dev->struct_mutex);
 739
 740         intel_modeset_init_hw(dev);
 741
 742         spin_lock_irq(&dev_priv->irq_lock);
 743         if (dev_priv->display.hpd_irq_setup)
 744                 dev_priv->display.hpd_irq_setup(dev);
 745         spin_unlock_irq(&dev_priv->irq_lock);
 746
 747         drm_modeset_lock_all(dev);
 748         intel_display_resume(dev);
 749         drm_modeset_unlock_all(dev);
 750
 751         intel_dp_mst_resume(dev);
 752
 753         /*
 754          * ... but also need to make sure that hotplug processing
 755          * doesn't cause havoc. Like in the driver load code we don't
 756          * bother with the tiny race here where we might loose hotplug
 757          * notifications.
 758          * */
 759         intel_hpd_init(dev_priv);
 760         /* Config may have changed between suspend and resume */
 761         drm_helper_hpd_irq_event(dev);
 762
 763         intel_opregion_init(dev);
 764
 765         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 766
 767         mutex_lock(&dev_priv->modeset_restore_lock);
 768         dev_priv->modeset_restore = MODESET_DONE;
 769         mutex_unlock(&dev_priv->modeset_restore_lock);
 770
 771         intel_opregion_notify_adapter(dev, PCI_D0);
 772
 773         drm_kms_helper_poll_enable(dev);
 774
 775         return 0;
 776 }
 777
 778 static int i915_drm_resume_early(struct drm_device *dev)
 779 {
 780         struct drm_i915_private *dev_priv = dev->dev_private;
 781         int ret = 0;
 782
 783         /*
 784          * We have a resume ordering issue with the snd-hda driver also
 785          * requiring our device to be power up. Due to the lack of a
 786          * parent/child relationship we currently solve this with an early
 787          * resume hook.
 788          *
 789          * FIXME: This should be solved with a special hdmi sink device or
 790          * similar so that power domains can be employed.
 791          */
 792         if (pci_enable_device(dev->pdev))
 793                 return -EIO;
 794
 795         pci_set_master(dev->pdev);
 796
 797         if (IS_VALLEYVIEW(dev_priv))
 798                 ret = vlv_resume_prepare(dev_priv, false);
 799         if (ret)
 800                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 801                           ret);
 802
 803         intel_uncore_early_sanitize(dev, true);
 804
 805         if (IS_BROXTON(dev))
 806                 ret = bxt_resume_prepare(dev_priv);
 807         else if (IS_SKYLAKE(dev_priv))
 808                 ret = skl_resume_prepare(dev_priv);
 809         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 810                 hsw_disable_pc8(dev_priv);
 811
 812         intel_uncore_sanitize(dev);
 813         intel_power_domains_init_hw(dev_priv);
 814
 815         return ret;
 816 }
 817
 818 int i915_resume_switcheroo(struct drm_device *dev)
 819 {
 820         int ret;
 821
 822         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 823                 return 0;
 824
 825         ret = i915_drm_resume_early(dev);
 826         if (ret)
 827                 return ret;
 828
 829         return i915_drm_resume(dev);
 830 }
 831
 832 /**
 833  * i915_reset - reset chip after a hang
 834  * @dev: drm device to reset
 835  *
 836  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 837  * reset or otherwise an error code.
 838  *
 839  * Procedure is fairly simple:
 840  *   - reset the chip using the reset reg
 841  *   - re-init context state
 842  *   - re-init hardware status page
 843  *   - re-init ring buffer
 844  *   - re-init interrupt state
 845  *   - re-init display
 846  */
 847 int i915_reset(struct drm_device *dev)
 848 {
 849         struct drm_i915_private *dev_priv = dev->dev_private;
 850         bool simulated;
 851         int ret;
 852
 853         intel_reset_gt_powersave(dev);
 854
 855         mutex_lock(&dev->struct_mutex);
 856
 857         i915_gem_reset(dev);
 858
 859         simulated = dev_priv->gpu_error.stop_rings != 0;
 860
 861         ret = intel_gpu_reset(dev);
 862
 863         /* Also reset the gpu hangman. */
 864         if (simulated) {
 865                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 866                 dev_priv->gpu_error.stop_rings = 0;
 867                 if (ret == -ENODEV) {
 868                         DRM_INFO("Reset not implemented, but ignoring "
 869                                  "error for simulated gpu hangs\n");
 870                         ret = 0;
 871                 }
 872         }
 873
 874         if (i915_stop_ring_allow_warn(dev_priv))
 875                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 876
 877         if (ret) {
 878                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 879                 mutex_unlock(&dev->struct_mutex);
 880                 return ret;
 881         }
 882
 883         intel_overlay_reset(dev_priv);
 884
 885         /* Ok, now get things going again... */
 886
 887         /*
 888          * Everything depends on having the GTT running, so we need to start
 889          * there.  Fortunately we don't need to do this unless we reset the
 890          * chip at a PCI level.
 891          *
 892          * Next we need to restore the context, but we don't use those
 893          * yet either...
 894          *
 895          * Ring buffer needs to be re-initialized in the KMS case, or if X
 896          * was running at the time of the reset (i.e. we weren't VT
 897          * switched away).
 898          */
 899
 900         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 901         dev_priv->gpu_error.reload_in_reset = true;
 902
 903         ret = i915_gem_init_hw(dev);
 904
 905         dev_priv->gpu_error.reload_in_reset = false;
 906
 907         mutex_unlock(&dev->struct_mutex);
 908         if (ret) {
 909                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 910                 return ret;
 911         }
 912
 913         /*
 914          * rps/rc6 re-init is necessary to restore state lost after the
 915          * reset and the re-install of gt irqs. Skip for ironlake per
 916          * previous concerns that it doesn't respond well to some forms
 917          * of re-init after reset.
 918          */
 919         if (INTEL_INFO(dev)->gen > 5)
 920                 intel_enable_gt_powersave(dev);
 921
 922         return 0;
 923 }
 924
 925 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 926 {
 927         struct intel_device_info *intel_info =
 928                 (struct intel_device_info *) ent->driver_data;
 929
 930         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 931                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 932                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 933                 return -ENODEV;
 934         }
 935
 936         /* Only bind to function 0 of the device. Early generations
 937          * used function 1 as a placeholder for multi-head. This causes
 938          * us confusion instead, especially on the systems where both
 939          * functions have the same PCI-ID!
 940          */
 941         if (PCI_FUNC(pdev->devfn))
 942                 return -ENODEV;
 943
 944         return drm_get_pci_dev(pdev, ent, &driver);
 945 }
 946
 947 static void
 948 i915_pci_remove(struct pci_dev *pdev)
 949 {
 950         struct drm_device *dev = pci_get_drvdata(pdev);
 951
 952         drm_put_dev(dev);
 953 }
 954
 955 static int i915_pm_suspend(struct device *dev)
 956 {
 957         struct pci_dev *pdev = to_pci_dev(dev);
 958         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 959
 960         if (!drm_dev || !drm_dev->dev_private) {
 961                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 962                 return -ENODEV;
 963         }
 964
 965         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 966                 return 0;
 967
 968         return i915_drm_suspend(drm_dev);
 969 }
 970
 971 static int i915_pm_suspend_late(struct device *dev)
 972 {
 973         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 974
 975         /*
 976          * We have a suspend ordering issue with the snd-hda driver also
 977          * requiring our device to be power up. Due to the lack of a
 978          * parent/child relationship we currently solve this with an late
 979          * suspend hook.
 980          *
 981          * FIXME: This should be solved with a special hdmi sink device or
 982          * similar so that power domains can be employed.
 983          */
 984         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 985                 return 0;
 986
 987         return i915_drm_suspend_late(drm_dev, false);
 988 }
 989
 990 static int i915_pm_poweroff_late(struct device *dev)
 991 {
 992         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 993
 994         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 995                 return 0;
 996
 997         return i915_drm_suspend_late(drm_dev, true);
 998 }
 999
1000 static int i915_pm_resume_early(struct device *dev)
1001 {
1002         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1003
1004         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1005                 return 0;
1006
1007         return i915_drm_resume_early(drm_dev);
1008 }
1009
1010 static int i915_pm_resume(struct device *dev)
1011 {
1012         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1013
1014         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1015                 return 0;
1016
1017         return i915_drm_resume(drm_dev);
1018 }
1019
1020 static int skl_suspend_complete(struct drm_i915_private *dev_priv)
1021 {
1022         /* Enabling DC6 is not a hard requirement to enter runtime D3 */
1023
1024         /*
1025          * This is to ensure that CSR isn't identified as loaded before
1026          * CSR-loading program is called during runtime-resume.
1027          */
1028         intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED);
1029
1030         skl_uninit_cdclk(dev_priv);
1031
1032         return 0;
1033 }
1034
1035 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1036 {
1037         hsw_enable_pc8(dev_priv);
1038
1039         return 0;
1040 }
1041
1042 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1043 {
1044         struct drm_device *dev = dev_priv->dev;
1045
1046         /* TODO: when DC5 support is added disable DC5 here. */
1047
1048         broxton_ddi_phy_uninit(dev);
1049         broxton_uninit_cdclk(dev);
1050         bxt_enable_dc9(dev_priv);
1051
1052         return 0;
1053 }
1054
1055 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1056 {
1057         struct drm_device *dev = dev_priv->dev;
1058
1059         /* TODO: when CSR FW support is added make sure the FW is loaded */
1060
1061         bxt_disable_dc9(dev_priv);
1062
1063         /*
1064          * TODO: when DC5 support is added enable DC5 here if the CSR FW
1065          * is available.
1066          */
1067         broxton_init_cdclk(dev);
1068         broxton_ddi_phy_init(dev);
1069         intel_prepare_ddi(dev);
1070
1071         return 0;
1072 }
1073
1074 static int skl_resume_prepare(struct drm_i915_private *dev_priv)
1075 {
1076         struct drm_device *dev = dev_priv->dev;
1077
1078         skl_init_cdclk(dev_priv);
1079         intel_csr_load_program(dev);
1080
1081         return 0;
1082 }
1083
1084 /*
1085  * Save all Gunit registers that may be lost after a D3 and a subsequent
1086  * S0i[R123] transition. The list of registers needing a save/restore is
1087  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1088  * registers in the following way:
1089  * - Driver: saved/restored by the driver
1090  * - Punit : saved/restored by the Punit firmware
1091  * - No, w/o marking: no need to save/restore, since the register is R/O or
1092  *                    used internally by the HW in a way that doesn't depend
1093  *                    keeping the content across a suspend/resume.
1094  * - Debug : used for debugging
1095  *
1096  * We save/restore all registers marked with 'Driver', with the following
1097  * exceptions:
1098  * - Registers out of use, including also registers marked with 'Debug'.
1099  *   These have no effect on the driver's operation, so we don't save/restore
1100  *   them to reduce the overhead.
1101  * - Registers that are fully setup by an initialization function called from
1102  *   the resume path. For example many clock gating and RPS/RC6 registers.
1103  * - Registers that provide the right functionality with their reset defaults.
1104  *
1105  * TODO: Except for registers that based on the above 3 criteria can be safely
1106  * ignored, we save/restore all others, practically treating the HW context as
1107  * a black-box for the driver. Further investigation is needed to reduce the
1108  * saved/restored registers even further, by following the same 3 criteria.
1109  */
1110 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1111 {
1112         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1113         int i;
1114
1115         /* GAM 0x4000-0x4770 */
1116         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1117         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1118         s->arb_mode             = I915_READ(ARB_MODE);
1119         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1120         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1121
1122         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1123                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1124
1125         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1126         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1127
1128         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1129         s->ecochk               = I915_READ(GAM_ECOCHK);
1130         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1131         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1132
1133         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1134
1135         /* MBC 0x9024-0x91D0, 0x8500 */
1136         s->g3dctl               = I915_READ(VLV_G3DCTL);
1137         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1138         s->mbctl                = I915_READ(GEN6_MBCTL);
1139
1140         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1141         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1142         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1143         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1144         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1145         s->rstctl               = I915_READ(GEN6_RSTCTL);
1146         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1147
1148         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1149         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1150         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1151         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1152         s->ecobus               = I915_READ(ECOBUS);
1153         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1154         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1155         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1156         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1157         s->rcedata              = I915_READ(VLV_RCEDATA);
1158         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1159
1160         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1161         s->gt_imr               = I915_READ(GTIMR);
1162         s->gt_ier               = I915_READ(GTIER);
1163         s->pm_imr               = I915_READ(GEN6_PMIMR);
1164         s->pm_ier               = I915_READ(GEN6_PMIER);
1165
1166         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1167                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1168
1169         /* GT SA CZ domain, 0x100000-0x138124 */
1170         s->tilectl              = I915_READ(TILECTL);
1171         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1172         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1173         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1174         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1175
1176         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1177         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1178         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1179         s->pcbr                 = I915_READ(VLV_PCBR);
1180         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1181
1182         /*
1183          * Not saving any of:
1184          * DFT,         0x9800-0x9EC0
1185          * SARB,        0xB000-0xB1FC
1186          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1187          * PCI CFG
1188          */
1189 }
1190
1191 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1192 {
1193         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1194         u32 val;
1195         int i;
1196
1197         /* GAM 0x4000-0x4770 */
1198         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1199         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1200         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1201         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1202         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1203
1204         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1205                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1206
1207         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1208         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1209
1210         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1211         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1212         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1213         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1214
1215         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1216
1217         /* MBC 0x9024-0x91D0, 0x8500 */
1218         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1219         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1220         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1221
1222         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1223         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1224         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1225         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1226         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1227         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1228         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1229
1230         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1231         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1232         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1233         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1234         I915_WRITE(ECOBUS,              s->ecobus);
1235         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1236         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1237         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1238         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1239         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1240         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1241
1242         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1243         I915_WRITE(GTIMR,               s->gt_imr);
1244         I915_WRITE(GTIER,               s->gt_ier);
1245         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1246         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1247
1248         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1249                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1250
1251         /* GT SA CZ domain, 0x100000-0x138124 */
1252         I915_WRITE(TILECTL,                     s->tilectl);
1253         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1254         /*
1255          * Preserve the GT allow wake and GFX force clock bit, they are not
1256          * be restored, as they are used to control the s0ix suspend/resume
1257          * sequence by the caller.
1258          */
1259         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1260         val &= VLV_GTLC_ALLOWWAKEREQ;
1261         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1262         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1263
1264         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1265         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1266         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1267         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1268
1269         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1270
1271         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1272         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1273         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1274         I915_WRITE(VLV_PCBR,                    s->pcbr);
1275         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1276 }
1277
1278 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1279 {
1280         u32 val;
1281         int err;
1282
1283 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1284
1285         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1286         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1287         if (force_on)
1288                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1289         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1290
1291         if (!force_on)
1292                 return 0;
1293
1294         err = wait_for(COND, 20);
1295         if (err)
1296                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1297                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1298
1299         return err;
1300 #undef COND
1301 }
1302
1303 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1304 {
1305         u32 val;
1306         int err = 0;
1307
1308         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1309         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1310         if (allow)
1311                 val |= VLV_GTLC_ALLOWWAKEREQ;
1312         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1313         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1314
1315 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1316               allow)
1317         err = wait_for(COND, 1);
1318         if (err)
1319                 DRM_ERROR("timeout disabling GT waking\n");
1320         return err;
1321 #undef COND
1322 }
1323
1324 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1325                                  bool wait_for_on)
1326 {
1327         u32 mask;
1328         u32 val;
1329         int err;
1330
1331         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1332         val = wait_for_on ? mask : 0;
1333 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1334         if (COND)
1335                 return 0;
1336
1337         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1338                         wait_for_on ? "on" : "off",
1339                         I915_READ(VLV_GTLC_PW_STATUS));
1340
1341         /*
1342          * RC6 transitioning can be delayed up to 2 msec (see
1343          * valleyview_enable_rps), use 3 msec for safety.
1344          */
1345         err = wait_for(COND, 3);
1346         if (err)
1347                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1348                           wait_for_on ? "on" : "off");
1349
1350         return err;
1351 #undef COND
1352 }
1353
1354 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1355 {
1356         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1357                 return;
1358
1359         DRM_ERROR("GT register access while GT waking disabled\n");
1360         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1361 }
1362
1363 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1364 {
1365         u32 mask;
1366         int err;
1367
1368         /*
1369          * Bspec defines the following GT well on flags as debug only, so
1370          * don't treat them as hard failures.
1371          */
1372         (void)vlv_wait_for_gt_wells(dev_priv, false);
1373
1374         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1375         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1376
1377         vlv_check_no_gt_access(dev_priv);
1378
1379         err = vlv_force_gfx_clock(dev_priv, true);
1380         if (err)
1381                 goto err1;
1382
1383         err = vlv_allow_gt_wake(dev_priv, false);
1384         if (err)
1385                 goto err2;
1386
1387         if (!IS_CHERRYVIEW(dev_priv->dev))
1388                 vlv_save_gunit_s0ix_state(dev_priv);
1389
1390         err = vlv_force_gfx_clock(dev_priv, false);
1391         if (err)
1392                 goto err2;
1393
1394         return 0;
1395
1396 err2:
1397         /* For safety always re-enable waking and disable gfx clock forcing */
1398         vlv_allow_gt_wake(dev_priv, true);
1399 err1:
1400         vlv_force_gfx_clock(dev_priv, false);
1401
1402         return err;
1403 }
1404
1405 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1406                                 bool rpm_resume)
1407 {
1408         struct drm_device *dev = dev_priv->dev;
1409         int err;
1410         int ret;
1411
1412         /*
1413          * If any of the steps fail just try to continue, that's the best we
1414          * can do at this point. Return the first error code (which will also
1415          * leave RPM permanently disabled).
1416          */
1417         ret = vlv_force_gfx_clock(dev_priv, true);
1418
1419         if (!IS_CHERRYVIEW(dev_priv->dev))
1420                 vlv_restore_gunit_s0ix_state(dev_priv);
1421
1422         err = vlv_allow_gt_wake(dev_priv, true);
1423         if (!ret)
1424                 ret = err;
1425
1426         err = vlv_force_gfx_clock(dev_priv, false);
1427         if (!ret)
1428                 ret = err;
1429
1430         vlv_check_no_gt_access(dev_priv);
1431
1432         if (rpm_resume) {
1433                 intel_init_clock_gating(dev);
1434                 i915_gem_restore_fences(dev);
1435         }
1436
1437         return ret;
1438 }
1439
1440 static int intel_runtime_suspend(struct device *device)
1441 {
1442         struct pci_dev *pdev = to_pci_dev(device);
1443         struct drm_device *dev = pci_get_drvdata(pdev);
1444         struct drm_i915_private *dev_priv = dev->dev_private;
1445         int ret;
1446
1447         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1448                 return -ENODEV;
1449
1450         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1451                 return -ENODEV;
1452
1453         DRM_DEBUG_KMS("Suspending device\n");
1454
1455         /*
1456          * We could deadlock here in case another thread holding struct_mutex
1457          * calls RPM suspend concurrently, since the RPM suspend will wait
1458          * first for this RPM suspend to finish. In this case the concurrent
1459          * RPM resume will be followed by its RPM suspend counterpart. Still
1460          * for consistency return -EAGAIN, which will reschedule this suspend.
1461          */
1462         if (!mutex_trylock(&dev->struct_mutex)) {
1463                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1464                 /*
1465                  * Bump the expiration timestamp, otherwise the suspend won't
1466                  * be rescheduled.
1467                  */
1468                 pm_runtime_mark_last_busy(device);
1469
1470                 return -EAGAIN;
1471         }
1472         /*
1473          * We are safe here against re-faults, since the fault handler takes
1474          * an RPM reference.
1475          */
1476         i915_gem_release_all_mmaps(dev_priv);
1477         mutex_unlock(&dev->struct_mutex);
1478
1479         intel_suspend_gt_powersave(dev);
1480         intel_runtime_pm_disable_interrupts(dev_priv);
1481
1482         ret = intel_suspend_complete(dev_priv);
1483         if (ret) {
1484                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1485                 intel_runtime_pm_enable_interrupts(dev_priv);
1486
1487                 return ret;
1488         }
1489
1490         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1491         intel_uncore_forcewake_reset(dev, false);
1492         dev_priv->pm.suspended = true;
1493
1494         /*
1495          * FIXME: We really should find a document that references the arguments
1496          * used below!
1497          */
1498         if (IS_BROADWELL(dev)) {
1499                 /*
1500                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1501                  * being detected, and the call we do at intel_runtime_resume()
1502                  * won't be able to restore them. Since PCI_D3hot matches the
1503                  * actual specification and appears to be working, use it.
1504                  */
1505                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1506         } else {
1507                 /*
1508                  * current versions of firmware which depend on this opregion
1509                  * notification have repurposed the D1 definition to mean
1510                  * "runtime suspended" vs. what you would normally expect (D3)
1511                  * to distinguish it from notifications that might be sent via
1512                  * the suspend path.
1513                  */
1514                 intel_opregion_notify_adapter(dev, PCI_D1);
1515         }
1516
1517         assert_forcewakes_inactive(dev_priv);
1518
1519         DRM_DEBUG_KMS("Device suspended\n");
1520         return 0;
1521 }
1522
1523 static int intel_runtime_resume(struct device *device)
1524 {
1525         struct pci_dev *pdev = to_pci_dev(device);
1526         struct drm_device *dev = pci_get_drvdata(pdev);
1527         struct drm_i915_private *dev_priv = dev->dev_private;
1528         int ret = 0;
1529
1530         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1531                 return -ENODEV;
1532
1533         DRM_DEBUG_KMS("Resuming device\n");
1534
1535         intel_opregion_notify_adapter(dev, PCI_D0);
1536         dev_priv->pm.suspended = false;
1537
1538         if (IS_GEN6(dev_priv))
1539                 intel_init_pch_refclk(dev);
1540
1541         if (IS_BROXTON(dev))
1542                 ret = bxt_resume_prepare(dev_priv);
1543         else if (IS_SKYLAKE(dev))
1544                 ret = skl_resume_prepare(dev_priv);
1545         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1546                 hsw_disable_pc8(dev_priv);
1547         else if (IS_VALLEYVIEW(dev_priv))
1548                 ret = vlv_resume_prepare(dev_priv, true);
1549
1550         /*
1551          * No point of rolling back things in case of an error, as the best
1552          * we can do is to hope that things will still work (and disable RPM).
1553          */
1554         i915_gem_init_swizzling(dev);
1555         gen6_update_ring_freq(dev);
1556
1557         intel_runtime_pm_enable_interrupts(dev_priv);
1558
1559         /*
1560          * On VLV/CHV display interrupts are part of the display
1561          * power well, so hpd is reinitialized from there. For
1562          * everyone else do it here.
1563          */
1564         if (!IS_VALLEYVIEW(dev_priv))
1565                 intel_hpd_init(dev_priv);
1566
1567         intel_enable_gt_powersave(dev);
1568
1569         if (ret)
1570                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1571         else
1572                 DRM_DEBUG_KMS("Device resumed\n");
1573
1574         return ret;
1575 }
1576
1577 /*
1578  * This function implements common functionality of runtime and system
1579  * suspend sequence.
1580  */
1581 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1582 {
1583         int ret;
1584
1585         if (IS_BROXTON(dev_priv))
1586                 ret = bxt_suspend_complete(dev_priv);
1587         else if (IS_SKYLAKE(dev_priv))
1588                 ret = skl_suspend_complete(dev_priv);
1589         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1590                 ret = hsw_suspend_complete(dev_priv);
1591         else if (IS_VALLEYVIEW(dev_priv))
1592                 ret = vlv_suspend_complete(dev_priv);
1593         else
1594                 ret = 0;
1595
1596         return ret;
1597 }
1598
1599 static const struct dev_pm_ops i915_pm_ops = {
1600         /*
1601          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1602          * PMSG_RESUME]
1603          */
1604         .suspend = i915_pm_suspend,
1605         .suspend_late = i915_pm_suspend_late,
1606         .resume_early = i915_pm_resume_early,
1607         .resume = i915_pm_resume,
1608
1609         /*
1610          * S4 event handlers
1611          * @freeze, @freeze_late    : called (1) before creating the
1612          *                            hibernation image [PMSG_FREEZE] and
1613          *                            (2) after rebooting, before restoring
1614          *                            the image [PMSG_QUIESCE]
1615          * @thaw, @thaw_early       : called (1) after creating the hibernation
1616          *                            image, before writing it [PMSG_THAW]
1617          *                            and (2) after failing to create or
1618          *                            restore the image [PMSG_RECOVER]
1619          * @poweroff, @poweroff_late: called after writing the hibernation
1620          *                            image, before rebooting [PMSG_HIBERNATE]
1621          * @restore, @restore_early : called after rebooting and restoring the
1622          *                            hibernation image [PMSG_RESTORE]
1623          */
1624         .freeze = i915_pm_suspend,
1625         .freeze_late = i915_pm_suspend_late,
1626         .thaw_early = i915_pm_resume_early,
1627         .thaw = i915_pm_resume,
1628         .poweroff = i915_pm_suspend,
1629         .poweroff_late = i915_pm_poweroff_late,
1630         .restore_early = i915_pm_resume_early,
1631         .restore = i915_pm_resume,
1632
1633         /* S0ix (via runtime suspend) event handlers */
1634         .runtime_suspend = intel_runtime_suspend,
1635         .runtime_resume = intel_runtime_resume,
1636 };
1637
1638 static const struct vm_operations_struct i915_gem_vm_ops = {
1639         .fault = i915_gem_fault,
1640         .open = drm_gem_vm_open,
1641         .close = drm_gem_vm_close,
1642 };
1643
1644 static const struct file_operations i915_driver_fops = {
1645         .owner = THIS_MODULE,
1646         .open = drm_open,
1647         .release = drm_release,
1648         .unlocked_ioctl = drm_ioctl,
1649         .mmap = drm_gem_mmap,
1650         .poll = drm_poll,
1651         .read = drm_read,
1652 #ifdef CONFIG_COMPAT
1653         .compat_ioctl = i915_compat_ioctl,
1654 #endif
1655         .llseek = noop_llseek,
1656 };
1657
1658 static struct drm_driver driver = {
1659         /* Don't use MTRRs here; the Xserver or userspace app should
1660          * deal with them for Intel hardware.
1661          */
1662         .driver_features =
1663             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1664             DRIVER_RENDER | DRIVER_MODESET,
1665         .load = i915_driver_load,
1666         .unload = i915_driver_unload,
1667         .open = i915_driver_open,
1668         .lastclose = i915_driver_lastclose,
1669         .preclose = i915_driver_preclose,
1670         .postclose = i915_driver_postclose,
1671         .set_busid = drm_pci_set_busid,
1672
1673 #if defined(CONFIG_DEBUG_FS)
1674         .debugfs_init = i915_debugfs_init,
1675         .debugfs_cleanup = i915_debugfs_cleanup,
1676 #endif
1677         .gem_free_object = i915_gem_free_object,
1678         .gem_vm_ops = &i915_gem_vm_ops,
1679
1680         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1681         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1682         .gem_prime_export = i915_gem_prime_export,
1683         .gem_prime_import = i915_gem_prime_import,
1684
1685         .dumb_create = i915_gem_dumb_create,
1686         .dumb_map_offset = i915_gem_mmap_gtt,
1687         .dumb_destroy = drm_gem_dumb_destroy,
1688         .ioctls = i915_ioctls,
1689         .fops = &i915_driver_fops,
1690         .name = DRIVER_NAME,
1691         .desc = DRIVER_DESC,
1692         .date = DRIVER_DATE,
1693         .major = DRIVER_MAJOR,
1694         .minor = DRIVER_MINOR,
1695         .patchlevel = DRIVER_PATCHLEVEL,
1696 };
1697
1698 static struct pci_driver i915_pci_driver = {
1699         .name = DRIVER_NAME,
1700         .id_table = pciidlist,
1701         .probe = i915_pci_probe,
1702         .remove = i915_pci_remove,
1703         .driver.pm = &i915_pm_ops,
1704 };
1705
1706 static int __init i915_init(void)
1707 {
1708         driver.num_ioctls = i915_max_ioctl;
1709
1710         /*
1711          * Enable KMS by default, unless explicitly overriden by
1712          * either the i915.modeset prarameter or by the
1713          * vga_text_mode_force boot option.
1714          */
1715
1716         if (i915.modeset == 0)
1717                 driver.driver_features &= ~DRIVER_MODESET;
1718
1719 #ifdef CONFIG_VGA_CONSOLE
1720         if (vgacon_text_force() && i915.modeset == -1)
1721                 driver.driver_features &= ~DRIVER_MODESET;
1722 #endif
1723
1724         if (!(driver.driver_features & DRIVER_MODESET)) {
1725                 /* Silently fail loading to not upset userspace. */
1726                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1727                 return 0;
1728         }
1729
1730         if (i915.nuclear_pageflip)
1731                 driver.driver_features |= DRIVER_ATOMIC;
1732
1733         return drm_pci_init(&driver, &i915_pci_driver);
1734 }
1735
1736 static void __exit i915_exit(void)
1737 {
1738         if (!(driver.driver_features & DRIVER_MODESET))
1739                 return; /* Never loaded a driver. */
1740
1741         drm_pci_exit(&driver, &i915_pci_driver);
1742 }
1743
1744 module_init(i915_init);
1745 module_exit(i915_exit);
1746
1747 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1748 MODULE_AUTHOR("Intel Corporation");
1749
1750 MODULE_DESCRIPTION(DRIVER_DESC);
1751 MODULE_LICENSE("GPL and additional rights");