2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
46 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
48 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
50 struct drm_i915_gem_object *obj);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
52 struct drm_i915_fence_reg *fence,
55 static bool cpu_cache_is_coherent(struct drm_device *dev,
56 enum i915_cache_level level)
58 return HAS_LLC(dev) || level != I915_CACHE_NONE;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
63 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
66 return obj->pin_display;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
72 i915_gem_release_mmap(obj);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj->fence_dirty = false;
78 obj->fence_reg = I915_FENCE_REG_NONE;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
85 spin_lock(&dev_priv->mm.object_stat_lock);
86 dev_priv->mm.object_count++;
87 dev_priv->mm.object_memory += size;
88 spin_unlock(&dev_priv->mm.object_stat_lock);
91 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
94 spin_lock(&dev_priv->mm.object_stat_lock);
95 dev_priv->mm.object_count--;
96 dev_priv->mm.object_memory -= size;
97 spin_unlock(&dev_priv->mm.object_stat_lock);
101 i915_gem_wait_for_error(struct i915_gpu_error *error)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret = wait_event_interruptible_timeout(error->reset_queue,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret < 0) {
129 int i915_mutex_lock_interruptible(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
134 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
138 ret = mutex_lock_interruptible(&dev->struct_mutex);
142 WARN_ON(i915_verify_lists(dev));
147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 struct drm_i915_gem_get_aperture *args = data;
152 struct drm_i915_gem_object *obj;
156 mutex_lock(&dev->struct_mutex);
157 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
158 if (i915_gem_obj_is_pinned(obj))
159 pinned += i915_gem_obj_ggtt_size(obj);
160 mutex_unlock(&dev->struct_mutex);
162 args->aper_size = dev_priv->gtt.base.total;
163 args->aper_available_size = args->aper_size - pinned;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
171 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
172 char *vaddr = obj->phys_handle->vaddr;
174 struct scatterlist *sg;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
180 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
184 page = shmem_read_mapping_page(mapping, i);
186 return PTR_ERR(page);
188 src = kmap_atomic(page);
189 memcpy(vaddr, src, PAGE_SIZE);
190 drm_clflush_virt_range(vaddr, PAGE_SIZE);
193 page_cache_release(page);
197 i915_gem_chipset_flush(obj->base.dev);
199 st = kmalloc(sizeof(*st), GFP_KERNEL);
203 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
210 sg->length = obj->base.size;
212 sg_dma_address(sg) = obj->phys_handle->busaddr;
213 sg_dma_len(sg) = obj->base.size;
216 obj->has_dma_mapping = true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
225 BUG_ON(obj->madv == __I915_MADV_PURGED);
227 ret = i915_gem_object_set_to_cpu_domain(obj, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret != -EIO);
233 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
236 if (obj->madv == I915_MADV_DONTNEED)
240 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
241 char *vaddr = obj->phys_handle->vaddr;
244 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
248 page = shmem_read_mapping_page(mapping, i);
252 dst = kmap_atomic(page);
253 drm_clflush_virt_range(vaddr, PAGE_SIZE);
254 memcpy(dst, vaddr, PAGE_SIZE);
257 set_page_dirty(page);
258 if (obj->madv == I915_MADV_WILLNEED)
259 mark_page_accessed(page);
260 page_cache_release(page);
266 sg_free_table(obj->pages);
269 obj->has_dma_mapping = false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
275 drm_pci_free(obj->base.dev, obj->phys_handle);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
279 .get_pages = i915_gem_object_get_pages_phys,
280 .put_pages = i915_gem_object_put_pages_phys,
281 .release = i915_gem_object_release_phys,
285 drop_pages(struct drm_i915_gem_object *obj)
287 struct i915_vma *vma, *next;
290 drm_gem_object_reference(&obj->base);
291 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
292 if (i915_vma_unbind(vma))
295 ret = i915_gem_object_put_pages(obj);
296 drm_gem_object_unreference(&obj->base);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
305 drm_dma_handle_t *phys;
308 if (obj->phys_handle) {
309 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
315 if (obj->madv != I915_MADV_WILLNEED)
318 if (obj->base.filp == NULL)
321 ret = drop_pages(obj);
325 /* create a new object */
326 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
330 obj->phys_handle = phys;
331 obj->ops = &i915_gem_phys_ops;
333 return i915_gem_object_get_pages(obj);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
338 struct drm_i915_gem_pwrite *args,
339 struct drm_file *file_priv)
341 struct drm_device *dev = obj->base.dev;
342 void *vaddr = obj->phys_handle->vaddr + args->offset;
343 char __user *user_data = to_user_ptr(args->data_ptr);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret = i915_gem_object_wait_rendering(obj, false);
353 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
354 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
355 unsigned long unwritten;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev->struct_mutex);
362 unwritten = copy_from_user(vaddr, user_data, args->size);
363 mutex_lock(&dev->struct_mutex);
370 drm_clflush_virt_range(vaddr, args->size);
371 i915_gem_chipset_flush(dev);
374 intel_fb_obj_flush(obj, false);
378 void *i915_gem_object_alloc(struct drm_device *dev)
380 struct drm_i915_private *dev_priv = dev->dev_private;
381 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
386 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
387 kmem_cache_free(dev_priv->objects, obj);
391 i915_gem_create(struct drm_file *file,
392 struct drm_device *dev,
396 struct drm_i915_gem_object *obj;
400 size = roundup(size, PAGE_SIZE);
404 /* Allocate the new object */
405 obj = i915_gem_alloc_object(dev, size);
409 ret = drm_gem_handle_create(file, &obj->base, &handle);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj->base);
420 i915_gem_dumb_create(struct drm_file *file,
421 struct drm_device *dev,
422 struct drm_mode_create_dumb *args)
424 /* have to work out size/pitch and return them */
425 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
426 args->size = args->pitch * args->height;
427 return i915_gem_create(file, dev,
428 args->size, &args->handle);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device *dev, void *data,
436 struct drm_file *file)
438 struct drm_i915_gem_create *args = data;
440 return i915_gem_create(file, dev,
441 args->size, &args->handle);
445 __copy_to_user_swizzled(char __user *cpu_vaddr,
446 const char *gpu_vaddr, int gpu_offset,
449 int ret, cpu_offset = 0;
452 int cacheline_end = ALIGN(gpu_offset + 1, 64);
453 int this_length = min(cacheline_end - gpu_offset, length);
454 int swizzled_gpu_offset = gpu_offset ^ 64;
456 ret = __copy_to_user(cpu_vaddr + cpu_offset,
457 gpu_vaddr + swizzled_gpu_offset,
462 cpu_offset += this_length;
463 gpu_offset += this_length;
464 length -= this_length;
471 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
472 const char __user *cpu_vaddr,
475 int ret, cpu_offset = 0;
478 int cacheline_end = ALIGN(gpu_offset + 1, 64);
479 int this_length = min(cacheline_end - gpu_offset, length);
480 int swizzled_gpu_offset = gpu_offset ^ 64;
482 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
483 cpu_vaddr + cpu_offset,
488 cpu_offset += this_length;
489 gpu_offset += this_length;
490 length -= this_length;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
511 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
518 ret = i915_gem_object_wait_rendering(obj, true);
523 ret = i915_gem_object_get_pages(obj);
527 i915_gem_object_pin_pages(obj);
532 /* Per-page copy function for the shmem pread fastpath.
533 * Flushes invalid cachelines before reading the target if
534 * needs_clflush is set. */
536 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
537 char __user *user_data,
538 bool page_do_bit17_swizzling, bool needs_clflush)
543 if (unlikely(page_do_bit17_swizzling))
546 vaddr = kmap_atomic(page);
548 drm_clflush_virt_range(vaddr + shmem_page_offset,
550 ret = __copy_to_user_inatomic(user_data,
551 vaddr + shmem_page_offset,
553 kunmap_atomic(vaddr);
555 return ret ? -EFAULT : 0;
559 shmem_clflush_swizzled_range(char *addr, unsigned long length,
562 if (unlikely(swizzled)) {
563 unsigned long start = (unsigned long) addr;
564 unsigned long end = (unsigned long) addr + length;
566 /* For swizzling simply ensure that we always flush both
567 * channels. Lame, but simple and it works. Swizzled
568 * pwrite/pread is far from a hotpath - current userspace
569 * doesn't use it at all. */
570 start = round_down(start, 128);
571 end = round_up(end, 128);
573 drm_clflush_virt_range((void *)start, end - start);
575 drm_clflush_virt_range(addr, length);
580 /* Only difference to the fast-path function is that this can handle bit17
581 * and uses non-atomic copy and kmap functions. */
583 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
584 char __user *user_data,
585 bool page_do_bit17_swizzling, bool needs_clflush)
592 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
594 page_do_bit17_swizzling);
596 if (page_do_bit17_swizzling)
597 ret = __copy_to_user_swizzled(user_data,
598 vaddr, shmem_page_offset,
601 ret = __copy_to_user(user_data,
602 vaddr + shmem_page_offset,
606 return ret ? - EFAULT : 0;
610 i915_gem_shmem_pread(struct drm_device *dev,
611 struct drm_i915_gem_object *obj,
612 struct drm_i915_gem_pread *args,
613 struct drm_file *file)
615 char __user *user_data;
618 int shmem_page_offset, page_length, ret = 0;
619 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
621 int needs_clflush = 0;
622 struct sg_page_iter sg_iter;
624 user_data = to_user_ptr(args->data_ptr);
627 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
629 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
633 offset = args->offset;
635 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
636 offset >> PAGE_SHIFT) {
637 struct page *page = sg_page_iter_page(&sg_iter);
642 /* Operation in this page
644 * shmem_page_offset = offset within page in shmem file
645 * page_length = bytes to copy for this page
647 shmem_page_offset = offset_in_page(offset);
648 page_length = remain;
649 if ((shmem_page_offset + page_length) > PAGE_SIZE)
650 page_length = PAGE_SIZE - shmem_page_offset;
652 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
653 (page_to_phys(page) & (1 << 17)) != 0;
655 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
656 user_data, page_do_bit17_swizzling,
661 mutex_unlock(&dev->struct_mutex);
663 if (likely(!i915.prefault_disable) && !prefaulted) {
664 ret = fault_in_multipages_writeable(user_data, remain);
665 /* Userspace is tricking us, but we've already clobbered
666 * its pages with the prefault and promised to write the
667 * data up to the first fault. Hence ignore any errors
668 * and just continue. */
673 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
674 user_data, page_do_bit17_swizzling,
677 mutex_lock(&dev->struct_mutex);
683 remain -= page_length;
684 user_data += page_length;
685 offset += page_length;
689 i915_gem_object_unpin_pages(obj);
695 * Reads data from the object referenced by handle.
697 * On error, the contents of *data are undefined.
700 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
701 struct drm_file *file)
703 struct drm_i915_gem_pread *args = data;
704 struct drm_i915_gem_object *obj;
710 if (!access_ok(VERIFY_WRITE,
711 to_user_ptr(args->data_ptr),
715 ret = i915_mutex_lock_interruptible(dev);
719 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
720 if (&obj->base == NULL) {
725 /* Bounds check source. */
726 if (args->offset > obj->base.size ||
727 args->size > obj->base.size - args->offset) {
732 /* prime objects have no backing filp to GEM pread/pwrite
735 if (!obj->base.filp) {
740 trace_i915_gem_object_pread(obj, args->offset, args->size);
742 ret = i915_gem_shmem_pread(dev, obj, args, file);
745 drm_gem_object_unreference(&obj->base);
747 mutex_unlock(&dev->struct_mutex);
751 /* This is the fast write path which cannot handle
752 * page faults in the source data
756 fast_user_write(struct io_mapping *mapping,
757 loff_t page_base, int page_offset,
758 char __user *user_data,
761 void __iomem *vaddr_atomic;
763 unsigned long unwritten;
765 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
766 /* We can use the cpu mem copy function because this is X86. */
767 vaddr = (void __force*)vaddr_atomic + page_offset;
768 unwritten = __copy_from_user_inatomic_nocache(vaddr,
770 io_mapping_unmap_atomic(vaddr_atomic);
775 * This is the fast pwrite path, where we copy the data directly from the
776 * user into the GTT, uncached.
779 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
780 struct drm_i915_gem_object *obj,
781 struct drm_i915_gem_pwrite *args,
782 struct drm_file *file)
784 struct drm_i915_private *dev_priv = dev->dev_private;
786 loff_t offset, page_base;
787 char __user *user_data;
788 int page_offset, page_length, ret;
790 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
794 ret = i915_gem_object_set_to_gtt_domain(obj, true);
798 ret = i915_gem_object_put_fence(obj);
802 user_data = to_user_ptr(args->data_ptr);
805 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
807 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
810 /* Operation in this page
812 * page_base = page offset within aperture
813 * page_offset = offset within page
814 * page_length = bytes to copy for this page
816 page_base = offset & PAGE_MASK;
817 page_offset = offset_in_page(offset);
818 page_length = remain;
819 if ((page_offset + remain) > PAGE_SIZE)
820 page_length = PAGE_SIZE - page_offset;
822 /* If we get a fault while copying data, then (presumably) our
823 * source page isn't available. Return the error and we'll
824 * retry in the slow path.
826 if (fast_user_write(dev_priv->gtt.mappable, page_base,
827 page_offset, user_data, page_length)) {
832 remain -= page_length;
833 user_data += page_length;
834 offset += page_length;
838 intel_fb_obj_flush(obj, false);
840 i915_gem_object_ggtt_unpin(obj);
845 /* Per-page copy function for the shmem pwrite fastpath.
846 * Flushes invalid cachelines before writing to the target if
847 * needs_clflush_before is set and flushes out any written cachelines after
848 * writing if needs_clflush is set. */
850 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
851 char __user *user_data,
852 bool page_do_bit17_swizzling,
853 bool needs_clflush_before,
854 bool needs_clflush_after)
859 if (unlikely(page_do_bit17_swizzling))
862 vaddr = kmap_atomic(page);
863 if (needs_clflush_before)
864 drm_clflush_virt_range(vaddr + shmem_page_offset,
866 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
867 user_data, page_length);
868 if (needs_clflush_after)
869 drm_clflush_virt_range(vaddr + shmem_page_offset,
871 kunmap_atomic(vaddr);
873 return ret ? -EFAULT : 0;
876 /* Only difference to the fast-path function is that this can handle bit17
877 * and uses non-atomic copy and kmap functions. */
879 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
880 char __user *user_data,
881 bool page_do_bit17_swizzling,
882 bool needs_clflush_before,
883 bool needs_clflush_after)
889 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
890 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
892 page_do_bit17_swizzling);
893 if (page_do_bit17_swizzling)
894 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
898 ret = __copy_from_user(vaddr + shmem_page_offset,
901 if (needs_clflush_after)
902 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
904 page_do_bit17_swizzling);
907 return ret ? -EFAULT : 0;
911 i915_gem_shmem_pwrite(struct drm_device *dev,
912 struct drm_i915_gem_object *obj,
913 struct drm_i915_gem_pwrite *args,
914 struct drm_file *file)
918 char __user *user_data;
919 int shmem_page_offset, page_length, ret = 0;
920 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
921 int hit_slowpath = 0;
922 int needs_clflush_after = 0;
923 int needs_clflush_before = 0;
924 struct sg_page_iter sg_iter;
926 user_data = to_user_ptr(args->data_ptr);
929 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
931 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
932 /* If we're not in the cpu write domain, set ourself into the gtt
933 * write domain and manually flush cachelines (if required). This
934 * optimizes for the case when the gpu will use the data
935 * right away and we therefore have to clflush anyway. */
936 needs_clflush_after = cpu_write_needs_clflush(obj);
937 ret = i915_gem_object_wait_rendering(obj, false);
941 /* Same trick applies to invalidate partially written cachelines read
943 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
944 needs_clflush_before =
945 !cpu_cache_is_coherent(dev, obj->cache_level);
947 ret = i915_gem_object_get_pages(obj);
951 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
953 i915_gem_object_pin_pages(obj);
955 offset = args->offset;
958 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
959 offset >> PAGE_SHIFT) {
960 struct page *page = sg_page_iter_page(&sg_iter);
961 int partial_cacheline_write;
966 /* Operation in this page
968 * shmem_page_offset = offset within page in shmem file
969 * page_length = bytes to copy for this page
971 shmem_page_offset = offset_in_page(offset);
973 page_length = remain;
974 if ((shmem_page_offset + page_length) > PAGE_SIZE)
975 page_length = PAGE_SIZE - shmem_page_offset;
977 /* If we don't overwrite a cacheline completely we need to be
978 * careful to have up-to-date data by first clflushing. Don't
979 * overcomplicate things and flush the entire patch. */
980 partial_cacheline_write = needs_clflush_before &&
981 ((shmem_page_offset | page_length)
982 & (boot_cpu_data.x86_clflush_size - 1));
984 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
985 (page_to_phys(page) & (1 << 17)) != 0;
987 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
988 user_data, page_do_bit17_swizzling,
989 partial_cacheline_write,
990 needs_clflush_after);
995 mutex_unlock(&dev->struct_mutex);
996 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
997 user_data, page_do_bit17_swizzling,
998 partial_cacheline_write,
999 needs_clflush_after);
1001 mutex_lock(&dev->struct_mutex);
1007 remain -= page_length;
1008 user_data += page_length;
1009 offset += page_length;
1013 i915_gem_object_unpin_pages(obj);
1017 * Fixup: Flush cpu caches in case we didn't flush the dirty
1018 * cachelines in-line while writing and the object moved
1019 * out of the cpu write domain while we've dropped the lock.
1021 if (!needs_clflush_after &&
1022 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1023 if (i915_gem_clflush_object(obj, obj->pin_display))
1024 i915_gem_chipset_flush(dev);
1028 if (needs_clflush_after)
1029 i915_gem_chipset_flush(dev);
1031 intel_fb_obj_flush(obj, false);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1042 struct drm_file *file)
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 struct drm_i915_gem_pwrite *args = data;
1046 struct drm_i915_gem_object *obj;
1049 if (args->size == 0)
1052 if (!access_ok(VERIFY_READ,
1053 to_user_ptr(args->data_ptr),
1057 if (likely(!i915.prefault_disable)) {
1058 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1064 intel_runtime_pm_get(dev_priv);
1066 ret = i915_mutex_lock_interruptible(dev);
1070 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1071 if (&obj->base == NULL) {
1076 /* Bounds check destination. */
1077 if (args->offset > obj->base.size ||
1078 args->size > obj->base.size - args->offset) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj->base.filp) {
1091 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj->tiling_mode == I915_TILING_NONE &&
1101 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1102 cpu_write_needs_clflush(obj)) {
1103 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret == -EFAULT || ret == -ENOSPC) {
1110 if (obj->phys_handle)
1111 ret = i915_gem_phys_pwrite(obj, args, file);
1113 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1117 drm_gem_object_unreference(&obj->base);
1119 mutex_unlock(&dev->struct_mutex);
1121 intel_runtime_pm_put(dev_priv);
1127 i915_gem_check_wedge(struct i915_gpu_error *error,
1130 if (i915_reset_in_progress(error)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error->reload_in_reset)
1153 * Compare arbitrary request against outstanding lazy request. Emit on match.
1156 i915_gem_check_olr(struct drm_i915_gem_request *req)
1160 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1163 if (req == req->ring->outstanding_lazy_request)
1164 ret = i915_add_request(req->ring);
1169 static void fake_irq(unsigned long data)
1171 wake_up_process((struct task_struct *)data);
1174 static bool missed_irq(struct drm_i915_private *dev_priv,
1175 struct intel_engine_cs *ring)
1177 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1180 static int __i915_spin_request(struct drm_i915_gem_request *req)
1182 unsigned long timeout;
1184 if (i915_gem_request_get_ring(req)->irq_refcount)
1187 timeout = jiffies + 1;
1188 while (!need_resched()) {
1189 if (i915_gem_request_completed(req, true))
1192 if (time_after_eq(jiffies, timeout))
1195 cpu_relax_lowlatency();
1197 if (i915_gem_request_completed(req, false))
1204 * __i915_wait_request - wait until execution of request has finished
1206 * @reset_counter: reset sequence associated with the given request
1207 * @interruptible: do an interruptible wait (normally yes)
1208 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1210 * Note: It is of utmost importance that the passed in seqno and reset_counter
1211 * values have been read by the caller in an smp safe manner. Where read-side
1212 * locks are involved, it is sufficient to read the reset_counter before
1213 * unlocking the lock that protects the seqno. For lockless tricks, the
1214 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1217 * Returns 0 if the request was found within the alloted time. Else returns the
1218 * errno with remaining time filled in timeout argument.
1220 int __i915_wait_request(struct drm_i915_gem_request *req,
1221 unsigned reset_counter,
1224 struct intel_rps_client *rps)
1226 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1227 struct drm_device *dev = ring->dev;
1228 struct drm_i915_private *dev_priv = dev->dev_private;
1229 const bool irq_test_in_progress =
1230 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1232 unsigned long timeout_expire;
1236 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1238 if (list_empty(&req->list))
1241 if (i915_gem_request_completed(req, true))
1244 timeout_expire = timeout ?
1245 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1247 if (INTEL_INFO(dev_priv)->gen >= 6)
1248 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1250 /* Record current time in case interrupted by signal, or wedged */
1251 trace_i915_gem_request_wait_begin(req);
1252 before = ktime_get_raw_ns();
1254 /* Optimistic spin for the next jiffie before touching IRQs */
1255 ret = __i915_spin_request(req);
1259 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1265 struct timer_list timer;
1267 prepare_to_wait(&ring->irq_queue, &wait,
1268 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1270 /* We need to check whether any gpu reset happened in between
1271 * the caller grabbing the seqno and now ... */
1272 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1273 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1274 * is truely gone. */
1275 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1281 if (i915_gem_request_completed(req, false)) {
1286 if (interruptible && signal_pending(current)) {
1291 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1296 timer.function = NULL;
1297 if (timeout || missed_irq(dev_priv, ring)) {
1298 unsigned long expire;
1300 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1301 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1302 mod_timer(&timer, expire);
1307 if (timer.function) {
1308 del_singleshot_timer_sync(&timer);
1309 destroy_timer_on_stack(&timer);
1312 if (!irq_test_in_progress)
1313 ring->irq_put(ring);
1315 finish_wait(&ring->irq_queue, &wait);
1318 now = ktime_get_raw_ns();
1319 trace_i915_gem_request_wait_end(req);
1322 s64 tres = *timeout - (now - before);
1324 *timeout = tres < 0 ? 0 : tres;
1327 * Apparently ktime isn't accurate enough and occasionally has a
1328 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1329 * things up to make the test happy. We allow up to 1 jiffy.
1331 * This is a regrssion from the timespec->ktime conversion.
1333 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1341 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1343 struct drm_i915_file_private *file_priv = request->file_priv;
1348 spin_lock(&file_priv->mm.lock);
1349 list_del(&request->client_list);
1350 request->file_priv = NULL;
1351 spin_unlock(&file_priv->mm.lock);
1354 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1356 trace_i915_gem_request_retire(request);
1358 /* We know the GPU must have read the request to have
1359 * sent us the seqno + interrupt, so use the position
1360 * of tail of the request to update the last known position
1363 * Note this requires that we are always called in request
1366 request->ringbuf->last_retired_head = request->postfix;
1368 list_del_init(&request->list);
1369 i915_gem_request_remove_from_client(request);
1371 put_pid(request->pid);
1373 i915_gem_request_unreference(request);
1377 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1379 struct intel_engine_cs *engine = req->ring;
1380 struct drm_i915_gem_request *tmp;
1382 lockdep_assert_held(&engine->dev->struct_mutex);
1384 if (list_empty(&req->list))
1388 tmp = list_first_entry(&engine->request_list,
1389 typeof(*tmp), list);
1391 i915_gem_request_retire(tmp);
1392 } while (tmp != req);
1394 WARN_ON(i915_verify_lists(engine->dev));
1398 * Waits for a request to be signaled, and cleans up the
1399 * request and object lists appropriately for that event.
1402 i915_wait_request(struct drm_i915_gem_request *req)
1404 struct drm_device *dev;
1405 struct drm_i915_private *dev_priv;
1409 BUG_ON(req == NULL);
1411 dev = req->ring->dev;
1412 dev_priv = dev->dev_private;
1413 interruptible = dev_priv->mm.interruptible;
1415 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1417 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1421 ret = i915_gem_check_olr(req);
1425 ret = __i915_wait_request(req,
1426 atomic_read(&dev_priv->gpu_error.reset_counter),
1427 interruptible, NULL, NULL);
1431 __i915_gem_request_retire__upto(req);
1436 * Ensures that all rendering to the object has completed and the object is
1437 * safe to unbind from the GTT or access from the CPU.
1440 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1449 if (obj->last_write_req != NULL) {
1450 ret = i915_wait_request(obj->last_write_req);
1454 i = obj->last_write_req->ring->id;
1455 if (obj->last_read_req[i] == obj->last_write_req)
1456 i915_gem_object_retire__read(obj, i);
1458 i915_gem_object_retire__write(obj);
1461 for (i = 0; i < I915_NUM_RINGS; i++) {
1462 if (obj->last_read_req[i] == NULL)
1465 ret = i915_wait_request(obj->last_read_req[i]);
1469 i915_gem_object_retire__read(obj, i);
1471 RQ_BUG_ON(obj->active);
1478 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1479 struct drm_i915_gem_request *req)
1481 int ring = req->ring->id;
1483 if (obj->last_read_req[ring] == req)
1484 i915_gem_object_retire__read(obj, ring);
1485 else if (obj->last_write_req == req)
1486 i915_gem_object_retire__write(obj);
1488 __i915_gem_request_retire__upto(req);
1491 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1492 * as the object state may change during this call.
1494 static __must_check int
1495 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1496 struct intel_rps_client *rps,
1499 struct drm_device *dev = obj->base.dev;
1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 struct drm_i915_gem_request *requests[I915_NUM_RINGS];
1502 unsigned reset_counter;
1505 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1506 BUG_ON(!dev_priv->mm.interruptible);
1511 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1515 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1518 struct drm_i915_gem_request *req;
1520 req = obj->last_write_req;
1524 ret = i915_gem_check_olr(req);
1528 requests[n++] = i915_gem_request_reference(req);
1530 for (i = 0; i < I915_NUM_RINGS; i++) {
1531 struct drm_i915_gem_request *req;
1533 req = obj->last_read_req[i];
1537 ret = i915_gem_check_olr(req);
1541 requests[n++] = i915_gem_request_reference(req);
1545 mutex_unlock(&dev->struct_mutex);
1546 for (i = 0; ret == 0 && i < n; i++)
1547 ret = __i915_wait_request(requests[i], reset_counter, true,
1549 mutex_lock(&dev->struct_mutex);
1552 for (i = 0; i < n; i++) {
1554 i915_gem_object_retire_request(obj, requests[i]);
1555 i915_gem_request_unreference(requests[i]);
1561 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1563 struct drm_i915_file_private *fpriv = file->driver_priv;
1568 * Called when user space prepares to use an object with the CPU, either
1569 * through the mmap ioctl's mapping or a GTT mapping.
1572 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1573 struct drm_file *file)
1575 struct drm_i915_gem_set_domain *args = data;
1576 struct drm_i915_gem_object *obj;
1577 uint32_t read_domains = args->read_domains;
1578 uint32_t write_domain = args->write_domain;
1581 /* Only handle setting domains to types used by the CPU. */
1582 if (write_domain & I915_GEM_GPU_DOMAINS)
1585 if (read_domains & I915_GEM_GPU_DOMAINS)
1588 /* Having something in the write domain implies it's in the read
1589 * domain, and only that read domain. Enforce that in the request.
1591 if (write_domain != 0 && read_domains != write_domain)
1594 ret = i915_mutex_lock_interruptible(dev);
1598 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1599 if (&obj->base == NULL) {
1604 /* Try to flush the object off the GPU without holding the lock.
1605 * We will repeat the flush holding the lock in the normal manner
1606 * to catch cases where we are gazumped.
1608 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1609 to_rps_client(file),
1614 if (read_domains & I915_GEM_DOMAIN_GTT)
1615 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1617 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1620 drm_gem_object_unreference(&obj->base);
1622 mutex_unlock(&dev->struct_mutex);
1627 * Called when user space has done writes to this buffer
1630 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1631 struct drm_file *file)
1633 struct drm_i915_gem_sw_finish *args = data;
1634 struct drm_i915_gem_object *obj;
1637 ret = i915_mutex_lock_interruptible(dev);
1641 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1642 if (&obj->base == NULL) {
1647 /* Pinned buffers may be scanout, so flush the cache */
1648 if (obj->pin_display)
1649 i915_gem_object_flush_cpu_write_domain(obj);
1651 drm_gem_object_unreference(&obj->base);
1653 mutex_unlock(&dev->struct_mutex);
1658 * Maps the contents of an object, returning the address it is mapped
1661 * While the mapping holds a reference on the contents of the object, it doesn't
1662 * imply a ref on the object itself.
1666 * DRM driver writers who look a this function as an example for how to do GEM
1667 * mmap support, please don't implement mmap support like here. The modern way
1668 * to implement DRM mmap support is with an mmap offset ioctl (like
1669 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1670 * That way debug tooling like valgrind will understand what's going on, hiding
1671 * the mmap call in a driver private ioctl will break that. The i915 driver only
1672 * does cpu mmaps this way because we didn't know better.
1675 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1676 struct drm_file *file)
1678 struct drm_i915_gem_mmap *args = data;
1679 struct drm_gem_object *obj;
1682 if (args->flags & ~(I915_MMAP_WC))
1685 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1688 obj = drm_gem_object_lookup(dev, file, args->handle);
1692 /* prime objects have no backing filp to GEM mmap
1696 drm_gem_object_unreference_unlocked(obj);
1700 addr = vm_mmap(obj->filp, 0, args->size,
1701 PROT_READ | PROT_WRITE, MAP_SHARED,
1703 if (args->flags & I915_MMAP_WC) {
1704 struct mm_struct *mm = current->mm;
1705 struct vm_area_struct *vma;
1707 down_write(&mm->mmap_sem);
1708 vma = find_vma(mm, addr);
1711 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1714 up_write(&mm->mmap_sem);
1716 drm_gem_object_unreference_unlocked(obj);
1717 if (IS_ERR((void *)addr))
1720 args->addr_ptr = (uint64_t) addr;
1726 * i915_gem_fault - fault a page into the GTT
1727 * vma: VMA in question
1730 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1731 * from userspace. The fault handler takes care of binding the object to
1732 * the GTT (if needed), allocating and programming a fence register (again,
1733 * only if needed based on whether the old reg is still valid or the object
1734 * is tiled) and inserting a new PTE into the faulting process.
1736 * Note that the faulting process may involve evicting existing objects
1737 * from the GTT and/or fence registers to make room. So performance may
1738 * suffer if the GTT working set is large or there are few fence registers
1741 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1743 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1744 struct drm_device *dev = obj->base.dev;
1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 struct i915_ggtt_view view = i915_ggtt_view_normal;
1747 pgoff_t page_offset;
1750 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1752 intel_runtime_pm_get(dev_priv);
1754 /* We don't use vmf->pgoff since that has the fake offset */
1755 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1758 ret = i915_mutex_lock_interruptible(dev);
1762 trace_i915_gem_object_fault(obj, page_offset, true, write);
1764 /* Try to flush the object off the GPU first without holding the lock.
1765 * Upon reacquiring the lock, we will perform our sanity checks and then
1766 * repeat the flush holding the lock in the normal manner to catch cases
1767 * where we are gazumped.
1769 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1773 /* Access to snoopable pages through the GTT is incoherent. */
1774 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1779 /* Use a partial view if the object is bigger than the aperture. */
1780 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1781 obj->tiling_mode == I915_TILING_NONE) {
1782 static const unsigned int chunk_size = 256; // 1 MiB
1784 memset(&view, 0, sizeof(view));
1785 view.type = I915_GGTT_VIEW_PARTIAL;
1786 view.params.partial.offset = rounddown(page_offset, chunk_size);
1787 view.params.partial.size =
1790 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1791 view.params.partial.offset);
1794 /* Now pin it into the GTT if needed */
1795 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1799 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1803 ret = i915_gem_object_get_fence(obj);
1807 /* Finally, remap it using the new GTT offset */
1808 pfn = dev_priv->gtt.mappable_base +
1809 i915_gem_obj_ggtt_offset_view(obj, &view);
1812 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1813 /* Overriding existing pages in partial view does not cause
1814 * us any trouble as TLBs are still valid because the fault
1815 * is due to userspace losing part of the mapping or never
1816 * having accessed it before (at this partials' range).
1818 unsigned long base = vma->vm_start +
1819 (view.params.partial.offset << PAGE_SHIFT);
1822 for (i = 0; i < view.params.partial.size; i++) {
1823 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1828 obj->fault_mappable = true;
1830 if (!obj->fault_mappable) {
1831 unsigned long size = min_t(unsigned long,
1832 vma->vm_end - vma->vm_start,
1836 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1837 ret = vm_insert_pfn(vma,
1838 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1844 obj->fault_mappable = true;
1846 ret = vm_insert_pfn(vma,
1847 (unsigned long)vmf->virtual_address,
1851 i915_gem_object_ggtt_unpin_view(obj, &view);
1853 mutex_unlock(&dev->struct_mutex);
1858 * We eat errors when the gpu is terminally wedged to avoid
1859 * userspace unduly crashing (gl has no provisions for mmaps to
1860 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1861 * and so needs to be reported.
1863 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1864 ret = VM_FAULT_SIGBUS;
1869 * EAGAIN means the gpu is hung and we'll wait for the error
1870 * handler to reset everything when re-faulting in
1871 * i915_mutex_lock_interruptible.
1878 * EBUSY is ok: this just means that another thread
1879 * already did the job.
1881 ret = VM_FAULT_NOPAGE;
1888 ret = VM_FAULT_SIGBUS;
1891 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1892 ret = VM_FAULT_SIGBUS;
1896 intel_runtime_pm_put(dev_priv);
1901 * i915_gem_release_mmap - remove physical page mappings
1902 * @obj: obj in question
1904 * Preserve the reservation of the mmapping with the DRM core code, but
1905 * relinquish ownership of the pages back to the system.
1907 * It is vital that we remove the page mapping if we have mapped a tiled
1908 * object through the GTT and then lose the fence register due to
1909 * resource pressure. Similarly if the object has been moved out of the
1910 * aperture, than pages mapped into userspace must be revoked. Removing the
1911 * mapping will then trigger a page fault on the next user access, allowing
1912 * fixup by i915_gem_fault().
1915 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1917 if (!obj->fault_mappable)
1920 drm_vma_node_unmap(&obj->base.vma_node,
1921 obj->base.dev->anon_inode->i_mapping);
1922 obj->fault_mappable = false;
1926 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1928 struct drm_i915_gem_object *obj;
1930 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1931 i915_gem_release_mmap(obj);
1935 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1939 if (INTEL_INFO(dev)->gen >= 4 ||
1940 tiling_mode == I915_TILING_NONE)
1943 /* Previous chips need a power-of-two fence region when tiling */
1944 if (INTEL_INFO(dev)->gen == 3)
1945 gtt_size = 1024*1024;
1947 gtt_size = 512*1024;
1949 while (gtt_size < size)
1956 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1957 * @obj: object to check
1959 * Return the required GTT alignment for an object, taking into account
1960 * potential fence register mapping.
1963 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1964 int tiling_mode, bool fenced)
1967 * Minimum alignment is 4k (GTT page size), but might be greater
1968 * if a fence register is needed for the object.
1970 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1971 tiling_mode == I915_TILING_NONE)
1975 * Previous chips need to be aligned to the size of the smallest
1976 * fence register that can contain the object.
1978 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1981 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1983 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1986 if (drm_vma_node_has_offset(&obj->base.vma_node))
1989 dev_priv->mm.shrinker_no_lock_stealing = true;
1991 ret = drm_gem_create_mmap_offset(&obj->base);
1995 /* Badly fragmented mmap space? The only way we can recover
1996 * space is by destroying unwanted objects. We can't randomly release
1997 * mmap_offsets as userspace expects them to be persistent for the
1998 * lifetime of the objects. The closest we can is to release the
1999 * offsets on purgeable objects by truncating it and marking it purged,
2000 * which prevents userspace from ever using that object again.
2002 i915_gem_shrink(dev_priv,
2003 obj->base.size >> PAGE_SHIFT,
2005 I915_SHRINK_UNBOUND |
2006 I915_SHRINK_PURGEABLE);
2007 ret = drm_gem_create_mmap_offset(&obj->base);
2011 i915_gem_shrink_all(dev_priv);
2012 ret = drm_gem_create_mmap_offset(&obj->base);
2014 dev_priv->mm.shrinker_no_lock_stealing = false;
2019 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2021 drm_gem_free_mmap_offset(&obj->base);
2025 i915_gem_mmap_gtt(struct drm_file *file,
2026 struct drm_device *dev,
2030 struct drm_i915_gem_object *obj;
2033 ret = i915_mutex_lock_interruptible(dev);
2037 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2038 if (&obj->base == NULL) {
2043 if (obj->madv != I915_MADV_WILLNEED) {
2044 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2049 ret = i915_gem_object_create_mmap_offset(obj);
2053 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2056 drm_gem_object_unreference(&obj->base);
2058 mutex_unlock(&dev->struct_mutex);
2063 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2065 * @data: GTT mapping ioctl data
2066 * @file: GEM object info
2068 * Simply returns the fake offset to userspace so it can mmap it.
2069 * The mmap call will end up in drm_gem_mmap(), which will set things
2070 * up so we can get faults in the handler above.
2072 * The fault handler will take care of binding the object into the GTT
2073 * (since it may have been evicted to make room for something), allocating
2074 * a fence register, and mapping the appropriate aperture address into
2078 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2079 struct drm_file *file)
2081 struct drm_i915_gem_mmap_gtt *args = data;
2083 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2086 /* Immediately discard the backing storage */
2088 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2090 i915_gem_object_free_mmap_offset(obj);
2092 if (obj->base.filp == NULL)
2095 /* Our goal here is to return as much of the memory as
2096 * is possible back to the system as we are called from OOM.
2097 * To do this we must instruct the shmfs to drop all of its
2098 * backing pages, *now*.
2100 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2101 obj->madv = __I915_MADV_PURGED;
2104 /* Try to discard unwanted pages */
2106 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2108 struct address_space *mapping;
2110 switch (obj->madv) {
2111 case I915_MADV_DONTNEED:
2112 i915_gem_object_truncate(obj);
2113 case __I915_MADV_PURGED:
2117 if (obj->base.filp == NULL)
2120 mapping = file_inode(obj->base.filp)->i_mapping,
2121 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2125 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2127 struct sg_page_iter sg_iter;
2130 BUG_ON(obj->madv == __I915_MADV_PURGED);
2132 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2134 /* In the event of a disaster, abandon all caches and
2135 * hope for the best.
2137 WARN_ON(ret != -EIO);
2138 i915_gem_clflush_object(obj, true);
2139 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2142 if (i915_gem_object_needs_bit17_swizzle(obj))
2143 i915_gem_object_save_bit_17_swizzle(obj);
2145 if (obj->madv == I915_MADV_DONTNEED)
2148 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2149 struct page *page = sg_page_iter_page(&sg_iter);
2152 set_page_dirty(page);
2154 if (obj->madv == I915_MADV_WILLNEED)
2155 mark_page_accessed(page);
2157 page_cache_release(page);
2161 sg_free_table(obj->pages);
2166 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2168 const struct drm_i915_gem_object_ops *ops = obj->ops;
2170 if (obj->pages == NULL)
2173 if (obj->pages_pin_count)
2176 BUG_ON(i915_gem_obj_bound_any(obj));
2178 /* ->put_pages might need to allocate memory for the bit17 swizzle
2179 * array, hence protect them from being reaped by removing them from gtt
2181 list_del(&obj->global_list);
2183 ops->put_pages(obj);
2186 i915_gem_object_invalidate(obj);
2192 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2194 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2196 struct address_space *mapping;
2197 struct sg_table *st;
2198 struct scatterlist *sg;
2199 struct sg_page_iter sg_iter;
2201 unsigned long last_pfn = 0; /* suppress gcc warning */
2204 /* Assert that the object is not currently in any GPU domain. As it
2205 * wasn't in the GTT, there shouldn't be any way it could have been in
2208 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2209 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2211 st = kmalloc(sizeof(*st), GFP_KERNEL);
2215 page_count = obj->base.size / PAGE_SIZE;
2216 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2221 /* Get the list of pages out of our struct file. They'll be pinned
2222 * at this point until we release them.
2224 * Fail silently without starting the shrinker
2226 mapping = file_inode(obj->base.filp)->i_mapping;
2227 gfp = mapping_gfp_mask(mapping);
2228 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2229 gfp &= ~(__GFP_IO | __GFP_WAIT);
2232 for (i = 0; i < page_count; i++) {
2233 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2235 i915_gem_shrink(dev_priv,
2238 I915_SHRINK_UNBOUND |
2239 I915_SHRINK_PURGEABLE);
2240 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2243 /* We've tried hard to allocate the memory by reaping
2244 * our own buffer, now let the real VM do its job and
2245 * go down in flames if truly OOM.
2247 i915_gem_shrink_all(dev_priv);
2248 page = shmem_read_mapping_page(mapping, i);
2252 #ifdef CONFIG_SWIOTLB
2253 if (swiotlb_nr_tbl()) {
2255 sg_set_page(sg, page, PAGE_SIZE, 0);
2260 if (!i || page_to_pfn(page) != last_pfn + 1) {
2264 sg_set_page(sg, page, PAGE_SIZE, 0);
2266 sg->length += PAGE_SIZE;
2268 last_pfn = page_to_pfn(page);
2270 /* Check that the i965g/gm workaround works. */
2271 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2273 #ifdef CONFIG_SWIOTLB
2274 if (!swiotlb_nr_tbl())
2279 if (i915_gem_object_needs_bit17_swizzle(obj))
2280 i915_gem_object_do_bit_17_swizzle(obj);
2282 if (obj->tiling_mode != I915_TILING_NONE &&
2283 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2284 i915_gem_object_pin_pages(obj);
2290 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2291 page_cache_release(sg_page_iter_page(&sg_iter));
2295 /* shmemfs first checks if there is enough memory to allocate the page
2296 * and reports ENOSPC should there be insufficient, along with the usual
2297 * ENOMEM for a genuine allocation failure.
2299 * We use ENOSPC in our driver to mean that we have run out of aperture
2300 * space and so want to translate the error from shmemfs back to our
2301 * usual understanding of ENOMEM.
2303 if (PTR_ERR(page) == -ENOSPC)
2306 return PTR_ERR(page);
2309 /* Ensure that the associated pages are gathered from the backing storage
2310 * and pinned into our object. i915_gem_object_get_pages() may be called
2311 * multiple times before they are released by a single call to
2312 * i915_gem_object_put_pages() - once the pages are no longer referenced
2313 * either as a result of memory pressure (reaping pages under the shrinker)
2314 * or as the object is itself released.
2317 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2319 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2320 const struct drm_i915_gem_object_ops *ops = obj->ops;
2326 if (obj->madv != I915_MADV_WILLNEED) {
2327 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2331 BUG_ON(obj->pages_pin_count);
2333 ret = ops->get_pages(obj);
2337 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2339 obj->get_page.sg = obj->pages->sgl;
2340 obj->get_page.last = 0;
2345 void i915_vma_move_to_active(struct i915_vma *vma,
2346 struct intel_engine_cs *ring)
2348 struct drm_i915_gem_object *obj = vma->obj;
2350 /* Add a reference if we're newly entering the active list. */
2351 if (obj->active == 0)
2352 drm_gem_object_reference(&obj->base);
2353 obj->active |= intel_ring_flag(ring);
2355 list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
2356 i915_gem_request_assign(&obj->last_read_req[ring->id],
2357 intel_ring_get_request(ring));
2359 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2363 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2365 RQ_BUG_ON(obj->last_write_req == NULL);
2366 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
2368 i915_gem_request_assign(&obj->last_write_req, NULL);
2369 intel_fb_obj_flush(obj, true);
2373 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2375 struct i915_vma *vma;
2377 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2378 RQ_BUG_ON(!(obj->active & (1 << ring)));
2380 list_del_init(&obj->ring_list[ring]);
2381 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2383 if (obj->last_write_req && obj->last_write_req->ring->id == ring)
2384 i915_gem_object_retire__write(obj);
2386 obj->active &= ~(1 << ring);
2390 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2391 if (!list_empty(&vma->mm_list))
2392 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2395 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2396 drm_gem_object_unreference(&obj->base);
2400 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct intel_engine_cs *ring;
2406 /* Carefully retire all requests without writing to the rings */
2407 for_each_ring(ring, dev_priv, i) {
2408 ret = intel_ring_idle(ring);
2412 i915_gem_retire_requests(dev);
2414 /* Finally reset hw state */
2415 for_each_ring(ring, dev_priv, i) {
2416 intel_ring_init_seqno(ring, seqno);
2418 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2419 ring->semaphore.sync_seqno[j] = 0;
2425 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2433 /* HWS page needs to be set less than what we
2434 * will inject to ring
2436 ret = i915_gem_init_seqno(dev, seqno - 1);
2440 /* Carefully set the last_seqno value so that wrap
2441 * detection still works
2443 dev_priv->next_seqno = seqno;
2444 dev_priv->last_seqno = seqno - 1;
2445 if (dev_priv->last_seqno == 0)
2446 dev_priv->last_seqno--;
2452 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2456 /* reserve 0 for non-seqno */
2457 if (dev_priv->next_seqno == 0) {
2458 int ret = i915_gem_init_seqno(dev, 0);
2462 dev_priv->next_seqno = 1;
2465 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2469 int __i915_add_request(struct intel_engine_cs *ring,
2470 struct drm_file *file,
2471 struct drm_i915_gem_object *obj)
2473 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2474 struct drm_i915_gem_request *request;
2475 struct intel_ringbuffer *ringbuf;
2479 request = ring->outstanding_lazy_request;
2480 if (WARN_ON(request == NULL))
2483 if (i915.enable_execlists) {
2484 ringbuf = request->ctx->engine[ring->id].ringbuf;
2486 ringbuf = ring->buffer;
2488 request_start = intel_ring_get_tail(ringbuf);
2490 * Emit any outstanding flushes - execbuf can fail to emit the flush
2491 * after having emitted the batchbuffer command. Hence we need to fix
2492 * things up similar to emitting the lazy request. The difference here
2493 * is that the flush _must_ happen before the next request, no matter
2496 if (i915.enable_execlists) {
2497 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2501 ret = intel_ring_flush_all_caches(ring);
2506 /* Record the position of the start of the request so that
2507 * should we detect the updated seqno part-way through the
2508 * GPU processing the request, we never over-estimate the
2509 * position of the head.
2511 request->postfix = intel_ring_get_tail(ringbuf);
2513 if (i915.enable_execlists) {
2514 ret = ring->emit_request(ringbuf, request);
2518 ret = ring->add_request(ring);
2522 request->tail = intel_ring_get_tail(ringbuf);
2525 request->head = request_start;
2527 /* Whilst this request exists, batch_obj will be on the
2528 * active_list, and so will hold the active reference. Only when this
2529 * request is retired will the the batch_obj be moved onto the
2530 * inactive_list and lose its active reference. Hence we do not need
2531 * to explicitly hold another reference here.
2533 request->batch_obj = obj;
2535 if (!i915.enable_execlists) {
2536 /* Hold a reference to the current context so that we can inspect
2537 * it later in case a hangcheck error event fires.
2539 request->ctx = ring->last_context;
2541 i915_gem_context_reference(request->ctx);
2544 request->emitted_jiffies = jiffies;
2545 list_add_tail(&request->list, &ring->request_list);
2546 request->file_priv = NULL;
2549 struct drm_i915_file_private *file_priv = file->driver_priv;
2551 spin_lock(&file_priv->mm.lock);
2552 request->file_priv = file_priv;
2553 list_add_tail(&request->client_list,
2554 &file_priv->mm.request_list);
2555 spin_unlock(&file_priv->mm.lock);
2557 request->pid = get_pid(task_pid(current));
2560 trace_i915_gem_request_add(request);
2561 ring->outstanding_lazy_request = NULL;
2563 i915_queue_hangcheck(ring->dev);
2565 queue_delayed_work(dev_priv->wq,
2566 &dev_priv->mm.retire_work,
2567 round_jiffies_up_relative(HZ));
2568 intel_mark_busy(dev_priv->dev);
2573 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2574 const struct intel_context *ctx)
2576 unsigned long elapsed;
2578 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2580 if (ctx->hang_stats.banned)
2583 if (ctx->hang_stats.ban_period_seconds &&
2584 elapsed <= ctx->hang_stats.ban_period_seconds) {
2585 if (!i915_gem_context_is_default(ctx)) {
2586 DRM_DEBUG("context hanging too fast, banning!\n");
2588 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2589 if (i915_stop_ring_allow_warn(dev_priv))
2590 DRM_ERROR("gpu hanging too fast, banning!\n");
2598 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2599 struct intel_context *ctx,
2602 struct i915_ctx_hang_stats *hs;
2607 hs = &ctx->hang_stats;
2610 hs->banned = i915_context_is_banned(dev_priv, ctx);
2612 hs->guilty_ts = get_seconds();
2614 hs->batch_pending++;
2618 void i915_gem_request_free(struct kref *req_ref)
2620 struct drm_i915_gem_request *req = container_of(req_ref,
2622 struct intel_context *ctx = req->ctx;
2625 if (i915.enable_execlists) {
2626 struct intel_engine_cs *ring = req->ring;
2628 if (ctx != ring->default_context)
2629 intel_lr_context_unpin(ring, ctx);
2632 i915_gem_context_unreference(ctx);
2635 kmem_cache_free(req->i915->requests, req);
2638 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2639 struct intel_context *ctx)
2641 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2642 struct drm_i915_gem_request *req;
2645 if (ring->outstanding_lazy_request)
2648 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2652 kref_init(&req->ref);
2653 req->i915 = dev_priv;
2655 ret = i915_gem_get_seqno(ring->dev, &req->seqno);
2661 if (i915.enable_execlists)
2662 ret = intel_logical_ring_alloc_request_extras(req, ctx);
2664 ret = intel_ring_alloc_request_extras(req);
2668 ring->outstanding_lazy_request = req;
2672 kmem_cache_free(dev_priv->requests, req);
2676 struct drm_i915_gem_request *
2677 i915_gem_find_active_request(struct intel_engine_cs *ring)
2679 struct drm_i915_gem_request *request;
2681 list_for_each_entry(request, &ring->request_list, list) {
2682 if (i915_gem_request_completed(request, false))
2691 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2692 struct intel_engine_cs *ring)
2694 struct drm_i915_gem_request *request;
2697 request = i915_gem_find_active_request(ring);
2699 if (request == NULL)
2702 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2704 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2706 list_for_each_entry_continue(request, &ring->request_list, list)
2707 i915_set_reset_status(dev_priv, request->ctx, false);
2710 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2711 struct intel_engine_cs *ring)
2713 while (!list_empty(&ring->active_list)) {
2714 struct drm_i915_gem_object *obj;
2716 obj = list_first_entry(&ring->active_list,
2717 struct drm_i915_gem_object,
2718 ring_list[ring->id]);
2720 i915_gem_object_retire__read(obj, ring->id);
2724 * Clear the execlists queue up before freeing the requests, as those
2725 * are the ones that keep the context and ringbuffer backing objects
2728 while (!list_empty(&ring->execlist_queue)) {
2729 struct drm_i915_gem_request *submit_req;
2731 submit_req = list_first_entry(&ring->execlist_queue,
2732 struct drm_i915_gem_request,
2734 list_del(&submit_req->execlist_link);
2736 if (submit_req->ctx != ring->default_context)
2737 intel_lr_context_unpin(ring, submit_req->ctx);
2739 i915_gem_request_unreference(submit_req);
2743 * We must free the requests after all the corresponding objects have
2744 * been moved off active lists. Which is the same order as the normal
2745 * retire_requests function does. This is important if object hold
2746 * implicit references on things like e.g. ppgtt address spaces through
2749 while (!list_empty(&ring->request_list)) {
2750 struct drm_i915_gem_request *request;
2752 request = list_first_entry(&ring->request_list,
2753 struct drm_i915_gem_request,
2756 i915_gem_request_retire(request);
2759 /* This may not have been flushed before the reset, so clean it now */
2760 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2763 void i915_gem_restore_fences(struct drm_device *dev)
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2768 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2769 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2772 * Commit delayed tiling changes if we have an object still
2773 * attached to the fence, otherwise just clear the fence.
2776 i915_gem_object_update_fence(reg->obj, reg,
2777 reg->obj->tiling_mode);
2779 i915_gem_write_fence(dev, i, NULL);
2784 void i915_gem_reset(struct drm_device *dev)
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 struct intel_engine_cs *ring;
2791 * Before we free the objects from the requests, we need to inspect
2792 * them for finding the guilty party. As the requests only borrow
2793 * their reference to the objects, the inspection must be done first.
2795 for_each_ring(ring, dev_priv, i)
2796 i915_gem_reset_ring_status(dev_priv, ring);
2798 for_each_ring(ring, dev_priv, i)
2799 i915_gem_reset_ring_cleanup(dev_priv, ring);
2801 i915_gem_context_reset(dev);
2803 i915_gem_restore_fences(dev);
2805 WARN_ON(i915_verify_lists(dev));
2809 * This function clears the request list as sequence numbers are passed.
2812 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2814 WARN_ON(i915_verify_lists(ring->dev));
2816 /* Retire requests first as we use it above for the early return.
2817 * If we retire requests last, we may use a later seqno and so clear
2818 * the requests lists without clearing the active list, leading to
2821 while (!list_empty(&ring->request_list)) {
2822 struct drm_i915_gem_request *request;
2824 request = list_first_entry(&ring->request_list,
2825 struct drm_i915_gem_request,
2828 if (!i915_gem_request_completed(request, true))
2831 i915_gem_request_retire(request);
2834 /* Move any buffers on the active list that are no longer referenced
2835 * by the ringbuffer to the flushing/inactive lists as appropriate,
2836 * before we free the context associated with the requests.
2838 while (!list_empty(&ring->active_list)) {
2839 struct drm_i915_gem_object *obj;
2841 obj = list_first_entry(&ring->active_list,
2842 struct drm_i915_gem_object,
2843 ring_list[ring->id]);
2845 if (!list_empty(&obj->last_read_req[ring->id]->list))
2848 i915_gem_object_retire__read(obj, ring->id);
2851 if (unlikely(ring->trace_irq_req &&
2852 i915_gem_request_completed(ring->trace_irq_req, true))) {
2853 ring->irq_put(ring);
2854 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2857 WARN_ON(i915_verify_lists(ring->dev));
2861 i915_gem_retire_requests(struct drm_device *dev)
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 struct intel_engine_cs *ring;
2868 for_each_ring(ring, dev_priv, i) {
2869 i915_gem_retire_requests_ring(ring);
2870 idle &= list_empty(&ring->request_list);
2871 if (i915.enable_execlists) {
2872 unsigned long flags;
2874 spin_lock_irqsave(&ring->execlist_lock, flags);
2875 idle &= list_empty(&ring->execlist_queue);
2876 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2878 intel_execlists_retire_requests(ring);
2883 mod_delayed_work(dev_priv->wq,
2884 &dev_priv->mm.idle_work,
2885 msecs_to_jiffies(100));
2891 i915_gem_retire_work_handler(struct work_struct *work)
2893 struct drm_i915_private *dev_priv =
2894 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2895 struct drm_device *dev = dev_priv->dev;
2898 /* Come back later if the device is busy... */
2900 if (mutex_trylock(&dev->struct_mutex)) {
2901 idle = i915_gem_retire_requests(dev);
2902 mutex_unlock(&dev->struct_mutex);
2905 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2906 round_jiffies_up_relative(HZ));
2910 i915_gem_idle_work_handler(struct work_struct *work)
2912 struct drm_i915_private *dev_priv =
2913 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2914 struct drm_device *dev = dev_priv->dev;
2915 struct intel_engine_cs *ring;
2918 for_each_ring(ring, dev_priv, i)
2919 if (!list_empty(&ring->request_list))
2922 intel_mark_idle(dev);
2924 if (mutex_trylock(&dev->struct_mutex)) {
2925 struct intel_engine_cs *ring;
2928 for_each_ring(ring, dev_priv, i)
2929 i915_gem_batch_pool_fini(&ring->batch_pool);
2931 mutex_unlock(&dev->struct_mutex);
2936 * Ensures that an object will eventually get non-busy by flushing any required
2937 * write domains, emitting any outstanding lazy request and retiring and
2938 * completed requests.
2941 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2948 for (i = 0; i < I915_NUM_RINGS; i++) {
2949 struct drm_i915_gem_request *req;
2951 req = obj->last_read_req[i];
2955 if (list_empty(&req->list))
2958 ret = i915_gem_check_olr(req);
2962 if (i915_gem_request_completed(req, true)) {
2963 __i915_gem_request_retire__upto(req);
2965 i915_gem_object_retire__read(obj, i);
2973 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2974 * @DRM_IOCTL_ARGS: standard ioctl arguments
2976 * Returns 0 if successful, else an error is returned with the remaining time in
2977 * the timeout parameter.
2978 * -ETIME: object is still busy after timeout
2979 * -ERESTARTSYS: signal interrupted the wait
2980 * -ENONENT: object doesn't exist
2981 * Also possible, but rare:
2982 * -EAGAIN: GPU wedged
2984 * -ENODEV: Internal IRQ fail
2985 * -E?: The add request failed
2987 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2988 * non-zero timeout parameter the wait ioctl will wait for the given number of
2989 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2990 * without holding struct_mutex the object may become re-busied before this
2991 * function completes. A similar but shorter * race condition exists in the busy
2995 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2997 struct drm_i915_private *dev_priv = dev->dev_private;
2998 struct drm_i915_gem_wait *args = data;
2999 struct drm_i915_gem_object *obj;
3000 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3001 unsigned reset_counter;
3005 if (args->flags != 0)
3008 ret = i915_mutex_lock_interruptible(dev);
3012 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3013 if (&obj->base == NULL) {
3014 mutex_unlock(&dev->struct_mutex);
3018 /* Need to make sure the object gets inactive eventually. */
3019 ret = i915_gem_object_flush_active(obj);
3026 /* Do this after OLR check to make sure we make forward progress polling
3027 * on this IOCTL with a timeout == 0 (like busy ioctl)
3029 if (args->timeout_ns == 0) {
3034 drm_gem_object_unreference(&obj->base);
3035 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3037 for (i = 0; i < I915_NUM_RINGS; i++) {
3038 if (obj->last_read_req[i] == NULL)
3041 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3044 mutex_unlock(&dev->struct_mutex);
3046 for (i = 0; i < n; i++) {
3048 ret = __i915_wait_request(req[i], reset_counter, true,
3049 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3051 i915_gem_request_unreference__unlocked(req[i]);
3056 drm_gem_object_unreference(&obj->base);
3057 mutex_unlock(&dev->struct_mutex);
3062 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3063 struct intel_engine_cs *to,
3064 struct drm_i915_gem_request *req)
3066 struct intel_engine_cs *from;
3069 from = i915_gem_request_get_ring(req);
3073 if (i915_gem_request_completed(req, true))
3076 ret = i915_gem_check_olr(req);
3080 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3081 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3082 ret = __i915_wait_request(req,
3083 atomic_read(&i915->gpu_error.reset_counter),
3084 i915->mm.interruptible,
3086 &i915->rps.semaphores);
3090 i915_gem_object_retire_request(obj, req);
3092 int idx = intel_ring_sync_index(from, to);
3093 u32 seqno = i915_gem_request_get_seqno(req);
3095 if (seqno <= from->semaphore.sync_seqno[idx])
3098 trace_i915_gem_ring_sync_to(from, to, req);
3099 ret = to->semaphore.sync_to(to, from, seqno);
3103 /* We use last_read_req because sync_to()
3104 * might have just caused seqno wrap under
3107 from->semaphore.sync_seqno[idx] =
3108 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3115 * i915_gem_object_sync - sync an object to a ring.
3117 * @obj: object which may be in use on another ring.
3118 * @to: ring we wish to use the object on. May be NULL.
3120 * This code is meant to abstract object synchronization with the GPU.
3121 * Calling with NULL implies synchronizing the object with the CPU
3122 * rather than a particular GPU ring. Conceptually we serialise writes
3123 * between engines inside the GPU. We only allow on engine to write
3124 * into a buffer at any time, but multiple readers. To ensure each has
3125 * a coherent view of memory, we must:
3127 * - If there is an outstanding write request to the object, the new
3128 * request must wait for it to complete (either CPU or in hw, requests
3129 * on the same ring will be naturally ordered).
3131 * - If we are a write request (pending_write_domain is set), the new
3132 * request must wait for outstanding read requests to complete.
3134 * Returns 0 if successful, else propagates up the lower layer error.
3137 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3138 struct intel_engine_cs *to)
3140 const bool readonly = obj->base.pending_write_domain == 0;
3141 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3148 return i915_gem_object_wait_rendering(obj, readonly);
3152 if (obj->last_write_req)
3153 req[n++] = obj->last_write_req;
3155 for (i = 0; i < I915_NUM_RINGS; i++)
3156 if (obj->last_read_req[i])
3157 req[n++] = obj->last_read_req[i];
3159 for (i = 0; i < n; i++) {
3160 ret = __i915_gem_object_sync(obj, to, req[i]);
3168 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3170 u32 old_write_domain, old_read_domains;
3172 /* Force a pagefault for domain tracking on next user access */
3173 i915_gem_release_mmap(obj);
3175 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3178 /* Wait for any direct GTT access to complete */
3181 old_read_domains = obj->base.read_domains;
3182 old_write_domain = obj->base.write_domain;
3184 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3185 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3187 trace_i915_gem_object_change_domain(obj,
3192 int i915_vma_unbind(struct i915_vma *vma)
3194 struct drm_i915_gem_object *obj = vma->obj;
3195 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3198 if (list_empty(&vma->vma_link))
3201 if (!drm_mm_node_allocated(&vma->node)) {
3202 i915_gem_vma_destroy(vma);
3209 BUG_ON(obj->pages == NULL);
3211 ret = i915_gem_object_wait_rendering(obj, false);
3214 /* Continue on if we fail due to EIO, the GPU is hung so we
3215 * should be safe and we need to cleanup or else we might
3216 * cause memory corruption through use-after-free.
3219 if (i915_is_ggtt(vma->vm) &&
3220 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3221 i915_gem_object_finish_gtt(obj);
3223 /* release the fence reg _after_ flushing */
3224 ret = i915_gem_object_put_fence(obj);
3229 trace_i915_vma_unbind(vma);
3231 vma->vm->unbind_vma(vma);
3234 list_del_init(&vma->mm_list);
3235 if (i915_is_ggtt(vma->vm)) {
3236 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3237 obj->map_and_fenceable = false;
3238 } else if (vma->ggtt_view.pages) {
3239 sg_free_table(vma->ggtt_view.pages);
3240 kfree(vma->ggtt_view.pages);
3241 vma->ggtt_view.pages = NULL;
3245 drm_mm_remove_node(&vma->node);
3246 i915_gem_vma_destroy(vma);
3248 /* Since the unbound list is global, only move to that list if
3249 * no more VMAs exist. */
3250 if (list_empty(&obj->vma_list)) {
3251 i915_gem_gtt_finish_object(obj);
3252 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3255 /* And finally now the object is completely decoupled from this vma,
3256 * we can drop its hold on the backing storage and allow it to be
3257 * reaped by the shrinker.
3259 i915_gem_object_unpin_pages(obj);
3264 int i915_gpu_idle(struct drm_device *dev)
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3267 struct intel_engine_cs *ring;
3270 /* Flush everything onto the inactive list. */
3271 for_each_ring(ring, dev_priv, i) {
3272 if (!i915.enable_execlists) {
3273 ret = i915_switch_context(ring, ring->default_context);
3278 ret = intel_ring_idle(ring);
3283 WARN_ON(i915_verify_lists(dev));
3287 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3288 struct drm_i915_gem_object *obj)
3290 struct drm_i915_private *dev_priv = dev->dev_private;
3292 int fence_pitch_shift;
3294 if (INTEL_INFO(dev)->gen >= 6) {
3295 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3296 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3298 fence_reg = FENCE_REG_965_0;
3299 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3302 fence_reg += reg * 8;
3304 /* To w/a incoherency with non-atomic 64-bit register updates,
3305 * we split the 64-bit update into two 32-bit writes. In order
3306 * for a partial fence not to be evaluated between writes, we
3307 * precede the update with write to turn off the fence register,
3308 * and only enable the fence as the last step.
3310 * For extra levels of paranoia, we make sure each step lands
3311 * before applying the next step.
3313 I915_WRITE(fence_reg, 0);
3314 POSTING_READ(fence_reg);
3317 u32 size = i915_gem_obj_ggtt_size(obj);
3320 /* Adjust fence size to match tiled area */
3321 if (obj->tiling_mode != I915_TILING_NONE) {
3322 uint32_t row_size = obj->stride *
3323 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3324 size = (size / row_size) * row_size;
3327 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3329 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3330 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3331 if (obj->tiling_mode == I915_TILING_Y)
3332 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3333 val |= I965_FENCE_REG_VALID;
3335 I915_WRITE(fence_reg + 4, val >> 32);
3336 POSTING_READ(fence_reg + 4);
3338 I915_WRITE(fence_reg + 0, val);
3339 POSTING_READ(fence_reg);
3341 I915_WRITE(fence_reg + 4, 0);
3342 POSTING_READ(fence_reg + 4);
3346 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3347 struct drm_i915_gem_object *obj)
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3353 u32 size = i915_gem_obj_ggtt_size(obj);
3357 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3358 (size & -size) != size ||
3359 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3360 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3361 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3363 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3368 /* Note: pitch better be a power of two tile widths */
3369 pitch_val = obj->stride / tile_width;
3370 pitch_val = ffs(pitch_val) - 1;
3372 val = i915_gem_obj_ggtt_offset(obj);
3373 if (obj->tiling_mode == I915_TILING_Y)
3374 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3375 val |= I915_FENCE_SIZE_BITS(size);
3376 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3377 val |= I830_FENCE_REG_VALID;
3382 reg = FENCE_REG_830_0 + reg * 4;
3384 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3386 I915_WRITE(reg, val);
3390 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3391 struct drm_i915_gem_object *obj)
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3397 u32 size = i915_gem_obj_ggtt_size(obj);
3400 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3401 (size & -size) != size ||
3402 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3403 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3404 i915_gem_obj_ggtt_offset(obj), size);
3406 pitch_val = obj->stride / 128;
3407 pitch_val = ffs(pitch_val) - 1;
3409 val = i915_gem_obj_ggtt_offset(obj);
3410 if (obj->tiling_mode == I915_TILING_Y)
3411 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3412 val |= I830_FENCE_SIZE_BITS(size);
3413 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3414 val |= I830_FENCE_REG_VALID;
3418 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3419 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3422 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3424 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3427 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3428 struct drm_i915_gem_object *obj)
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3432 /* Ensure that all CPU reads are completed before installing a fence
3433 * and all writes before removing the fence.
3435 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3438 WARN(obj && (!obj->stride || !obj->tiling_mode),
3439 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3440 obj->stride, obj->tiling_mode);
3443 i830_write_fence_reg(dev, reg, obj);
3444 else if (IS_GEN3(dev))
3445 i915_write_fence_reg(dev, reg, obj);
3446 else if (INTEL_INFO(dev)->gen >= 4)
3447 i965_write_fence_reg(dev, reg, obj);
3449 /* And similarly be paranoid that no direct access to this region
3450 * is reordered to before the fence is installed.
3452 if (i915_gem_object_needs_mb(obj))
3456 static inline int fence_number(struct drm_i915_private *dev_priv,
3457 struct drm_i915_fence_reg *fence)
3459 return fence - dev_priv->fence_regs;
3462 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3463 struct drm_i915_fence_reg *fence,
3466 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3467 int reg = fence_number(dev_priv, fence);
3469 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3472 obj->fence_reg = reg;
3474 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3476 obj->fence_reg = I915_FENCE_REG_NONE;
3478 list_del_init(&fence->lru_list);
3480 obj->fence_dirty = false;
3484 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3486 if (obj->last_fenced_req) {
3487 int ret = i915_wait_request(obj->last_fenced_req);
3491 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3498 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3500 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3501 struct drm_i915_fence_reg *fence;
3504 ret = i915_gem_object_wait_fence(obj);
3508 if (obj->fence_reg == I915_FENCE_REG_NONE)
3511 fence = &dev_priv->fence_regs[obj->fence_reg];
3513 if (WARN_ON(fence->pin_count))
3516 i915_gem_object_fence_lost(obj);
3517 i915_gem_object_update_fence(obj, fence, false);
3522 static struct drm_i915_fence_reg *
3523 i915_find_fence_reg(struct drm_device *dev)
3525 struct drm_i915_private *dev_priv = dev->dev_private;
3526 struct drm_i915_fence_reg *reg, *avail;
3529 /* First try to find a free reg */
3531 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3532 reg = &dev_priv->fence_regs[i];
3536 if (!reg->pin_count)
3543 /* None available, try to steal one or wait for a user to finish */
3544 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3552 /* Wait for completion of pending flips which consume fences */
3553 if (intel_has_pending_fb_unpin(dev))
3554 return ERR_PTR(-EAGAIN);
3556 return ERR_PTR(-EDEADLK);
3560 * i915_gem_object_get_fence - set up fencing for an object
3561 * @obj: object to map through a fence reg
3563 * When mapping objects through the GTT, userspace wants to be able to write
3564 * to them without having to worry about swizzling if the object is tiled.
3565 * This function walks the fence regs looking for a free one for @obj,
3566 * stealing one if it can't find any.
3568 * It then sets up the reg based on the object's properties: address, pitch
3569 * and tiling format.
3571 * For an untiled surface, this removes any existing fence.
3574 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3576 struct drm_device *dev = obj->base.dev;
3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578 bool enable = obj->tiling_mode != I915_TILING_NONE;
3579 struct drm_i915_fence_reg *reg;
3582 /* Have we updated the tiling parameters upon the object and so
3583 * will need to serialise the write to the associated fence register?
3585 if (obj->fence_dirty) {
3586 ret = i915_gem_object_wait_fence(obj);
3591 /* Just update our place in the LRU if our fence is getting reused. */
3592 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3593 reg = &dev_priv->fence_regs[obj->fence_reg];
3594 if (!obj->fence_dirty) {
3595 list_move_tail(®->lru_list,
3596 &dev_priv->mm.fence_list);
3599 } else if (enable) {
3600 if (WARN_ON(!obj->map_and_fenceable))
3603 reg = i915_find_fence_reg(dev);
3605 return PTR_ERR(reg);
3608 struct drm_i915_gem_object *old = reg->obj;
3610 ret = i915_gem_object_wait_fence(old);
3614 i915_gem_object_fence_lost(old);
3619 i915_gem_object_update_fence(obj, reg, enable);
3624 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3625 unsigned long cache_level)
3627 struct drm_mm_node *gtt_space = &vma->node;
3628 struct drm_mm_node *other;
3631 * On some machines we have to be careful when putting differing types
3632 * of snoopable memory together to avoid the prefetcher crossing memory
3633 * domains and dying. During vm initialisation, we decide whether or not
3634 * these constraints apply and set the drm_mm.color_adjust
3637 if (vma->vm->mm.color_adjust == NULL)
3640 if (!drm_mm_node_allocated(gtt_space))
3643 if (list_empty(>t_space->node_list))
3646 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3647 if (other->allocated && !other->hole_follows && other->color != cache_level)
3650 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3651 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3658 * Finds free space in the GTT aperture and binds the object or a view of it
3661 static struct i915_vma *
3662 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3663 struct i915_address_space *vm,
3664 const struct i915_ggtt_view *ggtt_view,
3668 struct drm_device *dev = obj->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 u32 size, fence_size, fence_alignment, unfenced_alignment;
3671 unsigned long start =
3672 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3674 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3675 struct i915_vma *vma;
3678 if (i915_is_ggtt(vm)) {
3681 if (WARN_ON(!ggtt_view))
3682 return ERR_PTR(-EINVAL);
3684 view_size = i915_ggtt_view_size(obj, ggtt_view);
3686 fence_size = i915_gem_get_gtt_size(dev,
3689 fence_alignment = i915_gem_get_gtt_alignment(dev,
3693 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3697 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3699 fence_size = i915_gem_get_gtt_size(dev,
3702 fence_alignment = i915_gem_get_gtt_alignment(dev,
3706 unfenced_alignment =
3707 i915_gem_get_gtt_alignment(dev,
3711 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3715 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3717 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3718 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3719 ggtt_view ? ggtt_view->type : 0,
3721 return ERR_PTR(-EINVAL);
3724 /* If binding the object/GGTT view requires more space than the entire
3725 * aperture has, reject it early before evicting everything in a vain
3726 * attempt to find space.
3729 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3730 ggtt_view ? ggtt_view->type : 0,
3732 flags & PIN_MAPPABLE ? "mappable" : "total",
3734 return ERR_PTR(-E2BIG);
3737 ret = i915_gem_object_get_pages(obj);
3739 return ERR_PTR(ret);
3741 i915_gem_object_pin_pages(obj);
3743 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3744 i915_gem_obj_lookup_or_create_vma(obj, vm);
3750 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3754 DRM_MM_SEARCH_DEFAULT,
3755 DRM_MM_CREATE_DEFAULT);
3757 ret = i915_gem_evict_something(dev, vm, size, alignment,
3766 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3768 goto err_remove_node;
3771 ret = i915_gem_gtt_prepare_object(obj);
3773 goto err_remove_node;
3775 trace_i915_vma_bind(vma, flags);
3776 ret = i915_vma_bind(vma, obj->cache_level, flags);
3778 goto err_finish_gtt;
3780 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3781 list_add_tail(&vma->mm_list, &vm->inactive_list);
3786 i915_gem_gtt_finish_object(obj);
3788 drm_mm_remove_node(&vma->node);
3790 i915_gem_vma_destroy(vma);
3793 i915_gem_object_unpin_pages(obj);
3798 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3801 /* If we don't have a page list set up, then we're not pinned
3802 * to GPU, and we can ignore the cache flush because it'll happen
3803 * again at bind time.
3805 if (obj->pages == NULL)
3809 * Stolen memory is always coherent with the GPU as it is explicitly
3810 * marked as wc by the system, or the system is cache-coherent.
3812 if (obj->stolen || obj->phys_handle)
3815 /* If the GPU is snooping the contents of the CPU cache,
3816 * we do not need to manually clear the CPU cache lines. However,
3817 * the caches are only snooped when the render cache is
3818 * flushed/invalidated. As we always have to emit invalidations
3819 * and flushes when moving into and out of the RENDER domain, correct
3820 * snooping behaviour occurs naturally as the result of our domain
3823 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3824 obj->cache_dirty = true;
3828 trace_i915_gem_object_clflush(obj);
3829 drm_clflush_sg(obj->pages);
3830 obj->cache_dirty = false;
3835 /** Flushes the GTT write domain for the object if it's dirty. */
3837 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3839 uint32_t old_write_domain;
3841 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3844 /* No actual flushing is required for the GTT write domain. Writes
3845 * to it immediately go to main memory as far as we know, so there's
3846 * no chipset flush. It also doesn't land in render cache.
3848 * However, we do have to enforce the order so that all writes through
3849 * the GTT land before any writes to the device, such as updates to
3854 old_write_domain = obj->base.write_domain;
3855 obj->base.write_domain = 0;
3857 intel_fb_obj_flush(obj, false);
3859 trace_i915_gem_object_change_domain(obj,
3860 obj->base.read_domains,
3864 /** Flushes the CPU write domain for the object if it's dirty. */
3866 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3868 uint32_t old_write_domain;
3870 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3873 if (i915_gem_clflush_object(obj, obj->pin_display))
3874 i915_gem_chipset_flush(obj->base.dev);
3876 old_write_domain = obj->base.write_domain;
3877 obj->base.write_domain = 0;
3879 intel_fb_obj_flush(obj, false);
3881 trace_i915_gem_object_change_domain(obj,
3882 obj->base.read_domains,
3887 * Moves a single object to the GTT read, and possibly write domain.
3889 * This function returns when the move is complete, including waiting on
3893 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3895 uint32_t old_write_domain, old_read_domains;
3896 struct i915_vma *vma;
3899 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3902 ret = i915_gem_object_wait_rendering(obj, !write);
3906 /* Flush and acquire obj->pages so that we are coherent through
3907 * direct access in memory with previous cached writes through
3908 * shmemfs and that our cache domain tracking remains valid.
3909 * For example, if the obj->filp was moved to swap without us
3910 * being notified and releasing the pages, we would mistakenly
3911 * continue to assume that the obj remained out of the CPU cached
3914 ret = i915_gem_object_get_pages(obj);
3918 i915_gem_object_flush_cpu_write_domain(obj);
3920 /* Serialise direct access to this object with the barriers for
3921 * coherent writes from the GPU, by effectively invalidating the
3922 * GTT domain upon first access.
3924 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3927 old_write_domain = obj->base.write_domain;
3928 old_read_domains = obj->base.read_domains;
3930 /* It should now be out of any other write domains, and we can update
3931 * the domain values for our changes.
3933 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3934 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3936 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3937 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3942 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
3944 trace_i915_gem_object_change_domain(obj,
3948 /* And bump the LRU for this access */
3949 vma = i915_gem_obj_to_ggtt(obj);
3950 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3951 list_move_tail(&vma->mm_list,
3952 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3957 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3958 enum i915_cache_level cache_level)
3960 struct drm_device *dev = obj->base.dev;
3961 struct i915_vma *vma, *next;
3964 if (obj->cache_level == cache_level)
3967 if (i915_gem_obj_is_pinned(obj)) {
3968 DRM_DEBUG("can not change the cache level of pinned objects\n");
3972 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3973 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3974 ret = i915_vma_unbind(vma);
3980 if (i915_gem_obj_bound_any(obj)) {
3981 ret = i915_gem_object_wait_rendering(obj, false);
3985 i915_gem_object_finish_gtt(obj);
3987 /* Before SandyBridge, you could not use tiling or fence
3988 * registers with snooped memory, so relinquish any fences
3989 * currently pointing to our region in the aperture.
3991 if (INTEL_INFO(dev)->gen < 6) {
3992 ret = i915_gem_object_put_fence(obj);
3997 list_for_each_entry(vma, &obj->vma_list, vma_link)
3998 if (drm_mm_node_allocated(&vma->node)) {
3999 ret = i915_vma_bind(vma, cache_level,
4006 list_for_each_entry(vma, &obj->vma_list, vma_link)
4007 vma->node.color = cache_level;
4008 obj->cache_level = cache_level;
4010 if (obj->cache_dirty &&
4011 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
4012 cpu_write_needs_clflush(obj)) {
4013 if (i915_gem_clflush_object(obj, true))
4014 i915_gem_chipset_flush(obj->base.dev);
4020 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
4021 struct drm_file *file)
4023 struct drm_i915_gem_caching *args = data;
4024 struct drm_i915_gem_object *obj;
4026 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4027 if (&obj->base == NULL)
4030 switch (obj->cache_level) {
4031 case I915_CACHE_LLC:
4032 case I915_CACHE_L3_LLC:
4033 args->caching = I915_CACHING_CACHED;
4037 args->caching = I915_CACHING_DISPLAY;
4041 args->caching = I915_CACHING_NONE;
4045 drm_gem_object_unreference_unlocked(&obj->base);
4049 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
4050 struct drm_file *file)
4052 struct drm_i915_gem_caching *args = data;
4053 struct drm_i915_gem_object *obj;
4054 enum i915_cache_level level;
4057 switch (args->caching) {
4058 case I915_CACHING_NONE:
4059 level = I915_CACHE_NONE;
4061 case I915_CACHING_CACHED:
4062 level = I915_CACHE_LLC;
4064 case I915_CACHING_DISPLAY:
4065 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4071 ret = i915_mutex_lock_interruptible(dev);
4075 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4076 if (&obj->base == NULL) {
4081 ret = i915_gem_object_set_cache_level(obj, level);
4083 drm_gem_object_unreference(&obj->base);
4085 mutex_unlock(&dev->struct_mutex);
4090 * Prepare buffer for display plane (scanout, cursors, etc).
4091 * Can be called from an uninterruptible phase (modesetting) and allows
4092 * any flushes to be pipelined (for pageflips).
4095 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4097 struct intel_engine_cs *pipelined,
4098 const struct i915_ggtt_view *view)
4100 u32 old_read_domains, old_write_domain;
4103 ret = i915_gem_object_sync(obj, pipelined);
4107 /* Mark the pin_display early so that we account for the
4108 * display coherency whilst setting up the cache domains.
4112 /* The display engine is not coherent with the LLC cache on gen6. As
4113 * a result, we make sure that the pinning that is about to occur is
4114 * done with uncached PTEs. This is lowest common denominator for all
4117 * However for gen6+, we could do better by using the GFDT bit instead
4118 * of uncaching, which would allow us to flush all the LLC-cached data
4119 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4121 ret = i915_gem_object_set_cache_level(obj,
4122 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4124 goto err_unpin_display;
4126 /* As the user may map the buffer once pinned in the display plane
4127 * (e.g. libkms for the bootup splash), we have to ensure that we
4128 * always use map_and_fenceable for all scanout buffers.
4130 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4131 view->type == I915_GGTT_VIEW_NORMAL ?
4134 goto err_unpin_display;
4136 i915_gem_object_flush_cpu_write_domain(obj);
4138 old_write_domain = obj->base.write_domain;
4139 old_read_domains = obj->base.read_domains;
4141 /* It should now be out of any other write domains, and we can update
4142 * the domain values for our changes.
4144 obj->base.write_domain = 0;
4145 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4147 trace_i915_gem_object_change_domain(obj,
4159 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4160 const struct i915_ggtt_view *view)
4162 if (WARN_ON(obj->pin_display == 0))
4165 i915_gem_object_ggtt_unpin_view(obj, view);
4171 * Moves a single object to the CPU read, and possibly write domain.
4173 * This function returns when the move is complete, including waiting on
4177 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4179 uint32_t old_write_domain, old_read_domains;
4182 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4185 ret = i915_gem_object_wait_rendering(obj, !write);
4189 i915_gem_object_flush_gtt_write_domain(obj);
4191 old_write_domain = obj->base.write_domain;
4192 old_read_domains = obj->base.read_domains;
4194 /* Flush the CPU cache if it's still invalid. */
4195 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4196 i915_gem_clflush_object(obj, false);
4198 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4201 /* It should now be out of any other write domains, and we can update
4202 * the domain values for our changes.
4204 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4206 /* If we're writing through the CPU, then the GPU read domains will
4207 * need to be invalidated at next use.
4210 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4211 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4215 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
4217 trace_i915_gem_object_change_domain(obj,
4224 /* Throttle our rendering by waiting until the ring has completed our requests
4225 * emitted over 20 msec ago.
4227 * Note that if we were to use the current jiffies each time around the loop,
4228 * we wouldn't escape the function with any frames outstanding if the time to
4229 * render a frame was over 20ms.
4231 * This should get us reasonable parallelism between CPU and GPU but also
4232 * relatively low latency when blocking on a particular request to finish.
4235 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 struct drm_i915_file_private *file_priv = file->driver_priv;
4239 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4240 struct drm_i915_gem_request *request, *target = NULL;
4241 unsigned reset_counter;
4244 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4248 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4252 spin_lock(&file_priv->mm.lock);
4253 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4254 if (time_after_eq(request->emitted_jiffies, recent_enough))
4259 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4261 i915_gem_request_reference(target);
4262 spin_unlock(&file_priv->mm.lock);
4267 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4269 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4271 i915_gem_request_unreference__unlocked(target);
4277 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4279 struct drm_i915_gem_object *obj = vma->obj;
4282 vma->node.start & (alignment - 1))
4285 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4288 if (flags & PIN_OFFSET_BIAS &&
4289 vma->node.start < (flags & PIN_OFFSET_MASK))
4296 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4297 struct i915_address_space *vm,
4298 const struct i915_ggtt_view *ggtt_view,
4302 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4303 struct i915_vma *vma;
4307 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4310 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4313 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4316 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4319 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4320 i915_gem_obj_to_vma(obj, vm);
4323 return PTR_ERR(vma);
4326 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4329 if (i915_vma_misplaced(vma, alignment, flags)) {
4330 unsigned long offset;
4331 offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) :
4332 i915_gem_obj_offset(obj, vm);
4333 WARN(vma->pin_count,
4334 "bo is already pinned in %s with incorrect alignment:"
4335 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4336 " obj->map_and_fenceable=%d\n",
4337 ggtt_view ? "ggtt" : "ppgtt",
4340 !!(flags & PIN_MAPPABLE),
4341 obj->map_and_fenceable);
4342 ret = i915_vma_unbind(vma);
4350 bound = vma ? vma->bound : 0;
4351 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4352 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4355 return PTR_ERR(vma);
4357 ret = i915_vma_bind(vma, obj->cache_level, flags);
4362 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4363 (bound ^ vma->bound) & GLOBAL_BIND) {
4364 bool mappable, fenceable;
4365 u32 fence_size, fence_alignment;
4367 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4370 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4375 fenceable = (vma->node.size == fence_size &&
4376 (vma->node.start & (fence_alignment - 1)) == 0);
4378 mappable = (vma->node.start + fence_size <=
4379 dev_priv->gtt.mappable_end);
4381 obj->map_and_fenceable = mappable && fenceable;
4383 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4391 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4392 struct i915_address_space *vm,
4396 return i915_gem_object_do_pin(obj, vm,
4397 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4402 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4403 const struct i915_ggtt_view *view,
4407 if (WARN_ONCE(!view, "no view specified"))
4410 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4411 alignment, flags | PIN_GLOBAL);
4415 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4416 const struct i915_ggtt_view *view)
4418 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4421 WARN_ON(vma->pin_count == 0);
4422 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4428 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4430 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4431 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4432 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4434 WARN_ON(!ggtt_vma ||
4435 dev_priv->fence_regs[obj->fence_reg].pin_count >
4436 ggtt_vma->pin_count);
4437 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4444 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4446 if (obj->fence_reg != I915_FENCE_REG_NONE) {
4447 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4448 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4449 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4454 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4455 struct drm_file *file)
4457 struct drm_i915_gem_busy *args = data;
4458 struct drm_i915_gem_object *obj;
4461 ret = i915_mutex_lock_interruptible(dev);
4465 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4466 if (&obj->base == NULL) {
4471 /* Count all active objects as busy, even if they are currently not used
4472 * by the gpu. Users of this interface expect objects to eventually
4473 * become non-busy without any further actions, therefore emit any
4474 * necessary flushes here.
4476 ret = i915_gem_object_flush_active(obj);
4480 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4481 args->busy = obj->active << 16;
4482 if (obj->last_write_req)
4483 args->busy |= obj->last_write_req->ring->id;
4486 drm_gem_object_unreference(&obj->base);
4488 mutex_unlock(&dev->struct_mutex);
4493 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4494 struct drm_file *file_priv)
4496 return i915_gem_ring_throttle(dev, file_priv);
4500 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4501 struct drm_file *file_priv)
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4504 struct drm_i915_gem_madvise *args = data;
4505 struct drm_i915_gem_object *obj;
4508 switch (args->madv) {
4509 case I915_MADV_DONTNEED:
4510 case I915_MADV_WILLNEED:
4516 ret = i915_mutex_lock_interruptible(dev);
4520 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4521 if (&obj->base == NULL) {
4526 if (i915_gem_obj_is_pinned(obj)) {
4532 obj->tiling_mode != I915_TILING_NONE &&
4533 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4534 if (obj->madv == I915_MADV_WILLNEED)
4535 i915_gem_object_unpin_pages(obj);
4536 if (args->madv == I915_MADV_WILLNEED)
4537 i915_gem_object_pin_pages(obj);
4540 if (obj->madv != __I915_MADV_PURGED)
4541 obj->madv = args->madv;
4543 /* if the object is no longer attached, discard its backing storage */
4544 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4545 i915_gem_object_truncate(obj);
4547 args->retained = obj->madv != __I915_MADV_PURGED;
4550 drm_gem_object_unreference(&obj->base);
4552 mutex_unlock(&dev->struct_mutex);
4556 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4557 const struct drm_i915_gem_object_ops *ops)
4561 INIT_LIST_HEAD(&obj->global_list);
4562 for (i = 0; i < I915_NUM_RINGS; i++)
4563 INIT_LIST_HEAD(&obj->ring_list[i]);
4564 INIT_LIST_HEAD(&obj->obj_exec_link);
4565 INIT_LIST_HEAD(&obj->vma_list);
4566 INIT_LIST_HEAD(&obj->batch_pool_link);
4570 obj->fence_reg = I915_FENCE_REG_NONE;
4571 obj->madv = I915_MADV_WILLNEED;
4573 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4576 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4577 .get_pages = i915_gem_object_get_pages_gtt,
4578 .put_pages = i915_gem_object_put_pages_gtt,
4581 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4584 struct drm_i915_gem_object *obj;
4585 struct address_space *mapping;
4588 obj = i915_gem_object_alloc(dev);
4592 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4593 i915_gem_object_free(obj);
4597 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4598 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4599 /* 965gm cannot relocate objects above 4GiB. */
4600 mask &= ~__GFP_HIGHMEM;
4601 mask |= __GFP_DMA32;
4604 mapping = file_inode(obj->base.filp)->i_mapping;
4605 mapping_set_gfp_mask(mapping, mask);
4607 i915_gem_object_init(obj, &i915_gem_object_ops);
4609 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4610 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4613 /* On some devices, we can have the GPU use the LLC (the CPU
4614 * cache) for about a 10% performance improvement
4615 * compared to uncached. Graphics requests other than
4616 * display scanout are coherent with the CPU in
4617 * accessing this cache. This means in this mode we
4618 * don't need to clflush on the CPU side, and on the
4619 * GPU side we only need to flush internal caches to
4620 * get data visible to the CPU.
4622 * However, we maintain the display planes as UC, and so
4623 * need to rebind when first used as such.
4625 obj->cache_level = I915_CACHE_LLC;
4627 obj->cache_level = I915_CACHE_NONE;
4629 trace_i915_gem_object_create(obj);
4634 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4636 /* If we are the last user of the backing storage (be it shmemfs
4637 * pages or stolen etc), we know that the pages are going to be
4638 * immediately released. In this case, we can then skip copying
4639 * back the contents from the GPU.
4642 if (obj->madv != I915_MADV_WILLNEED)
4645 if (obj->base.filp == NULL)
4648 /* At first glance, this looks racy, but then again so would be
4649 * userspace racing mmap against close. However, the first external
4650 * reference to the filp can only be obtained through the
4651 * i915_gem_mmap_ioctl() which safeguards us against the user
4652 * acquiring such a reference whilst we are in the middle of
4653 * freeing the object.
4655 return atomic_long_read(&obj->base.filp->f_count) == 1;
4658 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4660 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4661 struct drm_device *dev = obj->base.dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct i915_vma *vma, *next;
4665 intel_runtime_pm_get(dev_priv);
4667 trace_i915_gem_object_destroy(obj);
4669 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4673 ret = i915_vma_unbind(vma);
4674 if (WARN_ON(ret == -ERESTARTSYS)) {
4675 bool was_interruptible;
4677 was_interruptible = dev_priv->mm.interruptible;
4678 dev_priv->mm.interruptible = false;
4680 WARN_ON(i915_vma_unbind(vma));
4682 dev_priv->mm.interruptible = was_interruptible;
4686 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4687 * before progressing. */
4689 i915_gem_object_unpin_pages(obj);
4691 WARN_ON(obj->frontbuffer_bits);
4693 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4694 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4695 obj->tiling_mode != I915_TILING_NONE)
4696 i915_gem_object_unpin_pages(obj);
4698 if (WARN_ON(obj->pages_pin_count))
4699 obj->pages_pin_count = 0;
4700 if (discard_backing_storage(obj))
4701 obj->madv = I915_MADV_DONTNEED;
4702 i915_gem_object_put_pages(obj);
4703 i915_gem_object_free_mmap_offset(obj);
4707 if (obj->base.import_attach)
4708 drm_prime_gem_destroy(&obj->base, NULL);
4710 if (obj->ops->release)
4711 obj->ops->release(obj);
4713 drm_gem_object_release(&obj->base);
4714 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4717 i915_gem_object_free(obj);
4719 intel_runtime_pm_put(dev_priv);
4722 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4723 struct i915_address_space *vm)
4725 struct i915_vma *vma;
4726 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4727 if (i915_is_ggtt(vma->vm) &&
4728 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4736 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4737 const struct i915_ggtt_view *view)
4739 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4740 struct i915_vma *vma;
4742 if (WARN_ONCE(!view, "no view specified"))
4743 return ERR_PTR(-EINVAL);
4745 list_for_each_entry(vma, &obj->vma_list, vma_link)
4746 if (vma->vm == ggtt &&
4747 i915_ggtt_view_equal(&vma->ggtt_view, view))
4752 void i915_gem_vma_destroy(struct i915_vma *vma)
4754 struct i915_address_space *vm = NULL;
4755 WARN_ON(vma->node.allocated);
4757 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4758 if (!list_empty(&vma->exec_list))
4763 if (!i915_is_ggtt(vm))
4764 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4766 list_del(&vma->vma_link);
4768 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4772 i915_gem_stop_ringbuffers(struct drm_device *dev)
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775 struct intel_engine_cs *ring;
4778 for_each_ring(ring, dev_priv, i)
4779 dev_priv->gt.stop_ring(ring);
4783 i915_gem_suspend(struct drm_device *dev)
4785 struct drm_i915_private *dev_priv = dev->dev_private;
4788 mutex_lock(&dev->struct_mutex);
4789 ret = i915_gpu_idle(dev);
4793 i915_gem_retire_requests(dev);
4795 i915_gem_stop_ringbuffers(dev);
4796 mutex_unlock(&dev->struct_mutex);
4798 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4799 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4800 flush_delayed_work(&dev_priv->mm.idle_work);
4802 /* Assert that we sucessfully flushed all the work and
4803 * reset the GPU back to its idle, low power state.
4805 WARN_ON(dev_priv->mm.busy);
4810 mutex_unlock(&dev->struct_mutex);
4814 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4816 struct drm_device *dev = ring->dev;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4819 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4822 if (!HAS_L3_DPF(dev) || !remap_info)
4825 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4830 * Note: We do not worry about the concurrent register cacheline hang
4831 * here because no other code should access these registers other than
4832 * at initialization time.
4834 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4835 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4836 intel_ring_emit(ring, reg_base + i);
4837 intel_ring_emit(ring, remap_info[i/4]);
4840 intel_ring_advance(ring);
4845 void i915_gem_init_swizzling(struct drm_device *dev)
4847 struct drm_i915_private *dev_priv = dev->dev_private;
4849 if (INTEL_INFO(dev)->gen < 5 ||
4850 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4853 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4854 DISP_TILE_SURFACE_SWIZZLING);
4859 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4861 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4862 else if (IS_GEN7(dev))
4863 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4864 else if (IS_GEN8(dev))
4865 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4871 intel_enable_blt(struct drm_device *dev)
4876 /* The blitter was dysfunctional on early prototypes */
4877 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4878 DRM_INFO("BLT not supported on this pre-production hardware;"
4879 " graphics performance will be degraded.\n");
4886 static void init_unused_ring(struct drm_device *dev, u32 base)
4888 struct drm_i915_private *dev_priv = dev->dev_private;
4890 I915_WRITE(RING_CTL(base), 0);
4891 I915_WRITE(RING_HEAD(base), 0);
4892 I915_WRITE(RING_TAIL(base), 0);
4893 I915_WRITE(RING_START(base), 0);
4896 static void init_unused_rings(struct drm_device *dev)
4899 init_unused_ring(dev, PRB1_BASE);
4900 init_unused_ring(dev, SRB0_BASE);
4901 init_unused_ring(dev, SRB1_BASE);
4902 init_unused_ring(dev, SRB2_BASE);
4903 init_unused_ring(dev, SRB3_BASE);
4904 } else if (IS_GEN2(dev)) {
4905 init_unused_ring(dev, SRB0_BASE);
4906 init_unused_ring(dev, SRB1_BASE);
4907 } else if (IS_GEN3(dev)) {
4908 init_unused_ring(dev, PRB1_BASE);
4909 init_unused_ring(dev, PRB2_BASE);
4913 int i915_gem_init_rings(struct drm_device *dev)
4915 struct drm_i915_private *dev_priv = dev->dev_private;
4918 ret = intel_init_render_ring_buffer(dev);
4923 ret = intel_init_bsd_ring_buffer(dev);
4925 goto cleanup_render_ring;
4928 if (intel_enable_blt(dev)) {
4929 ret = intel_init_blt_ring_buffer(dev);
4931 goto cleanup_bsd_ring;
4934 if (HAS_VEBOX(dev)) {
4935 ret = intel_init_vebox_ring_buffer(dev);
4937 goto cleanup_blt_ring;
4940 if (HAS_BSD2(dev)) {
4941 ret = intel_init_bsd2_ring_buffer(dev);
4943 goto cleanup_vebox_ring;
4946 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4948 goto cleanup_bsd2_ring;
4953 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4955 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4957 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4959 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4960 cleanup_render_ring:
4961 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4967 i915_gem_init_hw(struct drm_device *dev)
4969 struct drm_i915_private *dev_priv = dev->dev_private;
4970 struct intel_engine_cs *ring;
4973 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4976 /* Double layer security blanket, see i915_gem_init() */
4977 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4979 if (dev_priv->ellc_size)
4980 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4982 if (IS_HASWELL(dev))
4983 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4984 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4986 if (HAS_PCH_NOP(dev)) {
4987 if (IS_IVYBRIDGE(dev)) {
4988 u32 temp = I915_READ(GEN7_MSG_CTL);
4989 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4990 I915_WRITE(GEN7_MSG_CTL, temp);
4991 } else if (INTEL_INFO(dev)->gen >= 7) {
4992 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4993 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4994 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4998 i915_gem_init_swizzling(dev);
5001 * At least 830 can leave some of the unused rings
5002 * "active" (ie. head != tail) after resume which
5003 * will prevent c3 entry. Makes sure all unused rings
5006 init_unused_rings(dev);
5008 for_each_ring(ring, dev_priv, i) {
5009 ret = ring->init_hw(ring);
5014 for (i = 0; i < NUM_L3_SLICES(dev); i++)
5015 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
5017 ret = i915_ppgtt_init_hw(dev);
5018 if (ret && ret != -EIO) {
5019 DRM_ERROR("PPGTT enable failed %d\n", ret);
5020 i915_gem_cleanup_ringbuffer(dev);
5023 ret = i915_gem_context_enable(dev_priv);
5024 if (ret && ret != -EIO) {
5025 DRM_ERROR("Context enable failed %d\n", ret);
5026 i915_gem_cleanup_ringbuffer(dev);
5032 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5036 int i915_gem_init(struct drm_device *dev)
5038 struct drm_i915_private *dev_priv = dev->dev_private;
5041 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
5042 i915.enable_execlists);
5044 mutex_lock(&dev->struct_mutex);
5046 if (IS_VALLEYVIEW(dev)) {
5047 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5048 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
5049 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
5050 VLV_GTLC_ALLOWWAKEACK), 10))
5051 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5054 if (!i915.enable_execlists) {
5055 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
5056 dev_priv->gt.init_rings = i915_gem_init_rings;
5057 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
5058 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
5060 dev_priv->gt.execbuf_submit = intel_execlists_submission;
5061 dev_priv->gt.init_rings = intel_logical_rings_init;
5062 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
5063 dev_priv->gt.stop_ring = intel_logical_ring_stop;
5066 /* This is just a security blanket to placate dragons.
5067 * On some systems, we very sporadically observe that the first TLBs
5068 * used by the CS may be stale, despite us poking the TLB reset. If
5069 * we hold the forcewake during initialisation these problems
5070 * just magically go away.
5072 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5074 ret = i915_gem_init_userptr(dev);
5078 i915_gem_init_global_gtt(dev);
5080 ret = i915_gem_context_init(dev);
5084 ret = dev_priv->gt.init_rings(dev);
5088 ret = i915_gem_init_hw(dev);
5090 /* Allow ring initialisation to fail by marking the GPU as
5091 * wedged. But we only want to do this where the GPU is angry,
5092 * for all other failure, such as an allocation failure, bail.
5094 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5095 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5100 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5101 mutex_unlock(&dev->struct_mutex);
5107 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110 struct intel_engine_cs *ring;
5113 for_each_ring(ring, dev_priv, i)
5114 dev_priv->gt.cleanup_ring(ring);
5118 init_ring_lists(struct intel_engine_cs *ring)
5120 INIT_LIST_HEAD(&ring->active_list);
5121 INIT_LIST_HEAD(&ring->request_list);
5124 void i915_init_vm(struct drm_i915_private *dev_priv,
5125 struct i915_address_space *vm)
5127 if (!i915_is_ggtt(vm))
5128 drm_mm_init(&vm->mm, vm->start, vm->total);
5129 vm->dev = dev_priv->dev;
5130 INIT_LIST_HEAD(&vm->active_list);
5131 INIT_LIST_HEAD(&vm->inactive_list);
5132 INIT_LIST_HEAD(&vm->global_link);
5133 list_add_tail(&vm->global_link, &dev_priv->vm_list);
5137 i915_gem_load(struct drm_device *dev)
5139 struct drm_i915_private *dev_priv = dev->dev_private;
5143 kmem_cache_create("i915_gem_object",
5144 sizeof(struct drm_i915_gem_object), 0,
5148 kmem_cache_create("i915_gem_vma",
5149 sizeof(struct i915_vma), 0,
5152 dev_priv->requests =
5153 kmem_cache_create("i915_gem_request",
5154 sizeof(struct drm_i915_gem_request), 0,
5158 INIT_LIST_HEAD(&dev_priv->vm_list);
5159 i915_init_vm(dev_priv, &dev_priv->gtt.base);
5161 INIT_LIST_HEAD(&dev_priv->context_list);
5162 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5163 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5164 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5165 for (i = 0; i < I915_NUM_RINGS; i++)
5166 init_ring_lists(&dev_priv->ring[i]);
5167 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5168 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5169 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5170 i915_gem_retire_work_handler);
5171 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5172 i915_gem_idle_work_handler);
5173 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5175 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5177 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5178 dev_priv->num_fence_regs = 32;
5179 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5180 dev_priv->num_fence_regs = 16;
5182 dev_priv->num_fence_regs = 8;
5184 if (intel_vgpu_active(dev))
5185 dev_priv->num_fence_regs =
5186 I915_READ(vgtif_reg(avail_rs.fence_num));
5188 /* Initialize fence registers to zero */
5189 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5190 i915_gem_restore_fences(dev);
5192 i915_gem_detect_bit_6_swizzle(dev);
5193 init_waitqueue_head(&dev_priv->pending_flip_queue);
5195 dev_priv->mm.interruptible = true;
5197 i915_gem_shrinker_init(dev_priv);
5199 mutex_init(&dev_priv->fb_tracking.lock);
5202 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5204 struct drm_i915_file_private *file_priv = file->driver_priv;
5206 /* Clean up our request list when the client is going away, so that
5207 * later retire_requests won't dereference our soon-to-be-gone
5210 spin_lock(&file_priv->mm.lock);
5211 while (!list_empty(&file_priv->mm.request_list)) {
5212 struct drm_i915_gem_request *request;
5214 request = list_first_entry(&file_priv->mm.request_list,
5215 struct drm_i915_gem_request,
5217 list_del(&request->client_list);
5218 request->file_priv = NULL;
5220 spin_unlock(&file_priv->mm.lock);
5222 if (!list_empty(&file_priv->rps.link)) {
5223 spin_lock(&to_i915(dev)->rps.client_lock);
5224 list_del(&file_priv->rps.link);
5225 spin_unlock(&to_i915(dev)->rps.client_lock);
5229 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5231 struct drm_i915_file_private *file_priv;
5234 DRM_DEBUG_DRIVER("\n");
5236 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5240 file->driver_priv = file_priv;
5241 file_priv->dev_priv = dev->dev_private;
5242 file_priv->file = file;
5243 INIT_LIST_HEAD(&file_priv->rps.link);
5245 spin_lock_init(&file_priv->mm.lock);
5246 INIT_LIST_HEAD(&file_priv->mm.request_list);
5248 ret = i915_gem_context_open(dev, file);
5256 * i915_gem_track_fb - update frontbuffer tracking
5257 * old: current GEM buffer for the frontbuffer slots
5258 * new: new GEM buffer for the frontbuffer slots
5259 * frontbuffer_bits: bitmask of frontbuffer slots
5261 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5262 * from @old and setting them in @new. Both @old and @new can be NULL.
5264 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5265 struct drm_i915_gem_object *new,
5266 unsigned frontbuffer_bits)
5269 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5270 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5271 old->frontbuffer_bits &= ~frontbuffer_bits;
5275 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5276 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5277 new->frontbuffer_bits |= frontbuffer_bits;
5281 /* All the new VM stuff */
5283 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5284 struct i915_address_space *vm)
5286 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5287 struct i915_vma *vma;
5289 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5291 list_for_each_entry(vma, &o->vma_list, vma_link) {
5292 if (i915_is_ggtt(vma->vm) &&
5293 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5296 return vma->node.start;
5299 WARN(1, "%s vma for this object not found.\n",
5300 i915_is_ggtt(vm) ? "global" : "ppgtt");
5305 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5306 const struct i915_ggtt_view *view)
5308 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5309 struct i915_vma *vma;
5311 list_for_each_entry(vma, &o->vma_list, vma_link)
5312 if (vma->vm == ggtt &&
5313 i915_ggtt_view_equal(&vma->ggtt_view, view))
5314 return vma->node.start;
5316 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5320 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5321 struct i915_address_space *vm)
5323 struct i915_vma *vma;
5325 list_for_each_entry(vma, &o->vma_list, vma_link) {
5326 if (i915_is_ggtt(vma->vm) &&
5327 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5329 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5336 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5337 const struct i915_ggtt_view *view)
5339 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5340 struct i915_vma *vma;
5342 list_for_each_entry(vma, &o->vma_list, vma_link)
5343 if (vma->vm == ggtt &&
5344 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5345 drm_mm_node_allocated(&vma->node))
5351 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5353 struct i915_vma *vma;
5355 list_for_each_entry(vma, &o->vma_list, vma_link)
5356 if (drm_mm_node_allocated(&vma->node))
5362 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5363 struct i915_address_space *vm)
5365 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5366 struct i915_vma *vma;
5368 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5370 BUG_ON(list_empty(&o->vma_list));
5372 list_for_each_entry(vma, &o->vma_list, vma_link) {
5373 if (i915_is_ggtt(vma->vm) &&
5374 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5377 return vma->node.size;
5382 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5384 struct i915_vma *vma;
5385 list_for_each_entry(vma, &obj->vma_list, vma_link)
5386 if (vma->pin_count > 0)