drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  *
  36  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
  37  * FW_LOADED, FW_FAILED.
  38  *
  39  * Once the firmware is written into the registers status will be moved from
  40  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
  41  * be moved to FW_FAILED.
  42  */
  43
  44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
  45
  46 MODULE_FIRMWARE(I915_CSR_SKL);
  47
  48 /*
  49 * SKL CSR registers for DC5 and DC6
  50 */
  51 #define CSR_PROGRAM_BASE                0x80000
  52 #define CSR_SSP_BASE_ADDR_GEN9          0x00002FC0
  53 #define CSR_HTP_ADDR_SKL                0x00500034
  54 #define CSR_SSP_BASE                    0x8F074
  55 #define CSR_HTP_SKL                     0x8F004
  56 #define CSR_LAST_WRITE                  0x8F034
  57 #define CSR_LAST_WRITE_VALUE            0xc003b400
  58 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
  59 #define CSR_MAX_FW_SIZE                 0x2FFF
  60 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  61 #define CSR_MMIO_START_RANGE    0x80000
  62 #define CSR_MMIO_END_RANGE              0x8FFFF
  63
  64 struct intel_css_header {
  65         /* 0x09 for DMC */
  66         uint32_t module_type;
  67
  68         /* Includes the DMC specific header in dwords */
  69         uint32_t header_len;
  70
  71         /* always value would be 0x10000 */
  72         uint32_t header_ver;
  73
  74         /* Not used */
  75         uint32_t module_id;
  76
  77         /* Not used */
  78         uint32_t module_vendor;
  79
  80         /* in YYYYMMDD format */
  81         uint32_t date;
  82
  83         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  84         uint32_t size;
  85
  86         /* Not used */
  87         uint32_t key_size;
  88
  89         /* Not used */
  90         uint32_t modulus_size;
  91
  92         /* Not used */
  93         uint32_t exponent_size;
  94
  95         /* Not used */
  96         uint32_t reserved1[12];
  97
  98         /* Major Minor */
  99         uint32_t version;
 100
 101         /* Not used */
 102         uint32_t reserved2[8];
 103
 104         /* Not used */
 105         uint32_t kernel_header_info;
 106 } __packed;
 107
 108 struct intel_fw_info {
 109         uint16_t reserved1;
 110
 111         /* Stepping (A, B, C, ..., *). * is a wildcard */
 112         char stepping;
 113
 114         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 115         char substepping;
 116
 117         uint32_t offset;
 118         uint32_t reserved2;
 119 } __packed;
 120
 121 struct intel_package_header {
 122         /* DMC container header length in dwords */
 123         unsigned char header_len;
 124
 125         /* always value would be 0x01 */
 126         unsigned char header_ver;
 127
 128         unsigned char reserved[10];
 129
 130         /* Number of valid entries in the FWInfo array below */
 131         uint32_t num_entries;
 132
 133         struct intel_fw_info fw_info[20];
 134 } __packed;
 135
 136 struct intel_dmc_header {
 137         /* always value would be 0x40403E3E */
 138         uint32_t signature;
 139
 140         /* DMC binary header length */
 141         unsigned char header_len;
 142
 143         /* 0x01 */
 144         unsigned char header_ver;
 145
 146         /* Reserved */
 147         uint16_t dmcc_ver;
 148
 149         /* Major, Minor */
 150         uint32_t        project;
 151
 152         /* Firmware program size (excluding header) in dwords */
 153         uint32_t        fw_size;
 154
 155         /* Major Minor version */
 156         uint32_t fw_version;
 157
 158         /* Number of valid MMIO cycles present. */
 159         uint32_t mmio_count;
 160
 161         /* MMIO address */
 162         uint32_t mmioaddr[8];
 163
 164         /* MMIO data */
 165         uint32_t mmiodata[8];
 166
 167         /* FW filename  */
 168         unsigned char dfile[32];
 169
 170         uint32_t reserved1[2];
 171 } __packed;
 172
 173 struct stepping_info {
 174         char stepping;
 175         char substepping;
 176 };
 177
 178 static const struct stepping_info skl_stepping_info[] = {
 179                 {'A', '0'}, {'B', '0'}, {'C', '0'},
 180                 {'D', '0'}, {'E', '0'}, {'F', '0'},
 181                 {'G', '0'}, {'H', '0'}, {'I', '0'}
 182 };
 183
 184 static char intel_get_stepping(struct drm_device *dev)
 185 {
 186         if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 187                         ARRAY_SIZE(skl_stepping_info)))
 188                 return skl_stepping_info[dev->pdev->revision].stepping;
 189         else
 190                 return -ENODATA;
 191 }
 192
 193 static char intel_get_substepping(struct drm_device *dev)
 194 {
 195         if (IS_SKYLAKE(dev) && (dev->pdev->revision <
 196                         ARRAY_SIZE(skl_stepping_info)))
 197                 return skl_stepping_info[dev->pdev->revision].substepping;
 198         else
 199                 return -ENODATA;
 200 }
 201
 202 /**
 203  * intel_csr_load_status_get() - to get firmware loading status.
 204  * @dev_priv: i915 device.
 205  *
 206  * This function helps to get the firmware loading status.
 207  *
 208  * Return: Firmware loading status.
 209  */
 210 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
 211 {
 212         enum csr_state state;
 213
 214         mutex_lock(&dev_priv->csr_lock);
 215         state = dev_priv->csr.state;
 216         mutex_unlock(&dev_priv->csr_lock);
 217
 218         return state;
 219 }
 220
 221 /**
 222  * intel_csr_load_status_set() - help to set firmware loading status.
 223  * @dev_priv: i915 device.
 224  * @state: enumeration of firmware loading status.
 225  *
 226  * Set the firmware loading status.
 227  */
 228 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
 229                         enum csr_state state)
 230 {
 231         mutex_lock(&dev_priv->csr_lock);
 232         dev_priv->csr.state = state;
 233         mutex_unlock(&dev_priv->csr_lock);
 234 }
 235
 236 /**
 237  * intel_csr_load_program() - write the firmware from memory to register.
 238  * @dev: drm device.
 239  *
 240  * CSR firmware is read from a .bin file and kept in internal memory one time.
 241  * Everytime display comes back from low power state this function is called to
 242  * copy the firmware from internal memory to registers.
 243  */
 244 void intel_csr_load_program(struct drm_device *dev)
 245 {
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         u32 *payload = dev_priv->csr.dmc_payload;
 248         uint32_t i, fw_size;
 249
 250         if (!IS_GEN9(dev)) {
 251                 DRM_ERROR("No CSR support available for this platform\n");
 252                 return;
 253         }
 254
 255         mutex_lock(&dev_priv->csr_lock);
 256         fw_size = dev_priv->csr.dmc_fw_size;
 257         for (i = 0; i < fw_size; i++)
 258                 I915_WRITE(CSR_PROGRAM_BASE + i * 4,
 259                         payload[i]);
 260
 261         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 262                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 263                         dev_priv->csr.mmiodata[i]);
 264         }
 265
 266         dev_priv->csr.state = FW_LOADED;
 267         mutex_unlock(&dev_priv->csr_lock);
 268 }
 269
 270 static void finish_csr_load(const struct firmware *fw, void *context)
 271 {
 272         struct drm_i915_private *dev_priv = context;
 273         struct drm_device *dev = dev_priv->dev;
 274         struct intel_css_header *css_header;
 275         struct intel_package_header *package_header;
 276         struct intel_dmc_header *dmc_header;
 277         struct intel_csr *csr = &dev_priv->csr;
 278         char stepping = intel_get_stepping(dev);
 279         char substepping = intel_get_substepping(dev);
 280         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 281         uint32_t i;
 282         uint32_t *dmc_payload;
 283         bool fw_loaded = false;
 284
 285         if (!fw) {
 286                 i915_firmware_load_error_print(csr->fw_path, 0);
 287                 goto out;
 288         }
 289
 290         if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
 291                 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
 292                 goto out;
 293         }
 294
 295         /* Extract CSS Header information*/
 296         css_header = (struct intel_css_header *)fw->data;
 297         if (sizeof(struct intel_css_header) !=
 298                 (css_header->header_len * 4)) {
 299                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 300                         (css_header->header_len * 4));
 301                 goto out;
 302         }
 303         readcount += sizeof(struct intel_css_header);
 304
 305         /* Extract Package Header information*/
 306         package_header = (struct intel_package_header *)
 307                                         &fw->data[readcount];
 308         if (sizeof(struct intel_package_header) !=
 309                 (package_header->header_len * 4)) {
 310                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 311                         (package_header->header_len * 4));
 312                 goto out;
 313         }
 314         readcount += sizeof(struct intel_package_header);
 315
 316         /* Search for dmc_offset to find firware binary. */
 317         for (i = 0; i < package_header->num_entries; i++) {
 318                 if (package_header->fw_info[i].substepping == '*' &&
 319                         stepping == package_header->fw_info[i].stepping) {
 320                         dmc_offset = package_header->fw_info[i].offset;
 321                         break;
 322                 } else if (stepping == package_header->fw_info[i].stepping &&
 323                         substepping == package_header->fw_info[i].substepping) {
 324                         dmc_offset = package_header->fw_info[i].offset;
 325                         break;
 326                 } else if (package_header->fw_info[i].stepping == '*' &&
 327                         package_header->fw_info[i].substepping == '*')
 328                         dmc_offset = package_header->fw_info[i].offset;
 329         }
 330         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 331                 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
 332                 goto out;
 333         }
 334         readcount += dmc_offset;
 335
 336         /* Extract dmc_header information. */
 337         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 338         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 339                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 340                                 (dmc_header->header_len));
 341                 goto out;
 342         }
 343         readcount += sizeof(struct intel_dmc_header);
 344
 345         /* Cache the dmc header info. */
 346         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 347                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 348                                                 dmc_header->mmio_count);
 349                 goto out;
 350         }
 351         csr->mmio_count = dmc_header->mmio_count;
 352         for (i = 0; i < dmc_header->mmio_count; i++) {
 353                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE &&
 354                         dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 355                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 356                                                 dmc_header->mmioaddr[i]);
 357                         goto out;
 358                 }
 359                 csr->mmioaddr[i] = dmc_header->mmioaddr[i];
 360                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 361         }
 362
 363         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 364         nbytes = dmc_header->fw_size * 4;
 365         if (nbytes > CSR_MAX_FW_SIZE) {
 366                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 367                 goto out;
 368         }
 369         csr->dmc_fw_size = dmc_header->fw_size;
 370
 371         csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 372         if (!csr->dmc_payload) {
 373                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 374                 goto out;
 375         }
 376
 377         dmc_payload = csr->dmc_payload;
 378         memcpy(dmc_payload, &fw->data[readcount], nbytes);
 379
 380         /* load csr program during system boot, as needed for DC states */
 381         intel_csr_load_program(dev);
 382         fw_loaded = true;
 383
 384         DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
 385 out:
 386         if (fw_loaded)
 387                 intel_runtime_pm_put(dev_priv);
 388         else
 389                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 390
 391         release_firmware(fw);
 392 }
 393
 394 /**
 395  * intel_csr_ucode_init() - initialize the firmware loading.
 396  * @dev: drm device.
 397  *
 398  * This function is called at the time of loading the display driver to read
 399  * firmware from a .bin file and copied into a internal memory.
 400  */
 401 void intel_csr_ucode_init(struct drm_device *dev)
 402 {
 403         struct drm_i915_private *dev_priv = dev->dev_private;
 404         struct intel_csr *csr = &dev_priv->csr;
 405         int ret;
 406
 407         if (!HAS_CSR(dev))
 408                 return;
 409
 410         if (IS_SKYLAKE(dev))
 411                 csr->fw_path = I915_CSR_SKL;
 412         else {
 413                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 414                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 415                 return;
 416         }
 417
 418         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 419
 420         /*
 421          * Obtain a runtime pm reference, until CSR is loaded,
 422          * to avoid entering runtime-suspend.
 423          */
 424         intel_runtime_pm_get(dev_priv);
 425
 426         /* CSR supported for platform, load firmware */
 427         ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path,
 428                                 &dev_priv->dev->pdev->dev,
 429                                 GFP_KERNEL, dev_priv,
 430                                 finish_csr_load);
 431         if (ret) {
 432                 i915_firmware_load_error_print(csr->fw_path, ret);
 433                 intel_csr_load_status_set(dev_priv, FW_FAILED);
 434         }
 435 }
 436
 437 /**
 438  * intel_csr_ucode_fini() - unload the CSR firmware.
 439  * @dev: drm device.
 440  *
 441  * Firmmware unloading includes freeing the internal momory and reset the
 442  * firmware loading status.
 443  */
 444 void intel_csr_ucode_fini(struct drm_device *dev)
 445 {
 446         struct drm_i915_private *dev_priv = dev->dev_private;
 447
 448         if (!HAS_CSR(dev))
 449                 return;
 450
 451         intel_csr_load_status_set(dev_priv, FW_FAILED);
 452         kfree(dev_priv->csr.dmc_payload);
 453 }
 454
 455 void assert_csr_loaded(struct drm_i915_private *dev_priv)
 456 {
 457         WARN(intel_csr_load_status_get(dev_priv) != FW_LOADED,
 458              "CSR is not loaded.\n");
 459         WARN(!I915_READ(CSR_PROGRAM_BASE),
 460                                 "CSR program storage start is NULL\n");
 461         WARN(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 462         WARN(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 463 }