drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  56 {
  57         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  58
  59         return intel_dig_port->base.base.dev;
  60 }
  61
  62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  63 {
  64         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  65 }
  66
  67 static void intel_dp_link_down(struct intel_dp *intel_dp);
  68
  69 static int
  70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  71 {
  72         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  73
  74         switch (max_link_bw) {
  75         case DP_LINK_BW_1_62:
  76         case DP_LINK_BW_2_7:
  77                 break;
  78         default:
  79                 max_link_bw = DP_LINK_BW_1_62;
  80                 break;
  81         }
  82         return max_link_bw;
  83 }
  84
  85 /*
  86  * The units on the numbers in the next two are... bizarre.  Examples will
  87  * make it clearer; this one parallels an example in the eDP spec.
  88  *
  89  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  90  *
  91  *     270000 * 1 * 8 / 10 == 216000
  92  *
  93  * The actual data capacity of that configuration is 2.16Gbit/s, so the
  94  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
  95  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
  96  * 119000.  At 18bpp that's 2142000 kilobits per second.
  97  *
  98  * Thus the strange-looking division by 10 in intel_dp_link_required, to
  99  * get the result in decakilobits instead of kilobits.
 100  */
 101
 102 static int
 103 intel_dp_link_required(int pixel_clock, int bpp)
 104 {
 105         return (pixel_clock * bpp + 9) / 10;
 106 }
 107
 108 static int
 109 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 110 {
 111         return (max_link_clock * max_lanes * 8) / 10;
 112 }
 113
 114 static int
 115 intel_dp_mode_valid(struct drm_connector *connector,
 116                     struct drm_display_mode *mode)
 117 {
 118         struct intel_dp *intel_dp = intel_attached_dp(connector);
 119         struct intel_connector *intel_connector = to_intel_connector(connector);
 120         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 121         int target_clock = mode->clock;
 122         int max_rate, mode_rate, max_lanes, max_link_clock;
 123
 124         if (is_edp(intel_dp) && fixed_mode) {
 125                 if (mode->hdisplay > fixed_mode->hdisplay)
 126                         return MODE_PANEL;
 127
 128                 if (mode->vdisplay > fixed_mode->vdisplay)
 129                         return MODE_PANEL;
 130
 131                 target_clock = fixed_mode->clock;
 132         }
 133
 134         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 135         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 136
 137         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 138         mode_rate = intel_dp_link_required(target_clock, 18);
 139
 140         if (mode_rate > max_rate)
 141                 return MODE_CLOCK_HIGH;
 142
 143         if (mode->clock < 10000)
 144                 return MODE_CLOCK_LOW;
 145
 146         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 147                 return MODE_H_ILLEGAL;
 148
 149         return MODE_OK;
 150 }
 151
 152 static uint32_t
 153 pack_aux(uint8_t *src, int src_bytes)
 154 {
 155         int     i;
 156         uint32_t v = 0;
 157
 158         if (src_bytes > 4)
 159                 src_bytes = 4;
 160         for (i = 0; i < src_bytes; i++)
 161                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 162         return v;
 163 }
 164
 165 static void
 166 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 167 {
 168         int i;
 169         if (dst_bytes > 4)
 170                 dst_bytes = 4;
 171         for (i = 0; i < dst_bytes; i++)
 172                 dst[i] = src >> ((3-i) * 8);
 173 }
 174
 175 /* hrawclock is 1/4 the FSB frequency */
 176 static int
 177 intel_hrawclk(struct drm_device *dev)
 178 {
 179         struct drm_i915_private *dev_priv = dev->dev_private;
 180         uint32_t clkcfg;
 181
 182         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 183         if (IS_VALLEYVIEW(dev))
 184                 return 200;
 185
 186         clkcfg = I915_READ(CLKCFG);
 187         switch (clkcfg & CLKCFG_FSB_MASK) {
 188         case CLKCFG_FSB_400:
 189                 return 100;
 190         case CLKCFG_FSB_533:
 191                 return 133;
 192         case CLKCFG_FSB_667:
 193                 return 166;
 194         case CLKCFG_FSB_800:
 195                 return 200;
 196         case CLKCFG_FSB_1067:
 197                 return 266;
 198         case CLKCFG_FSB_1333:
 199                 return 333;
 200         /* these two are just a guess; one of them might be right */
 201         case CLKCFG_FSB_1600:
 202         case CLKCFG_FSB_1600_ALT:
 203                 return 400;
 204         default:
 205                 return 133;
 206         }
 207 }
 208
 209 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 210 {
 211         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         u32 pp_stat_reg;
 214
 215         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 216         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 217 }
 218
 219 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 220 {
 221         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         u32 pp_ctrl_reg;
 224
 225         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 226         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 227 }
 228
 229 static void
 230 intel_dp_check_edp(struct intel_dp *intel_dp)
 231 {
 232         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 233         struct drm_i915_private *dev_priv = dev->dev_private;
 234         u32 pp_stat_reg, pp_ctrl_reg;
 235
 236         if (!is_edp(intel_dp))
 237                 return;
 238
 239         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 240         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 241
 242         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 243                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 244                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 245                                 I915_READ(pp_stat_reg),
 246                                 I915_READ(pp_ctrl_reg));
 247         }
 248 }
 249
 250 static uint32_t
 251 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 252 {
 253         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 254         struct drm_device *dev = intel_dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 257         uint32_t status;
 258         bool done;
 259
 260 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 261         if (has_aux_irq)
 262                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 263                                           msecs_to_jiffies_timeout(10));
 264         else
 265                 done = wait_for_atomic(C, 10) == 0;
 266         if (!done)
 267                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 268                           has_aux_irq);
 269 #undef C
 270
 271         return status;
 272 }
 273
 274 static int
 275 intel_dp_aux_ch(struct intel_dp *intel_dp,
 276                 uint8_t *send, int send_bytes,
 277                 uint8_t *recv, int recv_size)
 278 {
 279         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 280         struct drm_device *dev = intel_dig_port->base.base.dev;
 281         struct drm_i915_private *dev_priv = dev->dev_private;
 282         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 283         uint32_t ch_data = ch_ctl + 4;
 284         int i, ret, recv_bytes;
 285         uint32_t status;
 286         uint32_t aux_clock_divider;
 287         int try, precharge;
 288         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 289
 290         /* dp aux is extremely sensitive to irq latency, hence request the
 291          * lowest possible wakeup latency and so prevent the cpu from going into
 292          * deep sleep states.
 293          */
 294         pm_qos_update_request(&dev_priv->pm_qos, 0);
 295
 296         intel_dp_check_edp(intel_dp);
 297         /* The clock divider is based off the hrawclk,
 298          * and would like to run at 2MHz. So, take the
 299          * hrawclk value and divide by 2 and use that
 300          *
 301          * Note that PCH attached eDP panels should use a 125MHz input
 302          * clock divider.
 303          */
 304         if (IS_VALLEYVIEW(dev)) {
 305                 aux_clock_divider = 100;
 306         } else if (intel_dig_port->port == PORT_A) {
 307                 if (HAS_DDI(dev))
 308                         aux_clock_divider = DIV_ROUND_CLOSEST(
 309                                 intel_ddi_get_cdclk_freq(dev_priv), 2000);
 310                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 311                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 312                 else
 313                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 314         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 315                 /* Workaround for non-ULT HSW */
 316                 aux_clock_divider = 74;
 317         } else if (HAS_PCH_SPLIT(dev)) {
 318                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 319         } else {
 320                 aux_clock_divider = intel_hrawclk(dev) / 2;
 321         }
 322
 323         if (IS_GEN6(dev))
 324                 precharge = 3;
 325         else
 326                 precharge = 5;
 327
 328         /* Try to wait for any previous AUX channel activity */
 329         for (try = 0; try < 3; try++) {
 330                 status = I915_READ_NOTRACE(ch_ctl);
 331                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 332                         break;
 333                 msleep(1);
 334         }
 335
 336         if (try == 3) {
 337                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 338                      I915_READ(ch_ctl));
 339                 ret = -EBUSY;
 340                 goto out;
 341         }
 342
 343         /* Must try at least 3 times according to DP spec */
 344         for (try = 0; try < 5; try++) {
 345                 /* Load the send data into the aux channel data registers */
 346                 for (i = 0; i < send_bytes; i += 4)
 347                         I915_WRITE(ch_data + i,
 348                                    pack_aux(send + i, send_bytes - i));
 349
 350                 /* Send the command and wait for it to complete */
 351                 I915_WRITE(ch_ctl,
 352                            DP_AUX_CH_CTL_SEND_BUSY |
 353                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 354                            DP_AUX_CH_CTL_TIME_OUT_400us |
 355                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 356                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 357                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 358                            DP_AUX_CH_CTL_DONE |
 359                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 360                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 361
 362                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 363
 364                 /* Clear done status and any errors */
 365                 I915_WRITE(ch_ctl,
 366                            status |
 367                            DP_AUX_CH_CTL_DONE |
 368                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 369                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 370
 371                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 372                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 373                         continue;
 374                 if (status & DP_AUX_CH_CTL_DONE)
 375                         break;
 376         }
 377
 378         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 379                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 380                 ret = -EBUSY;
 381                 goto out;
 382         }
 383
 384         /* Check for timeout or receive error.
 385          * Timeouts occur when the sink is not connected
 386          */
 387         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 388                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 389                 ret = -EIO;
 390                 goto out;
 391         }
 392
 393         /* Timeouts occur when the device isn't connected, so they're
 394          * "normal" -- don't fill the kernel log with these */
 395         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 396                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 397                 ret = -ETIMEDOUT;
 398                 goto out;
 399         }
 400
 401         /* Unload any bytes sent back from the other side */
 402         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 403                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 404         if (recv_bytes > recv_size)
 405                 recv_bytes = recv_size;
 406
 407         for (i = 0; i < recv_bytes; i += 4)
 408                 unpack_aux(I915_READ(ch_data + i),
 409                            recv + i, recv_bytes - i);
 410
 411         ret = recv_bytes;
 412 out:
 413         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 414
 415         return ret;
 416 }
 417
 418 /* Write data to the aux channel in native mode */
 419 static int
 420 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 421                           uint16_t address, uint8_t *send, int send_bytes)
 422 {
 423         int ret;
 424         uint8_t msg[20];
 425         int msg_bytes;
 426         uint8_t ack;
 427
 428         intel_dp_check_edp(intel_dp);
 429         if (send_bytes > 16)
 430                 return -1;
 431         msg[0] = AUX_NATIVE_WRITE << 4;
 432         msg[1] = address >> 8;
 433         msg[2] = address & 0xff;
 434         msg[3] = send_bytes - 1;
 435         memcpy(&msg[4], send, send_bytes);
 436         msg_bytes = send_bytes + 4;
 437         for (;;) {
 438                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 439                 if (ret < 0)
 440                         return ret;
 441                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 442                         break;
 443                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 444                         udelay(100);
 445                 else
 446                         return -EIO;
 447         }
 448         return send_bytes;
 449 }
 450
 451 /* Write a single byte to the aux channel in native mode */
 452 static int
 453 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 454                             uint16_t address, uint8_t byte)
 455 {
 456         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 457 }
 458
 459 /* read bytes from a native aux channel */
 460 static int
 461 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 462                          uint16_t address, uint8_t *recv, int recv_bytes)
 463 {
 464         uint8_t msg[4];
 465         int msg_bytes;
 466         uint8_t reply[20];
 467         int reply_bytes;
 468         uint8_t ack;
 469         int ret;
 470
 471         intel_dp_check_edp(intel_dp);
 472         msg[0] = AUX_NATIVE_READ << 4;
 473         msg[1] = address >> 8;
 474         msg[2] = address & 0xff;
 475         msg[3] = recv_bytes - 1;
 476
 477         msg_bytes = 4;
 478         reply_bytes = recv_bytes + 1;
 479
 480         for (;;) {
 481                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 482                                       reply, reply_bytes);
 483                 if (ret == 0)
 484                         return -EPROTO;
 485                 if (ret < 0)
 486                         return ret;
 487                 ack = reply[0];
 488                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 489                         memcpy(recv, reply + 1, ret - 1);
 490                         return ret - 1;
 491                 }
 492                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 493                         udelay(100);
 494                 else
 495                         return -EIO;
 496         }
 497 }
 498
 499 static int
 500 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 501                     uint8_t write_byte, uint8_t *read_byte)
 502 {
 503         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 504         struct intel_dp *intel_dp = container_of(adapter,
 505                                                 struct intel_dp,
 506                                                 adapter);
 507         uint16_t address = algo_data->address;
 508         uint8_t msg[5];
 509         uint8_t reply[2];
 510         unsigned retry;
 511         int msg_bytes;
 512         int reply_bytes;
 513         int ret;
 514
 515         intel_dp_check_edp(intel_dp);
 516         /* Set up the command byte */
 517         if (mode & MODE_I2C_READ)
 518                 msg[0] = AUX_I2C_READ << 4;
 519         else
 520                 msg[0] = AUX_I2C_WRITE << 4;
 521
 522         if (!(mode & MODE_I2C_STOP))
 523                 msg[0] |= AUX_I2C_MOT << 4;
 524
 525         msg[1] = address >> 8;
 526         msg[2] = address;
 527
 528         switch (mode) {
 529         case MODE_I2C_WRITE:
 530                 msg[3] = 0;
 531                 msg[4] = write_byte;
 532                 msg_bytes = 5;
 533                 reply_bytes = 1;
 534                 break;
 535         case MODE_I2C_READ:
 536                 msg[3] = 0;
 537                 msg_bytes = 4;
 538                 reply_bytes = 2;
 539                 break;
 540         default:
 541                 msg_bytes = 3;
 542                 reply_bytes = 1;
 543                 break;
 544         }
 545
 546         for (retry = 0; retry < 5; retry++) {
 547                 ret = intel_dp_aux_ch(intel_dp,
 548                                       msg, msg_bytes,
 549                                       reply, reply_bytes);
 550                 if (ret < 0) {
 551                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 552                         return ret;
 553                 }
 554
 555                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 556                 case AUX_NATIVE_REPLY_ACK:
 557                         /* I2C-over-AUX Reply field is only valid
 558                          * when paired with AUX ACK.
 559                          */
 560                         break;
 561                 case AUX_NATIVE_REPLY_NACK:
 562                         DRM_DEBUG_KMS("aux_ch native nack\n");
 563                         return -EREMOTEIO;
 564                 case AUX_NATIVE_REPLY_DEFER:
 565                         udelay(100);
 566                         continue;
 567                 default:
 568                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 569                                   reply[0]);
 570                         return -EREMOTEIO;
 571                 }
 572
 573                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 574                 case AUX_I2C_REPLY_ACK:
 575                         if (mode == MODE_I2C_READ) {
 576                                 *read_byte = reply[1];
 577                         }
 578                         return reply_bytes - 1;
 579                 case AUX_I2C_REPLY_NACK:
 580                         DRM_DEBUG_KMS("aux_i2c nack\n");
 581                         return -EREMOTEIO;
 582                 case AUX_I2C_REPLY_DEFER:
 583                         DRM_DEBUG_KMS("aux_i2c defer\n");
 584                         udelay(100);
 585                         break;
 586                 default:
 587                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 588                         return -EREMOTEIO;
 589                 }
 590         }
 591
 592         DRM_ERROR("too many retries, giving up\n");
 593         return -EREMOTEIO;
 594 }
 595
 596 static int
 597 intel_dp_i2c_init(struct intel_dp *intel_dp,
 598                   struct intel_connector *intel_connector, const char *name)
 599 {
 600         int     ret;
 601
 602         DRM_DEBUG_KMS("i2c_init %s\n", name);
 603         intel_dp->algo.running = false;
 604         intel_dp->algo.address = 0;
 605         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 606
 607         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 608         intel_dp->adapter.owner = THIS_MODULE;
 609         intel_dp->adapter.class = I2C_CLASS_DDC;
 610         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 611         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 612         intel_dp->adapter.algo_data = &intel_dp->algo;
 613         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 614
 615         ironlake_edp_panel_vdd_on(intel_dp);
 616         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 617         ironlake_edp_panel_vdd_off(intel_dp, false);
 618         return ret;
 619 }
 620
 621 static void
 622 intel_dp_set_clock(struct intel_encoder *encoder,
 623                    struct intel_crtc_config *pipe_config, int link_bw)
 624 {
 625         struct drm_device *dev = encoder->base.dev;
 626
 627         if (IS_G4X(dev)) {
 628                 if (link_bw == DP_LINK_BW_1_62) {
 629                         pipe_config->dpll.p1 = 2;
 630                         pipe_config->dpll.p2 = 10;
 631                         pipe_config->dpll.n = 2;
 632                         pipe_config->dpll.m1 = 23;
 633                         pipe_config->dpll.m2 = 8;
 634                 } else {
 635                         pipe_config->dpll.p1 = 1;
 636                         pipe_config->dpll.p2 = 10;
 637                         pipe_config->dpll.n = 1;
 638                         pipe_config->dpll.m1 = 14;
 639                         pipe_config->dpll.m2 = 2;
 640                 }
 641                 pipe_config->clock_set = true;
 642         } else if (IS_HASWELL(dev)) {
 643                 /* Haswell has special-purpose DP DDI clocks. */
 644         } else if (HAS_PCH_SPLIT(dev)) {
 645                 if (link_bw == DP_LINK_BW_1_62) {
 646                         pipe_config->dpll.n = 1;
 647                         pipe_config->dpll.p1 = 2;
 648                         pipe_config->dpll.p2 = 10;
 649                         pipe_config->dpll.m1 = 12;
 650                         pipe_config->dpll.m2 = 9;
 651                 } else {
 652                         pipe_config->dpll.n = 2;
 653                         pipe_config->dpll.p1 = 1;
 654                         pipe_config->dpll.p2 = 10;
 655                         pipe_config->dpll.m1 = 14;
 656                         pipe_config->dpll.m2 = 8;
 657                 }
 658                 pipe_config->clock_set = true;
 659         } else if (IS_VALLEYVIEW(dev)) {
 660                 /* FIXME: Need to figure out optimized DP clocks for vlv. */
 661         }
 662 }
 663
 664 bool
 665 intel_dp_compute_config(struct intel_encoder *encoder,
 666                         struct intel_crtc_config *pipe_config)
 667 {
 668         struct drm_device *dev = encoder->base.dev;
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 671         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 672         enum port port = dp_to_dig_port(intel_dp)->port;
 673         struct intel_crtc *intel_crtc = encoder->new_crtc;
 674         struct intel_connector *intel_connector = intel_dp->attached_connector;
 675         int lane_count, clock;
 676         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 677         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 678         int bpp, mode_rate;
 679         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 680         int link_avail, link_clock;
 681
 682         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 683                 pipe_config->has_pch_encoder = true;
 684
 685         pipe_config->has_dp_encoder = true;
 686
 687         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 688                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 689                                        adjusted_mode);
 690                 if (!HAS_PCH_SPLIT(dev))
 691                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 692                                                  intel_connector->panel.fitting_mode);
 693                 else
 694                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 695                                                 intel_connector->panel.fitting_mode);
 696         }
 697
 698         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 699                 return false;
 700
 701         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 702                       "max bw %02x pixel clock %iKHz\n",
 703                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 704
 705         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 706          * bpc in between. */
 707         bpp = pipe_config->pipe_bpp;
 708         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
 709                 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
 710
 711         for (; bpp >= 6*3; bpp -= 2*3) {
 712                 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 713
 714                 for (clock = 0; clock <= max_clock; clock++) {
 715                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 716                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 717                                 link_avail = intel_dp_max_data_rate(link_clock,
 718                                                                     lane_count);
 719
 720                                 if (mode_rate <= link_avail) {
 721                                         goto found;
 722                                 }
 723                         }
 724                 }
 725         }
 726
 727         return false;
 728
 729 found:
 730         if (intel_dp->color_range_auto) {
 731                 /*
 732                  * See:
 733                  * CEA-861-E - 5.1 Default Encoding Parameters
 734                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 735                  */
 736                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 737                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 738                 else
 739                         intel_dp->color_range = 0;
 740         }
 741
 742         if (intel_dp->color_range)
 743                 pipe_config->limited_color_range = true;
 744
 745         intel_dp->link_bw = bws[clock];
 746         intel_dp->lane_count = lane_count;
 747         pipe_config->pipe_bpp = bpp;
 748         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 749
 750         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 751                       intel_dp->link_bw, intel_dp->lane_count,
 752                       pipe_config->port_clock, bpp);
 753         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 754                       mode_rate, link_avail);
 755
 756         intel_link_compute_m_n(bpp, lane_count,
 757                                adjusted_mode->clock, pipe_config->port_clock,
 758                                &pipe_config->dp_m_n);
 759
 760         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 761
 762         return true;
 763 }
 764
 765 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 766 {
 767         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 768         intel_dp->link_configuration[0] = intel_dp->link_bw;
 769         intel_dp->link_configuration[1] = intel_dp->lane_count;
 770         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 771         /*
 772          * Check for DPCD version > 1.1 and enhanced framing support
 773          */
 774         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 775             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 776                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 777         }
 778 }
 779
 780 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 781 {
 782         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 783         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 784         struct drm_device *dev = crtc->base.dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         u32 dpa_ctl;
 787
 788         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 789         dpa_ctl = I915_READ(DP_A);
 790         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 791
 792         if (crtc->config.port_clock == 162000) {
 793                 /* For a long time we've carried around a ILK-DevA w/a for the
 794                  * 160MHz clock. If we're really unlucky, it's still required.
 795                  */
 796                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 797                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 798                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 799         } else {
 800                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 801                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 802         }
 803
 804         I915_WRITE(DP_A, dpa_ctl);
 805
 806         POSTING_READ(DP_A);
 807         udelay(500);
 808 }
 809
 810 static void
 811 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 812                   struct drm_display_mode *adjusted_mode)
 813 {
 814         struct drm_device *dev = encoder->dev;
 815         struct drm_i915_private *dev_priv = dev->dev_private;
 816         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 817         enum port port = dp_to_dig_port(intel_dp)->port;
 818         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 819
 820         /*
 821          * There are four kinds of DP registers:
 822          *
 823          *      IBX PCH
 824          *      SNB CPU
 825          *      IVB CPU
 826          *      CPT PCH
 827          *
 828          * IBX PCH and CPU are the same for almost everything,
 829          * except that the CPU DP PLL is configured in this
 830          * register
 831          *
 832          * CPT PCH is quite different, having many bits moved
 833          * to the TRANS_DP_CTL register instead. That
 834          * configuration happens (oddly) in ironlake_pch_enable
 835          */
 836
 837         /* Preserve the BIOS-computed detected bit. This is
 838          * supposed to be read-only.
 839          */
 840         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 841
 842         /* Handle DP bits in common between all three register formats */
 843         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 844         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 845
 846         if (intel_dp->has_audio) {
 847                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 848                                  pipe_name(crtc->pipe));
 849                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 850                 intel_write_eld(encoder, adjusted_mode);
 851         }
 852
 853         intel_dp_init_link_config(intel_dp);
 854
 855         /* Split out the IBX/CPU vs CPT settings */
 856
 857         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 858                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 859                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 860                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 861                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 862                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 863
 864                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 865                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 866
 867                 intel_dp->DP |= crtc->pipe << 29;
 868         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 869                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 870                         intel_dp->DP |= intel_dp->color_range;
 871
 872                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 873                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 874                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 875                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 876                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 877
 878                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 879                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 880
 881                 if (crtc->pipe == 1)
 882                         intel_dp->DP |= DP_PIPEB_SELECT;
 883         } else {
 884                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 885         }
 886
 887         if (port == PORT_A && !IS_VALLEYVIEW(dev))
 888                 ironlake_set_pll_cpu_edp(intel_dp);
 889 }
 890
 891 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 892 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 893
 894 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 895 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 896
 897 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 898 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 899
 900 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 901                                        u32 mask,
 902                                        u32 value)
 903 {
 904         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 905         struct drm_i915_private *dev_priv = dev->dev_private;
 906         u32 pp_stat_reg, pp_ctrl_reg;
 907
 908         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 909         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 910
 911         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 912                         mask, value,
 913                         I915_READ(pp_stat_reg),
 914                         I915_READ(pp_ctrl_reg));
 915
 916         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 917                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 918                                 I915_READ(pp_stat_reg),
 919                                 I915_READ(pp_ctrl_reg));
 920         }
 921 }
 922
 923 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 924 {
 925         DRM_DEBUG_KMS("Wait for panel power on\n");
 926         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 927 }
 928
 929 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 930 {
 931         DRM_DEBUG_KMS("Wait for panel power off time\n");
 932         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 933 }
 934
 935 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 936 {
 937         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 938         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 939 }
 940
 941
 942 /* Read the current pp_control value, unlocking the register if it
 943  * is locked
 944  */
 945
 946 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 947 {
 948         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950         u32 control;
 951         u32 pp_ctrl_reg;
 952
 953         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 954         control = I915_READ(pp_ctrl_reg);
 955
 956         control &= ~PANEL_UNLOCK_MASK;
 957         control |= PANEL_UNLOCK_REGS;
 958         return control;
 959 }
 960
 961 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 962 {
 963         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 964         struct drm_i915_private *dev_priv = dev->dev_private;
 965         u32 pp;
 966         u32 pp_stat_reg, pp_ctrl_reg;
 967
 968         if (!is_edp(intel_dp))
 969                 return;
 970         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 971
 972         WARN(intel_dp->want_panel_vdd,
 973              "eDP VDD already requested on\n");
 974
 975         intel_dp->want_panel_vdd = true;
 976
 977         if (ironlake_edp_have_panel_vdd(intel_dp)) {
 978                 DRM_DEBUG_KMS("eDP VDD already on\n");
 979                 return;
 980         }
 981
 982         if (!ironlake_edp_have_panel_power(intel_dp))
 983                 ironlake_wait_panel_power_cycle(intel_dp);
 984
 985         pp = ironlake_get_pp_control(intel_dp);
 986         pp |= EDP_FORCE_VDD;
 987
 988         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 989         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 990
 991         I915_WRITE(pp_ctrl_reg, pp);
 992         POSTING_READ(pp_ctrl_reg);
 993         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 994                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 995         /*
 996          * If the panel wasn't on, delay before accessing aux channel
 997          */
 998         if (!ironlake_edp_have_panel_power(intel_dp)) {
 999                 DRM_DEBUG_KMS("eDP was not running\n");
1000                 msleep(intel_dp->panel_power_up_delay);
1001         }
1002 }
1003
1004 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1005 {
1006         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1007         struct drm_i915_private *dev_priv = dev->dev_private;
1008         u32 pp;
1009         u32 pp_stat_reg, pp_ctrl_reg;
1010
1011         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1012
1013         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1014                 pp = ironlake_get_pp_control(intel_dp);
1015                 pp &= ~EDP_FORCE_VDD;
1016
1017                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1018                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1019
1020                 I915_WRITE(pp_ctrl_reg, pp);
1021                 POSTING_READ(pp_ctrl_reg);
1022
1023                 /* Make sure sequencer is idle before allowing subsequent activity */
1024                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1025                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1026                 msleep(intel_dp->panel_power_down_delay);
1027         }
1028 }
1029
1030 static void ironlake_panel_vdd_work(struct work_struct *__work)
1031 {
1032         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1033                                                  struct intel_dp, panel_vdd_work);
1034         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1035
1036         mutex_lock(&dev->mode_config.mutex);
1037         ironlake_panel_vdd_off_sync(intel_dp);
1038         mutex_unlock(&dev->mode_config.mutex);
1039 }
1040
1041 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1042 {
1043         if (!is_edp(intel_dp))
1044                 return;
1045
1046         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1047         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1048
1049         intel_dp->want_panel_vdd = false;
1050
1051         if (sync) {
1052                 ironlake_panel_vdd_off_sync(intel_dp);
1053         } else {
1054                 /*
1055                  * Queue the timer to fire a long
1056                  * time from now (relative to the power down delay)
1057                  * to keep the panel power up across a sequence of operations
1058                  */
1059                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1060                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1061         }
1062 }
1063
1064 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1065 {
1066         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1067         struct drm_i915_private *dev_priv = dev->dev_private;
1068         u32 pp;
1069         u32 pp_ctrl_reg;
1070
1071         if (!is_edp(intel_dp))
1072                 return;
1073
1074         DRM_DEBUG_KMS("Turn eDP power on\n");
1075
1076         if (ironlake_edp_have_panel_power(intel_dp)) {
1077                 DRM_DEBUG_KMS("eDP power already on\n");
1078                 return;
1079         }
1080
1081         ironlake_wait_panel_power_cycle(intel_dp);
1082
1083         pp = ironlake_get_pp_control(intel_dp);
1084         if (IS_GEN5(dev)) {
1085                 /* ILK workaround: disable reset around power sequence */
1086                 pp &= ~PANEL_POWER_RESET;
1087                 I915_WRITE(PCH_PP_CONTROL, pp);
1088                 POSTING_READ(PCH_PP_CONTROL);
1089         }
1090
1091         pp |= POWER_TARGET_ON;
1092         if (!IS_GEN5(dev))
1093                 pp |= PANEL_POWER_RESET;
1094
1095         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1096
1097         I915_WRITE(pp_ctrl_reg, pp);
1098         POSTING_READ(pp_ctrl_reg);
1099
1100         ironlake_wait_panel_on(intel_dp);
1101
1102         if (IS_GEN5(dev)) {
1103                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1104                 I915_WRITE(PCH_PP_CONTROL, pp);
1105                 POSTING_READ(PCH_PP_CONTROL);
1106         }
1107 }
1108
1109 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1110 {
1111         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113         u32 pp;
1114         u32 pp_ctrl_reg;
1115
1116         if (!is_edp(intel_dp))
1117                 return;
1118
1119         DRM_DEBUG_KMS("Turn eDP power off\n");
1120
1121         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1122
1123         pp = ironlake_get_pp_control(intel_dp);
1124         /* We need to switch off panel power _and_ force vdd, for otherwise some
1125          * panels get very unhappy and cease to work. */
1126         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1127
1128         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1129
1130         I915_WRITE(pp_ctrl_reg, pp);
1131         POSTING_READ(pp_ctrl_reg);
1132
1133         intel_dp->want_panel_vdd = false;
1134
1135         ironlake_wait_panel_off(intel_dp);
1136 }
1137
1138 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1139 {
1140         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1141         struct drm_device *dev = intel_dig_port->base.base.dev;
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1144         u32 pp;
1145         u32 pp_ctrl_reg;
1146
1147         if (!is_edp(intel_dp))
1148                 return;
1149
1150         DRM_DEBUG_KMS("\n");
1151         /*
1152          * If we enable the backlight right away following a panel power
1153          * on, we may see slight flicker as the panel syncs with the eDP
1154          * link.  So delay a bit to make sure the image is solid before
1155          * allowing it to appear.
1156          */
1157         msleep(intel_dp->backlight_on_delay);
1158         pp = ironlake_get_pp_control(intel_dp);
1159         pp |= EDP_BLC_ENABLE;
1160
1161         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1162
1163         I915_WRITE(pp_ctrl_reg, pp);
1164         POSTING_READ(pp_ctrl_reg);
1165
1166         intel_panel_enable_backlight(dev, pipe);
1167 }
1168
1169 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1170 {
1171         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1172         struct drm_i915_private *dev_priv = dev->dev_private;
1173         u32 pp;
1174         u32 pp_ctrl_reg;
1175
1176         if (!is_edp(intel_dp))
1177                 return;
1178
1179         intel_panel_disable_backlight(dev);
1180
1181         DRM_DEBUG_KMS("\n");
1182         pp = ironlake_get_pp_control(intel_dp);
1183         pp &= ~EDP_BLC_ENABLE;
1184
1185         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1186
1187         I915_WRITE(pp_ctrl_reg, pp);
1188         POSTING_READ(pp_ctrl_reg);
1189         msleep(intel_dp->backlight_off_delay);
1190 }
1191
1192 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1193 {
1194         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1195         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1196         struct drm_device *dev = crtc->dev;
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         u32 dpa_ctl;
1199
1200         assert_pipe_disabled(dev_priv,
1201                              to_intel_crtc(crtc)->pipe);
1202
1203         DRM_DEBUG_KMS("\n");
1204         dpa_ctl = I915_READ(DP_A);
1205         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1206         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1207
1208         /* We don't adjust intel_dp->DP while tearing down the link, to
1209          * facilitate link retraining (e.g. after hotplug). Hence clear all
1210          * enable bits here to ensure that we don't enable too much. */
1211         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1212         intel_dp->DP |= DP_PLL_ENABLE;
1213         I915_WRITE(DP_A, intel_dp->DP);
1214         POSTING_READ(DP_A);
1215         udelay(200);
1216 }
1217
1218 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1219 {
1220         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222         struct drm_device *dev = crtc->dev;
1223         struct drm_i915_private *dev_priv = dev->dev_private;
1224         u32 dpa_ctl;
1225
1226         assert_pipe_disabled(dev_priv,
1227                              to_intel_crtc(crtc)->pipe);
1228
1229         dpa_ctl = I915_READ(DP_A);
1230         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1231              "dp pll off, should be on\n");
1232         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234         /* We can't rely on the value tracked for the DP register in
1235          * intel_dp->DP because link_down must not change that (otherwise link
1236          * re-training will fail. */
1237         dpa_ctl &= ~DP_PLL_ENABLE;
1238         I915_WRITE(DP_A, dpa_ctl);
1239         POSTING_READ(DP_A);
1240         udelay(200);
1241 }
1242
1243 /* If the sink supports it, try to set the power state appropriately */
1244 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1245 {
1246         int ret, i;
1247
1248         /* Should have a valid DPCD by this point */
1249         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1250                 return;
1251
1252         if (mode != DRM_MODE_DPMS_ON) {
1253                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1254                                                   DP_SET_POWER_D3);
1255                 if (ret != 1)
1256                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1257         } else {
1258                 /*
1259                  * When turning on, we need to retry for 1ms to give the sink
1260                  * time to wake up.
1261                  */
1262                 for (i = 0; i < 3; i++) {
1263                         ret = intel_dp_aux_native_write_1(intel_dp,
1264                                                           DP_SET_POWER,
1265                                                           DP_SET_POWER_D0);
1266                         if (ret == 1)
1267                                 break;
1268                         msleep(1);
1269                 }
1270         }
1271 }
1272
1273 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1274                                   enum pipe *pipe)
1275 {
1276         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1277         enum port port = dp_to_dig_port(intel_dp)->port;
1278         struct drm_device *dev = encoder->base.dev;
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280         u32 tmp = I915_READ(intel_dp->output_reg);
1281
1282         if (!(tmp & DP_PORT_EN))
1283                 return false;
1284
1285         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1286                 *pipe = PORT_TO_PIPE_CPT(tmp);
1287         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1288                 *pipe = PORT_TO_PIPE(tmp);
1289         } else {
1290                 u32 trans_sel;
1291                 u32 trans_dp;
1292                 int i;
1293
1294                 switch (intel_dp->output_reg) {
1295                 case PCH_DP_B:
1296                         trans_sel = TRANS_DP_PORT_SEL_B;
1297                         break;
1298                 case PCH_DP_C:
1299                         trans_sel = TRANS_DP_PORT_SEL_C;
1300                         break;
1301                 case PCH_DP_D:
1302                         trans_sel = TRANS_DP_PORT_SEL_D;
1303                         break;
1304                 default:
1305                         return true;
1306                 }
1307
1308                 for_each_pipe(i) {
1309                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1310                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1311                                 *pipe = i;
1312                                 return true;
1313                         }
1314                 }
1315
1316                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1317                               intel_dp->output_reg);
1318         }
1319
1320         return true;
1321 }
1322
1323 static void intel_dp_get_config(struct intel_encoder *encoder,
1324                                 struct intel_crtc_config *pipe_config)
1325 {
1326         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1327         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1328         u32 tmp, flags = 0;
1329
1330         tmp = I915_READ(intel_dp->output_reg);
1331
1332         if (tmp & DP_SYNC_HS_HIGH)
1333                 flags |= DRM_MODE_FLAG_PHSYNC;
1334         else
1335                 flags |= DRM_MODE_FLAG_NHSYNC;
1336
1337         if (tmp & DP_SYNC_VS_HIGH)
1338                 flags |= DRM_MODE_FLAG_PVSYNC;
1339         else
1340                 flags |= DRM_MODE_FLAG_NVSYNC;
1341
1342         pipe_config->adjusted_mode.flags |= flags;
1343 }
1344
1345 static void intel_disable_dp(struct intel_encoder *encoder)
1346 {
1347         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1348         enum port port = dp_to_dig_port(intel_dp)->port;
1349         struct drm_device *dev = encoder->base.dev;
1350
1351         /* Make sure the panel is off before trying to change the mode. But also
1352          * ensure that we have vdd while we switch off the panel. */
1353         ironlake_edp_panel_vdd_on(intel_dp);
1354         ironlake_edp_backlight_off(intel_dp);
1355         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1356         ironlake_edp_panel_off(intel_dp);
1357
1358         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1359         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1360                 intel_dp_link_down(intel_dp);
1361 }
1362
1363 static void intel_post_disable_dp(struct intel_encoder *encoder)
1364 {
1365         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1366         enum port port = dp_to_dig_port(intel_dp)->port;
1367         struct drm_device *dev = encoder->base.dev;
1368
1369         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1370                 intel_dp_link_down(intel_dp);
1371                 if (!IS_VALLEYVIEW(dev))
1372                         ironlake_edp_pll_off(intel_dp);
1373         }
1374 }
1375
1376 static void intel_enable_dp(struct intel_encoder *encoder)
1377 {
1378         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379         struct drm_device *dev = encoder->base.dev;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1382
1383         if (WARN_ON(dp_reg & DP_PORT_EN))
1384                 return;
1385
1386         ironlake_edp_panel_vdd_on(intel_dp);
1387         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1388         intel_dp_start_link_train(intel_dp);
1389         ironlake_edp_panel_on(intel_dp);
1390         ironlake_edp_panel_vdd_off(intel_dp, true);
1391         intel_dp_complete_link_train(intel_dp);
1392         intel_dp_stop_link_train(intel_dp);
1393         ironlake_edp_backlight_on(intel_dp);
1394
1395         if (IS_VALLEYVIEW(dev)) {
1396                 struct intel_digital_port *dport =
1397                         enc_to_dig_port(&encoder->base);
1398                 int channel = vlv_dport_to_channel(dport);
1399
1400                 vlv_wait_port_ready(dev_priv, channel);
1401         }
1402 }
1403
1404 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1405 {
1406         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1407         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1408         struct drm_device *dev = encoder->base.dev;
1409         struct drm_i915_private *dev_priv = dev->dev_private;
1410
1411         if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1412                 ironlake_edp_pll_on(intel_dp);
1413
1414         if (IS_VALLEYVIEW(dev)) {
1415                 struct intel_crtc *intel_crtc =
1416                         to_intel_crtc(encoder->base.crtc);
1417                 int port = vlv_dport_to_channel(dport);
1418                 int pipe = intel_crtc->pipe;
1419                 u32 val;
1420
1421                 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1422                 val = 0;
1423                 if (pipe)
1424                         val |= (1<<21);
1425                 else
1426                         val &= ~(1<<21);
1427                 val |= 0x001000c4;
1428                 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1429
1430                 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1431                                  0x00760018);
1432                 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1433                                  0x00400888);
1434         }
1435 }
1436
1437 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1438 {
1439         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1440         struct drm_device *dev = encoder->base.dev;
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         int port = vlv_dport_to_channel(dport);
1443
1444         if (!IS_VALLEYVIEW(dev))
1445                 return;
1446
1447         /* Program Tx lane resets to default */
1448         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1449                          DPIO_PCS_TX_LANE2_RESET |
1450                          DPIO_PCS_TX_LANE1_RESET);
1451         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1452                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1453                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1454                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1455                                  DPIO_PCS_CLK_SOFT_RESET);
1456
1457         /* Fix up inter-pair skew failure */
1458         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1459         vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1460         vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1461 }
1462
1463 /*
1464  * Native read with retry for link status and receiver capability reads for
1465  * cases where the sink may still be asleep.
1466  */
1467 static bool
1468 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1469                                uint8_t *recv, int recv_bytes)
1470 {
1471         int ret, i;
1472
1473         /*
1474          * Sinks are *supposed* to come up within 1ms from an off state,
1475          * but we're also supposed to retry 3 times per the spec.
1476          */
1477         for (i = 0; i < 3; i++) {
1478                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1479                                                recv_bytes);
1480                 if (ret == recv_bytes)
1481                         return true;
1482                 msleep(1);
1483         }
1484
1485         return false;
1486 }
1487
1488 /*
1489  * Fetch AUX CH registers 0x202 - 0x207 which contain
1490  * link status information
1491  */
1492 static bool
1493 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1494 {
1495         return intel_dp_aux_native_read_retry(intel_dp,
1496                                               DP_LANE0_1_STATUS,
1497                                               link_status,
1498                                               DP_LINK_STATUS_SIZE);
1499 }
1500
1501 #if 0
1502 static char     *voltage_names[] = {
1503         "0.4V", "0.6V", "0.8V", "1.2V"
1504 };
1505 static char     *pre_emph_names[] = {
1506         "0dB", "3.5dB", "6dB", "9.5dB"
1507 };
1508 static char     *link_train_names[] = {
1509         "pattern 1", "pattern 2", "idle", "off"
1510 };
1511 #endif
1512
1513 /*
1514  * These are source-specific values; current Intel hardware supports
1515  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1516  */
1517
1518 static uint8_t
1519 intel_dp_voltage_max(struct intel_dp *intel_dp)
1520 {
1521         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1522         enum port port = dp_to_dig_port(intel_dp)->port;
1523
1524         if (IS_VALLEYVIEW(dev))
1525                 return DP_TRAIN_VOLTAGE_SWING_1200;
1526         else if (IS_GEN7(dev) && port == PORT_A)
1527                 return DP_TRAIN_VOLTAGE_SWING_800;
1528         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1529                 return DP_TRAIN_VOLTAGE_SWING_1200;
1530         else
1531                 return DP_TRAIN_VOLTAGE_SWING_800;
1532 }
1533
1534 static uint8_t
1535 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1536 {
1537         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1538         enum port port = dp_to_dig_port(intel_dp)->port;
1539
1540         if (HAS_DDI(dev)) {
1541                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1542                 case DP_TRAIN_VOLTAGE_SWING_400:
1543                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1544                 case DP_TRAIN_VOLTAGE_SWING_600:
1545                         return DP_TRAIN_PRE_EMPHASIS_6;
1546                 case DP_TRAIN_VOLTAGE_SWING_800:
1547                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1548                 case DP_TRAIN_VOLTAGE_SWING_1200:
1549                 default:
1550                         return DP_TRAIN_PRE_EMPHASIS_0;
1551                 }
1552         } else if (IS_VALLEYVIEW(dev)) {
1553                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1554                 case DP_TRAIN_VOLTAGE_SWING_400:
1555                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1556                 case DP_TRAIN_VOLTAGE_SWING_600:
1557                         return DP_TRAIN_PRE_EMPHASIS_6;
1558                 case DP_TRAIN_VOLTAGE_SWING_800:
1559                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1560                 case DP_TRAIN_VOLTAGE_SWING_1200:
1561                 default:
1562                         return DP_TRAIN_PRE_EMPHASIS_0;
1563                 }
1564         } else if (IS_GEN7(dev) && port == PORT_A) {
1565                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1566                 case DP_TRAIN_VOLTAGE_SWING_400:
1567                         return DP_TRAIN_PRE_EMPHASIS_6;
1568                 case DP_TRAIN_VOLTAGE_SWING_600:
1569                 case DP_TRAIN_VOLTAGE_SWING_800:
1570                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1571                 default:
1572                         return DP_TRAIN_PRE_EMPHASIS_0;
1573                 }
1574         } else {
1575                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576                 case DP_TRAIN_VOLTAGE_SWING_400:
1577                         return DP_TRAIN_PRE_EMPHASIS_6;
1578                 case DP_TRAIN_VOLTAGE_SWING_600:
1579                         return DP_TRAIN_PRE_EMPHASIS_6;
1580                 case DP_TRAIN_VOLTAGE_SWING_800:
1581                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1582                 case DP_TRAIN_VOLTAGE_SWING_1200:
1583                 default:
1584                         return DP_TRAIN_PRE_EMPHASIS_0;
1585                 }
1586         }
1587 }
1588
1589 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1590 {
1591         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1592         struct drm_i915_private *dev_priv = dev->dev_private;
1593         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1594         unsigned long demph_reg_value, preemph_reg_value,
1595                 uniqtranscale_reg_value;
1596         uint8_t train_set = intel_dp->train_set[0];
1597         int port = vlv_dport_to_channel(dport);
1598
1599         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1600         case DP_TRAIN_PRE_EMPHASIS_0:
1601                 preemph_reg_value = 0x0004000;
1602                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1603                 case DP_TRAIN_VOLTAGE_SWING_400:
1604                         demph_reg_value = 0x2B405555;
1605                         uniqtranscale_reg_value = 0x552AB83A;
1606                         break;
1607                 case DP_TRAIN_VOLTAGE_SWING_600:
1608                         demph_reg_value = 0x2B404040;
1609                         uniqtranscale_reg_value = 0x5548B83A;
1610                         break;
1611                 case DP_TRAIN_VOLTAGE_SWING_800:
1612                         demph_reg_value = 0x2B245555;
1613                         uniqtranscale_reg_value = 0x5560B83A;
1614                         break;
1615                 case DP_TRAIN_VOLTAGE_SWING_1200:
1616                         demph_reg_value = 0x2B405555;
1617                         uniqtranscale_reg_value = 0x5598DA3A;
1618                         break;
1619                 default:
1620                         return 0;
1621                 }
1622                 break;
1623         case DP_TRAIN_PRE_EMPHASIS_3_5:
1624                 preemph_reg_value = 0x0002000;
1625                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1626                 case DP_TRAIN_VOLTAGE_SWING_400:
1627                         demph_reg_value = 0x2B404040;
1628                         uniqtranscale_reg_value = 0x5552B83A;
1629                         break;
1630                 case DP_TRAIN_VOLTAGE_SWING_600:
1631                         demph_reg_value = 0x2B404848;
1632                         uniqtranscale_reg_value = 0x5580B83A;
1633                         break;
1634                 case DP_TRAIN_VOLTAGE_SWING_800:
1635                         demph_reg_value = 0x2B404040;
1636                         uniqtranscale_reg_value = 0x55ADDA3A;
1637                         break;
1638                 default:
1639                         return 0;
1640                 }
1641                 break;
1642         case DP_TRAIN_PRE_EMPHASIS_6:
1643                 preemph_reg_value = 0x0000000;
1644                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1645                 case DP_TRAIN_VOLTAGE_SWING_400:
1646                         demph_reg_value = 0x2B305555;
1647                         uniqtranscale_reg_value = 0x5570B83A;
1648                         break;
1649                 case DP_TRAIN_VOLTAGE_SWING_600:
1650                         demph_reg_value = 0x2B2B4040;
1651                         uniqtranscale_reg_value = 0x55ADDA3A;
1652                         break;
1653                 default:
1654                         return 0;
1655                 }
1656                 break;
1657         case DP_TRAIN_PRE_EMPHASIS_9_5:
1658                 preemph_reg_value = 0x0006000;
1659                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1660                 case DP_TRAIN_VOLTAGE_SWING_400:
1661                         demph_reg_value = 0x1B405555;
1662                         uniqtranscale_reg_value = 0x55ADDA3A;
1663                         break;
1664                 default:
1665                         return 0;
1666                 }
1667                 break;
1668         default:
1669                 return 0;
1670         }
1671
1672         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1673         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1674         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1675                          uniqtranscale_reg_value);
1676         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1677         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1678         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1679         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1680
1681         return 0;
1682 }
1683
1684 static void
1685 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1686 {
1687         uint8_t v = 0;
1688         uint8_t p = 0;
1689         int lane;
1690         uint8_t voltage_max;
1691         uint8_t preemph_max;
1692
1693         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1694                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1695                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1696
1697                 if (this_v > v)
1698                         v = this_v;
1699                 if (this_p > p)
1700                         p = this_p;
1701         }
1702
1703         voltage_max = intel_dp_voltage_max(intel_dp);
1704         if (v >= voltage_max)
1705                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1706
1707         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1708         if (p >= preemph_max)
1709                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1710
1711         for (lane = 0; lane < 4; lane++)
1712                 intel_dp->train_set[lane] = v | p;
1713 }
1714
1715 static uint32_t
1716 intel_gen4_signal_levels(uint8_t train_set)
1717 {
1718         uint32_t        signal_levels = 0;
1719
1720         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1721         case DP_TRAIN_VOLTAGE_SWING_400:
1722         default:
1723                 signal_levels |= DP_VOLTAGE_0_4;
1724                 break;
1725         case DP_TRAIN_VOLTAGE_SWING_600:
1726                 signal_levels |= DP_VOLTAGE_0_6;
1727                 break;
1728         case DP_TRAIN_VOLTAGE_SWING_800:
1729                 signal_levels |= DP_VOLTAGE_0_8;
1730                 break;
1731         case DP_TRAIN_VOLTAGE_SWING_1200:
1732                 signal_levels |= DP_VOLTAGE_1_2;
1733                 break;
1734         }
1735         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1736         case DP_TRAIN_PRE_EMPHASIS_0:
1737         default:
1738                 signal_levels |= DP_PRE_EMPHASIS_0;
1739                 break;
1740         case DP_TRAIN_PRE_EMPHASIS_3_5:
1741                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1742                 break;
1743         case DP_TRAIN_PRE_EMPHASIS_6:
1744                 signal_levels |= DP_PRE_EMPHASIS_6;
1745                 break;
1746         case DP_TRAIN_PRE_EMPHASIS_9_5:
1747                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1748                 break;
1749         }
1750         return signal_levels;
1751 }
1752
1753 /* Gen6's DP voltage swing and pre-emphasis control */
1754 static uint32_t
1755 intel_gen6_edp_signal_levels(uint8_t train_set)
1756 {
1757         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1758                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1759         switch (signal_levels) {
1760         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1761         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1762                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1763         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1764                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1765         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1766         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1767                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1768         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1769         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1770                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1771         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1772         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1773                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1774         default:
1775                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1776                               "0x%x\n", signal_levels);
1777                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1778         }
1779 }
1780
1781 /* Gen7's DP voltage swing and pre-emphasis control */
1782 static uint32_t
1783 intel_gen7_edp_signal_levels(uint8_t train_set)
1784 {
1785         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1786                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1787         switch (signal_levels) {
1788         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1789                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1790         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1791                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1792         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1793                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1794
1795         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1796                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1797         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1798                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1799
1800         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1801                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1802         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1803                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1804
1805         default:
1806                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1807                               "0x%x\n", signal_levels);
1808                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1809         }
1810 }
1811
1812 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1813 static uint32_t
1814 intel_hsw_signal_levels(uint8_t train_set)
1815 {
1816         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1817                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1818         switch (signal_levels) {
1819         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1820                 return DDI_BUF_EMP_400MV_0DB_HSW;
1821         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1822                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1823         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1824                 return DDI_BUF_EMP_400MV_6DB_HSW;
1825         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1826                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1827
1828         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1829                 return DDI_BUF_EMP_600MV_0DB_HSW;
1830         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1831                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1832         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1833                 return DDI_BUF_EMP_600MV_6DB_HSW;
1834
1835         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1836                 return DDI_BUF_EMP_800MV_0DB_HSW;
1837         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1838                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1839         default:
1840                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1841                               "0x%x\n", signal_levels);
1842                 return DDI_BUF_EMP_400MV_0DB_HSW;
1843         }
1844 }
1845
1846 /* Properly updates "DP" with the correct signal levels. */
1847 static void
1848 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1849 {
1850         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1851         enum port port = intel_dig_port->port;
1852         struct drm_device *dev = intel_dig_port->base.base.dev;
1853         uint32_t signal_levels, mask;
1854         uint8_t train_set = intel_dp->train_set[0];
1855
1856         if (HAS_DDI(dev)) {
1857                 signal_levels = intel_hsw_signal_levels(train_set);
1858                 mask = DDI_BUF_EMP_MASK;
1859         } else if (IS_VALLEYVIEW(dev)) {
1860                 signal_levels = intel_vlv_signal_levels(intel_dp);
1861                 mask = 0;
1862         } else if (IS_GEN7(dev) && port == PORT_A) {
1863                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1864                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1865         } else if (IS_GEN6(dev) && port == PORT_A) {
1866                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1867                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1868         } else {
1869                 signal_levels = intel_gen4_signal_levels(train_set);
1870                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1871         }
1872
1873         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1874
1875         *DP = (*DP & ~mask) | signal_levels;
1876 }
1877
1878 static bool
1879 intel_dp_set_link_train(struct intel_dp *intel_dp,
1880                         uint32_t dp_reg_value,
1881                         uint8_t dp_train_pat)
1882 {
1883         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1884         struct drm_device *dev = intel_dig_port->base.base.dev;
1885         struct drm_i915_private *dev_priv = dev->dev_private;
1886         enum port port = intel_dig_port->port;
1887         int ret;
1888
1889         if (HAS_DDI(dev)) {
1890                 uint32_t temp = I915_READ(DP_TP_CTL(port));
1891
1892                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1893                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1894                 else
1895                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1896
1897                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1898                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1899                 case DP_TRAINING_PATTERN_DISABLE:
1900                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1901
1902                         break;
1903                 case DP_TRAINING_PATTERN_1:
1904                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1905                         break;
1906                 case DP_TRAINING_PATTERN_2:
1907                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1908                         break;
1909                 case DP_TRAINING_PATTERN_3:
1910                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1911                         break;
1912                 }
1913                 I915_WRITE(DP_TP_CTL(port), temp);
1914
1915         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
1916                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1917
1918                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1919                 case DP_TRAINING_PATTERN_DISABLE:
1920                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1921                         break;
1922                 case DP_TRAINING_PATTERN_1:
1923                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1924                         break;
1925                 case DP_TRAINING_PATTERN_2:
1926                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1927                         break;
1928                 case DP_TRAINING_PATTERN_3:
1929                         DRM_ERROR("DP training pattern 3 not supported\n");
1930                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1931                         break;
1932                 }
1933
1934         } else {
1935                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1936
1937                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1938                 case DP_TRAINING_PATTERN_DISABLE:
1939                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1940                         break;
1941                 case DP_TRAINING_PATTERN_1:
1942                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1943                         break;
1944                 case DP_TRAINING_PATTERN_2:
1945                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1946                         break;
1947                 case DP_TRAINING_PATTERN_3:
1948                         DRM_ERROR("DP training pattern 3 not supported\n");
1949                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1950                         break;
1951                 }
1952         }
1953
1954         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1955         POSTING_READ(intel_dp->output_reg);
1956
1957         intel_dp_aux_native_write_1(intel_dp,
1958                                     DP_TRAINING_PATTERN_SET,
1959                                     dp_train_pat);
1960
1961         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1962             DP_TRAINING_PATTERN_DISABLE) {
1963                 ret = intel_dp_aux_native_write(intel_dp,
1964                                                 DP_TRAINING_LANE0_SET,
1965                                                 intel_dp->train_set,
1966                                                 intel_dp->lane_count);
1967                 if (ret != intel_dp->lane_count)
1968                         return false;
1969         }
1970
1971         return true;
1972 }
1973
1974 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1975 {
1976         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1977         struct drm_device *dev = intel_dig_port->base.base.dev;
1978         struct drm_i915_private *dev_priv = dev->dev_private;
1979         enum port port = intel_dig_port->port;
1980         uint32_t val;
1981
1982         if (!HAS_DDI(dev))
1983                 return;
1984
1985         val = I915_READ(DP_TP_CTL(port));
1986         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1987         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1988         I915_WRITE(DP_TP_CTL(port), val);
1989
1990         /*
1991          * On PORT_A we can have only eDP in SST mode. There the only reason
1992          * we need to set idle transmission mode is to work around a HW issue
1993          * where we enable the pipe while not in idle link-training mode.
1994          * In this case there is requirement to wait for a minimum number of
1995          * idle patterns to be sent.
1996          */
1997         if (port == PORT_A)
1998                 return;
1999
2000         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2001                      1))
2002                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2003 }
2004
2005 /* Enable corresponding port and start training pattern 1 */
2006 void
2007 intel_dp_start_link_train(struct intel_dp *intel_dp)
2008 {
2009         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2010         struct drm_device *dev = encoder->dev;
2011         int i;
2012         uint8_t voltage;
2013         bool clock_recovery = false;
2014         int voltage_tries, loop_tries;
2015         uint32_t DP = intel_dp->DP;
2016
2017         if (HAS_DDI(dev))
2018                 intel_ddi_prepare_link_retrain(encoder);
2019
2020         /* Write the link configuration data */
2021         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2022                                   intel_dp->link_configuration,
2023                                   DP_LINK_CONFIGURATION_SIZE);
2024
2025         DP |= DP_PORT_EN;
2026
2027         memset(intel_dp->train_set, 0, 4);
2028         voltage = 0xff;
2029         voltage_tries = 0;
2030         loop_tries = 0;
2031         clock_recovery = false;
2032         for (;;) {
2033                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2034                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2035
2036                 intel_dp_set_signal_levels(intel_dp, &DP);
2037
2038                 /* Set training pattern 1 */
2039                 if (!intel_dp_set_link_train(intel_dp, DP,
2040                                              DP_TRAINING_PATTERN_1 |
2041                                              DP_LINK_SCRAMBLING_DISABLE))
2042                         break;
2043
2044                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2045                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2046                         DRM_ERROR("failed to get link status\n");
2047                         break;
2048                 }
2049
2050                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2051                         DRM_DEBUG_KMS("clock recovery OK\n");
2052                         clock_recovery = true;
2053                         break;
2054                 }
2055
2056                 /* Check to see if we've tried the max voltage */
2057                 for (i = 0; i < intel_dp->lane_count; i++)
2058                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2059                                 break;
2060                 if (i == intel_dp->lane_count) {
2061                         ++loop_tries;
2062                         if (loop_tries == 5) {
2063                                 DRM_DEBUG_KMS("too many full retries, give up\n");
2064                                 break;
2065                         }
2066                         memset(intel_dp->train_set, 0, 4);
2067                         voltage_tries = 0;
2068                         continue;
2069                 }
2070
2071                 /* Check to see if we've tried the same voltage 5 times */
2072                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2073                         ++voltage_tries;
2074                         if (voltage_tries == 5) {
2075                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2076                                 break;
2077                         }
2078                 } else
2079                         voltage_tries = 0;
2080                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2081
2082                 /* Compute new intel_dp->train_set as requested by target */
2083                 intel_get_adjust_train(intel_dp, link_status);
2084         }
2085
2086         intel_dp->DP = DP;
2087 }
2088
2089 void
2090 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2091 {
2092         bool channel_eq = false;
2093         int tries, cr_tries;
2094         uint32_t DP = intel_dp->DP;
2095
2096         /* channel equalization */
2097         tries = 0;
2098         cr_tries = 0;
2099         channel_eq = false;
2100         for (;;) {
2101                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2102
2103                 if (cr_tries > 5) {
2104                         DRM_ERROR("failed to train DP, aborting\n");
2105                         intel_dp_link_down(intel_dp);
2106                         break;
2107                 }
2108
2109                 intel_dp_set_signal_levels(intel_dp, &DP);
2110
2111                 /* channel eq pattern */
2112                 if (!intel_dp_set_link_train(intel_dp, DP,
2113                                              DP_TRAINING_PATTERN_2 |
2114                                              DP_LINK_SCRAMBLING_DISABLE))
2115                         break;
2116
2117                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2118                 if (!intel_dp_get_link_status(intel_dp, link_status))
2119                         break;
2120
2121                 /* Make sure clock is still ok */
2122                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2123                         intel_dp_start_link_train(intel_dp);
2124                         cr_tries++;
2125                         continue;
2126                 }
2127
2128                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2129                         channel_eq = true;
2130                         break;
2131                 }
2132
2133                 /* Try 5 times, then try clock recovery if that fails */
2134                 if (tries > 5) {
2135                         intel_dp_link_down(intel_dp);
2136                         intel_dp_start_link_train(intel_dp);
2137                         tries = 0;
2138                         cr_tries++;
2139                         continue;
2140                 }
2141
2142                 /* Compute new intel_dp->train_set as requested by target */
2143                 intel_get_adjust_train(intel_dp, link_status);
2144                 ++tries;
2145         }
2146
2147         intel_dp_set_idle_link_train(intel_dp);
2148
2149         intel_dp->DP = DP;
2150
2151         if (channel_eq)
2152                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2153
2154 }
2155
2156 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2157 {
2158         intel_dp_set_link_train(intel_dp, intel_dp->DP,
2159                                 DP_TRAINING_PATTERN_DISABLE);
2160 }
2161
2162 static void
2163 intel_dp_link_down(struct intel_dp *intel_dp)
2164 {
2165         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2166         enum port port = intel_dig_port->port;
2167         struct drm_device *dev = intel_dig_port->base.base.dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169         struct intel_crtc *intel_crtc =
2170                 to_intel_crtc(intel_dig_port->base.base.crtc);
2171         uint32_t DP = intel_dp->DP;
2172
2173         /*
2174          * DDI code has a strict mode set sequence and we should try to respect
2175          * it, otherwise we might hang the machine in many different ways. So we
2176          * really should be disabling the port only on a complete crtc_disable
2177          * sequence. This function is just called under two conditions on DDI
2178          * code:
2179          * - Link train failed while doing crtc_enable, and on this case we
2180          *   really should respect the mode set sequence and wait for a
2181          *   crtc_disable.
2182          * - Someone turned the monitor off and intel_dp_check_link_status
2183          *   called us. We don't need to disable the whole port on this case, so
2184          *   when someone turns the monitor on again,
2185          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2186          *   train.
2187          */
2188         if (HAS_DDI(dev))
2189                 return;
2190
2191         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2192                 return;
2193
2194         DRM_DEBUG_KMS("\n");
2195
2196         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2197                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2198                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2199         } else {
2200                 DP &= ~DP_LINK_TRAIN_MASK;
2201                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2202         }
2203         POSTING_READ(intel_dp->output_reg);
2204
2205         /* We don't really know why we're doing this */
2206         intel_wait_for_vblank(dev, intel_crtc->pipe);
2207
2208         if (HAS_PCH_IBX(dev) &&
2209             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2210                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2211
2212                 /* Hardware workaround: leaving our transcoder select
2213                  * set to transcoder B while it's off will prevent the
2214                  * corresponding HDMI output on transcoder A.
2215                  *
2216                  * Combine this with another hardware workaround:
2217                  * transcoder select bit can only be cleared while the
2218                  * port is enabled.
2219                  */
2220                 DP &= ~DP_PIPEB_SELECT;
2221                 I915_WRITE(intel_dp->output_reg, DP);
2222
2223                 /* Changes to enable or select take place the vblank
2224                  * after being written.
2225                  */
2226                 if (WARN_ON(crtc == NULL)) {
2227                         /* We should never try to disable a port without a crtc
2228                          * attached. For paranoia keep the code around for a
2229                          * bit. */
2230                         POSTING_READ(intel_dp->output_reg);
2231                         msleep(50);
2232                 } else
2233                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2234         }
2235
2236         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2237         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2238         POSTING_READ(intel_dp->output_reg);
2239         msleep(intel_dp->panel_power_down_delay);
2240 }
2241
2242 static bool
2243 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2244 {
2245         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2246
2247         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2248                                            sizeof(intel_dp->dpcd)) == 0)
2249                 return false; /* aux transfer failed */
2250
2251         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2252                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2253         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2254
2255         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2256                 return false; /* DPCD not present */
2257
2258         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2259               DP_DWN_STRM_PORT_PRESENT))
2260                 return true; /* native DP sink */
2261
2262         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2263                 return true; /* no per-port downstream info */
2264
2265         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2266                                            intel_dp->downstream_ports,
2267                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2268                 return false; /* downstream port status fetch failed */
2269
2270         return true;
2271 }
2272
2273 static void
2274 intel_dp_probe_oui(struct intel_dp *intel_dp)
2275 {
2276         u8 buf[3];
2277
2278         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2279                 return;
2280
2281         ironlake_edp_panel_vdd_on(intel_dp);
2282
2283         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2284                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2285                               buf[0], buf[1], buf[2]);
2286
2287         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2288                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2289                               buf[0], buf[1], buf[2]);
2290
2291         ironlake_edp_panel_vdd_off(intel_dp, false);
2292 }
2293
2294 static bool
2295 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2296 {
2297         int ret;
2298
2299         ret = intel_dp_aux_native_read_retry(intel_dp,
2300                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2301                                              sink_irq_vector, 1);
2302         if (!ret)
2303                 return false;
2304
2305         return true;
2306 }
2307
2308 static void
2309 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2310 {
2311         /* NAK by default */
2312         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2313 }
2314
2315 /*
2316  * According to DP spec
2317  * 5.1.2:
2318  *  1. Read DPCD
2319  *  2. Configure link according to Receiver Capabilities
2320  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2321  *  4. Check link status on receipt of hot-plug interrupt
2322  */
2323
2324 void
2325 intel_dp_check_link_status(struct intel_dp *intel_dp)
2326 {
2327         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2328         u8 sink_irq_vector;
2329         u8 link_status[DP_LINK_STATUS_SIZE];
2330
2331         if (!intel_encoder->connectors_active)
2332                 return;
2333
2334         if (WARN_ON(!intel_encoder->base.crtc))
2335                 return;
2336
2337         /* Try to read receiver status if the link appears to be up */
2338         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2339                 intel_dp_link_down(intel_dp);
2340                 return;
2341         }
2342
2343         /* Now read the DPCD to see if it's actually running */
2344         if (!intel_dp_get_dpcd(intel_dp)) {
2345                 intel_dp_link_down(intel_dp);
2346                 return;
2347         }
2348
2349         /* Try to read the source of the interrupt */
2350         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2351             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2352                 /* Clear interrupt source */
2353                 intel_dp_aux_native_write_1(intel_dp,
2354                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2355                                             sink_irq_vector);
2356
2357                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2358                         intel_dp_handle_test_request(intel_dp);
2359                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2360                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2361         }
2362
2363         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2364                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2365                               drm_get_encoder_name(&intel_encoder->base));
2366                 intel_dp_start_link_train(intel_dp);
2367                 intel_dp_complete_link_train(intel_dp);
2368                 intel_dp_stop_link_train(intel_dp);
2369         }
2370 }
2371
2372 /* XXX this is probably wrong for multiple downstream ports */
2373 static enum drm_connector_status
2374 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2375 {
2376         uint8_t *dpcd = intel_dp->dpcd;
2377         bool hpd;
2378         uint8_t type;
2379
2380         if (!intel_dp_get_dpcd(intel_dp))
2381                 return connector_status_disconnected;
2382
2383         /* if there's no downstream port, we're done */
2384         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2385                 return connector_status_connected;
2386
2387         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2388         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2389         if (hpd) {
2390                 uint8_t reg;
2391                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2392                                                     &reg, 1))
2393                         return connector_status_unknown;
2394                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2395                                               : connector_status_disconnected;
2396         }
2397
2398         /* If no HPD, poke DDC gently */
2399         if (drm_probe_ddc(&intel_dp->adapter))
2400                 return connector_status_connected;
2401
2402         /* Well we tried, say unknown for unreliable port types */
2403         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2404         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2405                 return connector_status_unknown;
2406
2407         /* Anything else is out of spec, warn and ignore */
2408         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2409         return connector_status_disconnected;
2410 }
2411
2412 static enum drm_connector_status
2413 ironlake_dp_detect(struct intel_dp *intel_dp)
2414 {
2415         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2416         struct drm_i915_private *dev_priv = dev->dev_private;
2417         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2418         enum drm_connector_status status;
2419
2420         /* Can't disconnect eDP, but you can close the lid... */
2421         if (is_edp(intel_dp)) {
2422                 status = intel_panel_detect(dev);
2423                 if (status == connector_status_unknown)
2424                         status = connector_status_connected;
2425                 return status;
2426         }
2427
2428         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2429                 return connector_status_disconnected;
2430
2431         return intel_dp_detect_dpcd(intel_dp);
2432 }
2433
2434 static enum drm_connector_status
2435 g4x_dp_detect(struct intel_dp *intel_dp)
2436 {
2437         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2438         struct drm_i915_private *dev_priv = dev->dev_private;
2439         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2440         uint32_t bit;
2441
2442         /* Can't disconnect eDP, but you can close the lid... */
2443         if (is_edp(intel_dp)) {
2444                 enum drm_connector_status status;
2445
2446                 status = intel_panel_detect(dev);
2447                 if (status == connector_status_unknown)
2448                         status = connector_status_connected;
2449                 return status;
2450         }
2451
2452         switch (intel_dig_port->port) {
2453         case PORT_B:
2454                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2455                 break;
2456         case PORT_C:
2457                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2458                 break;
2459         case PORT_D:
2460                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2461                 break;
2462         default:
2463                 return connector_status_unknown;
2464         }
2465
2466         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2467                 return connector_status_disconnected;
2468
2469         return intel_dp_detect_dpcd(intel_dp);
2470 }
2471
2472 static struct edid *
2473 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2474 {
2475         struct intel_connector *intel_connector = to_intel_connector(connector);
2476
2477         /* use cached edid if we have one */
2478         if (intel_connector->edid) {
2479                 struct edid *edid;
2480                 int size;
2481
2482                 /* invalid edid */
2483                 if (IS_ERR(intel_connector->edid))
2484                         return NULL;
2485
2486                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2487                 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2488                 if (!edid)
2489                         return NULL;
2490
2491                 return edid;
2492         }
2493
2494         return drm_get_edid(connector, adapter);
2495 }
2496
2497 static int
2498 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2499 {
2500         struct intel_connector *intel_connector = to_intel_connector(connector);
2501
2502         /* use cached edid if we have one */
2503         if (intel_connector->edid) {
2504                 /* invalid edid */
2505                 if (IS_ERR(intel_connector->edid))
2506                         return 0;
2507
2508                 return intel_connector_update_modes(connector,
2509                                                     intel_connector->edid);
2510         }
2511
2512         return intel_ddc_get_modes(connector, adapter);
2513 }
2514
2515 static enum drm_connector_status
2516 intel_dp_detect(struct drm_connector *connector, bool force)
2517 {
2518         struct intel_dp *intel_dp = intel_attached_dp(connector);
2519         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2520         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2521         struct drm_device *dev = connector->dev;
2522         enum drm_connector_status status;
2523         struct edid *edid = NULL;
2524
2525         intel_dp->has_audio = false;
2526
2527         if (HAS_PCH_SPLIT(dev))
2528                 status = ironlake_dp_detect(intel_dp);
2529         else
2530                 status = g4x_dp_detect(intel_dp);
2531
2532         if (status != connector_status_connected)
2533                 return status;
2534
2535         intel_dp_probe_oui(intel_dp);
2536
2537         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2538                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2539         } else {
2540                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2541                 if (edid) {
2542                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2543                         kfree(edid);
2544                 }
2545         }
2546
2547         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2548                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2549         return connector_status_connected;
2550 }
2551
2552 static int intel_dp_get_modes(struct drm_connector *connector)
2553 {
2554         struct intel_dp *intel_dp = intel_attached_dp(connector);
2555         struct intel_connector *intel_connector = to_intel_connector(connector);
2556         struct drm_device *dev = connector->dev;
2557         int ret;
2558
2559         /* We should parse the EDID data and find out if it has an audio sink
2560          */
2561
2562         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2563         if (ret)
2564                 return ret;
2565
2566         /* if eDP has no EDID, fall back to fixed mode */
2567         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2568                 struct drm_display_mode *mode;
2569                 mode = drm_mode_duplicate(dev,
2570                                           intel_connector->panel.fixed_mode);
2571                 if (mode) {
2572                         drm_mode_probed_add(connector, mode);
2573                         return 1;
2574                 }
2575         }
2576         return 0;
2577 }
2578
2579 static bool
2580 intel_dp_detect_audio(struct drm_connector *connector)
2581 {
2582         struct intel_dp *intel_dp = intel_attached_dp(connector);
2583         struct edid *edid;
2584         bool has_audio = false;
2585
2586         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2587         if (edid) {
2588                 has_audio = drm_detect_monitor_audio(edid);
2589                 kfree(edid);
2590         }
2591
2592         return has_audio;
2593 }
2594
2595 static int
2596 intel_dp_set_property(struct drm_connector *connector,
2597                       struct drm_property *property,
2598                       uint64_t val)
2599 {
2600         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2601         struct intel_connector *intel_connector = to_intel_connector(connector);
2602         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2603         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2604         int ret;
2605
2606         ret = drm_object_property_set_value(&connector->base, property, val);
2607         if (ret)
2608                 return ret;
2609
2610         if (property == dev_priv->force_audio_property) {
2611                 int i = val;
2612                 bool has_audio;
2613
2614                 if (i == intel_dp->force_audio)
2615                         return 0;
2616
2617                 intel_dp->force_audio = i;
2618
2619                 if (i == HDMI_AUDIO_AUTO)
2620                         has_audio = intel_dp_detect_audio(connector);
2621                 else
2622                         has_audio = (i == HDMI_AUDIO_ON);
2623
2624                 if (has_audio == intel_dp->has_audio)
2625                         return 0;
2626
2627                 intel_dp->has_audio = has_audio;
2628                 goto done;
2629         }
2630
2631         if (property == dev_priv->broadcast_rgb_property) {
2632                 bool old_auto = intel_dp->color_range_auto;
2633                 uint32_t old_range = intel_dp->color_range;
2634
2635                 switch (val) {
2636                 case INTEL_BROADCAST_RGB_AUTO:
2637                         intel_dp->color_range_auto = true;
2638                         break;
2639                 case INTEL_BROADCAST_RGB_FULL:
2640                         intel_dp->color_range_auto = false;
2641                         intel_dp->color_range = 0;
2642                         break;
2643                 case INTEL_BROADCAST_RGB_LIMITED:
2644                         intel_dp->color_range_auto = false;
2645                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2646                         break;
2647                 default:
2648                         return -EINVAL;
2649                 }
2650
2651                 if (old_auto == intel_dp->color_range_auto &&
2652                     old_range == intel_dp->color_range)
2653                         return 0;
2654
2655                 goto done;
2656         }
2657
2658         if (is_edp(intel_dp) &&
2659             property == connector->dev->mode_config.scaling_mode_property) {
2660                 if (val == DRM_MODE_SCALE_NONE) {
2661                         DRM_DEBUG_KMS("no scaling not supported\n");
2662                         return -EINVAL;
2663                 }
2664
2665                 if (intel_connector->panel.fitting_mode == val) {
2666                         /* the eDP scaling property is not changed */
2667                         return 0;
2668                 }
2669                 intel_connector->panel.fitting_mode = val;
2670
2671                 goto done;
2672         }
2673
2674         return -EINVAL;
2675
2676 done:
2677         if (intel_encoder->base.crtc)
2678                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2679
2680         return 0;
2681 }
2682
2683 static void
2684 intel_dp_destroy(struct drm_connector *connector)
2685 {
2686         struct intel_dp *intel_dp = intel_attached_dp(connector);
2687         struct intel_connector *intel_connector = to_intel_connector(connector);
2688
2689         if (!IS_ERR_OR_NULL(intel_connector->edid))
2690                 kfree(intel_connector->edid);
2691
2692         if (is_edp(intel_dp))
2693                 intel_panel_fini(&intel_connector->panel);
2694
2695         drm_sysfs_connector_remove(connector);
2696         drm_connector_cleanup(connector);
2697         kfree(connector);
2698 }
2699
2700 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2701 {
2702         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2703         struct intel_dp *intel_dp = &intel_dig_port->dp;
2704         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2705
2706         i2c_del_adapter(&intel_dp->adapter);
2707         drm_encoder_cleanup(encoder);
2708         if (is_edp(intel_dp)) {
2709                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2710                 mutex_lock(&dev->mode_config.mutex);
2711                 ironlake_panel_vdd_off_sync(intel_dp);
2712                 mutex_unlock(&dev->mode_config.mutex);
2713         }
2714         kfree(intel_dig_port);
2715 }
2716
2717 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2718         .mode_set = intel_dp_mode_set,
2719 };
2720
2721 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2722         .dpms = intel_connector_dpms,
2723         .detect = intel_dp_detect,
2724         .fill_modes = drm_helper_probe_single_connector_modes,
2725         .set_property = intel_dp_set_property,
2726         .destroy = intel_dp_destroy,
2727 };
2728
2729 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2730         .get_modes = intel_dp_get_modes,
2731         .mode_valid = intel_dp_mode_valid,
2732         .best_encoder = intel_best_encoder,
2733 };
2734
2735 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2736         .destroy = intel_dp_encoder_destroy,
2737 };
2738
2739 static void
2740 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2741 {
2742         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2743
2744         intel_dp_check_link_status(intel_dp);
2745 }
2746
2747 /* Return which DP Port should be selected for Transcoder DP control */
2748 int
2749 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2750 {
2751         struct drm_device *dev = crtc->dev;
2752         struct intel_encoder *intel_encoder;
2753         struct intel_dp *intel_dp;
2754
2755         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2756                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2757
2758                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2759                     intel_encoder->type == INTEL_OUTPUT_EDP)
2760                         return intel_dp->output_reg;
2761         }
2762
2763         return -1;
2764 }
2765
2766 /* check the VBT to see whether the eDP is on DP-D port */
2767 bool intel_dpd_is_edp(struct drm_device *dev)
2768 {
2769         struct drm_i915_private *dev_priv = dev->dev_private;
2770         struct child_device_config *p_child;
2771         int i;
2772
2773         if (!dev_priv->vbt.child_dev_num)
2774                 return false;
2775
2776         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2777                 p_child = dev_priv->vbt.child_dev + i;
2778
2779                 if (p_child->dvo_port == PORT_IDPD &&
2780                     p_child->device_type == DEVICE_TYPE_eDP)
2781                         return true;
2782         }
2783         return false;
2784 }
2785
2786 static void
2787 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2788 {
2789         struct intel_connector *intel_connector = to_intel_connector(connector);
2790
2791         intel_attach_force_audio_property(connector);
2792         intel_attach_broadcast_rgb_property(connector);
2793         intel_dp->color_range_auto = true;
2794
2795         if (is_edp(intel_dp)) {
2796                 drm_mode_create_scaling_mode_property(connector->dev);
2797                 drm_object_attach_property(
2798                         &connector->base,
2799                         connector->dev->mode_config.scaling_mode_property,
2800                         DRM_MODE_SCALE_ASPECT);
2801                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2802         }
2803 }
2804
2805 static void
2806 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2807                                     struct intel_dp *intel_dp,
2808                                     struct edp_power_seq *out)
2809 {
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         struct edp_power_seq cur, vbt, spec, final;
2812         u32 pp_on, pp_off, pp_div, pp;
2813         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2814
2815         if (HAS_PCH_SPLIT(dev)) {
2816                 pp_control_reg = PCH_PP_CONTROL;
2817                 pp_on_reg = PCH_PP_ON_DELAYS;
2818                 pp_off_reg = PCH_PP_OFF_DELAYS;
2819                 pp_div_reg = PCH_PP_DIVISOR;
2820         } else {
2821                 pp_control_reg = PIPEA_PP_CONTROL;
2822                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2823                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2824                 pp_div_reg = PIPEA_PP_DIVISOR;
2825         }
2826
2827         /* Workaround: Need to write PP_CONTROL with the unlock key as
2828          * the very first thing. */
2829         pp = ironlake_get_pp_control(intel_dp);
2830         I915_WRITE(pp_control_reg, pp);
2831
2832         pp_on = I915_READ(pp_on_reg);
2833         pp_off = I915_READ(pp_off_reg);
2834         pp_div = I915_READ(pp_div_reg);
2835
2836         /* Pull timing values out of registers */
2837         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2838                 PANEL_POWER_UP_DELAY_SHIFT;
2839
2840         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2841                 PANEL_LIGHT_ON_DELAY_SHIFT;
2842
2843         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2844                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2845
2846         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2847                 PANEL_POWER_DOWN_DELAY_SHIFT;
2848
2849         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2850                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2851
2852         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2853                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2854
2855         vbt = dev_priv->vbt.edp_pps;
2856
2857         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2858          * our hw here, which are all in 100usec. */
2859         spec.t1_t3 = 210 * 10;
2860         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2861         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2862         spec.t10 = 500 * 10;
2863         /* This one is special and actually in units of 100ms, but zero
2864          * based in the hw (so we need to add 100 ms). But the sw vbt
2865          * table multiplies it with 1000 to make it in units of 100usec,
2866          * too. */
2867         spec.t11_t12 = (510 + 100) * 10;
2868
2869         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2870                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2871
2872         /* Use the max of the register settings and vbt. If both are
2873          * unset, fall back to the spec limits. */
2874 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2875                                        spec.field : \
2876                                        max(cur.field, vbt.field))
2877         assign_final(t1_t3);
2878         assign_final(t8);
2879         assign_final(t9);
2880         assign_final(t10);
2881         assign_final(t11_t12);
2882 #undef assign_final
2883
2884 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2885         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2886         intel_dp->backlight_on_delay = get_delay(t8);
2887         intel_dp->backlight_off_delay = get_delay(t9);
2888         intel_dp->panel_power_down_delay = get_delay(t10);
2889         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2890 #undef get_delay
2891
2892         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2893                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2894                       intel_dp->panel_power_cycle_delay);
2895
2896         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2897                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2898
2899         if (out)
2900                 *out = final;
2901 }
2902
2903 static void
2904 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2905                                               struct intel_dp *intel_dp,
2906                                               struct edp_power_seq *seq)
2907 {
2908         struct drm_i915_private *dev_priv = dev->dev_private;
2909         u32 pp_on, pp_off, pp_div, port_sel = 0;
2910         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2911         int pp_on_reg, pp_off_reg, pp_div_reg;
2912
2913         if (HAS_PCH_SPLIT(dev)) {
2914                 pp_on_reg = PCH_PP_ON_DELAYS;
2915                 pp_off_reg = PCH_PP_OFF_DELAYS;
2916                 pp_div_reg = PCH_PP_DIVISOR;
2917         } else {
2918                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2919                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2920                 pp_div_reg = PIPEA_PP_DIVISOR;
2921         }
2922
2923         /* And finally store the new values in the power sequencer. */
2924         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2925                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2926         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2927                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2928         /* Compute the divisor for the pp clock, simply match the Bspec
2929          * formula. */
2930         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2931         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2932                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2933
2934         /* Haswell doesn't have any port selection bits for the panel
2935          * power sequencer any more. */
2936         if (IS_VALLEYVIEW(dev)) {
2937                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2938         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2939                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
2940                         port_sel = PANEL_POWER_PORT_DP_A;
2941                 else
2942                         port_sel = PANEL_POWER_PORT_DP_D;
2943         }
2944
2945         pp_on |= port_sel;
2946
2947         I915_WRITE(pp_on_reg, pp_on);
2948         I915_WRITE(pp_off_reg, pp_off);
2949         I915_WRITE(pp_div_reg, pp_div);
2950
2951         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2952                       I915_READ(pp_on_reg),
2953                       I915_READ(pp_off_reg),
2954                       I915_READ(pp_div_reg));
2955 }
2956
2957 void
2958 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2959                         struct intel_connector *intel_connector)
2960 {
2961         struct drm_connector *connector = &intel_connector->base;
2962         struct intel_dp *intel_dp = &intel_dig_port->dp;
2963         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2964         struct drm_device *dev = intel_encoder->base.dev;
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966         struct drm_display_mode *fixed_mode = NULL;
2967         struct edp_power_seq power_seq = { 0 };
2968         enum port port = intel_dig_port->port;
2969         const char *name = NULL;
2970         int type;
2971
2972         /* Preserve the current hw state. */
2973         intel_dp->DP = I915_READ(intel_dp->output_reg);
2974         intel_dp->attached_connector = intel_connector;
2975
2976         type = DRM_MODE_CONNECTOR_DisplayPort;
2977         /*
2978          * FIXME : We need to initialize built-in panels before external panels.
2979          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2980          */
2981         switch (port) {
2982         case PORT_A:
2983                 type = DRM_MODE_CONNECTOR_eDP;
2984                 break;
2985         case PORT_C:
2986                 if (IS_VALLEYVIEW(dev))
2987                         type = DRM_MODE_CONNECTOR_eDP;
2988                 break;
2989         case PORT_D:
2990                 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
2991                         type = DRM_MODE_CONNECTOR_eDP;
2992                 break;
2993         default:        /* silence GCC warning */
2994                 break;
2995         }
2996
2997         /*
2998          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
2999          * for DP the encoder type can be set by the caller to
3000          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3001          */
3002         if (type == DRM_MODE_CONNECTOR_eDP)
3003                 intel_encoder->type = INTEL_OUTPUT_EDP;
3004
3005         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3006                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3007                         port_name(port));
3008
3009         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3010         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3011
3012         connector->interlace_allowed = true;
3013         connector->doublescan_allowed = 0;
3014
3015         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3016                           ironlake_panel_vdd_work);
3017
3018         intel_connector_attach_encoder(intel_connector, intel_encoder);
3019         drm_sysfs_connector_add(connector);
3020
3021         if (HAS_DDI(dev))
3022                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3023         else
3024                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3025
3026         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3027         if (HAS_DDI(dev)) {
3028                 switch (intel_dig_port->port) {
3029                 case PORT_A:
3030                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3031                         break;
3032                 case PORT_B:
3033                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3034                         break;
3035                 case PORT_C:
3036                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3037                         break;
3038                 case PORT_D:
3039                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3040                         break;
3041                 default:
3042                         BUG();
3043                 }
3044         }
3045
3046         /* Set up the DDC bus. */
3047         switch (port) {
3048         case PORT_A:
3049                 intel_encoder->hpd_pin = HPD_PORT_A;
3050                 name = "DPDDC-A";
3051                 break;
3052         case PORT_B:
3053                 intel_encoder->hpd_pin = HPD_PORT_B;
3054                 name = "DPDDC-B";
3055                 break;
3056         case PORT_C:
3057                 intel_encoder->hpd_pin = HPD_PORT_C;
3058                 name = "DPDDC-C";
3059                 break;
3060         case PORT_D:
3061                 intel_encoder->hpd_pin = HPD_PORT_D;
3062                 name = "DPDDC-D";
3063                 break;
3064         default:
3065                 BUG();
3066         }
3067
3068         if (is_edp(intel_dp))
3069                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3070
3071         intel_dp_i2c_init(intel_dp, intel_connector, name);
3072
3073         /* Cache DPCD and EDID for edp. */
3074         if (is_edp(intel_dp)) {
3075                 bool ret;
3076                 struct drm_display_mode *scan;
3077                 struct edid *edid;
3078
3079                 ironlake_edp_panel_vdd_on(intel_dp);
3080                 ret = intel_dp_get_dpcd(intel_dp);
3081                 ironlake_edp_panel_vdd_off(intel_dp, false);
3082
3083                 if (ret) {
3084                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3085                                 dev_priv->no_aux_handshake =
3086                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3087                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3088                 } else {
3089                         /* if this fails, presume the device is a ghost */
3090                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
3091                         intel_dp_encoder_destroy(&intel_encoder->base);
3092                         intel_dp_destroy(connector);
3093                         return;
3094                 }
3095
3096                 /* We now know it's not a ghost, init power sequence regs. */
3097                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3098                                                               &power_seq);
3099
3100                 ironlake_edp_panel_vdd_on(intel_dp);
3101                 edid = drm_get_edid(connector, &intel_dp->adapter);
3102                 if (edid) {
3103                         if (drm_add_edid_modes(connector, edid)) {
3104                                 drm_mode_connector_update_edid_property(connector, edid);
3105                                 drm_edid_to_eld(connector, edid);
3106                         } else {
3107                                 kfree(edid);
3108                                 edid = ERR_PTR(-EINVAL);
3109                         }
3110                 } else {
3111                         edid = ERR_PTR(-ENOENT);
3112                 }
3113                 intel_connector->edid = edid;
3114
3115                 /* prefer fixed mode from EDID if available */
3116                 list_for_each_entry(scan, &connector->probed_modes, head) {
3117                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3118                                 fixed_mode = drm_mode_duplicate(dev, scan);
3119                                 break;
3120                         }
3121                 }
3122
3123                 /* fallback to VBT if available for eDP */
3124                 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3125                         fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
3126                         if (fixed_mode)
3127                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3128                 }
3129
3130                 ironlake_edp_panel_vdd_off(intel_dp, false);
3131         }
3132
3133         if (is_edp(intel_dp)) {
3134                 intel_panel_init(&intel_connector->panel, fixed_mode);
3135                 intel_panel_setup_backlight(connector);
3136         }
3137
3138         intel_dp_add_properties(intel_dp, connector);
3139
3140         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3141          * 0xd.  Failure to do so will result in spurious interrupts being
3142          * generated on the port when a cable is not attached.
3143          */
3144         if (IS_G4X(dev) && !IS_GM45(dev)) {
3145                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3146                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3147         }
3148 }
3149
3150 void
3151 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3152 {
3153         struct intel_digital_port *intel_dig_port;
3154         struct intel_encoder *intel_encoder;
3155         struct drm_encoder *encoder;
3156         struct intel_connector *intel_connector;
3157
3158         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3159         if (!intel_dig_port)
3160                 return;
3161
3162         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3163         if (!intel_connector) {
3164                 kfree(intel_dig_port);
3165                 return;
3166         }
3167
3168         intel_encoder = &intel_dig_port->base;
3169         encoder = &intel_encoder->base;
3170
3171         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3172                          DRM_MODE_ENCODER_TMDS);
3173         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3174
3175         intel_encoder->compute_config = intel_dp_compute_config;
3176         intel_encoder->enable = intel_enable_dp;
3177         intel_encoder->pre_enable = intel_pre_enable_dp;
3178         intel_encoder->disable = intel_disable_dp;
3179         intel_encoder->post_disable = intel_post_disable_dp;
3180         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3181         intel_encoder->get_config = intel_dp_get_config;
3182         if (IS_VALLEYVIEW(dev))
3183                 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3184
3185         intel_dig_port->port = port;
3186         intel_dig_port->dp.output_reg = output_reg;
3187
3188         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3189         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3190         intel_encoder->cloneable = false;
3191         intel_encoder->hot_plug = intel_dp_hot_plug;
3192
3193         intel_dp_init_connector(intel_dig_port, intel_connector);
3194 }