drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/consumer.h>
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37 #include "intel_dsi.h"
  38
  39 static const struct {
  40         u16 panel_id;
  41         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  42 } intel_dsi_drivers[] = {
  43         {
  44                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  45                 .init = vbt_panel_init,
  46         },
  47 };
  48
  49 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  50 {
  51         struct drm_encoder *encoder = &intel_dsi->base.base;
  52         struct drm_device *dev = encoder->dev;
  53         struct drm_i915_private *dev_priv = dev->dev_private;
  54         u32 mask;
  55
  56         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  57                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  58
  59         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
  60                 DRM_ERROR("DPI FIFOs are not empty\n");
  61 }
  62
  63 static void write_data(struct drm_i915_private *dev_priv, u32 reg,
  64                        const u8 *data, u32 len)
  65 {
  66         u32 i, j;
  67
  68         for (i = 0; i < len; i += 4) {
  69                 u32 val = 0;
  70
  71                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  72                         val |= *data++ << 8 * j;
  73
  74                 I915_WRITE(reg, val);
  75         }
  76 }
  77
  78 static void read_data(struct drm_i915_private *dev_priv, u32 reg,
  79                       u8 *data, u32 len)
  80 {
  81         u32 i, j;
  82
  83         for (i = 0; i < len; i += 4) {
  84                 u32 val = I915_READ(reg);
  85
  86                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  87                         *data++ = val >> 8 * j;
  88         }
  89 }
  90
  91 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
  92                                        const struct mipi_dsi_msg *msg)
  93 {
  94         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
  95         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
  96         struct drm_i915_private *dev_priv = dev->dev_private;
  97         enum port port = intel_dsi_host->port;
  98         struct mipi_dsi_packet packet;
  99         ssize_t ret;
 100         const u8 *header, *data;
 101         u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
 102
 103         ret = mipi_dsi_create_packet(&packet, msg);
 104         if (ret < 0)
 105                 return ret;
 106
 107         header = packet.header;
 108         data = packet.payload;
 109
 110         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 111                 data_reg = MIPI_LP_GEN_DATA(port);
 112                 data_mask = LP_DATA_FIFO_FULL;
 113                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 114                 ctrl_mask = LP_CTRL_FIFO_FULL;
 115         } else {
 116                 data_reg = MIPI_HS_GEN_DATA(port);
 117                 data_mask = HS_DATA_FIFO_FULL;
 118                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 119                 ctrl_mask = HS_CTRL_FIFO_FULL;
 120         }
 121
 122         /* note: this is never true for reads */
 123         if (packet.payload_length) {
 124
 125                 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
 126                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 127
 128                 write_data(dev_priv, data_reg, packet.payload,
 129                            packet.payload_length);
 130         }
 131
 132         if (msg->rx_len) {
 133                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 134         }
 135
 136         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
 137                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 138         }
 139
 140         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 141
 142         /* ->rx_len is set only for reads */
 143         if (msg->rx_len) {
 144                 data_mask = GEN_READ_DATA_AVAIL;
 145                 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
 146                         DRM_ERROR("Timeout waiting for read data.\n");
 147
 148                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 149         }
 150
 151         /* XXX: fix for reads and writes */
 152         return 4 + packet.payload_length;
 153 }
 154
 155 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 156                                  struct mipi_dsi_device *dsi)
 157 {
 158         return 0;
 159 }
 160
 161 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 162                                  struct mipi_dsi_device *dsi)
 163 {
 164         return 0;
 165 }
 166
 167 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 168         .attach = intel_dsi_host_attach,
 169         .detach = intel_dsi_host_detach,
 170         .transfer = intel_dsi_host_transfer,
 171 };
 172
 173 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 174                                                   enum port port)
 175 {
 176         struct intel_dsi_host *host;
 177         struct mipi_dsi_device *device;
 178
 179         host = kzalloc(sizeof(*host), GFP_KERNEL);
 180         if (!host)
 181                 return NULL;
 182
 183         host->base.ops = &intel_dsi_host_ops;
 184         host->intel_dsi = intel_dsi;
 185         host->port = port;
 186
 187         /*
 188          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 189          * have a host->dev, and we don't have OF stuff either. So just use the
 190          * dsi framework as a library and hope for the best. Create the dsi
 191          * devices by ourselves here too. Need to be careful though, because we
 192          * don't initialize any of the driver model devices here.
 193          */
 194         device = kzalloc(sizeof(*device), GFP_KERNEL);
 195         if (!device) {
 196                 kfree(host);
 197                 return NULL;
 198         }
 199
 200         device->host = &host->base;
 201         host->device = device;
 202
 203         return host;
 204 }
 205
 206 /*
 207  * send a video mode command
 208  *
 209  * XXX: commands with data in MIPI_DPI_DATA?
 210  */
 211 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 212                         enum port port)
 213 {
 214         struct drm_encoder *encoder = &intel_dsi->base.base;
 215         struct drm_device *dev = encoder->dev;
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         u32 mask;
 218
 219         /* XXX: pipe, hs */
 220         if (hs)
 221                 cmd &= ~DPI_LP_MODE;
 222         else
 223                 cmd |= DPI_LP_MODE;
 224
 225         /* clear bit */
 226         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 227
 228         /* XXX: old code skips write if control unchanged */
 229         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 230                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 231
 232         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 233
 234         mask = SPL_PKT_SENT_INTERRUPT;
 235         if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
 236                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 237
 238         return 0;
 239 }
 240
 241 static void band_gap_reset(struct drm_i915_private *dev_priv)
 242 {
 243         mutex_lock(&dev_priv->sb_lock);
 244
 245         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 246         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 247         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 248         udelay(150);
 249         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 250         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 251
 252         mutex_unlock(&dev_priv->sb_lock);
 253 }
 254
 255 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 256 {
 257         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 258 }
 259
 260 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 261 {
 262         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 263 }
 264
 265 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 266                                      struct intel_crtc_state *config)
 267 {
 268         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 269                                                    base);
 270         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 271         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 272         struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
 273
 274         DRM_DEBUG_KMS("\n");
 275
 276         if (fixed_mode)
 277                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 278
 279         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 280         adjusted_mode->flags = 0;
 281
 282         return true;
 283 }
 284
 285 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 286 {
 287         struct drm_device *dev = encoder->base.dev;
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 290         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 291         enum port port;
 292         u32 temp;
 293
 294         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 295                 temp = I915_READ(VLV_CHICKEN_3);
 296                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 297                                         intel_dsi->pixel_overlap <<
 298                                         PIXEL_OVERLAP_CNT_SHIFT;
 299                 I915_WRITE(VLV_CHICKEN_3, temp);
 300         }
 301
 302         for_each_dsi_port(port, intel_dsi->ports) {
 303                 temp = I915_READ(MIPI_PORT_CTRL(port));
 304                 temp &= ~LANE_CONFIGURATION_MASK;
 305                 temp &= ~DUAL_LINK_MODE_MASK;
 306
 307                 if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
 308                         temp |= (intel_dsi->dual_link - 1)
 309                                                 << DUAL_LINK_MODE_SHIFT;
 310                         temp |= intel_crtc->pipe ?
 311                                         LANE_CONFIGURATION_DUAL_LINK_B :
 312                                         LANE_CONFIGURATION_DUAL_LINK_A;
 313                 }
 314                 /* assert ip_tg_enable signal */
 315                 I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
 316                 POSTING_READ(MIPI_PORT_CTRL(port));
 317         }
 318 }
 319
 320 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 321 {
 322         struct drm_device *dev = encoder->base.dev;
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 325         enum port port;
 326         u32 temp;
 327
 328         for_each_dsi_port(port, intel_dsi->ports) {
 329                 /* de-assert ip_tg_enable signal */
 330                 temp = I915_READ(MIPI_PORT_CTRL(port));
 331                 I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
 332                 POSTING_READ(MIPI_PORT_CTRL(port));
 333         }
 334 }
 335
 336 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 337 {
 338         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 339         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 340         enum port port;
 341         u32 val;
 342
 343         DRM_DEBUG_KMS("\n");
 344
 345         mutex_lock(&dev_priv->sb_lock);
 346         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 347          * needed everytime after power gate */
 348         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 349         mutex_unlock(&dev_priv->sb_lock);
 350
 351         /* bandgap reset is needed after everytime we do power gate */
 352         band_gap_reset(dev_priv);
 353
 354         for_each_dsi_port(port, intel_dsi->ports) {
 355
 356                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 357                 usleep_range(2500, 3000);
 358
 359                 /* Enable MIPI PHY transparent latch
 360                  * Common bit for both MIPI Port A & MIPI Port C
 361                  * No similar bit in MIPI Port C reg
 362                  */
 363                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 364                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 365                 usleep_range(1000, 1500);
 366
 367                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 368                 usleep_range(2500, 3000);
 369
 370                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 371                 usleep_range(2500, 3000);
 372         }
 373 }
 374
 375 static void intel_dsi_enable(struct intel_encoder *encoder)
 376 {
 377         struct drm_device *dev = encoder->base.dev;
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 380         enum port port;
 381
 382         DRM_DEBUG_KMS("\n");
 383
 384         if (is_cmd_mode(intel_dsi)) {
 385                 for_each_dsi_port(port, intel_dsi->ports)
 386                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 387         } else {
 388                 msleep(20); /* XXX */
 389                 for_each_dsi_port(port, intel_dsi->ports)
 390                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 391                 msleep(100);
 392
 393                 drm_panel_enable(intel_dsi->panel);
 394
 395                 for_each_dsi_port(port, intel_dsi->ports)
 396                         wait_for_dsi_fifo_empty(intel_dsi, port);
 397
 398                 intel_dsi_port_enable(encoder);
 399         }
 400
 401         intel_panel_enable_backlight(intel_dsi->attached_connector);
 402 }
 403
 404 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 405 {
 406         struct drm_device *dev = encoder->base.dev;
 407         struct drm_i915_private *dev_priv = dev->dev_private;
 408         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 409         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 410         enum pipe pipe = intel_crtc->pipe;
 411         enum port port;
 412         u32 tmp;
 413
 414         DRM_DEBUG_KMS("\n");
 415
 416         /* Panel Enable over CRC PMIC */
 417         if (intel_dsi->gpio_panel)
 418                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 419
 420         msleep(intel_dsi->panel_on_delay);
 421
 422         /* Disable DPOunit clock gating, can stall pipe
 423          * and we need DPLL REFA always enabled */
 424         tmp = I915_READ(DPLL(pipe));
 425         tmp |= DPLL_REF_CLK_ENABLE_VLV;
 426         I915_WRITE(DPLL(pipe), tmp);
 427
 428         /* update the hw state for DPLL */
 429         intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
 430                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 431
 432         tmp = I915_READ(DSPCLK_GATE_D);
 433         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 434         I915_WRITE(DSPCLK_GATE_D, tmp);
 435
 436         /* put device in ready state */
 437         intel_dsi_device_ready(encoder);
 438
 439         drm_panel_prepare(intel_dsi->panel);
 440
 441         for_each_dsi_port(port, intel_dsi->ports)
 442                 wait_for_dsi_fifo_empty(intel_dsi, port);
 443
 444         /* Enable port in pre-enable phase itself because as per hw team
 445          * recommendation, port should be enabled befor plane & pipe */
 446         intel_dsi_enable(encoder);
 447 }
 448
 449 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 450 {
 451         DRM_DEBUG_KMS("\n");
 452
 453         /* for DSI port enable has to be done before pipe
 454          * and plane enable, so port enable is done in
 455          * pre_enable phase itself unlike other encoders
 456          */
 457 }
 458
 459 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 460 {
 461         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 462         enum port port;
 463
 464         DRM_DEBUG_KMS("\n");
 465
 466         intel_panel_disable_backlight(intel_dsi->attached_connector);
 467
 468         if (is_vid_mode(intel_dsi)) {
 469                 /* Send Shutdown command to the panel in LP mode */
 470                 for_each_dsi_port(port, intel_dsi->ports)
 471                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 472                 msleep(10);
 473         }
 474 }
 475
 476 static void intel_dsi_disable(struct intel_encoder *encoder)
 477 {
 478         struct drm_device *dev = encoder->base.dev;
 479         struct drm_i915_private *dev_priv = dev->dev_private;
 480         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 481         enum port port;
 482         u32 temp;
 483
 484         DRM_DEBUG_KMS("\n");
 485
 486         if (is_vid_mode(intel_dsi)) {
 487                 for_each_dsi_port(port, intel_dsi->ports)
 488                         wait_for_dsi_fifo_empty(intel_dsi, port);
 489
 490                 intel_dsi_port_disable(encoder);
 491                 msleep(2);
 492         }
 493
 494         for_each_dsi_port(port, intel_dsi->ports) {
 495                 /* Panel commands can be sent when clock is in LP11 */
 496                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 497
 498                 temp = I915_READ(MIPI_CTRL(port));
 499                 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 500                 I915_WRITE(MIPI_CTRL(port), temp |
 501                            intel_dsi->escape_clk_div <<
 502                            ESCAPE_CLOCK_DIVIDER_SHIFT);
 503
 504                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 505
 506                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 507                 temp &= ~VID_MODE_FORMAT_MASK;
 508                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 509
 510                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 511         }
 512         /* if disable packets are sent before sending shutdown packet then in
 513          * some next enable sequence send turn on packet error is observed */
 514         drm_panel_disable(intel_dsi->panel);
 515
 516         for_each_dsi_port(port, intel_dsi->ports)
 517                 wait_for_dsi_fifo_empty(intel_dsi, port);
 518 }
 519
 520 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 521 {
 522         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 523         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 524         enum port port;
 525         u32 val;
 526
 527         DRM_DEBUG_KMS("\n");
 528         for_each_dsi_port(port, intel_dsi->ports) {
 529
 530                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 531                                                         ULPS_STATE_ENTER);
 532                 usleep_range(2000, 2500);
 533
 534                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 535                                                         ULPS_STATE_EXIT);
 536                 usleep_range(2000, 2500);
 537
 538                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 539                                                         ULPS_STATE_ENTER);
 540                 usleep_range(2000, 2500);
 541
 542                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 543                  * only. MIPI Port C has no similar bit for checking
 544                  */
 545                 if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
 546                                                         == 0x00000), 30))
 547                         DRM_ERROR("DSI LP not going Low\n");
 548
 549                 /* Disable MIPI PHY transparent latch
 550                  * Common bit for both MIPI Port A & MIPI Port C
 551                  */
 552                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 553                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
 554                 usleep_range(1000, 1500);
 555
 556                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 557                 usleep_range(2000, 2500);
 558         }
 559
 560         intel_disable_dsi_pll(encoder);
 561 }
 562
 563 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 564 {
 565         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 566         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 567         u32 val;
 568
 569         DRM_DEBUG_KMS("\n");
 570
 571         intel_dsi_disable(encoder);
 572
 573         intel_dsi_clear_device_ready(encoder);
 574
 575         val = I915_READ(DSPCLK_GATE_D);
 576         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 577         I915_WRITE(DSPCLK_GATE_D, val);
 578
 579         drm_panel_unprepare(intel_dsi->panel);
 580
 581         msleep(intel_dsi->panel_off_delay);
 582         msleep(intel_dsi->panel_pwr_cycle_delay);
 583
 584         /* Panel Disable over CRC PMIC */
 585         if (intel_dsi->gpio_panel)
 586                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 587 }
 588
 589 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 590                                    enum pipe *pipe)
 591 {
 592         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 593         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 594         struct drm_device *dev = encoder->base.dev;
 595         enum intel_display_power_domain power_domain;
 596         u32 dpi_enabled, func;
 597         enum port port;
 598
 599         DRM_DEBUG_KMS("\n");
 600
 601         power_domain = intel_display_port_power_domain(encoder);
 602         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 603                 return false;
 604
 605         /* XXX: this only works for one DSI output */
 606         for_each_dsi_port(port, intel_dsi->ports) {
 607                 func = I915_READ(MIPI_DSI_FUNC_PRG(port));
 608                 dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
 609                                                         DPI_ENABLE;
 610
 611                 /* Due to some hardware limitations on BYT, MIPI Port C DPI
 612                  * Enable bit does not get set. To check whether DSI Port C
 613                  * was enabled in BIOS, check the Pipe B enable bit
 614                  */
 615                 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 616                     (port == PORT_C))
 617                         dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 618                                                         PIPECONF_ENABLE;
 619
 620                 if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 621                         if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
 622                                 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 623                                 return true;
 624                         }
 625                 }
 626         }
 627
 628         return false;
 629 }
 630
 631 static void intel_dsi_get_config(struct intel_encoder *encoder,
 632                                  struct intel_crtc_state *pipe_config)
 633 {
 634         u32 pclk;
 635         DRM_DEBUG_KMS("\n");
 636
 637         /*
 638          * DPLL_MD is not used in case of DSI, reading will get some default value
 639          * set dpll_md = 0
 640          */
 641         pipe_config->dpll_hw_state.dpll_md = 0;
 642
 643         pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 644         if (!pclk)
 645                 return;
 646
 647         pipe_config->base.adjusted_mode.crtc_clock = pclk;
 648         pipe_config->port_clock = pclk;
 649 }
 650
 651 static enum drm_mode_status
 652 intel_dsi_mode_valid(struct drm_connector *connector,
 653                      struct drm_display_mode *mode)
 654 {
 655         struct intel_connector *intel_connector = to_intel_connector(connector);
 656         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 657         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 658
 659         DRM_DEBUG_KMS("\n");
 660
 661         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 662                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 663                 return MODE_NO_DBLESCAN;
 664         }
 665
 666         if (fixed_mode) {
 667                 if (mode->hdisplay > fixed_mode->hdisplay)
 668                         return MODE_PANEL;
 669                 if (mode->vdisplay > fixed_mode->vdisplay)
 670                         return MODE_PANEL;
 671                 if (fixed_mode->clock > max_dotclk)
 672                         return MODE_CLOCK_HIGH;
 673         }
 674
 675         return MODE_OK;
 676 }
 677
 678 /* return txclkesc cycles in terms of divider and duration in us */
 679 static u16 txclkesc(u32 divider, unsigned int us)
 680 {
 681         switch (divider) {
 682         case ESCAPE_CLOCK_DIVIDER_1:
 683         default:
 684                 return 20 * us;
 685         case ESCAPE_CLOCK_DIVIDER_2:
 686                 return 10 * us;
 687         case ESCAPE_CLOCK_DIVIDER_4:
 688                 return 5 * us;
 689         }
 690 }
 691
 692 /* return pixels in terms of txbyteclkhs */
 693 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
 694                        u16 burst_mode_ratio)
 695 {
 696         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
 697                                          8 * 100), lane_count);
 698 }
 699
 700 static void set_dsi_timings(struct drm_encoder *encoder,
 701                             const struct drm_display_mode *mode)
 702 {
 703         struct drm_device *dev = encoder->dev;
 704         struct drm_i915_private *dev_priv = dev->dev_private;
 705         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 706         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 707         enum port port;
 708         unsigned int bpp = intel_crtc->config->pipe_bpp;
 709         unsigned int lane_count = intel_dsi->lane_count;
 710
 711         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 712
 713         hactive = mode->hdisplay;
 714         hfp = mode->hsync_start - mode->hdisplay;
 715         hsync = mode->hsync_end - mode->hsync_start;
 716         hbp = mode->htotal - mode->hsync_end;
 717
 718         if (intel_dsi->dual_link) {
 719                 hactive /= 2;
 720                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 721                         hactive += intel_dsi->pixel_overlap;
 722                 hfp /= 2;
 723                 hsync /= 2;
 724                 hbp /= 2;
 725         }
 726
 727         vfp = mode->vsync_start - mode->vdisplay;
 728         vsync = mode->vsync_end - mode->vsync_start;
 729         vbp = mode->vtotal - mode->vsync_end;
 730
 731         /* horizontal values are in terms of high speed byte clock */
 732         hactive = txbyteclkhs(hactive, bpp, lane_count,
 733                               intel_dsi->burst_mode_ratio);
 734         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 735         hsync = txbyteclkhs(hsync, bpp, lane_count,
 736                             intel_dsi->burst_mode_ratio);
 737         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 738
 739         for_each_dsi_port(port, intel_dsi->ports) {
 740                 if (IS_BROXTON(dev)) {
 741                         /*
 742                          * Program hdisplay and vdisplay on MIPI transcoder.
 743                          * This is different from calculated hactive and
 744                          * vactive, as they are calculated per channel basis,
 745                          * whereas these values should be based on resolution.
 746                          */
 747                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
 748                                         mode->hdisplay);
 749                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
 750                                         mode->vdisplay);
 751                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
 752                                         mode->vtotal);
 753                 }
 754
 755                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
 756                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
 757
 758                 /* meaningful for video mode non-burst sync pulse mode only,
 759                  * can be zero for non-burst sync events and burst modes */
 760                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
 761                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
 762
 763                 /* vertical values are in terms of lines */
 764                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
 765                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
 766                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
 767         }
 768 }
 769
 770 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 771 {
 772         struct drm_encoder *encoder = &intel_encoder->base;
 773         struct drm_device *dev = encoder->dev;
 774         struct drm_i915_private *dev_priv = dev->dev_private;
 775         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 776         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 777         struct drm_display_mode *adjusted_mode =
 778                 &intel_crtc->config->base.adjusted_mode;
 779         enum port port;
 780         unsigned int bpp = intel_crtc->config->pipe_bpp;
 781         u32 val, tmp;
 782         u16 mode_hdisplay;
 783
 784         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 785
 786         mode_hdisplay = adjusted_mode->hdisplay;
 787
 788         if (intel_dsi->dual_link) {
 789                 mode_hdisplay /= 2;
 790                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 791                         mode_hdisplay += intel_dsi->pixel_overlap;
 792         }
 793
 794         for_each_dsi_port(port, intel_dsi->ports) {
 795                 if (IS_VALLEYVIEW(dev)) {
 796                         /*
 797                          * escape clock divider, 20MHz, shared for A and C.
 798                          * device ready must be off when doing this! txclkesc?
 799                          */
 800                         tmp = I915_READ(MIPI_CTRL(PORT_A));
 801                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 802                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
 803                                         ESCAPE_CLOCK_DIVIDER_1);
 804
 805                         /* read request priority is per pipe */
 806                         tmp = I915_READ(MIPI_CTRL(port));
 807                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 808                         I915_WRITE(MIPI_CTRL(port), tmp |
 809                                         READ_REQUEST_PRIORITY_HIGH);
 810                 } else if (IS_BROXTON(dev)) {
 811                         /*
 812                          * FIXME:
 813                          * BXT can connect any PIPE to any MIPI port.
 814                          * Select the pipe based on the MIPI port read from
 815                          * VBT for now. Pick PIPE A for MIPI port A and C
 816                          * for port C.
 817                          */
 818                         tmp = I915_READ(MIPI_CTRL(port));
 819                         tmp &= ~BXT_PIPE_SELECT_MASK;
 820
 821                         if (port == PORT_A)
 822                                 tmp |= BXT_PIPE_SELECT_A;
 823                         else if (port == PORT_C)
 824                                 tmp |= BXT_PIPE_SELECT_C;
 825
 826                         I915_WRITE(MIPI_CTRL(port), tmp);
 827                 }
 828
 829                 /* XXX: why here, why like this? handling in irq handler?! */
 830                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
 831                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
 832
 833                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
 834
 835                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
 836                         adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 837                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 838         }
 839
 840         set_dsi_timings(encoder, adjusted_mode);
 841
 842         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 843         if (is_cmd_mode(intel_dsi)) {
 844                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 845                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 846         } else {
 847                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 848
 849                 /* XXX: cross-check bpp vs. pixel format? */
 850                 val |= intel_dsi->pixel_format;
 851         }
 852
 853         tmp = 0;
 854         if (intel_dsi->eotp_pkt == 0)
 855                 tmp |= EOT_DISABLE;
 856         if (intel_dsi->clock_stop)
 857                 tmp |= CLOCKSTOP;
 858
 859         for_each_dsi_port(port, intel_dsi->ports) {
 860                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 861
 862                 /* timeouts for recovery. one frame IIUC. if counter expires,
 863                  * EOT and stop state. */
 864
 865                 /*
 866                  * In burst mode, value greater than one DPI line Time in byte
 867                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
 868                  * said value is recommended.
 869                  *
 870                  * In non-burst mode, Value greater than one DPI frame time in
 871                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 872                  * said value is recommended.
 873                  *
 874                  * In DBI only mode, value greater than one DBI frame time in
 875                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 876                  * said value is recommended.
 877                  */
 878
 879                 if (is_vid_mode(intel_dsi) &&
 880                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 881                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 882                                 txbyteclkhs(adjusted_mode->htotal, bpp,
 883                                         intel_dsi->lane_count,
 884                                         intel_dsi->burst_mode_ratio) + 1);
 885                 } else {
 886                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 887                                 txbyteclkhs(adjusted_mode->vtotal *
 888                                         adjusted_mode->htotal,
 889                                         bpp, intel_dsi->lane_count,
 890                                         intel_dsi->burst_mode_ratio) + 1);
 891                 }
 892                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
 893                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
 894                                                 intel_dsi->turn_arnd_val);
 895                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
 896                                                 intel_dsi->rst_timer_val);
 897
 898                 /* dphy stuff */
 899
 900                 /* in terms of low power clock */
 901                 I915_WRITE(MIPI_INIT_COUNT(port),
 902                                 txclkesc(intel_dsi->escape_clk_div, 100));
 903
 904                 if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
 905                         /*
 906                          * BXT spec says write MIPI_INIT_COUNT for
 907                          * both the ports, even if only one is
 908                          * getting used. So write the other port
 909                          * if not in dual link mode.
 910                          */
 911                         I915_WRITE(MIPI_INIT_COUNT(port ==
 912                                                 PORT_A ? PORT_C : PORT_A),
 913                                         intel_dsi->init_count);
 914                 }
 915
 916                 /* recovery disables */
 917                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
 918
 919                 /* in terms of low power clock */
 920                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
 921
 922                 /* in terms of txbyteclkhs. actual high to low switch +
 923                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 924                  *
 925                  * XXX: write MIPI_STOP_STATE_STALL?
 926                  */
 927                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
 928                                                 intel_dsi->hs_to_lp_count);
 929
 930                 /* XXX: low power clock equivalence in terms of byte clock.
 931                  * the number of byte clocks occupied in one low power clock.
 932                  * based on txbyteclkhs and txclkesc.
 933                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
 934                  * ) / 105.???
 935                  */
 936                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
 937
 938                 /* the bw essential for transmitting 16 long packets containing
 939                  * 252 bytes meant for dcs write memory command is programmed in
 940                  * this register in terms of byte clocks. based on dsi transfer
 941                  * rate and the number of lanes configured the time taken to
 942                  * transmit 16 long packets in a dsi stream varies. */
 943                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
 944
 945                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
 946                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 947                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 948
 949                 if (is_vid_mode(intel_dsi))
 950                         /* Some panels might have resolution which is not a
 951                          * multiple of 64 like 1366 x 768. Enable RANDOM
 952                          * resolution support for such panels by default */
 953                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
 954                                 intel_dsi->video_frmt_cfg_bits |
 955                                 intel_dsi->video_mode_format |
 956                                 IP_TG_CONFIG |
 957                                 RANDOM_DPI_DISPLAY_RESOLUTION);
 958         }
 959 }
 960
 961 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 962 {
 963         DRM_DEBUG_KMS("\n");
 964
 965         intel_dsi_prepare(encoder);
 966         intel_enable_dsi_pll(encoder);
 967
 968 }
 969
 970 static enum drm_connector_status
 971 intel_dsi_detect(struct drm_connector *connector, bool force)
 972 {
 973         return connector_status_connected;
 974 }
 975
 976 static int intel_dsi_get_modes(struct drm_connector *connector)
 977 {
 978         struct intel_connector *intel_connector = to_intel_connector(connector);
 979         struct drm_display_mode *mode;
 980
 981         DRM_DEBUG_KMS("\n");
 982
 983         if (!intel_connector->panel.fixed_mode) {
 984                 DRM_DEBUG_KMS("no fixed mode\n");
 985                 return 0;
 986         }
 987
 988         mode = drm_mode_duplicate(connector->dev,
 989                                   intel_connector->panel.fixed_mode);
 990         if (!mode) {
 991                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 992                 return 0;
 993         }
 994
 995         drm_mode_probed_add(connector, mode);
 996         return 1;
 997 }
 998
 999 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1000 {
1001         struct intel_connector *intel_connector = to_intel_connector(connector);
1002
1003         DRM_DEBUG_KMS("\n");
1004         intel_panel_fini(&intel_connector->panel);
1005         drm_connector_cleanup(connector);
1006         kfree(connector);
1007 }
1008
1009 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1010 {
1011         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1012
1013         if (intel_dsi->panel) {
1014                 drm_panel_detach(intel_dsi->panel);
1015                 /* XXX: Logically this call belongs in the panel driver. */
1016                 drm_panel_remove(intel_dsi->panel);
1017         }
1018
1019         /* dispose of the gpios */
1020         if (intel_dsi->gpio_panel)
1021                 gpiod_put(intel_dsi->gpio_panel);
1022
1023         intel_encoder_destroy(encoder);
1024 }
1025
1026 static const struct drm_encoder_funcs intel_dsi_funcs = {
1027         .destroy = intel_dsi_encoder_destroy,
1028 };
1029
1030 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1031         .get_modes = intel_dsi_get_modes,
1032         .mode_valid = intel_dsi_mode_valid,
1033         .best_encoder = intel_best_encoder,
1034 };
1035
1036 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1037         .dpms = drm_atomic_helper_connector_dpms,
1038         .detect = intel_dsi_detect,
1039         .destroy = intel_dsi_connector_destroy,
1040         .fill_modes = drm_helper_probe_single_connector_modes,
1041         .atomic_get_property = intel_connector_atomic_get_property,
1042         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1043         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1044 };
1045
1046 void intel_dsi_init(struct drm_device *dev)
1047 {
1048         struct intel_dsi *intel_dsi;
1049         struct intel_encoder *intel_encoder;
1050         struct drm_encoder *encoder;
1051         struct intel_connector *intel_connector;
1052         struct drm_connector *connector;
1053         struct drm_display_mode *scan, *fixed_mode = NULL;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         enum port port;
1056         unsigned int i;
1057
1058         DRM_DEBUG_KMS("\n");
1059
1060         /* There is no detection method for MIPI so rely on VBT */
1061         if (!dev_priv->vbt.has_mipi)
1062                 return;
1063
1064         if (IS_VALLEYVIEW(dev)) {
1065                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1066         } else {
1067                 DRM_ERROR("Unsupported Mipi device to reg base");
1068                 return;
1069         }
1070
1071         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1072         if (!intel_dsi)
1073                 return;
1074
1075         intel_connector = intel_connector_alloc();
1076         if (!intel_connector) {
1077                 kfree(intel_dsi);
1078                 return;
1079         }
1080
1081         intel_encoder = &intel_dsi->base;
1082         encoder = &intel_encoder->base;
1083         intel_dsi->attached_connector = intel_connector;
1084
1085         connector = &intel_connector->base;
1086
1087         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
1088
1089         /* XXX: very likely not all of these are needed */
1090         intel_encoder->compute_config = intel_dsi_compute_config;
1091         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
1092         intel_encoder->pre_enable = intel_dsi_pre_enable;
1093         intel_encoder->enable = intel_dsi_enable_nop;
1094         intel_encoder->disable = intel_dsi_pre_disable;
1095         intel_encoder->post_disable = intel_dsi_post_disable;
1096         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1097         intel_encoder->get_config = intel_dsi_get_config;
1098
1099         intel_connector->get_hw_state = intel_connector_get_hw_state;
1100         intel_connector->unregister = intel_connector_unregister;
1101
1102         /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1103         if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
1104                 intel_encoder->crtc_mask = (1 << PIPE_A);
1105                 intel_dsi->ports = (1 << PORT_A);
1106         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
1107                 intel_encoder->crtc_mask = (1 << PIPE_B);
1108                 intel_dsi->ports = (1 << PORT_C);
1109         }
1110
1111         if (dev_priv->vbt.dsi.config->dual_link)
1112                 intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
1113
1114         /* Create a DSI host (and a device) for each port. */
1115         for_each_dsi_port(port, intel_dsi->ports) {
1116                 struct intel_dsi_host *host;
1117
1118                 host = intel_dsi_host_init(intel_dsi, port);
1119                 if (!host)
1120                         goto err;
1121
1122                 intel_dsi->dsi_hosts[port] = host;
1123         }
1124
1125         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1126                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1127                                                              intel_dsi_drivers[i].panel_id);
1128                 if (intel_dsi->panel)
1129                         break;
1130         }
1131
1132         if (!intel_dsi->panel) {
1133                 DRM_DEBUG_KMS("no device found\n");
1134                 goto err;
1135         }
1136
1137         /*
1138          * In case of BYT with CRC PMIC, we need to use GPIO for
1139          * Panel control.
1140          */
1141         if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1142                 intel_dsi->gpio_panel =
1143                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1144
1145                 if (IS_ERR(intel_dsi->gpio_panel)) {
1146                         DRM_ERROR("Failed to own gpio for panel control\n");
1147                         intel_dsi->gpio_panel = NULL;
1148                 }
1149         }
1150
1151         intel_encoder->type = INTEL_OUTPUT_DSI;
1152         intel_encoder->cloneable = 0;
1153         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1154                            DRM_MODE_CONNECTOR_DSI);
1155
1156         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1157
1158         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1159         connector->interlace_allowed = false;
1160         connector->doublescan_allowed = false;
1161
1162         intel_connector_attach_encoder(intel_connector, intel_encoder);
1163
1164         drm_connector_register(connector);
1165
1166         drm_panel_attach(intel_dsi->panel, connector);
1167
1168         mutex_lock(&dev->mode_config.mutex);
1169         drm_panel_get_modes(intel_dsi->panel);
1170         list_for_each_entry(scan, &connector->probed_modes, head) {
1171                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1172                         fixed_mode = drm_mode_duplicate(dev, scan);
1173                         break;
1174                 }
1175         }
1176         mutex_unlock(&dev->mode_config.mutex);
1177
1178         if (!fixed_mode) {
1179                 DRM_DEBUG_KMS("no fixed mode\n");
1180                 goto err;
1181         }
1182
1183         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1184         intel_panel_setup_backlight(connector, INVALID_PIPE);
1185
1186         return;
1187
1188 err:
1189         drm_encoder_cleanup(&intel_encoder->base);
1190         kfree(intel_dsi);
1191         kfree(intel_connector);
1192 }