drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 static bool
  43 format_is_yuv(uint32_t format)
  44 {
  45         switch (format) {
  46         case DRM_FORMAT_YUYV:
  47         case DRM_FORMAT_UYVY:
  48         case DRM_FORMAT_VYUY:
  49         case DRM_FORMAT_YVYU:
  50                 return true;
  51         default:
  52                 return false;
  53         }
  54 }
  55
  56 static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
  57 {
  58         /* paranoia */
  59         if (!mode->crtc_htotal)
  60                 return 1;
  61
  62         return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
  63 }
  64
  65 /**
  66  * intel_pipe_update_start() - start update of a set of display registers
  67  * @crtc: the crtc of which the registers are going to be updated
  68  * @start_vbl_count: vblank counter return pointer used for error checking
  69  *
  70  * Mark the start of an update to pipe registers that should be updated
  71  * atomically regarding vblank. If the next vblank will happens within
  72  * the next 100 us, this function waits until the vblank passes.
  73  *
  74  * After a successful call to this function, interrupts will be disabled
  75  * until a subsequent call to intel_pipe_update_end(). That is done to
  76  * avoid random delays. The value written to @start_vbl_count should be
  77  * supplied to intel_pipe_update_end() for error checking.
  78  */
  79 void intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
  80 {
  81         struct drm_device *dev = crtc->base.dev;
  82         const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
  83         enum pipe pipe = crtc->pipe;
  84         long timeout = msecs_to_jiffies_timeout(1);
  85         int scanline, min, max, vblank_start;
  86         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  87         DEFINE_WAIT(wait);
  88
  89         vblank_start = mode->crtc_vblank_start;
  90         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  91                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  92
  93         /* FIXME needs to be calibrated sensibly */
  94         min = vblank_start - usecs_to_scanlines(mode, 100);
  95         max = vblank_start - 1;
  96
  97         local_irq_disable();
  98         *start_vbl_count = 0;
  99
 100         if (min <= 0 || max <= 0)
 101                 return;
 102
 103         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 104                 return;
 105
 106         trace_i915_pipe_update_start(crtc, min, max);
 107
 108         for (;;) {
 109                 /*
 110                  * prepare_to_wait() has a memory barrier, which guarantees
 111                  * other CPUs can see the task state update by the time we
 112                  * read the scanline.
 113                  */
 114                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 115
 116                 scanline = intel_get_crtc_scanline(crtc);
 117                 if (scanline < min || scanline > max)
 118                         break;
 119
 120                 if (timeout <= 0) {
 121                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 122                                   pipe_name(crtc->pipe));
 123                         break;
 124                 }
 125
 126                 local_irq_enable();
 127
 128                 timeout = schedule_timeout(timeout);
 129
 130                 local_irq_disable();
 131         }
 132
 133         finish_wait(wq, &wait);
 134
 135         drm_crtc_vblank_put(&crtc->base);
 136
 137         *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 138
 139         trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
 140 }
 141
 142 /**
 143  * intel_pipe_update_end() - end update of a set of display registers
 144  * @crtc: the crtc of which the registers were updated
 145  * @start_vbl_count: start vblank counter (used for error checking)
 146  *
 147  * Mark the end of an update started with intel_pipe_update_start(). This
 148  * re-enables interrupts and verifies the update was actually completed
 149  * before a vblank using the value of @start_vbl_count.
 150  */
 151 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
 152 {
 153         struct drm_device *dev = crtc->base.dev;
 154         enum pipe pipe = crtc->pipe;
 155         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 156
 157         trace_i915_pipe_update_end(crtc, end_vbl_count);
 158
 159         local_irq_enable();
 160
 161         if (start_vbl_count && start_vbl_count != end_vbl_count)
 162                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
 163                           pipe_name(pipe), start_vbl_count, end_vbl_count);
 164 }
 165
 166 static void
 167 skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 168                  struct drm_framebuffer *fb,
 169                  int crtc_x, int crtc_y,
 170                  unsigned int crtc_w, unsigned int crtc_h,
 171                  uint32_t x, uint32_t y,
 172                  uint32_t src_w, uint32_t src_h)
 173 {
 174         struct drm_device *dev = drm_plane->dev;
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 177         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 178         const int pipe = intel_plane->pipe;
 179         const int plane = intel_plane->plane + 1;
 180         u32 plane_ctl, stride_div, stride;
 181         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 182         const struct drm_intel_sprite_colorkey *key =
 183                 &to_intel_plane_state(drm_plane->state)->ckey;
 184         unsigned long surf_addr;
 185         u32 tile_height, plane_offset, plane_size;
 186         unsigned int rotation;
 187         int x_offset, y_offset;
 188         struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
 189         int scaler_id;
 190
 191         plane_ctl = PLANE_CTL_ENABLE |
 192                 PLANE_CTL_PIPE_CSC_ENABLE;
 193
 194         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 195         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 196
 197         rotation = drm_plane->state->rotation;
 198         plane_ctl |= skl_plane_ctl_rotation(rotation);
 199
 200         intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
 201                                        pixel_size, true,
 202                                        src_w != crtc_w || src_h != crtc_h);
 203
 204         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
 205                                                fb->pixel_format);
 206
 207         scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
 208
 209         /* Sizes are 0 based */
 210         src_w--;
 211         src_h--;
 212         crtc_w--;
 213         crtc_h--;
 214
 215         if (key->flags) {
 216                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 217                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 218                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 219         }
 220
 221         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 222                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 223         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 224                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 225
 226         surf_addr = intel_plane_obj_offset(intel_plane, obj);
 227
 228         if (intel_rotation_90_or_270(rotation)) {
 229                 /* stride: Surface height in tiles */
 230                 tile_height = intel_tile_height(dev, fb->pixel_format,
 231                                                 fb->modifier[0]);
 232                 stride = DIV_ROUND_UP(fb->height, tile_height);
 233                 plane_size = (src_w << 16) | src_h;
 234                 x_offset = stride * tile_height - y - (src_h + 1);
 235                 y_offset = x;
 236         } else {
 237                 stride = fb->pitches[0] / stride_div;
 238                 plane_size = (src_h << 16) | src_w;
 239                 x_offset = x;
 240                 y_offset = y;
 241         }
 242         plane_offset = y_offset << 16 | x_offset;
 243
 244         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
 245         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 246         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
 247
 248         /* program plane scaler */
 249         if (scaler_id >= 0) {
 250                 uint32_t ps_ctrl = 0;
 251
 252                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 253                         PS_PLANE_SEL(plane));
 254                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
 255                         crtc_state->scaler_state.scalers[scaler_id].mode;
 256                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
 257                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 258                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 259                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 260                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 261
 262                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 263         } else {
 264                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 265         }
 266
 267         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 268         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
 269         POSTING_READ(PLANE_SURF(pipe, plane));
 270 }
 271
 272 static void
 273 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 274 {
 275         struct drm_device *dev = dplane->dev;
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         struct intel_plane *intel_plane = to_intel_plane(dplane);
 278         const int pipe = intel_plane->pipe;
 279         const int plane = intel_plane->plane + 1;
 280
 281         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 282
 283         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 284         POSTING_READ(PLANE_SURF(pipe, plane));
 285
 286         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
 287 }
 288
 289 static void
 290 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 291 {
 292         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
 293         int plane = intel_plane->plane;
 294
 295         /* Seems RGB data bypasses the CSC always */
 296         if (!format_is_yuv(format))
 297                 return;
 298
 299         /*
 300          * BT.601 limited range YCbCr -> full range RGB
 301          *
 302          * |r|   | 6537 4769     0|   |cr  |
 303          * |g| = |-3330 4769 -1605| x |y-64|
 304          * |b|   |    0 4769  8263|   |cb  |
 305          *
 306          * Cb and Cr apparently come in as signed already, so no
 307          * need for any offset. For Y we need to remove the offset.
 308          */
 309         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 310         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 311         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 312
 313         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 314         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 315         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 316         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 317         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 318
 319         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 320         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 321         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 322
 323         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 324         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 325         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 326 }
 327
 328 static void
 329 vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 330                  struct drm_framebuffer *fb,
 331                  int crtc_x, int crtc_y,
 332                  unsigned int crtc_w, unsigned int crtc_h,
 333                  uint32_t x, uint32_t y,
 334                  uint32_t src_w, uint32_t src_h)
 335 {
 336         struct drm_device *dev = dplane->dev;
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         struct intel_plane *intel_plane = to_intel_plane(dplane);
 339         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 340         int pipe = intel_plane->pipe;
 341         int plane = intel_plane->plane;
 342         u32 sprctl;
 343         unsigned long sprsurf_offset, linear_offset;
 344         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 345         const struct drm_intel_sprite_colorkey *key =
 346                 &to_intel_plane_state(dplane->state)->ckey;
 347
 348         sprctl = SP_ENABLE;
 349
 350         switch (fb->pixel_format) {
 351         case DRM_FORMAT_YUYV:
 352                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 353                 break;
 354         case DRM_FORMAT_YVYU:
 355                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 356                 break;
 357         case DRM_FORMAT_UYVY:
 358                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 359                 break;
 360         case DRM_FORMAT_VYUY:
 361                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 362                 break;
 363         case DRM_FORMAT_RGB565:
 364                 sprctl |= SP_FORMAT_BGR565;
 365                 break;
 366         case DRM_FORMAT_XRGB8888:
 367                 sprctl |= SP_FORMAT_BGRX8888;
 368                 break;
 369         case DRM_FORMAT_ARGB8888:
 370                 sprctl |= SP_FORMAT_BGRA8888;
 371                 break;
 372         case DRM_FORMAT_XBGR2101010:
 373                 sprctl |= SP_FORMAT_RGBX1010102;
 374                 break;
 375         case DRM_FORMAT_ABGR2101010:
 376                 sprctl |= SP_FORMAT_RGBA1010102;
 377                 break;
 378         case DRM_FORMAT_XBGR8888:
 379                 sprctl |= SP_FORMAT_RGBX8888;
 380                 break;
 381         case DRM_FORMAT_ABGR8888:
 382                 sprctl |= SP_FORMAT_RGBA8888;
 383                 break;
 384         default:
 385                 /*
 386                  * If we get here one of the upper layers failed to filter
 387                  * out the unsupported plane formats
 388                  */
 389                 BUG();
 390                 break;
 391         }
 392
 393         /*
 394          * Enable gamma to match primary/cursor plane behaviour.
 395          * FIXME should be user controllable via propertiesa.
 396          */
 397         sprctl |= SP_GAMMA_ENABLE;
 398
 399         if (obj->tiling_mode != I915_TILING_NONE)
 400                 sprctl |= SP_TILED;
 401
 402         /* Sizes are 0 based */
 403         src_w--;
 404         src_h--;
 405         crtc_w--;
 406         crtc_h--;
 407
 408         linear_offset = y * fb->pitches[0] + x * pixel_size;
 409         sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
 410                                                         &x, &y,
 411                                                         obj->tiling_mode,
 412                                                         pixel_size,
 413                                                         fb->pitches[0]);
 414         linear_offset -= sprsurf_offset;
 415
 416         if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
 417                 sprctl |= SP_ROTATE_180;
 418
 419                 x += src_w;
 420                 y += src_h;
 421                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 422         }
 423
 424         if (key->flags) {
 425                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 426                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 427                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 428         }
 429
 430         if (key->flags & I915_SET_COLORKEY_SOURCE)
 431                 sprctl |= SP_SOURCE_KEY;
 432
 433         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 434                 chv_update_csc(intel_plane, fb->pixel_format);
 435
 436         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 437         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 438
 439         if (obj->tiling_mode != I915_TILING_NONE)
 440                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 441         else
 442                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 443
 444         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 445
 446         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 447         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 448         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 449                    sprsurf_offset);
 450         POSTING_READ(SPSURF(pipe, plane));
 451 }
 452
 453 static void
 454 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 455 {
 456         struct drm_device *dev = dplane->dev;
 457         struct drm_i915_private *dev_priv = dev->dev_private;
 458         struct intel_plane *intel_plane = to_intel_plane(dplane);
 459         int pipe = intel_plane->pipe;
 460         int plane = intel_plane->plane;
 461
 462         I915_WRITE(SPCNTR(pipe, plane), 0);
 463
 464         I915_WRITE(SPSURF(pipe, plane), 0);
 465         POSTING_READ(SPSURF(pipe, plane));
 466 }
 467
 468 static void
 469 ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 470                  struct drm_framebuffer *fb,
 471                  int crtc_x, int crtc_y,
 472                  unsigned int crtc_w, unsigned int crtc_h,
 473                  uint32_t x, uint32_t y,
 474                  uint32_t src_w, uint32_t src_h)
 475 {
 476         struct drm_device *dev = plane->dev;
 477         struct drm_i915_private *dev_priv = dev->dev_private;
 478         struct intel_plane *intel_plane = to_intel_plane(plane);
 479         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 480         enum pipe pipe = intel_plane->pipe;
 481         u32 sprctl, sprscale = 0;
 482         unsigned long sprsurf_offset, linear_offset;
 483         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 484         const struct drm_intel_sprite_colorkey *key =
 485                 &to_intel_plane_state(plane->state)->ckey;
 486
 487         sprctl = SPRITE_ENABLE;
 488
 489         switch (fb->pixel_format) {
 490         case DRM_FORMAT_XBGR8888:
 491                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 492                 break;
 493         case DRM_FORMAT_XRGB8888:
 494                 sprctl |= SPRITE_FORMAT_RGBX888;
 495                 break;
 496         case DRM_FORMAT_YUYV:
 497                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 498                 break;
 499         case DRM_FORMAT_YVYU:
 500                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 501                 break;
 502         case DRM_FORMAT_UYVY:
 503                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 504                 break;
 505         case DRM_FORMAT_VYUY:
 506                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 507                 break;
 508         default:
 509                 BUG();
 510         }
 511
 512         /*
 513          * Enable gamma to match primary/cursor plane behaviour.
 514          * FIXME should be user controllable via propertiesa.
 515          */
 516         sprctl |= SPRITE_GAMMA_ENABLE;
 517
 518         if (obj->tiling_mode != I915_TILING_NONE)
 519                 sprctl |= SPRITE_TILED;
 520
 521         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 522                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 523         else
 524                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 525
 526         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 527                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 528
 529         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
 530                                        true,
 531                                        src_w != crtc_w || src_h != crtc_h);
 532
 533         /* Sizes are 0 based */
 534         src_w--;
 535         src_h--;
 536         crtc_w--;
 537         crtc_h--;
 538
 539         if (crtc_w != src_w || crtc_h != src_h)
 540                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 541
 542         linear_offset = y * fb->pitches[0] + x * pixel_size;
 543         sprsurf_offset =
 544                 intel_gen4_compute_page_offset(dev_priv,
 545                                                &x, &y, obj->tiling_mode,
 546                                                pixel_size, fb->pitches[0]);
 547         linear_offset -= sprsurf_offset;
 548
 549         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 550                 sprctl |= SPRITE_ROTATE_180;
 551
 552                 /* HSW and BDW does this automagically in hardware */
 553                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 554                         x += src_w;
 555                         y += src_h;
 556                         linear_offset += src_h * fb->pitches[0] +
 557                                 src_w * pixel_size;
 558                 }
 559         }
 560
 561         if (key->flags) {
 562                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 563                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 564                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 565         }
 566
 567         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 568                 sprctl |= SPRITE_DEST_KEY;
 569         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 570                 sprctl |= SPRITE_SOURCE_KEY;
 571
 572         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 573         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 574
 575         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 576          * register */
 577         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 578                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 579         else if (obj->tiling_mode != I915_TILING_NONE)
 580                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 581         else
 582                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 583
 584         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 585         if (intel_plane->can_scale)
 586                 I915_WRITE(SPRSCALE(pipe), sprscale);
 587         I915_WRITE(SPRCTL(pipe), sprctl);
 588         I915_WRITE(SPRSURF(pipe),
 589                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 590         POSTING_READ(SPRSURF(pipe));
 591 }
 592
 593 static void
 594 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 595 {
 596         struct drm_device *dev = plane->dev;
 597         struct drm_i915_private *dev_priv = dev->dev_private;
 598         struct intel_plane *intel_plane = to_intel_plane(plane);
 599         int pipe = intel_plane->pipe;
 600
 601         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 602         /* Can't leave the scaler enabled... */
 603         if (intel_plane->can_scale)
 604                 I915_WRITE(SPRSCALE(pipe), 0);
 605
 606         I915_WRITE(SPRSURF(pipe), 0);
 607         POSTING_READ(SPRSURF(pipe));
 608 }
 609
 610 static void
 611 ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 612                  struct drm_framebuffer *fb,
 613                  int crtc_x, int crtc_y,
 614                  unsigned int crtc_w, unsigned int crtc_h,
 615                  uint32_t x, uint32_t y,
 616                  uint32_t src_w, uint32_t src_h)
 617 {
 618         struct drm_device *dev = plane->dev;
 619         struct drm_i915_private *dev_priv = dev->dev_private;
 620         struct intel_plane *intel_plane = to_intel_plane(plane);
 621         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 622         int pipe = intel_plane->pipe;
 623         unsigned long dvssurf_offset, linear_offset;
 624         u32 dvscntr, dvsscale;
 625         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 626         const struct drm_intel_sprite_colorkey *key =
 627                 &to_intel_plane_state(plane->state)->ckey;
 628
 629         dvscntr = DVS_ENABLE;
 630
 631         switch (fb->pixel_format) {
 632         case DRM_FORMAT_XBGR8888:
 633                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 634                 break;
 635         case DRM_FORMAT_XRGB8888:
 636                 dvscntr |= DVS_FORMAT_RGBX888;
 637                 break;
 638         case DRM_FORMAT_YUYV:
 639                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 640                 break;
 641         case DRM_FORMAT_YVYU:
 642                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 643                 break;
 644         case DRM_FORMAT_UYVY:
 645                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 646                 break;
 647         case DRM_FORMAT_VYUY:
 648                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 649                 break;
 650         default:
 651                 BUG();
 652         }
 653
 654         /*
 655          * Enable gamma to match primary/cursor plane behaviour.
 656          * FIXME should be user controllable via propertiesa.
 657          */
 658         dvscntr |= DVS_GAMMA_ENABLE;
 659
 660         if (obj->tiling_mode != I915_TILING_NONE)
 661                 dvscntr |= DVS_TILED;
 662
 663         if (IS_GEN6(dev))
 664                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 665
 666         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
 667                                        pixel_size, true,
 668                                        src_w != crtc_w || src_h != crtc_h);
 669
 670         /* Sizes are 0 based */
 671         src_w--;
 672         src_h--;
 673         crtc_w--;
 674         crtc_h--;
 675
 676         dvsscale = 0;
 677         if (crtc_w != src_w || crtc_h != src_h)
 678                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 679
 680         linear_offset = y * fb->pitches[0] + x * pixel_size;
 681         dvssurf_offset =
 682                 intel_gen4_compute_page_offset(dev_priv,
 683                                                &x, &y, obj->tiling_mode,
 684                                                pixel_size, fb->pitches[0]);
 685         linear_offset -= dvssurf_offset;
 686
 687         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
 688                 dvscntr |= DVS_ROTATE_180;
 689
 690                 x += src_w;
 691                 y += src_h;
 692                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
 693         }
 694
 695         if (key->flags) {
 696                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 697                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 698                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 699         }
 700
 701         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 702                 dvscntr |= DVS_DEST_KEY;
 703         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 704                 dvscntr |= DVS_SOURCE_KEY;
 705
 706         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 707         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 708
 709         if (obj->tiling_mode != I915_TILING_NONE)
 710                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 711         else
 712                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 713
 714         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 715         I915_WRITE(DVSSCALE(pipe), dvsscale);
 716         I915_WRITE(DVSCNTR(pipe), dvscntr);
 717         I915_WRITE(DVSSURF(pipe),
 718                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 719         POSTING_READ(DVSSURF(pipe));
 720 }
 721
 722 static void
 723 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 724 {
 725         struct drm_device *dev = plane->dev;
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         struct intel_plane *intel_plane = to_intel_plane(plane);
 728         int pipe = intel_plane->pipe;
 729
 730         I915_WRITE(DVSCNTR(pipe), 0);
 731         /* Disable the scaler */
 732         I915_WRITE(DVSSCALE(pipe), 0);
 733
 734         I915_WRITE(DVSSURF(pipe), 0);
 735         POSTING_READ(DVSSURF(pipe));
 736 }
 737
 738 static int
 739 intel_check_sprite_plane(struct drm_plane *plane,
 740                          struct intel_crtc_state *crtc_state,
 741                          struct intel_plane_state *state)
 742 {
 743         struct drm_device *dev = plane->dev;
 744         struct drm_crtc *crtc = state->base.crtc;
 745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 746         struct intel_plane *intel_plane = to_intel_plane(plane);
 747         struct drm_framebuffer *fb = state->base.fb;
 748         int crtc_x, crtc_y;
 749         unsigned int crtc_w, crtc_h;
 750         uint32_t src_x, src_y, src_w, src_h;
 751         struct drm_rect *src = &state->src;
 752         struct drm_rect *dst = &state->dst;
 753         const struct drm_rect *clip = &state->clip;
 754         int hscale, vscale;
 755         int max_scale, min_scale;
 756         bool can_scale;
 757         int pixel_size;
 758
 759         if (!fb) {
 760                 state->visible = false;
 761                 return 0;
 762         }
 763
 764         /* Don't modify another pipe's plane */
 765         if (intel_plane->pipe != intel_crtc->pipe) {
 766                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 767                 return -EINVAL;
 768         }
 769
 770         /* FIXME check all gen limits */
 771         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 772                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 773                 return -EINVAL;
 774         }
 775
 776         /* setup can_scale, min_scale, max_scale */
 777         if (INTEL_INFO(dev)->gen >= 9) {
 778                 /* use scaler when colorkey is not required */
 779                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 780                         can_scale = 1;
 781                         min_scale = 1;
 782                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 783                 } else {
 784                         can_scale = 0;
 785                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 786                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 787                 }
 788         } else {
 789                 can_scale = intel_plane->can_scale;
 790                 max_scale = intel_plane->max_downscale << 16;
 791                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 792         }
 793
 794         /*
 795          * FIXME the following code does a bunch of fuzzy adjustments to the
 796          * coordinates and sizes. We probably need some way to decide whether
 797          * more strict checking should be done instead.
 798          */
 799         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 800                         state->base.rotation);
 801
 802         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 803         BUG_ON(hscale < 0);
 804
 805         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 806         BUG_ON(vscale < 0);
 807
 808         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 809
 810         crtc_x = dst->x1;
 811         crtc_y = dst->y1;
 812         crtc_w = drm_rect_width(dst);
 813         crtc_h = drm_rect_height(dst);
 814
 815         if (state->visible) {
 816                 /* check again in case clipping clamped the results */
 817                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 818                 if (hscale < 0) {
 819                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 820                         drm_rect_debug_print(src, true);
 821                         drm_rect_debug_print(dst, false);
 822
 823                         return hscale;
 824                 }
 825
 826                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 827                 if (vscale < 0) {
 828                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 829                         drm_rect_debug_print(src, true);
 830                         drm_rect_debug_print(dst, false);
 831
 832                         return vscale;
 833                 }
 834
 835                 /* Make the source viewport size an exact multiple of the scaling factors. */
 836                 drm_rect_adjust_size(src,
 837                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 838                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 839
 840                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 841                                     state->base.rotation);
 842
 843                 /* sanity check to make sure the src viewport wasn't enlarged */
 844                 WARN_ON(src->x1 < (int) state->base.src_x ||
 845                         src->y1 < (int) state->base.src_y ||
 846                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 847                         src->y2 > (int) state->base.src_y + state->base.src_h);
 848
 849                 /*
 850                  * Hardware doesn't handle subpixel coordinates.
 851                  * Adjust to (macro)pixel boundary, but be careful not to
 852                  * increase the source viewport size, because that could
 853                  * push the downscaling factor out of bounds.
 854                  */
 855                 src_x = src->x1 >> 16;
 856                 src_w = drm_rect_width(src) >> 16;
 857                 src_y = src->y1 >> 16;
 858                 src_h = drm_rect_height(src) >> 16;
 859
 860                 if (format_is_yuv(fb->pixel_format)) {
 861                         src_x &= ~1;
 862                         src_w &= ~1;
 863
 864                         /*
 865                          * Must keep src and dst the
 866                          * same if we can't scale.
 867                          */
 868                         if (!can_scale)
 869                                 crtc_w &= ~1;
 870
 871                         if (crtc_w == 0)
 872                                 state->visible = false;
 873                 }
 874         }
 875
 876         /* Check size restrictions when scaling */
 877         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 878                 unsigned int width_bytes;
 879
 880                 WARN_ON(!can_scale);
 881
 882                 /* FIXME interlacing min height is 6 */
 883
 884                 if (crtc_w < 3 || crtc_h < 3)
 885                         state->visible = false;
 886
 887                 if (src_w < 3 || src_h < 3)
 888                         state->visible = false;
 889
 890                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 891                 width_bytes = ((src_x * pixel_size) & 63) +
 892                                         src_w * pixel_size;
 893
 894                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 895                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 896                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 897                         return -EINVAL;
 898                 }
 899         }
 900
 901         if (state->visible) {
 902                 src->x1 = src_x << 16;
 903                 src->x2 = (src_x + src_w) << 16;
 904                 src->y1 = src_y << 16;
 905                 src->y2 = (src_y + src_h) << 16;
 906         }
 907
 908         dst->x1 = crtc_x;
 909         dst->x2 = crtc_x + crtc_w;
 910         dst->y1 = crtc_y;
 911         dst->y2 = crtc_y + crtc_h;
 912
 913         return 0;
 914 }
 915
 916 static void
 917 intel_commit_sprite_plane(struct drm_plane *plane,
 918                           struct intel_plane_state *state)
 919 {
 920         struct drm_crtc *crtc = state->base.crtc;
 921         struct intel_plane *intel_plane = to_intel_plane(plane);
 922         struct drm_framebuffer *fb = state->base.fb;
 923
 924         crtc = crtc ? crtc : plane->crtc;
 925
 926         plane->fb = fb;
 927
 928         if (!crtc->state->active)
 929                 return;
 930
 931         if (state->visible) {
 932                 intel_plane->update_plane(plane, crtc, fb,
 933                                           state->dst.x1, state->dst.y1,
 934                                           drm_rect_width(&state->dst),
 935                                           drm_rect_height(&state->dst),
 936                                           state->src.x1 >> 16,
 937                                           state->src.y1 >> 16,
 938                                           drm_rect_width(&state->src) >> 16,
 939                                           drm_rect_height(&state->src) >> 16);
 940         } else {
 941                 intel_plane->disable_plane(plane, crtc);
 942         }
 943 }
 944
 945 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 946                               struct drm_file *file_priv)
 947 {
 948         struct drm_intel_sprite_colorkey *set = data;
 949         struct drm_plane *plane;
 950         struct drm_plane_state *plane_state;
 951         struct drm_atomic_state *state;
 952         struct drm_modeset_acquire_ctx ctx;
 953         int ret = 0;
 954
 955         /* Make sure we don't try to enable both src & dest simultaneously */
 956         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 957                 return -EINVAL;
 958
 959         if (IS_VALLEYVIEW(dev) &&
 960             set->flags & I915_SET_COLORKEY_DESTINATION)
 961                 return -EINVAL;
 962
 963         plane = drm_plane_find(dev, set->plane_id);
 964         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 965                 return -ENOENT;
 966
 967         drm_modeset_acquire_init(&ctx, 0);
 968
 969         state = drm_atomic_state_alloc(plane->dev);
 970         if (!state) {
 971                 ret = -ENOMEM;
 972                 goto out;
 973         }
 974         state->acquire_ctx = &ctx;
 975
 976         while (1) {
 977                 plane_state = drm_atomic_get_plane_state(state, plane);
 978                 ret = PTR_ERR_OR_ZERO(plane_state);
 979                 if (!ret) {
 980                         to_intel_plane_state(plane_state)->ckey = *set;
 981                         ret = drm_atomic_commit(state);
 982                 }
 983
 984                 if (ret != -EDEADLK)
 985                         break;
 986
 987                 drm_atomic_state_clear(state);
 988                 drm_modeset_backoff(&ctx);
 989         }
 990
 991         if (ret)
 992                 drm_atomic_state_free(state);
 993
 994 out:
 995         drm_modeset_drop_locks(&ctx);
 996         drm_modeset_acquire_fini(&ctx);
 997         return ret;
 998 }
 999
1000 static const uint32_t ilk_plane_formats[] = {
1001         DRM_FORMAT_XRGB8888,
1002         DRM_FORMAT_YUYV,
1003         DRM_FORMAT_YVYU,
1004         DRM_FORMAT_UYVY,
1005         DRM_FORMAT_VYUY,
1006 };
1007
1008 static const uint32_t snb_plane_formats[] = {
1009         DRM_FORMAT_XBGR8888,
1010         DRM_FORMAT_XRGB8888,
1011         DRM_FORMAT_YUYV,
1012         DRM_FORMAT_YVYU,
1013         DRM_FORMAT_UYVY,
1014         DRM_FORMAT_VYUY,
1015 };
1016
1017 static const uint32_t vlv_plane_formats[] = {
1018         DRM_FORMAT_RGB565,
1019         DRM_FORMAT_ABGR8888,
1020         DRM_FORMAT_ARGB8888,
1021         DRM_FORMAT_XBGR8888,
1022         DRM_FORMAT_XRGB8888,
1023         DRM_FORMAT_XBGR2101010,
1024         DRM_FORMAT_ABGR2101010,
1025         DRM_FORMAT_YUYV,
1026         DRM_FORMAT_YVYU,
1027         DRM_FORMAT_UYVY,
1028         DRM_FORMAT_VYUY,
1029 };
1030
1031 static uint32_t skl_plane_formats[] = {
1032         DRM_FORMAT_RGB565,
1033         DRM_FORMAT_ABGR8888,
1034         DRM_FORMAT_ARGB8888,
1035         DRM_FORMAT_XBGR8888,
1036         DRM_FORMAT_XRGB8888,
1037         DRM_FORMAT_YUYV,
1038         DRM_FORMAT_YVYU,
1039         DRM_FORMAT_UYVY,
1040         DRM_FORMAT_VYUY,
1041 };
1042
1043 int
1044 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1045 {
1046         struct intel_plane *intel_plane;
1047         struct intel_plane_state *state;
1048         unsigned long possible_crtcs;
1049         const uint32_t *plane_formats;
1050         int num_plane_formats;
1051         int ret;
1052
1053         if (INTEL_INFO(dev)->gen < 5)
1054                 return -ENODEV;
1055
1056         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1057         if (!intel_plane)
1058                 return -ENOMEM;
1059
1060         state = intel_create_plane_state(&intel_plane->base);
1061         if (!state) {
1062                 kfree(intel_plane);
1063                 return -ENOMEM;
1064         }
1065         intel_plane->base.state = &state->base;
1066
1067         switch (INTEL_INFO(dev)->gen) {
1068         case 5:
1069         case 6:
1070                 intel_plane->can_scale = true;
1071                 intel_plane->max_downscale = 16;
1072                 intel_plane->update_plane = ilk_update_plane;
1073                 intel_plane->disable_plane = ilk_disable_plane;
1074
1075                 if (IS_GEN6(dev)) {
1076                         plane_formats = snb_plane_formats;
1077                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1078                 } else {
1079                         plane_formats = ilk_plane_formats;
1080                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1081                 }
1082                 break;
1083
1084         case 7:
1085         case 8:
1086                 if (IS_IVYBRIDGE(dev)) {
1087                         intel_plane->can_scale = true;
1088                         intel_plane->max_downscale = 2;
1089                 } else {
1090                         intel_plane->can_scale = false;
1091                         intel_plane->max_downscale = 1;
1092                 }
1093
1094                 if (IS_VALLEYVIEW(dev)) {
1095                         intel_plane->update_plane = vlv_update_plane;
1096                         intel_plane->disable_plane = vlv_disable_plane;
1097
1098                         plane_formats = vlv_plane_formats;
1099                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1100                 } else {
1101                         intel_plane->update_plane = ivb_update_plane;
1102                         intel_plane->disable_plane = ivb_disable_plane;
1103
1104                         plane_formats = snb_plane_formats;
1105                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1106                 }
1107                 break;
1108         case 9:
1109                 intel_plane->can_scale = true;
1110                 intel_plane->update_plane = skl_update_plane;
1111                 intel_plane->disable_plane = skl_disable_plane;
1112                 state->scaler_id = -1;
1113
1114                 plane_formats = skl_plane_formats;
1115                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1116                 break;
1117         default:
1118                 kfree(intel_plane);
1119                 return -ENODEV;
1120         }
1121
1122         intel_plane->pipe = pipe;
1123         intel_plane->plane = plane;
1124         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe);
1125         intel_plane->check_plane = intel_check_sprite_plane;
1126         intel_plane->commit_plane = intel_commit_sprite_plane;
1127         possible_crtcs = (1 << pipe);
1128         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1129                                        &intel_plane_funcs,
1130                                        plane_formats, num_plane_formats,
1131                                        DRM_PLANE_TYPE_OVERLAY);
1132         if (ret) {
1133                 kfree(intel_plane);
1134                 goto out;
1135         }
1136
1137         intel_create_rotation_property(dev, intel_plane);
1138
1139         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1140
1141 out:
1142         return ret;
1143 }