drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c

   1 /*
   2  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "mdp5_kms.h"
  20
  21 #include <linux/sort.h>
  22 #include <drm/drm_mode.h>
  23 #include "drm_crtc.h"
  24 #include "drm_crtc_helper.h"
  25 #include "drm_flip_work.h"
  26
  27 #define CURSOR_WIDTH    64
  28 #define CURSOR_HEIGHT   64
  29
  30 #define SSPP_MAX        (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */
  31
  32 struct mdp5_crtc {
  33         struct drm_crtc base;
  34         char name[8];
  35         int id;
  36         bool enabled;
  37
  38         /* layer mixer used for this CRTC (+ its lock): */
  39 #define GET_LM_ID(crtc_id)      ((crtc_id == 3) ? 5 : crtc_id)
  40         int lm;
  41         spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
  42
  43         /* CTL used for this CRTC: */
  44         struct mdp5_ctl *ctl;
  45
  46         /* if there is a pending flip, these will be non-null: */
  47         struct drm_pending_vblank_event *event;
  48
  49 #define PENDING_CURSOR 0x1
  50 #define PENDING_FLIP   0x2
  51         atomic_t pending;
  52
  53         /* for unref'ing cursor bo's after scanout completes: */
  54         struct drm_flip_work unref_cursor_work;
  55
  56         struct mdp_irq vblank;
  57         struct mdp_irq err;
  58
  59         struct {
  60                 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
  61                 spinlock_t lock;
  62
  63                 /* current cursor being scanned out: */
  64                 struct drm_gem_object *scanout_bo;
  65                 uint32_t width, height;
  66                 uint32_t x, y;
  67         } cursor;
  68 };
  69 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  70
  71 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  72 {
  73         struct msm_drm_private *priv = crtc->dev->dev_private;
  74         return to_mdp5_kms(to_mdp_kms(priv->kms));
  75 }
  76
  77 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  78 {
  79         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  80
  81         atomic_or(pending, &mdp5_crtc->pending);
  82         mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
  83 }
  84
  85 #define mdp5_lm_get_flush(lm)   mdp_ctl_flush_mask_lm(lm)
  86
  87 static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
  88 {
  89         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  90
  91         DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask);
  92         mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
  93 }
  94
  95 /*
  96  * flush updates, to make sure hw is updated to new scanout fb,
  97  * so that we can safely queue unref to current fb (ie. next
  98  * vblank we know hw is done w/ previous scanout_fb).
  99  */
 100 static void crtc_flush_all(struct drm_crtc *crtc)
 101 {
 102         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 103         struct drm_plane *plane;
 104         uint32_t flush_mask = 0;
 105
 106         /* this should not happen: */
 107         if (WARN_ON(!mdp5_crtc->ctl))
 108                 return;
 109
 110         drm_atomic_crtc_for_each_plane(plane, crtc) {
 111                 flush_mask |= mdp5_plane_get_flush(plane);
 112         }
 113         flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
 114         flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm);
 115
 116         crtc_flush(crtc, flush_mask);
 117 }
 118
 119 /* if file!=NULL, this is preclose potential cancel-flip path */
 120 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 121 {
 122         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 123         struct drm_device *dev = crtc->dev;
 124         struct drm_pending_vblank_event *event;
 125         struct drm_plane *plane;
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&dev->event_lock, flags);
 129         event = mdp5_crtc->event;
 130         if (event) {
 131                 /* if regular vblank case (!file) or if cancel-flip from
 132                  * preclose on file that requested flip, then send the
 133                  * event:
 134                  */
 135                 if (!file || (event->base.file_priv == file)) {
 136                         mdp5_crtc->event = NULL;
 137                         DBG("%s: send event: %p", mdp5_crtc->name, event);
 138                         drm_send_vblank_event(dev, mdp5_crtc->id, event);
 139                 }
 140         }
 141         spin_unlock_irqrestore(&dev->event_lock, flags);
 142
 143         drm_atomic_crtc_for_each_plane(plane, crtc) {
 144                 mdp5_plane_complete_flip(plane);
 145         }
 146
 147         if (mdp5_crtc->ctl && !crtc->state->enable) {
 148                 mdp5_ctl_release(mdp5_crtc->ctl);
 149                 mdp5_crtc->ctl = NULL;
 150         }
 151 }
 152
 153 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 154 {
 155         struct mdp5_crtc *mdp5_crtc =
 156                 container_of(work, struct mdp5_crtc, unref_cursor_work);
 157         struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
 158
 159         msm_gem_put_iova(val, mdp5_kms->id);
 160         drm_gem_object_unreference_unlocked(val);
 161 }
 162
 163 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
 164 {
 165         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 166
 167         drm_crtc_cleanup(crtc);
 168         drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
 169
 170         kfree(mdp5_crtc);
 171 }
 172
 173 static bool mdp5_crtc_mode_fixup(struct drm_crtc *crtc,
 174                 const struct drm_display_mode *mode,
 175                 struct drm_display_mode *adjusted_mode)
 176 {
 177         return true;
 178 }
 179
 180 /*
 181  * blend_setup() - blend all the planes of a CRTC
 182  *
 183  * When border is enabled, the border color will ALWAYS be the base layer.
 184  * Therefore, the first plane (private RGB pipe) will start at STAGE0.
 185  * If disabled, the first plane starts at STAGE_BASE.
 186  *
 187  * Note:
 188  * Border is not enabled here because the private plane is exactly
 189  * the CRTC resolution.
 190  */
 191 static void blend_setup(struct drm_crtc *crtc)
 192 {
 193         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 194         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 195         struct drm_plane *plane;
 196         const struct mdp5_cfg_hw *hw_cfg;
 197         uint32_t lm = mdp5_crtc->lm, blend_cfg = 0;
 198         unsigned long flags;
 199 #define blender(stage)  ((stage) - STAGE_BASE)
 200
 201         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 202
 203         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 204
 205         /* ctl could be released already when we are shutting down: */
 206         if (!mdp5_crtc->ctl)
 207                 goto out;
 208
 209         drm_atomic_crtc_for_each_plane(plane, crtc) {
 210                 enum mdp_mixer_stage_id stage =
 211                         to_mdp5_plane_state(plane->state)->stage;
 212
 213                 /*
 214                  * Note: This cannot happen with current implementation but
 215                  * we need to check this condition once z property is added
 216                  */
 217                 BUG_ON(stage > hw_cfg->lm.nb_stages);
 218
 219                 /* LM */
 220                 mdp5_write(mdp5_kms,
 221                                 REG_MDP5_LM_BLEND_OP_MODE(lm, blender(stage)),
 222                                 MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 223                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST));
 224                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
 225                                 blender(stage)), 0xff);
 226                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
 227                                 blender(stage)), 0x00);
 228                 /* CTL */
 229                 blend_cfg |= mdp_ctl_blend_mask(mdp5_plane_pipe(plane), stage);
 230                 DBG("%s: blending pipe %s on stage=%d", mdp5_crtc->name,
 231                                 pipe2name(mdp5_plane_pipe(plane)), stage);
 232         }
 233
 234         DBG("%s: lm%d: blend config = 0x%08x", mdp5_crtc->name, lm, blend_cfg);
 235         mdp5_ctl_blend(mdp5_crtc->ctl, lm, blend_cfg);
 236
 237 out:
 238         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 239 }
 240
 241 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
 242 {
 243         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 244         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 245         unsigned long flags;
 246         struct drm_display_mode *mode;
 247
 248         if (WARN_ON(!crtc->state))
 249                 return;
 250
 251         mode = &crtc->state->adjusted_mode;
 252
 253         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 254                         mdp5_crtc->name, mode->base.id, mode->name,
 255                         mode->vrefresh, mode->clock,
 256                         mode->hdisplay, mode->hsync_start,
 257                         mode->hsync_end, mode->htotal,
 258                         mode->vdisplay, mode->vsync_start,
 259                         mode->vsync_end, mode->vtotal,
 260                         mode->type, mode->flags);
 261
 262         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 263         mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm),
 264                         MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |
 265                         MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 266         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 267 }
 268
 269 static void mdp5_crtc_disable(struct drm_crtc *crtc)
 270 {
 271         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 272         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 273
 274         DBG("%s", mdp5_crtc->name);
 275
 276         if (WARN_ON(!mdp5_crtc->enabled))
 277                 return;
 278
 279         /* set STAGE_UNUSED for all layers */
 280         mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, 0x00000000);
 281
 282         mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
 283         mdp5_disable(mdp5_kms);
 284
 285         mdp5_crtc->enabled = false;
 286 }
 287
 288 static void mdp5_crtc_enable(struct drm_crtc *crtc)
 289 {
 290         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 291         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 292
 293         DBG("%s", mdp5_crtc->name);
 294
 295         if (WARN_ON(mdp5_crtc->enabled))
 296                 return;
 297
 298         mdp5_enable(mdp5_kms);
 299         mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
 300
 301         crtc_flush_all(crtc);
 302
 303         mdp5_crtc->enabled = true;
 304 }
 305
 306 struct plane_state {
 307         struct drm_plane *plane;
 308         struct mdp5_plane_state *state;
 309 };
 310
 311 static int pstate_cmp(const void *a, const void *b)
 312 {
 313         struct plane_state *pa = (struct plane_state *)a;
 314         struct plane_state *pb = (struct plane_state *)b;
 315         return pa->state->zpos - pb->state->zpos;
 316 }
 317
 318 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 319                 struct drm_crtc_state *state)
 320 {
 321         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 322         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 323         struct drm_plane *plane;
 324         struct drm_device *dev = crtc->dev;
 325         struct plane_state pstates[STAGE3 + 1];
 326         int cnt = 0, i;
 327
 328         DBG("%s: check", mdp5_crtc->name);
 329
 330         /* request a free CTL, if none is already allocated for this CRTC */
 331         if (state->enable && !mdp5_crtc->ctl) {
 332                 mdp5_crtc->ctl = mdp5_ctlm_request(mdp5_kms->ctlm, crtc);
 333                 if (WARN_ON(!mdp5_crtc->ctl))
 334                         return -EINVAL;
 335         }
 336
 337         /* verify that there are not too many planes attached to crtc
 338          * and that we don't have conflicting mixer stages:
 339          */
 340         drm_atomic_crtc_state_for_each_plane(plane, state) {
 341                 struct drm_plane_state *pstate;
 342
 343                 if (cnt >= ARRAY_SIZE(pstates)) {
 344                         dev_err(dev->dev, "too many planes!\n");
 345                         return -EINVAL;
 346                 }
 347
 348                 pstate = state->state->plane_states[drm_plane_index(plane)];
 349
 350                 /* plane might not have changed, in which case take
 351                  * current state:
 352                  */
 353                 if (!pstate)
 354                         pstate = plane->state;
 355
 356                 pstates[cnt].plane = plane;
 357                 pstates[cnt].state = to_mdp5_plane_state(pstate);
 358
 359                 cnt++;
 360         }
 361
 362         sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
 363
 364         for (i = 0; i < cnt; i++) {
 365                 pstates[i].state->stage = STAGE_BASE + i;
 366                 DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
 367                                 pipe2name(mdp5_plane_pipe(pstates[i].plane)),
 368                                 pstates[i].state->stage);
 369         }
 370
 371         return 0;
 372 }
 373
 374 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc)
 375 {
 376         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 377         DBG("%s: begin", mdp5_crtc->name);
 378 }
 379
 380 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc)
 381 {
 382         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 383         struct drm_device *dev = crtc->dev;
 384         unsigned long flags;
 385
 386         DBG("%s: event: %p", mdp5_crtc->name, crtc->state->event);
 387
 388         WARN_ON(mdp5_crtc->event);
 389
 390         spin_lock_irqsave(&dev->event_lock, flags);
 391         mdp5_crtc->event = crtc->state->event;
 392         spin_unlock_irqrestore(&dev->event_lock, flags);
 393
 394         /*
 395          * If no CTL has been allocated in mdp5_crtc_atomic_check(),
 396          * it means we are trying to flush a CRTC whose state is disabled:
 397          * nothing else needs to be done.
 398          */
 399         if (unlikely(!mdp5_crtc->ctl))
 400                 return;
 401
 402         blend_setup(crtc);
 403         crtc_flush_all(crtc);
 404         request_pending(crtc, PENDING_FLIP);
 405 }
 406
 407 static int mdp5_crtc_set_property(struct drm_crtc *crtc,
 408                 struct drm_property *property, uint64_t val)
 409 {
 410         // XXX
 411         return -EINVAL;
 412 }
 413
 414 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
 415 {
 416         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 417         uint32_t xres = crtc->mode.hdisplay;
 418         uint32_t yres = crtc->mode.vdisplay;
 419
 420         /*
 421          * Cursor Region Of Interest (ROI) is a plane read from cursor
 422          * buffer to render. The ROI region is determined by the visibility of
 423          * the cursor point. In the default Cursor image the cursor point will
 424          * be at the top left of the cursor image, unless it is specified
 425          * otherwise using hotspot feature.
 426          *
 427          * If the cursor point reaches the right (xres - x < cursor.width) or
 428          * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 429          * width and ROI height need to be evaluated to crop the cursor image
 430          * accordingly.
 431          * (xres-x) will be new cursor width when x > (xres - cursor.width)
 432          * (yres-y) will be new cursor height when y > (yres - cursor.height)
 433          */
 434         *roi_w = min(mdp5_crtc->cursor.width, xres -
 435                         mdp5_crtc->cursor.x);
 436         *roi_h = min(mdp5_crtc->cursor.height, yres -
 437                         mdp5_crtc->cursor.y);
 438 }
 439
 440 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
 441                 struct drm_file *file, uint32_t handle,
 442                 uint32_t width, uint32_t height)
 443 {
 444         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 445         struct drm_device *dev = crtc->dev;
 446         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 447         struct drm_gem_object *cursor_bo, *old_bo;
 448         uint32_t blendcfg, cursor_addr, stride;
 449         int ret, bpp, lm;
 450         unsigned int depth;
 451         enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
 452         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 453         uint32_t roi_w, roi_h;
 454         unsigned long flags;
 455
 456         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 457                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
 458                 return -EINVAL;
 459         }
 460
 461         if (NULL == mdp5_crtc->ctl)
 462                 return -EINVAL;
 463
 464         if (!handle) {
 465                 DBG("Cursor off");
 466                 return mdp5_ctl_set_cursor(mdp5_crtc->ctl, false);
 467         }
 468
 469         cursor_bo = drm_gem_object_lookup(dev, file, handle);
 470         if (!cursor_bo)
 471                 return -ENOENT;
 472
 473         ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr);
 474         if (ret)
 475                 return -EINVAL;
 476
 477         lm = mdp5_crtc->lm;
 478         drm_fb_get_bpp_depth(DRM_FORMAT_ARGB8888, &depth, &bpp);
 479         stride = width * (bpp >> 3);
 480
 481         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 482         old_bo = mdp5_crtc->cursor.scanout_bo;
 483
 484         mdp5_crtc->cursor.scanout_bo = cursor_bo;
 485         mdp5_crtc->cursor.width = width;
 486         mdp5_crtc->cursor.height = height;
 487
 488         get_roi(crtc, &roi_w, &roi_h);
 489
 490         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
 491         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
 492                         MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
 493         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
 494                         MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
 495                         MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
 496         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 497                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 498                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 499         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
 500
 501         blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
 502         blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
 503         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
 504
 505         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 506
 507         ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, true);
 508         if (ret)
 509                 goto end;
 510
 511         flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
 512         crtc_flush(crtc, flush_mask);
 513
 514 end:
 515         if (old_bo) {
 516                 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
 517                 /* enable vblank to complete cursor work: */
 518                 request_pending(crtc, PENDING_CURSOR);
 519         }
 520         return ret;
 521 }
 522
 523 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 524 {
 525         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 526         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 527         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 528         uint32_t roi_w;
 529         uint32_t roi_h;
 530         unsigned long flags;
 531
 532         /* In case the CRTC is disabled, just drop the cursor update */
 533         if (unlikely(!crtc->state->enable))
 534                 return 0;
 535
 536         mdp5_crtc->cursor.x = x = max(x, 0);
 537         mdp5_crtc->cursor.y = y = max(y, 0);
 538
 539         get_roi(crtc, &roi_w, &roi_h);
 540
 541         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 542         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm),
 543                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 544                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 545         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(mdp5_crtc->lm),
 546                         MDP5_LM_CURSOR_START_XY_Y_START(y) |
 547                         MDP5_LM_CURSOR_START_XY_X_START(x));
 548         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 549
 550         crtc_flush(crtc, flush_mask);
 551
 552         return 0;
 553 }
 554
 555 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
 556         .set_config = drm_atomic_helper_set_config,
 557         .destroy = mdp5_crtc_destroy,
 558         .page_flip = drm_atomic_helper_page_flip,
 559         .set_property = mdp5_crtc_set_property,
 560         .reset = drm_atomic_helper_crtc_reset,
 561         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 562         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 563         .cursor_set = mdp5_crtc_cursor_set,
 564         .cursor_move = mdp5_crtc_cursor_move,
 565 };
 566
 567 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
 568         .mode_fixup = mdp5_crtc_mode_fixup,
 569         .mode_set_nofb = mdp5_crtc_mode_set_nofb,
 570         .disable = mdp5_crtc_disable,
 571         .enable = mdp5_crtc_enable,
 572         .atomic_check = mdp5_crtc_atomic_check,
 573         .atomic_begin = mdp5_crtc_atomic_begin,
 574         .atomic_flush = mdp5_crtc_atomic_flush,
 575 };
 576
 577 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 578 {
 579         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
 580         struct drm_crtc *crtc = &mdp5_crtc->base;
 581         struct msm_drm_private *priv = crtc->dev->dev_private;
 582         unsigned pending;
 583
 584         mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
 585
 586         pending = atomic_xchg(&mdp5_crtc->pending, 0);
 587
 588         if (pending & PENDING_FLIP) {
 589                 complete_flip(crtc, NULL);
 590         }
 591
 592         if (pending & PENDING_CURSOR)
 593                 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
 594 }
 595
 596 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 597 {
 598         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
 599
 600         DBG("%s: error: %08x", mdp5_crtc->name, irqstatus);
 601 }
 602
 603 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
 604 {
 605         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 606         return mdp5_crtc->vblank.irqmask;
 607 }
 608
 609 void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
 610 {
 611         DBG("cancel: %p", file);
 612         complete_flip(crtc, file);
 613 }
 614
 615 /* set interface for routing crtc->encoder: */
 616 void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
 617                 enum mdp5_intf intf_id)
 618 {
 619         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 620         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 621         uint32_t flush_mask = 0;
 622         uint32_t intf_sel;
 623         unsigned long flags;
 624
 625         /* now that we know what irq's we want: */
 626         mdp5_crtc->err.irqmask = intf2err(intf);
 627         mdp5_crtc->vblank.irqmask = intf2vblank(intf);
 628         mdp_irq_update(&mdp5_kms->base);
 629
 630         spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
 631         intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
 632
 633         switch (intf) {
 634         case 0:
 635                 intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
 636                 intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf_id);
 637                 break;
 638         case 1:
 639                 intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
 640                 intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf_id);
 641                 break;
 642         case 2:
 643                 intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
 644                 intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf_id);
 645                 break;
 646         case 3:
 647                 intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
 648                 intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf_id);
 649                 break;
 650         default:
 651                 BUG();
 652                 break;
 653         }
 654
 655         mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
 656         spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
 657
 658         DBG("%s: intf_sel=%08x", mdp5_crtc->name, intf_sel);
 659         mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
 660         flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl);
 661         flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm);
 662
 663         crtc_flush(crtc, flush_mask);
 664 }
 665
 666 int mdp5_crtc_get_lm(struct drm_crtc *crtc)
 667 {
 668         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 669
 670         if (WARN_ON(!crtc))
 671                 return -EINVAL;
 672
 673         return mdp5_crtc->lm;
 674 }
 675
 676 /* initialize crtc */
 677 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
 678                 struct drm_plane *plane, int id)
 679 {
 680         struct drm_crtc *crtc = NULL;
 681         struct mdp5_crtc *mdp5_crtc;
 682
 683         mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
 684         if (!mdp5_crtc)
 685                 return ERR_PTR(-ENOMEM);
 686
 687         crtc = &mdp5_crtc->base;
 688
 689         mdp5_crtc->id = id;
 690         mdp5_crtc->lm = GET_LM_ID(id);
 691
 692         spin_lock_init(&mdp5_crtc->lm_lock);
 693         spin_lock_init(&mdp5_crtc->cursor.lock);
 694
 695         mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
 696         mdp5_crtc->err.irq = mdp5_crtc_err_irq;
 697
 698         snprintf(mdp5_crtc->name, sizeof(mdp5_crtc->name), "%s:%d",
 699                         pipe2name(mdp5_plane_pipe(plane)), id);
 700
 701         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs);
 702
 703         drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
 704                         "unref cursor", unref_cursor_worker);
 705
 706         drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
 707         plane->crtc = crtc;
 708
 709         mdp5_plane_install_properties(plane, &crtc->base);
 710
 711         return crtc;
 712 }