2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <mach/iommu.h>
24 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
26 static int mdp4_hw_init(struct msm_kms *kms)
28 struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
29 struct drm_device *dev = mdp4_kms->dev;
30 uint32_t version, major, minor, dmap_cfg, vg_cfg;
34 pm_runtime_get_sync(dev->dev);
36 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
38 major = FIELD(version, MDP4_VERSION_MAJOR);
39 minor = FIELD(version, MDP4_VERSION_MINOR);
41 DBG("found MDP version v%d.%d", major, minor);
44 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
50 mdp4_kms->rev = minor;
52 if (mdp4_kms->dsi_pll_vdda) {
53 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
54 ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
58 "failed to set dsi_pll_vdda voltage: %d\n", ret);
64 if (mdp4_kms->dsi_pll_vddio) {
65 if (mdp4_kms->rev == 2) {
66 ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
70 "failed to set dsi_pll_vddio voltage: %d\n", ret);
76 if (mdp4_kms->rev > 1) {
77 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
78 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
81 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
83 /* max read pending cmd config, 3 pending requests: */
84 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
86 clk = clk_get_rate(mdp4_kms->clk);
88 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
89 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
90 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
92 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
93 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
96 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
98 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
99 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
101 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
102 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
103 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
104 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
106 if (mdp4_kms->rev >= 2)
107 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
109 /* disable CSC matrix / YUV by default: */
110 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
111 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
112 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
113 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
114 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
115 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
117 if (mdp4_kms->rev > 1)
118 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
121 pm_runtime_put_sync(dev->dev);
126 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
127 struct drm_encoder *encoder)
129 /* if we had >1 encoder, we'd need something more clever: */
130 return mdp4_dtv_round_pixclk(encoder, rate);
133 static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
135 struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
136 struct msm_drm_private *priv = mdp4_kms->dev->dev_private;
139 for (i = 0; i < priv->num_crtcs; i++)
140 mdp4_crtc_cancel_pending_flip(priv->crtcs[i]);
143 static void mdp4_destroy(struct msm_kms *kms)
145 struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
149 static const struct msm_kms_funcs kms_funcs = {
150 .hw_init = mdp4_hw_init,
151 .irq_preinstall = mdp4_irq_preinstall,
152 .irq_postinstall = mdp4_irq_postinstall,
153 .irq_uninstall = mdp4_irq_uninstall,
155 .enable_vblank = mdp4_enable_vblank,
156 .disable_vblank = mdp4_disable_vblank,
157 .get_format = mdp4_get_format,
158 .round_pixclk = mdp4_round_pixclk,
159 .preclose = mdp4_preclose,
160 .destroy = mdp4_destroy,
163 int mdp4_disable(struct mdp4_kms *mdp4_kms)
167 clk_disable_unprepare(mdp4_kms->clk);
169 clk_disable_unprepare(mdp4_kms->pclk);
170 clk_disable_unprepare(mdp4_kms->lut_clk);
175 int mdp4_enable(struct mdp4_kms *mdp4_kms)
179 clk_prepare_enable(mdp4_kms->clk);
181 clk_prepare_enable(mdp4_kms->pclk);
182 clk_prepare_enable(mdp4_kms->lut_clk);
187 static int modeset_init(struct mdp4_kms *mdp4_kms)
189 struct drm_device *dev = mdp4_kms->dev;
190 struct msm_drm_private *priv = dev->dev_private;
191 struct drm_plane *plane;
192 struct drm_crtc *crtc;
193 struct drm_encoder *encoder;
194 struct drm_connector *connector;
198 * NOTE: this is a bit simplistic until we add support
199 * for more than just RGB1->DMA_E->DTV->HDMI
202 /* the CRTCs get constructed with a private plane: */
203 plane = mdp4_plane_init(dev, RGB1, true);
205 dev_err(dev->dev, "failed to construct plane for RGB1\n");
206 ret = PTR_ERR(plane);
210 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, 1, DMA_E);
212 dev_err(dev->dev, "failed to construct crtc for DMA_E\n");
216 priv->crtcs[priv->num_crtcs++] = crtc;
218 encoder = mdp4_dtv_encoder_init(dev);
219 if (IS_ERR(encoder)) {
220 dev_err(dev->dev, "failed to construct DTV encoder\n");
221 ret = PTR_ERR(encoder);
224 encoder->possible_crtcs = 0x1; /* DTV can be hooked to DMA_E */
225 priv->encoders[priv->num_encoders++] = encoder;
227 connector = hdmi_connector_init(dev, encoder);
228 if (IS_ERR(connector)) {
229 dev_err(dev->dev, "failed to construct HDMI connector\n");
230 ret = PTR_ERR(connector);
233 priv->connectors[priv->num_connectors++] = connector;
241 static const char *iommu_ports[] = {
242 "mdp_port0_cb0", "mdp_port1_cb0",
245 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
247 struct platform_device *pdev = dev->platformdev;
248 struct mdp4_platform_config *config = mdp4_get_config(pdev);
249 struct mdp4_kms *mdp4_kms;
250 struct msm_kms *kms = NULL;
253 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
255 dev_err(dev->dev, "failed to allocate kms\n");
260 kms = &mdp4_kms->base;
261 kms->funcs = &kms_funcs;
265 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
266 if (IS_ERR(mdp4_kms->mmio)) {
267 ret = PTR_ERR(mdp4_kms->mmio);
271 mdp4_kms->dsi_pll_vdda = devm_regulator_get(&pdev->dev, "dsi_pll_vdda");
272 if (IS_ERR(mdp4_kms->dsi_pll_vdda))
273 mdp4_kms->dsi_pll_vdda = NULL;
275 mdp4_kms->dsi_pll_vddio = devm_regulator_get(&pdev->dev, "dsi_pll_vddio");
276 if (IS_ERR(mdp4_kms->dsi_pll_vddio))
277 mdp4_kms->dsi_pll_vddio = NULL;
279 mdp4_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
280 if (IS_ERR(mdp4_kms->vdd))
281 mdp4_kms->vdd = NULL;
284 ret = regulator_enable(mdp4_kms->vdd);
286 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
291 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
292 if (IS_ERR(mdp4_kms->clk)) {
293 dev_err(dev->dev, "failed to get core_clk\n");
294 ret = PTR_ERR(mdp4_kms->clk);
298 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
299 if (IS_ERR(mdp4_kms->pclk))
300 mdp4_kms->pclk = NULL;
302 // XXX if (rev >= MDP_REV_42) { ???
303 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
304 if (IS_ERR(mdp4_kms->lut_clk)) {
305 dev_err(dev->dev, "failed to get lut_clk\n");
306 ret = PTR_ERR(mdp4_kms->lut_clk);
310 clk_set_rate(mdp4_kms->clk, config->max_clk);
311 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
313 if (!config->iommu) {
314 dev_err(dev->dev, "no iommu\n");
319 /* make sure things are off before attaching iommu (bootloader could
320 * have left things on, in which case we'll start getting faults if
323 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
324 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
325 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
328 ret = msm_iommu_attach(dev, config->iommu,
329 iommu_ports, ARRAY_SIZE(iommu_ports));
333 mdp4_kms->id = msm_register_iommu(dev, config->iommu);
334 if (mdp4_kms->id < 0) {
336 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
340 ret = modeset_init(mdp4_kms);
342 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
354 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
356 static struct mdp4_platform_config config = {};
360 if (cpu_is_apq8064())
361 config.max_clk = 266667000;
363 config.max_clk = 200000000;
365 config.iommu = msm_get_iommu_domain(DISPLAY_READ_DOMAIN);