drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35
  36 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  37 {
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39         struct drm_device *dev = crtc->dev;
  40         struct radeon_device *rdev = dev->dev_private;
  41         int i;
  42
  43         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  44         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  45
  46         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  47         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  51         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  53
  54         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  55         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  56         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  57
  58         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  59         for (i = 0; i < 256; i++) {
  60                 WREG32(AVIVO_DC_LUT_30_COLOR,
  61                              (radeon_crtc->lut_r[i] << 20) |
  62                              (radeon_crtc->lut_g[i] << 10) |
  63                              (radeon_crtc->lut_b[i] << 0));
  64         }
  65
  66         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  67 }
  68
  69 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  70 {
  71         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  72         struct drm_device *dev = crtc->dev;
  73         struct radeon_device *rdev = dev->dev_private;
  74         int i;
  75
  76         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  77         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  78
  79         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  80         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  82
  83         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  84         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  86
  87         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  88         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  91         for (i = 0; i < 256; i++) {
  92                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  93                        (radeon_crtc->lut_r[i] << 20) |
  94                        (radeon_crtc->lut_g[i] << 10) |
  95                        (radeon_crtc->lut_b[i] << 0));
  96         }
  97 }
  98
  99 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 100 {
 101         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 102         struct drm_device *dev = crtc->dev;
 103         struct radeon_device *rdev = dev->dev_private;
 104         int i;
 105
 106         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 107
 108         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 109                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 110                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 111         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 112                NI_GRPH_PRESCALE_BYPASS);
 113         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 114                NI_OVL_PRESCALE_BYPASS);
 115         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 116                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 117                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 118
 119         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 120
 121         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 122         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 123         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 124
 125         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 126         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 127         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 128
 129         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 130         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 133         for (i = 0; i < 256; i++) {
 134                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 135                        (radeon_crtc->lut_r[i] << 20) |
 136                        (radeon_crtc->lut_g[i] << 10) |
 137                        (radeon_crtc->lut_b[i] << 0));
 138         }
 139
 140         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 141                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 142                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 143                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 144                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 145         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 146                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 147                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 148         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 150                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 151         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 153                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 154         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 155         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 156         if (ASIC_IS_DCE8(rdev)) {
 157                 /* XXX this only needs to be programmed once per crtc at startup,
 158                  * not sure where the best place for it is
 159                  */
 160                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 161                        CIK_CURSOR_ALPHA_BLND_ENA);
 162         }
 163 }
 164
 165 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 166 {
 167         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 168         struct drm_device *dev = crtc->dev;
 169         struct radeon_device *rdev = dev->dev_private;
 170         int i;
 171         uint32_t dac2_cntl;
 172
 173         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 174         if (radeon_crtc->crtc_id == 0)
 175                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 176         else
 177                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 178         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 179
 180         WREG8(RADEON_PALETTE_INDEX, 0);
 181         for (i = 0; i < 256; i++) {
 182                 WREG32(RADEON_PALETTE_30_DATA,
 183                              (radeon_crtc->lut_r[i] << 20) |
 184                              (radeon_crtc->lut_g[i] << 10) |
 185                              (radeon_crtc->lut_b[i] << 0));
 186         }
 187 }
 188
 189 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 190 {
 191         struct drm_device *dev = crtc->dev;
 192         struct radeon_device *rdev = dev->dev_private;
 193
 194         if (!crtc->enabled)
 195                 return;
 196
 197         if (ASIC_IS_DCE5(rdev))
 198                 dce5_crtc_load_lut(crtc);
 199         else if (ASIC_IS_DCE4(rdev))
 200                 dce4_crtc_load_lut(crtc);
 201         else if (ASIC_IS_AVIVO(rdev))
 202                 avivo_crtc_load_lut(crtc);
 203         else
 204                 legacy_crtc_load_lut(crtc);
 205 }
 206
 207 /** Sets the color ramps on behalf of fbcon */
 208 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 209                               u16 blue, int regno)
 210 {
 211         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 212
 213         radeon_crtc->lut_r[regno] = red >> 6;
 214         radeon_crtc->lut_g[regno] = green >> 6;
 215         radeon_crtc->lut_b[regno] = blue >> 6;
 216 }
 217
 218 /** Gets the color ramps on behalf of fbcon */
 219 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 220                               u16 *blue, int regno)
 221 {
 222         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 223
 224         *red = radeon_crtc->lut_r[regno] << 6;
 225         *green = radeon_crtc->lut_g[regno] << 6;
 226         *blue = radeon_crtc->lut_b[regno] << 6;
 227 }
 228
 229 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 230                                   u16 *blue, uint32_t start, uint32_t size)
 231 {
 232         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 233         int end = (start + size > 256) ? 256 : start + size, i;
 234
 235         /* userspace palettes are always correct as is */
 236         for (i = start; i < end; i++) {
 237                 radeon_crtc->lut_r[i] = red[i] >> 6;
 238                 radeon_crtc->lut_g[i] = green[i] >> 6;
 239                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 240         }
 241         radeon_crtc_load_lut(crtc);
 242 }
 243
 244 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 245 {
 246         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 247
 248         drm_crtc_cleanup(crtc);
 249         kfree(radeon_crtc);
 250 }
 251
 252 /*
 253  * Handle unpin events outside the interrupt handler proper.
 254  */
 255 static void radeon_unpin_work_func(struct work_struct *__work)
 256 {
 257         struct radeon_unpin_work *work =
 258                 container_of(__work, struct radeon_unpin_work, work);
 259         int r;
 260
 261         /* unpin of the old buffer */
 262         r = radeon_bo_reserve(work->old_rbo, false);
 263         if (likely(r == 0)) {
 264                 r = radeon_bo_unpin(work->old_rbo);
 265                 if (unlikely(r != 0)) {
 266                         DRM_ERROR("failed to unpin buffer after flip\n");
 267                 }
 268                 radeon_bo_unreserve(work->old_rbo);
 269         } else
 270                 DRM_ERROR("failed to reserve buffer after flip\n");
 271
 272         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 273         kfree(work);
 274 }
 275
 276 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 277 {
 278         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 279         struct radeon_unpin_work *work;
 280         unsigned long flags;
 281         u32 update_pending;
 282         int vpos, hpos;
 283
 284         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 285         work = radeon_crtc->unpin_work;
 286         if (work == NULL ||
 287             (work->fence && !radeon_fence_signaled(work->fence))) {
 288                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 289                 return;
 290         }
 291         /* New pageflip, or just completion of a previous one? */
 292         if (!radeon_crtc->deferred_flip_completion) {
 293                 /* do the flip (mmio) */
 294                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 295         } else {
 296                 /* This is just a completion of a flip queued in crtc
 297                  * at last invocation. Make sure we go directly to
 298                  * completion routine.
 299                  */
 300                 update_pending = 0;
 301                 radeon_crtc->deferred_flip_completion = 0;
 302         }
 303
 304         /* Has the pageflip already completed in crtc, or is it certain
 305          * to complete in this vblank?
 306          */
 307         if (update_pending &&
 308             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 309                                                                &vpos, &hpos)) &&
 310             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 311              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 312                 /* crtc didn't flip in this target vblank interval,
 313                  * but flip is pending in crtc. Based on the current
 314                  * scanout position we know that the current frame is
 315                  * (nearly) complete and the flip will (likely)
 316                  * complete before the start of the next frame.
 317                  */
 318                 update_pending = 0;
 319         }
 320         if (update_pending) {
 321                 /* crtc didn't flip in this target vblank interval,
 322                  * but flip is pending in crtc. It will complete it
 323                  * in next vblank interval, so complete the flip at
 324                  * next vblank irq.
 325                  */
 326                 radeon_crtc->deferred_flip_completion = 1;
 327                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 328                 return;
 329         }
 330
 331         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 332         radeon_crtc->unpin_work = NULL;
 333
 334         /* wakeup userspace */
 335         if (work->event)
 336                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 337
 338         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 339
 340         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 341         radeon_fence_unref(&work->fence);
 342         radeon_post_page_flip(work->rdev, work->crtc_id);
 343         schedule_work(&work->work);
 344 }
 345
 346 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 347                                  struct drm_framebuffer *fb,
 348                                  struct drm_pending_vblank_event *event,
 349                                  uint32_t page_flip_flags)
 350 {
 351         struct drm_device *dev = crtc->dev;
 352         struct radeon_device *rdev = dev->dev_private;
 353         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 354         struct radeon_framebuffer *old_radeon_fb;
 355         struct radeon_framebuffer *new_radeon_fb;
 356         struct drm_gem_object *obj;
 357         struct radeon_bo *rbo;
 358         struct radeon_unpin_work *work;
 359         unsigned long flags;
 360         u32 tiling_flags, pitch_pixels;
 361         u64 base;
 362         int r;
 363
 364         work = kzalloc(sizeof *work, GFP_KERNEL);
 365         if (work == NULL)
 366                 return -ENOMEM;
 367
 368         work->event = event;
 369         work->rdev = rdev;
 370         work->crtc_id = radeon_crtc->crtc_id;
 371         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 372         new_radeon_fb = to_radeon_framebuffer(fb);
 373         /* schedule unpin of the old buffer */
 374         obj = old_radeon_fb->obj;
 375         /* take a reference to the old object */
 376         drm_gem_object_reference(obj);
 377         rbo = gem_to_radeon_bo(obj);
 378         work->old_rbo = rbo;
 379         obj = new_radeon_fb->obj;
 380         rbo = gem_to_radeon_bo(obj);
 381
 382         spin_lock(&rbo->tbo.bdev->fence_lock);
 383         if (rbo->tbo.sync_obj)
 384                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 385         spin_unlock(&rbo->tbo.bdev->fence_lock);
 386
 387         INIT_WORK(&work->work, radeon_unpin_work_func);
 388
 389         /* We borrow the event spin lock for protecting unpin_work */
 390         spin_lock_irqsave(&dev->event_lock, flags);
 391         if (radeon_crtc->unpin_work) {
 392                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 393                 r = -EBUSY;
 394                 goto unlock_free;
 395         }
 396         radeon_crtc->unpin_work = work;
 397         radeon_crtc->deferred_flip_completion = 0;
 398         spin_unlock_irqrestore(&dev->event_lock, flags);
 399
 400         /* pin the new buffer */
 401         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 402                          work->old_rbo, rbo);
 403
 404         r = radeon_bo_reserve(rbo, false);
 405         if (unlikely(r != 0)) {
 406                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 407                 goto pflip_cleanup;
 408         }
 409         /* Only 27 bit offset for legacy CRTC */
 410         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 411                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 412         if (unlikely(r != 0)) {
 413                 radeon_bo_unreserve(rbo);
 414                 r = -EINVAL;
 415                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 416                 goto pflip_cleanup;
 417         }
 418         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 419         radeon_bo_unreserve(rbo);
 420
 421         if (!ASIC_IS_AVIVO(rdev)) {
 422                 /* crtc offset is from display base addr not FB location */
 423                 base -= radeon_crtc->legacy_display_base_addr;
 424                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 425
 426                 if (tiling_flags & RADEON_TILING_MACRO) {
 427                         if (ASIC_IS_R300(rdev)) {
 428                                 base &= ~0x7ff;
 429                         } else {
 430                                 int byteshift = fb->bits_per_pixel >> 4;
 431                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 432                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 433                         }
 434                 } else {
 435                         int offset = crtc->y * pitch_pixels + crtc->x;
 436                         switch (fb->bits_per_pixel) {
 437                         case 8:
 438                         default:
 439                                 offset *= 1;
 440                                 break;
 441                         case 15:
 442                         case 16:
 443                                 offset *= 2;
 444                                 break;
 445                         case 24:
 446                                 offset *= 3;
 447                                 break;
 448                         case 32:
 449                                 offset *= 4;
 450                                 break;
 451                         }
 452                         base += offset;
 453                 }
 454                 base &= ~7;
 455         }
 456
 457         spin_lock_irqsave(&dev->event_lock, flags);
 458         work->new_crtc_base = base;
 459         spin_unlock_irqrestore(&dev->event_lock, flags);
 460
 461         /* update crtc fb */
 462         crtc->fb = fb;
 463
 464         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 465         if (r) {
 466                 DRM_ERROR("failed to get vblank before flip\n");
 467                 goto pflip_cleanup1;
 468         }
 469
 470         /* set the proper interrupt */
 471         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 472
 473         return 0;
 474
 475 pflip_cleanup1:
 476         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 477                 DRM_ERROR("failed to reserve new rbo in error path\n");
 478                 goto pflip_cleanup;
 479         }
 480         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 481                 DRM_ERROR("failed to unpin new rbo in error path\n");
 482         }
 483         radeon_bo_unreserve(rbo);
 484
 485 pflip_cleanup:
 486         spin_lock_irqsave(&dev->event_lock, flags);
 487         radeon_crtc->unpin_work = NULL;
 488 unlock_free:
 489         spin_unlock_irqrestore(&dev->event_lock, flags);
 490         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 491         radeon_fence_unref(&work->fence);
 492         kfree(work);
 493
 494         return r;
 495 }
 496
 497 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 498         .cursor_set = radeon_crtc_cursor_set,
 499         .cursor_move = radeon_crtc_cursor_move,
 500         .gamma_set = radeon_crtc_gamma_set,
 501         .set_config = drm_crtc_helper_set_config,
 502         .destroy = radeon_crtc_destroy,
 503         .page_flip = radeon_crtc_page_flip,
 504 };
 505
 506 static void radeon_crtc_init(struct drm_device *dev, int index)
 507 {
 508         struct radeon_device *rdev = dev->dev_private;
 509         struct radeon_crtc *radeon_crtc;
 510         int i;
 511
 512         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 513         if (radeon_crtc == NULL)
 514                 return;
 515
 516         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 517
 518         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 519         radeon_crtc->crtc_id = index;
 520         rdev->mode_info.crtcs[index] = radeon_crtc;
 521
 522         if (rdev->family >= CHIP_BONAIRE) {
 523                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 524                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 525         } else {
 526                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 527                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 528         }
 529
 530 #if 0
 531         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 532         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 533         radeon_crtc->mode_set.num_connectors = 0;
 534 #endif
 535
 536         for (i = 0; i < 256; i++) {
 537                 radeon_crtc->lut_r[i] = i << 2;
 538                 radeon_crtc->lut_g[i] = i << 2;
 539                 radeon_crtc->lut_b[i] = i << 2;
 540         }
 541
 542         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 543                 radeon_atombios_init_crtc(dev, radeon_crtc);
 544         else
 545                 radeon_legacy_init_crtc(dev, radeon_crtc);
 546 }
 547
 548 static const char *encoder_names[38] = {
 549         "NONE",
 550         "INTERNAL_LVDS",
 551         "INTERNAL_TMDS1",
 552         "INTERNAL_TMDS2",
 553         "INTERNAL_DAC1",
 554         "INTERNAL_DAC2",
 555         "INTERNAL_SDVOA",
 556         "INTERNAL_SDVOB",
 557         "SI170B",
 558         "CH7303",
 559         "CH7301",
 560         "INTERNAL_DVO1",
 561         "EXTERNAL_SDVOA",
 562         "EXTERNAL_SDVOB",
 563         "TITFP513",
 564         "INTERNAL_LVTM1",
 565         "VT1623",
 566         "HDMI_SI1930",
 567         "HDMI_INTERNAL",
 568         "INTERNAL_KLDSCP_TMDS1",
 569         "INTERNAL_KLDSCP_DVO1",
 570         "INTERNAL_KLDSCP_DAC1",
 571         "INTERNAL_KLDSCP_DAC2",
 572         "SI178",
 573         "MVPU_FPGA",
 574         "INTERNAL_DDI",
 575         "VT1625",
 576         "HDMI_SI1932",
 577         "DP_AN9801",
 578         "DP_DP501",
 579         "INTERNAL_UNIPHY",
 580         "INTERNAL_KLDSCP_LVTMA",
 581         "INTERNAL_UNIPHY1",
 582         "INTERNAL_UNIPHY2",
 583         "NUTMEG",
 584         "TRAVIS",
 585         "INTERNAL_VCE",
 586         "INTERNAL_UNIPHY3",
 587 };
 588
 589 static const char *hpd_names[6] = {
 590         "HPD1",
 591         "HPD2",
 592         "HPD3",
 593         "HPD4",
 594         "HPD5",
 595         "HPD6",
 596 };
 597
 598 static void radeon_print_display_setup(struct drm_device *dev)
 599 {
 600         struct drm_connector *connector;
 601         struct radeon_connector *radeon_connector;
 602         struct drm_encoder *encoder;
 603         struct radeon_encoder *radeon_encoder;
 604         uint32_t devices;
 605         int i = 0;
 606
 607         DRM_INFO("Radeon Display Connectors\n");
 608         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 609                 radeon_connector = to_radeon_connector(connector);
 610                 DRM_INFO("Connector %d:\n", i);
 611                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 612                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 613                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 614                 if (radeon_connector->ddc_bus) {
 615                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 616                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 617                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 618                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 619                                  radeon_connector->ddc_bus->rec.a_data_reg,
 620                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 621                                  radeon_connector->ddc_bus->rec.en_data_reg,
 622                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 623                                  radeon_connector->ddc_bus->rec.y_data_reg);
 624                         if (radeon_connector->router.ddc_valid)
 625                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 626                                          radeon_connector->router.ddc_mux_control_pin,
 627                                          radeon_connector->router.ddc_mux_state);
 628                         if (radeon_connector->router.cd_valid)
 629                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 630                                          radeon_connector->router.cd_mux_control_pin,
 631                                          radeon_connector->router.cd_mux_state);
 632                 } else {
 633                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 634                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 635                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 636                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 637                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 638                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 639                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 640                 }
 641                 DRM_INFO("  Encoders:\n");
 642                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 643                         radeon_encoder = to_radeon_encoder(encoder);
 644                         devices = radeon_encoder->devices & radeon_connector->devices;
 645                         if (devices) {
 646                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 647                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 648                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 649                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 650                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 651                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 652                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 653                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 654                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 655                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 656                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 657                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 658                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 659                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 660                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 661                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 662                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 663                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 664                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 665                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 666                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 667                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 668                         }
 669                 }
 670                 i++;
 671         }
 672 }
 673
 674 static bool radeon_setup_enc_conn(struct drm_device *dev)
 675 {
 676         struct radeon_device *rdev = dev->dev_private;
 677         bool ret = false;
 678
 679         if (rdev->bios) {
 680                 if (rdev->is_atom_bios) {
 681                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 682                         if (ret == false)
 683                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 684                 } else {
 685                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 686                         if (ret == false)
 687                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 688                 }
 689         } else {
 690                 if (!ASIC_IS_AVIVO(rdev))
 691                         ret = radeon_get_legacy_connector_info_from_table(dev);
 692         }
 693         if (ret) {
 694                 radeon_setup_encoder_clones(dev);
 695                 radeon_print_display_setup(dev);
 696         }
 697
 698         return ret;
 699 }
 700
 701 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 702 {
 703         struct drm_device *dev = radeon_connector->base.dev;
 704         struct radeon_device *rdev = dev->dev_private;
 705         int ret = 0;
 706
 707         /* on hw with routers, select right port */
 708         if (radeon_connector->router.ddc_valid)
 709                 radeon_router_select_ddc_port(radeon_connector);
 710
 711         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 712             ENCODER_OBJECT_ID_NONE) {
 713                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 714
 715                 if (dig->dp_i2c_bus)
 716                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 717                                                               &dig->dp_i2c_bus->adapter);
 718         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 719                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 720                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 721
 722                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 723                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 724                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 725                                                               &dig->dp_i2c_bus->adapter);
 726                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 727                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 728                                                               &radeon_connector->ddc_bus->adapter);
 729         } else {
 730                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 731                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 732                                                               &radeon_connector->ddc_bus->adapter);
 733         }
 734
 735         if (!radeon_connector->edid) {
 736                 if (rdev->is_atom_bios) {
 737                         /* some laptops provide a hardcoded edid in rom for LCDs */
 738                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 739                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 740                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 741                 } else
 742                         /* some servers provide a hardcoded edid in rom for KVMs */
 743                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 744         }
 745         if (radeon_connector->edid) {
 746                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 747                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 748                 return ret;
 749         }
 750         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 751         return 0;
 752 }
 753
 754 /* avivo */
 755 static void avivo_get_fb_div(struct radeon_pll *pll,
 756                              u32 target_clock,
 757                              u32 post_div,
 758                              u32 ref_div,
 759                              u32 *fb_div,
 760                              u32 *frac_fb_div)
 761 {
 762         u32 tmp = post_div * ref_div;
 763
 764         tmp *= target_clock;
 765         *fb_div = tmp / pll->reference_freq;
 766         *frac_fb_div = tmp % pll->reference_freq;
 767
 768         if (*fb_div > pll->max_feedback_div)
 769                 *fb_div = pll->max_feedback_div;
 770         else if (*fb_div < pll->min_feedback_div)
 771                 *fb_div = pll->min_feedback_div;
 772 }
 773
 774 static u32 avivo_get_post_div(struct radeon_pll *pll,
 775                               u32 target_clock)
 776 {
 777         u32 vco, post_div, tmp;
 778
 779         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 780                 return pll->post_div;
 781
 782         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 783                 if (pll->flags & RADEON_PLL_IS_LCD)
 784                         vco = pll->lcd_pll_out_min;
 785                 else
 786                         vco = pll->pll_out_min;
 787         } else {
 788                 if (pll->flags & RADEON_PLL_IS_LCD)
 789                         vco = pll->lcd_pll_out_max;
 790                 else
 791                         vco = pll->pll_out_max;
 792         }
 793
 794         post_div = vco / target_clock;
 795         tmp = vco % target_clock;
 796
 797         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 798                 if (tmp)
 799                         post_div++;
 800         } else {
 801                 if (!tmp)
 802                         post_div--;
 803         }
 804
 805         if (post_div > pll->max_post_div)
 806                 post_div = pll->max_post_div;
 807         else if (post_div < pll->min_post_div)
 808                 post_div = pll->min_post_div;
 809
 810         return post_div;
 811 }
 812
 813 #define MAX_TOLERANCE 10
 814
 815 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 816                               u32 freq,
 817                               u32 *dot_clock_p,
 818                               u32 *fb_div_p,
 819                               u32 *frac_fb_div_p,
 820                               u32 *ref_div_p,
 821                               u32 *post_div_p)
 822 {
 823         u32 target_clock = freq / 10;
 824         u32 post_div = avivo_get_post_div(pll, target_clock);
 825         u32 ref_div = pll->min_ref_div;
 826         u32 fb_div = 0, frac_fb_div = 0, tmp;
 827
 828         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 829                 ref_div = pll->reference_div;
 830
 831         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 832                 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 833                 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 834                 if (frac_fb_div >= 5) {
 835                         frac_fb_div -= 5;
 836                         frac_fb_div = frac_fb_div / 10;
 837                         frac_fb_div++;
 838                 }
 839                 if (frac_fb_div >= 10) {
 840                         fb_div++;
 841                         frac_fb_div = 0;
 842                 }
 843         } else {
 844                 while (ref_div <= pll->max_ref_div) {
 845                         avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 846                                          &fb_div, &frac_fb_div);
 847                         if (frac_fb_div >= (pll->reference_freq / 2))
 848                                 fb_div++;
 849                         frac_fb_div = 0;
 850                         tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 851                         tmp = (tmp * 10000) / target_clock;
 852
 853                         if (tmp > (10000 + MAX_TOLERANCE))
 854                                 ref_div++;
 855                         else if (tmp >= (10000 - MAX_TOLERANCE))
 856                                 break;
 857                         else
 858                                 ref_div++;
 859                 }
 860         }
 861
 862         *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 863                 (ref_div * post_div * 10);
 864         *fb_div_p = fb_div;
 865         *frac_fb_div_p = frac_fb_div;
 866         *ref_div_p = ref_div;
 867         *post_div_p = post_div;
 868         DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 869                       *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 870 }
 871
 872 /* pre-avivo */
 873 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 874 {
 875         uint64_t mod;
 876
 877         n += d / 2;
 878
 879         mod = do_div(n, d);
 880         return n;
 881 }
 882
 883 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 884                                uint64_t freq,
 885                                uint32_t *dot_clock_p,
 886                                uint32_t *fb_div_p,
 887                                uint32_t *frac_fb_div_p,
 888                                uint32_t *ref_div_p,
 889                                uint32_t *post_div_p)
 890 {
 891         uint32_t min_ref_div = pll->min_ref_div;
 892         uint32_t max_ref_div = pll->max_ref_div;
 893         uint32_t min_post_div = pll->min_post_div;
 894         uint32_t max_post_div = pll->max_post_div;
 895         uint32_t min_fractional_feed_div = 0;
 896         uint32_t max_fractional_feed_div = 0;
 897         uint32_t best_vco = pll->best_vco;
 898         uint32_t best_post_div = 1;
 899         uint32_t best_ref_div = 1;
 900         uint32_t best_feedback_div = 1;
 901         uint32_t best_frac_feedback_div = 0;
 902         uint32_t best_freq = -1;
 903         uint32_t best_error = 0xffffffff;
 904         uint32_t best_vco_diff = 1;
 905         uint32_t post_div;
 906         u32 pll_out_min, pll_out_max;
 907
 908         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 909         freq = freq * 1000;
 910
 911         if (pll->flags & RADEON_PLL_IS_LCD) {
 912                 pll_out_min = pll->lcd_pll_out_min;
 913                 pll_out_max = pll->lcd_pll_out_max;
 914         } else {
 915                 pll_out_min = pll->pll_out_min;
 916                 pll_out_max = pll->pll_out_max;
 917         }
 918
 919         if (pll_out_min > 64800)
 920                 pll_out_min = 64800;
 921
 922         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 923                 min_ref_div = max_ref_div = pll->reference_div;
 924         else {
 925                 while (min_ref_div < max_ref_div-1) {
 926                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 927                         uint32_t pll_in = pll->reference_freq / mid;
 928                         if (pll_in < pll->pll_in_min)
 929                                 max_ref_div = mid;
 930                         else if (pll_in > pll->pll_in_max)
 931                                 min_ref_div = mid;
 932                         else
 933                                 break;
 934                 }
 935         }
 936
 937         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 938                 min_post_div = max_post_div = pll->post_div;
 939
 940         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 941                 min_fractional_feed_div = pll->min_frac_feedback_div;
 942                 max_fractional_feed_div = pll->max_frac_feedback_div;
 943         }
 944
 945         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 946                 uint32_t ref_div;
 947
 948                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 949                         continue;
 950
 951                 /* legacy radeons only have a few post_divs */
 952                 if (pll->flags & RADEON_PLL_LEGACY) {
 953                         if ((post_div == 5) ||
 954                             (post_div == 7) ||
 955                             (post_div == 9) ||
 956                             (post_div == 10) ||
 957                             (post_div == 11) ||
 958                             (post_div == 13) ||
 959                             (post_div == 14) ||
 960                             (post_div == 15))
 961                                 continue;
 962                 }
 963
 964                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 965                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 966                         uint32_t pll_in = pll->reference_freq / ref_div;
 967                         uint32_t min_feed_div = pll->min_feedback_div;
 968                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 969
 970                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 971                                 continue;
 972
 973                         while (min_feed_div < max_feed_div) {
 974                                 uint32_t vco;
 975                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 976                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 977                                 uint32_t frac_feedback_div;
 978                                 uint64_t tmp;
 979
 980                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 981
 982                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 983                                 vco = radeon_div(tmp, ref_div);
 984
 985                                 if (vco < pll_out_min) {
 986                                         min_feed_div = feedback_div + 1;
 987                                         continue;
 988                                 } else if (vco > pll_out_max) {
 989                                         max_feed_div = feedback_div;
 990                                         continue;
 991                                 }
 992
 993                                 while (min_frac_feed_div < max_frac_feed_div) {
 994                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 995                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 996                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 997                                         current_freq = radeon_div(tmp, ref_div * post_div);
 998
 999                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1000                                                 if (freq < current_freq)
1001                                                         error = 0xffffffff;
1002                                                 else
1003                                                         error = freq - current_freq;
1004                                         } else
1005                                                 error = abs(current_freq - freq);
1006                                         vco_diff = abs(vco - best_vco);
1007
1008                                         if ((best_vco == 0 && error < best_error) ||
1009                                             (best_vco != 0 &&
1010                                              ((best_error > 100 && error < best_error - 100) ||
1011                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1012                                                 best_post_div = post_div;
1013                                                 best_ref_div = ref_div;
1014                                                 best_feedback_div = feedback_div;
1015                                                 best_frac_feedback_div = frac_feedback_div;
1016                                                 best_freq = current_freq;
1017                                                 best_error = error;
1018                                                 best_vco_diff = vco_diff;
1019                                         } else if (current_freq == freq) {
1020                                                 if (best_freq == -1) {
1021                                                         best_post_div = post_div;
1022                                                         best_ref_div = ref_div;
1023                                                         best_feedback_div = feedback_div;
1024                                                         best_frac_feedback_div = frac_feedback_div;
1025                                                         best_freq = current_freq;
1026                                                         best_error = error;
1027                                                         best_vco_diff = vco_diff;
1028                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1029                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1030                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1031                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1032                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1033                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1034                                                         best_post_div = post_div;
1035                                                         best_ref_div = ref_div;
1036                                                         best_feedback_div = feedback_div;
1037                                                         best_frac_feedback_div = frac_feedback_div;
1038                                                         best_freq = current_freq;
1039                                                         best_error = error;
1040                                                         best_vco_diff = vco_diff;
1041                                                 }
1042                                         }
1043                                         if (current_freq < freq)
1044                                                 min_frac_feed_div = frac_feedback_div + 1;
1045                                         else
1046                                                 max_frac_feed_div = frac_feedback_div;
1047                                 }
1048                                 if (current_freq < freq)
1049                                         min_feed_div = feedback_div + 1;
1050                                 else
1051                                         max_feed_div = feedback_div;
1052                         }
1053                 }
1054         }
1055
1056         *dot_clock_p = best_freq / 10000;
1057         *fb_div_p = best_feedback_div;
1058         *frac_fb_div_p = best_frac_feedback_div;
1059         *ref_div_p = best_ref_div;
1060         *post_div_p = best_post_div;
1061         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1062                       (long long)freq,
1063                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1064                       best_ref_div, best_post_div);
1065
1066 }
1067
1068 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1069 {
1070         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1071
1072         if (radeon_fb->obj) {
1073                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1074         }
1075         drm_framebuffer_cleanup(fb);
1076         kfree(radeon_fb);
1077 }
1078
1079 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1080                                                   struct drm_file *file_priv,
1081                                                   unsigned int *handle)
1082 {
1083         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1084
1085         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1086 }
1087
1088 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1089         .destroy = radeon_user_framebuffer_destroy,
1090         .create_handle = radeon_user_framebuffer_create_handle,
1091 };
1092
1093 int
1094 radeon_framebuffer_init(struct drm_device *dev,
1095                         struct radeon_framebuffer *rfb,
1096                         struct drm_mode_fb_cmd2 *mode_cmd,
1097                         struct drm_gem_object *obj)
1098 {
1099         int ret;
1100         rfb->obj = obj;
1101         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1102         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1103         if (ret) {
1104                 rfb->obj = NULL;
1105                 return ret;
1106         }
1107         return 0;
1108 }
1109
1110 static struct drm_framebuffer *
1111 radeon_user_framebuffer_create(struct drm_device *dev,
1112                                struct drm_file *file_priv,
1113                                struct drm_mode_fb_cmd2 *mode_cmd)
1114 {
1115         struct drm_gem_object *obj;
1116         struct radeon_framebuffer *radeon_fb;
1117         int ret;
1118
1119         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1120         if (obj ==  NULL) {
1121                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1122                         "can't create framebuffer\n", mode_cmd->handles[0]);
1123                 return ERR_PTR(-ENOENT);
1124         }
1125
1126         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1127         if (radeon_fb == NULL) {
1128                 drm_gem_object_unreference_unlocked(obj);
1129                 return ERR_PTR(-ENOMEM);
1130         }
1131
1132         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1133         if (ret) {
1134                 kfree(radeon_fb);
1135                 drm_gem_object_unreference_unlocked(obj);
1136                 return ERR_PTR(ret);
1137         }
1138
1139         return &radeon_fb->base;
1140 }
1141
1142 static void radeon_output_poll_changed(struct drm_device *dev)
1143 {
1144         struct radeon_device *rdev = dev->dev_private;
1145         radeon_fb_output_poll_changed(rdev);
1146 }
1147
1148 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1149         .fb_create = radeon_user_framebuffer_create,
1150         .output_poll_changed = radeon_output_poll_changed
1151 };
1152
1153 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1154 {       { 0, "driver" },
1155         { 1, "bios" },
1156 };
1157
1158 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1159 {       { TV_STD_NTSC, "ntsc" },
1160         { TV_STD_PAL, "pal" },
1161         { TV_STD_PAL_M, "pal-m" },
1162         { TV_STD_PAL_60, "pal-60" },
1163         { TV_STD_NTSC_J, "ntsc-j" },
1164         { TV_STD_SCART_PAL, "scart-pal" },
1165         { TV_STD_PAL_CN, "pal-cn" },
1166         { TV_STD_SECAM, "secam" },
1167 };
1168
1169 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1170 {       { UNDERSCAN_OFF, "off" },
1171         { UNDERSCAN_ON, "on" },
1172         { UNDERSCAN_AUTO, "auto" },
1173 };
1174
1175 static int radeon_modeset_create_props(struct radeon_device *rdev)
1176 {
1177         int sz;
1178
1179         if (rdev->is_atom_bios) {
1180                 rdev->mode_info.coherent_mode_property =
1181                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1182                 if (!rdev->mode_info.coherent_mode_property)
1183                         return -ENOMEM;
1184         }
1185
1186         if (!ASIC_IS_AVIVO(rdev)) {
1187                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1188                 rdev->mode_info.tmds_pll_property =
1189                         drm_property_create_enum(rdev->ddev, 0,
1190                                             "tmds_pll",
1191                                             radeon_tmds_pll_enum_list, sz);
1192         }
1193
1194         rdev->mode_info.load_detect_property =
1195                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1196         if (!rdev->mode_info.load_detect_property)
1197                 return -ENOMEM;
1198
1199         drm_mode_create_scaling_mode_property(rdev->ddev);
1200
1201         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1202         rdev->mode_info.tv_std_property =
1203                 drm_property_create_enum(rdev->ddev, 0,
1204                                     "tv standard",
1205                                     radeon_tv_std_enum_list, sz);
1206
1207         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1208         rdev->mode_info.underscan_property =
1209                 drm_property_create_enum(rdev->ddev, 0,
1210                                     "underscan",
1211                                     radeon_underscan_enum_list, sz);
1212
1213         rdev->mode_info.underscan_hborder_property =
1214                 drm_property_create_range(rdev->ddev, 0,
1215                                         "underscan hborder", 0, 128);
1216         if (!rdev->mode_info.underscan_hborder_property)
1217                 return -ENOMEM;
1218
1219         rdev->mode_info.underscan_vborder_property =
1220                 drm_property_create_range(rdev->ddev, 0,
1221                                         "underscan vborder", 0, 128);
1222         if (!rdev->mode_info.underscan_vborder_property)
1223                 return -ENOMEM;
1224
1225         return 0;
1226 }
1227
1228 void radeon_update_display_priority(struct radeon_device *rdev)
1229 {
1230         /* adjustment options for the display watermarks */
1231         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1232                 /* set display priority to high for r3xx, rv515 chips
1233                  * this avoids flickering due to underflow to the
1234                  * display controllers during heavy acceleration.
1235                  * Don't force high on rs4xx igp chips as it seems to
1236                  * affect the sound card.  See kernel bug 15982.
1237                  */
1238                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1239                     !(rdev->flags & RADEON_IS_IGP))
1240                         rdev->disp_priority = 2;
1241                 else
1242                         rdev->disp_priority = 0;
1243         } else
1244                 rdev->disp_priority = radeon_disp_priority;
1245
1246 }
1247
1248 /*
1249  * Allocate hdmi structs and determine register offsets
1250  */
1251 static void radeon_afmt_init(struct radeon_device *rdev)
1252 {
1253         int i;
1254
1255         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1256                 rdev->mode_info.afmt[i] = NULL;
1257
1258         if (ASIC_IS_NODCE(rdev)) {
1259                 /* nothing to do */
1260         } else if (ASIC_IS_DCE4(rdev)) {
1261                 static uint32_t eg_offsets[] = {
1262                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1263                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1264                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1265                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1266                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1267                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1268                         0x13830 - 0x7030,
1269                 };
1270                 int num_afmt;
1271
1272                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1273                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1274                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1275                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1276                 if (ASIC_IS_DCE8(rdev))
1277                         num_afmt = 7;
1278                 else if (ASIC_IS_DCE6(rdev))
1279                         num_afmt = 6;
1280                 else if (ASIC_IS_DCE5(rdev))
1281                         num_afmt = 6;
1282                 else if (ASIC_IS_DCE41(rdev))
1283                         num_afmt = 2;
1284                 else /* DCE4 */
1285                         num_afmt = 6;
1286
1287                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1288                 for (i = 0; i < num_afmt; i++) {
1289                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1290                         if (rdev->mode_info.afmt[i]) {
1291                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1292                                 rdev->mode_info.afmt[i]->id = i;
1293                         }
1294                 }
1295         } else if (ASIC_IS_DCE3(rdev)) {
1296                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1297                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1298                 if (rdev->mode_info.afmt[0]) {
1299                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1300                         rdev->mode_info.afmt[0]->id = 0;
1301                 }
1302                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1303                 if (rdev->mode_info.afmt[1]) {
1304                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1305                         rdev->mode_info.afmt[1]->id = 1;
1306                 }
1307         } else if (ASIC_IS_DCE2(rdev)) {
1308                 /* DCE2 has at least 1 routable audio block */
1309                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1310                 if (rdev->mode_info.afmt[0]) {
1311                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1312                         rdev->mode_info.afmt[0]->id = 0;
1313                 }
1314                 /* r6xx has 2 routable audio blocks */
1315                 if (rdev->family >= CHIP_R600) {
1316                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1317                         if (rdev->mode_info.afmt[1]) {
1318                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1319                                 rdev->mode_info.afmt[1]->id = 1;
1320                         }
1321                 }
1322         }
1323 }
1324
1325 static void radeon_afmt_fini(struct radeon_device *rdev)
1326 {
1327         int i;
1328
1329         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1330                 kfree(rdev->mode_info.afmt[i]);
1331                 rdev->mode_info.afmt[i] = NULL;
1332         }
1333 }
1334
1335 int radeon_modeset_init(struct radeon_device *rdev)
1336 {
1337         int i;
1338         int ret;
1339
1340         drm_mode_config_init(rdev->ddev);
1341         rdev->mode_info.mode_config_initialized = true;
1342
1343         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1344
1345         if (ASIC_IS_DCE5(rdev)) {
1346                 rdev->ddev->mode_config.max_width = 16384;
1347                 rdev->ddev->mode_config.max_height = 16384;
1348         } else if (ASIC_IS_AVIVO(rdev)) {
1349                 rdev->ddev->mode_config.max_width = 8192;
1350                 rdev->ddev->mode_config.max_height = 8192;
1351         } else {
1352                 rdev->ddev->mode_config.max_width = 4096;
1353                 rdev->ddev->mode_config.max_height = 4096;
1354         }
1355
1356         rdev->ddev->mode_config.preferred_depth = 24;
1357         rdev->ddev->mode_config.prefer_shadow = 1;
1358
1359         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1360
1361         ret = radeon_modeset_create_props(rdev);
1362         if (ret) {
1363                 return ret;
1364         }
1365
1366         /* init i2c buses */
1367         radeon_i2c_init(rdev);
1368
1369         /* check combios for a valid hardcoded EDID - Sun servers */
1370         if (!rdev->is_atom_bios) {
1371                 /* check for hardcoded EDID in BIOS */
1372                 radeon_combios_check_hardcoded_edid(rdev);
1373         }
1374
1375         /* allocate crtcs */
1376         for (i = 0; i < rdev->num_crtc; i++) {
1377                 radeon_crtc_init(rdev->ddev, i);
1378         }
1379
1380         /* okay we should have all the bios connectors */
1381         ret = radeon_setup_enc_conn(rdev->ddev);
1382         if (!ret) {
1383                 return ret;
1384         }
1385
1386         /* init dig PHYs, disp eng pll */
1387         if (rdev->is_atom_bios) {
1388                 radeon_atom_encoder_init(rdev);
1389                 radeon_atom_disp_eng_pll_init(rdev);
1390         }
1391
1392         /* initialize hpd */
1393         radeon_hpd_init(rdev);
1394
1395         /* setup afmt */
1396         radeon_afmt_init(rdev);
1397
1398         /* Initialize power management */
1399         radeon_pm_init(rdev);
1400
1401         radeon_fbdev_init(rdev);
1402         drm_kms_helper_poll_init(rdev->ddev);
1403
1404         return 0;
1405 }
1406
1407 void radeon_modeset_fini(struct radeon_device *rdev)
1408 {
1409         radeon_fbdev_fini(rdev);
1410         kfree(rdev->mode_info.bios_hardcoded_edid);
1411         radeon_pm_fini(rdev);
1412
1413         if (rdev->mode_info.mode_config_initialized) {
1414                 radeon_afmt_fini(rdev);
1415                 drm_kms_helper_poll_fini(rdev->ddev);
1416                 radeon_hpd_fini(rdev);
1417                 drm_mode_config_cleanup(rdev->ddev);
1418                 rdev->mode_info.mode_config_initialized = false;
1419         }
1420         /* free i2c buses */
1421         radeon_i2c_fini(rdev);
1422 }
1423
1424 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1425 {
1426         /* try and guess if this is a tv or a monitor */
1427         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1428             (mode->vdisplay == 576) || /* 576p */
1429             (mode->vdisplay == 720) || /* 720p */
1430             (mode->vdisplay == 1080)) /* 1080p */
1431                 return true;
1432         else
1433                 return false;
1434 }
1435
1436 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1437                                 const struct drm_display_mode *mode,
1438                                 struct drm_display_mode *adjusted_mode)
1439 {
1440         struct drm_device *dev = crtc->dev;
1441         struct radeon_device *rdev = dev->dev_private;
1442         struct drm_encoder *encoder;
1443         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1444         struct radeon_encoder *radeon_encoder;
1445         struct drm_connector *connector;
1446         struct radeon_connector *radeon_connector;
1447         bool first = true;
1448         u32 src_v = 1, dst_v = 1;
1449         u32 src_h = 1, dst_h = 1;
1450
1451         radeon_crtc->h_border = 0;
1452         radeon_crtc->v_border = 0;
1453
1454         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1455                 if (encoder->crtc != crtc)
1456                         continue;
1457                 radeon_encoder = to_radeon_encoder(encoder);
1458                 connector = radeon_get_connector_for_encoder(encoder);
1459                 radeon_connector = to_radeon_connector(connector);
1460
1461                 if (first) {
1462                         /* set scaling */
1463                         if (radeon_encoder->rmx_type == RMX_OFF)
1464                                 radeon_crtc->rmx_type = RMX_OFF;
1465                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1466                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1467                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1468                         else
1469                                 radeon_crtc->rmx_type = RMX_OFF;
1470                         /* copy native mode */
1471                         memcpy(&radeon_crtc->native_mode,
1472                                &radeon_encoder->native_mode,
1473                                 sizeof(struct drm_display_mode));
1474                         src_v = crtc->mode.vdisplay;
1475                         dst_v = radeon_crtc->native_mode.vdisplay;
1476                         src_h = crtc->mode.hdisplay;
1477                         dst_h = radeon_crtc->native_mode.hdisplay;
1478
1479                         /* fix up for overscan on hdmi */
1480                         if (ASIC_IS_AVIVO(rdev) &&
1481                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1482                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1483                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1484                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1485                               is_hdtv_mode(mode)))) {
1486                                 if (radeon_encoder->underscan_hborder != 0)
1487                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1488                                 else
1489                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1490                                 if (radeon_encoder->underscan_vborder != 0)
1491                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1492                                 else
1493                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1494                                 radeon_crtc->rmx_type = RMX_FULL;
1495                                 src_v = crtc->mode.vdisplay;
1496                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1497                                 src_h = crtc->mode.hdisplay;
1498                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1499                         }
1500                         first = false;
1501                 } else {
1502                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1503                                 /* WARNING: Right now this can't happen but
1504                                  * in the future we need to check that scaling
1505                                  * are consistent across different encoder
1506                                  * (ie all encoder can work with the same
1507                                  *  scaling).
1508                                  */
1509                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1510                                 return false;
1511                         }
1512                 }
1513         }
1514         if (radeon_crtc->rmx_type != RMX_OFF) {
1515                 fixed20_12 a, b;
1516                 a.full = dfixed_const(src_v);
1517                 b.full = dfixed_const(dst_v);
1518                 radeon_crtc->vsc.full = dfixed_div(a, b);
1519                 a.full = dfixed_const(src_h);
1520                 b.full = dfixed_const(dst_h);
1521                 radeon_crtc->hsc.full = dfixed_div(a, b);
1522         } else {
1523                 radeon_crtc->vsc.full = dfixed_const(1);
1524                 radeon_crtc->hsc.full = dfixed_const(1);
1525         }
1526         return true;
1527 }
1528
1529 /*
1530  * Retrieve current video scanout position of crtc on a given gpu.
1531  *
1532  * \param dev Device to query.
1533  * \param crtc Crtc to query.
1534  * \param *vpos Location where vertical scanout position should be stored.
1535  * \param *hpos Location where horizontal scanout position should go.
1536  *
1537  * Returns vpos as a positive number while in active scanout area.
1538  * Returns vpos as a negative number inside vblank, counting the number
1539  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1540  * until start of active scanout / end of vblank."
1541  *
1542  * \return Flags, or'ed together as follows:
1543  *
1544  * DRM_SCANOUTPOS_VALID = Query successful.
1545  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1546  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1547  * this flag means that returned position may be offset by a constant but
1548  * unknown small number of scanlines wrt. real scanout position.
1549  *
1550  */
1551 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1552 {
1553         u32 stat_crtc = 0, vbl = 0, position = 0;
1554         int vbl_start, vbl_end, vtotal, ret = 0;
1555         bool in_vbl = true;
1556
1557         struct radeon_device *rdev = dev->dev_private;
1558
1559         if (ASIC_IS_DCE4(rdev)) {
1560                 if (crtc == 0) {
1561                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1562                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1563                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1564                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1565                         ret |= DRM_SCANOUTPOS_VALID;
1566                 }
1567                 if (crtc == 1) {
1568                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1569                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1570                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1571                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1572                         ret |= DRM_SCANOUTPOS_VALID;
1573                 }
1574                 if (crtc == 2) {
1575                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1576                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1577                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1578                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1579                         ret |= DRM_SCANOUTPOS_VALID;
1580                 }
1581                 if (crtc == 3) {
1582                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1583                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1584                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1585                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1586                         ret |= DRM_SCANOUTPOS_VALID;
1587                 }
1588                 if (crtc == 4) {
1589                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1590                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1591                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1592                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1593                         ret |= DRM_SCANOUTPOS_VALID;
1594                 }
1595                 if (crtc == 5) {
1596                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1597                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1598                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1599                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1600                         ret |= DRM_SCANOUTPOS_VALID;
1601                 }
1602         } else if (ASIC_IS_AVIVO(rdev)) {
1603                 if (crtc == 0) {
1604                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1605                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1606                         ret |= DRM_SCANOUTPOS_VALID;
1607                 }
1608                 if (crtc == 1) {
1609                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1610                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1611                         ret |= DRM_SCANOUTPOS_VALID;
1612                 }
1613         } else {
1614                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1615                 if (crtc == 0) {
1616                         /* Assume vbl_end == 0, get vbl_start from
1617                          * upper 16 bits.
1618                          */
1619                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1620                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1621                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1622                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1623                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1624                         if (!(stat_crtc & 1))
1625                                 in_vbl = false;
1626
1627                         ret |= DRM_SCANOUTPOS_VALID;
1628                 }
1629                 if (crtc == 1) {
1630                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1631                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1632                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1633                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1634                         if (!(stat_crtc & 1))
1635                                 in_vbl = false;
1636
1637                         ret |= DRM_SCANOUTPOS_VALID;
1638                 }
1639         }
1640
1641         /* Decode into vertical and horizontal scanout position. */
1642         *vpos = position & 0x1fff;
1643         *hpos = (position >> 16) & 0x1fff;
1644
1645         /* Valid vblank area boundaries from gpu retrieved? */
1646         if (vbl > 0) {
1647                 /* Yes: Decode. */
1648                 ret |= DRM_SCANOUTPOS_ACCURATE;
1649                 vbl_start = vbl & 0x1fff;
1650                 vbl_end = (vbl >> 16) & 0x1fff;
1651         }
1652         else {
1653                 /* No: Fake something reasonable which gives at least ok results. */
1654                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1655                 vbl_end = 0;
1656         }
1657
1658         /* Test scanout position against vblank region. */
1659         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1660                 in_vbl = false;
1661
1662         /* Check if inside vblank area and apply corrective offsets:
1663          * vpos will then be >=0 in video scanout area, but negative
1664          * within vblank area, counting down the number of lines until
1665          * start of scanout.
1666          */
1667
1668         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1669         if (in_vbl && (*vpos >= vbl_start)) {
1670                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1671                 *vpos = *vpos - vtotal;
1672         }
1673
1674         /* Correct for shifted end of vbl at vbl_end. */
1675         *vpos = *vpos - vbl_end;
1676
1677         /* In vblank? */
1678         if (in_vbl)
1679                 ret |= DRM_SCANOUTPOS_INVBL;
1680
1681         return ret;
1682 }