drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_update_memory_usage(struct radeon_bo *bo,
  50                                        unsigned mem_type, int sign)
  51 {
  52         struct radeon_device *rdev = bo->rdev;
  53         u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
  54
  55         switch (mem_type) {
  56         case TTM_PL_TT:
  57                 if (sign > 0)
  58                         atomic64_add(size, &rdev->gtt_usage);
  59                 else
  60                         atomic64_sub(size, &rdev->gtt_usage);
  61                 break;
  62         case TTM_PL_VRAM:
  63                 if (sign > 0)
  64                         atomic64_add(size, &rdev->vram_usage);
  65                 else
  66                         atomic64_sub(size, &rdev->vram_usage);
  67                 break;
  68         }
  69 }
  70
  71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  72 {
  73         struct radeon_bo *bo;
  74
  75         bo = container_of(tbo, struct radeon_bo, tbo);
  76
  77         radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
  78         radeon_mn_unregister(bo);
  79
  80         mutex_lock(&bo->rdev->gem.mutex);
  81         list_del_init(&bo->list);
  82         mutex_unlock(&bo->rdev->gem.mutex);
  83         radeon_bo_clear_surface_reg(bo);
  84         WARN_ON(!list_empty(&bo->va));
  85         drm_gem_object_release(&bo->gem_base);
  86         kfree(bo);
  87 }
  88
  89 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  90 {
  91         if (bo->destroy == &radeon_ttm_bo_destroy)
  92                 return true;
  93         return false;
  94 }
  95
  96 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  97 {
  98         u32 c = 0, i;
  99
 100         rbo->placement.placement = rbo->placements;
 101         rbo->placement.busy_placement = rbo->placements;
 102         if (domain & RADEON_GEM_DOMAIN_VRAM)
 103                 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 104                                              TTM_PL_FLAG_UNCACHED |
 105                                              TTM_PL_FLAG_VRAM;
 106
 107         if (domain & RADEON_GEM_DOMAIN_GTT) {
 108                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 109                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 110                                 TTM_PL_FLAG_TT;
 111
 112                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 113                            (rbo->rdev->flags & RADEON_IS_AGP)) {
 114                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 115                                 TTM_PL_FLAG_UNCACHED |
 116                                 TTM_PL_FLAG_TT;
 117                 } else {
 118                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 119                                                      TTM_PL_FLAG_TT;
 120                 }
 121         }
 122
 123         if (domain & RADEON_GEM_DOMAIN_CPU) {
 124                 if (rbo->flags & RADEON_GEM_GTT_UC) {
 125                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 126                                 TTM_PL_FLAG_SYSTEM;
 127
 128                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 129                     rbo->rdev->flags & RADEON_IS_AGP) {
 130                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 131                                 TTM_PL_FLAG_UNCACHED |
 132                                 TTM_PL_FLAG_SYSTEM;
 133                 } else {
 134                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 135                                                      TTM_PL_FLAG_SYSTEM;
 136                 }
 137         }
 138         if (!c)
 139                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
 140                                              TTM_PL_FLAG_SYSTEM;
 141
 142         rbo->placement.num_placement = c;
 143         rbo->placement.num_busy_placement = c;
 144
 145         for (i = 0; i < c; ++i) {
 146                 rbo->placements[i].fpfn = 0;
 147                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 148                     (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
 149                         rbo->placements[i].lpfn =
 150                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 151                 else
 152                         rbo->placements[i].lpfn = 0;
 153         }
 154
 155         /*
 156          * Use two-ended allocation depending on the buffer size to
 157          * improve fragmentation quality.
 158          * 512kb was measured as the most optimal number.
 159          */
 160         if (!((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
 161               (rbo->placements[i].flags & TTM_PL_FLAG_VRAM)) &&
 162             rbo->tbo.mem.size > 512 * 1024) {
 163                 for (i = 0; i < c; i++) {
 164                         rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
 165                 }
 166         }
 167 }
 168
 169 int radeon_bo_create(struct radeon_device *rdev,
 170                      unsigned long size, int byte_align, bool kernel,
 171                      u32 domain, u32 flags, struct sg_table *sg,
 172                      struct reservation_object *resv,
 173                      struct radeon_bo **bo_ptr)
 174 {
 175         struct radeon_bo *bo;
 176         enum ttm_bo_type type;
 177         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 178         size_t acc_size;
 179         int r;
 180
 181         size = ALIGN(size, PAGE_SIZE);
 182
 183         if (kernel) {
 184                 type = ttm_bo_type_kernel;
 185         } else if (sg) {
 186                 type = ttm_bo_type_sg;
 187         } else {
 188                 type = ttm_bo_type_device;
 189         }
 190         *bo_ptr = NULL;
 191
 192         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 193                                        sizeof(struct radeon_bo));
 194
 195         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 196         if (bo == NULL)
 197                 return -ENOMEM;
 198         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 199         if (unlikely(r)) {
 200                 kfree(bo);
 201                 return r;
 202         }
 203         bo->rdev = rdev;
 204         bo->surface_reg = -1;
 205         INIT_LIST_HEAD(&bo->list);
 206         INIT_LIST_HEAD(&bo->va);
 207         bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
 208                                        RADEON_GEM_DOMAIN_GTT |
 209                                        RADEON_GEM_DOMAIN_CPU);
 210
 211         bo->flags = flags;
 212         /* PCI GART is always snooped */
 213         if (!(rdev->flags & RADEON_IS_PCIE))
 214                 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
 215
 216         radeon_ttm_placement_from_domain(bo, domain);
 217         /* Kernel allocation are uninterruptible */
 218         down_read(&rdev->pm.mclk_lock);
 219         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 220                         &bo->placement, page_align, !kernel, NULL,
 221                         acc_size, sg, resv, &radeon_ttm_bo_destroy);
 222         up_read(&rdev->pm.mclk_lock);
 223         if (unlikely(r != 0)) {
 224                 return r;
 225         }
 226         *bo_ptr = bo;
 227
 228         trace_radeon_bo_create(bo);
 229
 230         return 0;
 231 }
 232
 233 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 234 {
 235         bool is_iomem;
 236         int r;
 237
 238         if (bo->kptr) {
 239                 if (ptr) {
 240                         *ptr = bo->kptr;
 241                 }
 242                 return 0;
 243         }
 244         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 245         if (r) {
 246                 return r;
 247         }
 248         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 249         if (ptr) {
 250                 *ptr = bo->kptr;
 251         }
 252         radeon_bo_check_tiling(bo, 0, 0);
 253         return 0;
 254 }
 255
 256 void radeon_bo_kunmap(struct radeon_bo *bo)
 257 {
 258         if (bo->kptr == NULL)
 259                 return;
 260         bo->kptr = NULL;
 261         radeon_bo_check_tiling(bo, 0, 0);
 262         ttm_bo_kunmap(&bo->kmap);
 263 }
 264
 265 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
 266 {
 267         if (bo == NULL)
 268                 return NULL;
 269
 270         ttm_bo_reference(&bo->tbo);
 271         return bo;
 272 }
 273
 274 void radeon_bo_unref(struct radeon_bo **bo)
 275 {
 276         struct ttm_buffer_object *tbo;
 277         struct radeon_device *rdev;
 278
 279         if ((*bo) == NULL)
 280                 return;
 281         rdev = (*bo)->rdev;
 282         tbo = &((*bo)->tbo);
 283         ttm_bo_unref(&tbo);
 284         if (tbo == NULL)
 285                 *bo = NULL;
 286 }
 287
 288 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 289                              u64 *gpu_addr)
 290 {
 291         int r, i;
 292
 293         if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
 294                 return -EPERM;
 295
 296         if (bo->pin_count) {
 297                 bo->pin_count++;
 298                 if (gpu_addr)
 299                         *gpu_addr = radeon_bo_gpu_offset(bo);
 300
 301                 if (max_offset != 0) {
 302                         u64 domain_start;
 303
 304                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 305                                 domain_start = bo->rdev->mc.vram_start;
 306                         else
 307                                 domain_start = bo->rdev->mc.gtt_start;
 308                         WARN_ON_ONCE(max_offset <
 309                                      (radeon_bo_gpu_offset(bo) - domain_start));
 310                 }
 311
 312                 return 0;
 313         }
 314         radeon_ttm_placement_from_domain(bo, domain);
 315         for (i = 0; i < bo->placement.num_placement; i++) {
 316                 /* force to pin into visible video ram */
 317                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 318                     !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
 319                     (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
 320                         bo->placements[i].lpfn =
 321                                 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 322                 else
 323                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 324
 325                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 326         }
 327
 328         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 329         if (likely(r == 0)) {
 330                 bo->pin_count = 1;
 331                 if (gpu_addr != NULL)
 332                         *gpu_addr = radeon_bo_gpu_offset(bo);
 333                 if (domain == RADEON_GEM_DOMAIN_VRAM)
 334                         bo->rdev->vram_pin_size += radeon_bo_size(bo);
 335                 else
 336                         bo->rdev->gart_pin_size += radeon_bo_size(bo);
 337         } else {
 338                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 339         }
 340         return r;
 341 }
 342
 343 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 344 {
 345         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 346 }
 347
 348 int radeon_bo_unpin(struct radeon_bo *bo)
 349 {
 350         int r, i;
 351
 352         if (!bo->pin_count) {
 353                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 354                 return 0;
 355         }
 356         bo->pin_count--;
 357         if (bo->pin_count)
 358                 return 0;
 359         for (i = 0; i < bo->placement.num_placement; i++) {
 360                 bo->placements[i].lpfn = 0;
 361                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 362         }
 363         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 364         if (likely(r == 0)) {
 365                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 366                         bo->rdev->vram_pin_size -= radeon_bo_size(bo);
 367                 else
 368                         bo->rdev->gart_pin_size -= radeon_bo_size(bo);
 369         } else {
 370                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 371         }
 372         return r;
 373 }
 374
 375 int radeon_bo_evict_vram(struct radeon_device *rdev)
 376 {
 377         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 378         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 379                 if (rdev->mc.igp_sideport_enabled == false)
 380                         /* Useless to evict on IGP chips */
 381                         return 0;
 382         }
 383         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 384 }
 385
 386 void radeon_bo_force_delete(struct radeon_device *rdev)
 387 {
 388         struct radeon_bo *bo, *n;
 389
 390         if (list_empty(&rdev->gem.objects)) {
 391                 return;
 392         }
 393         dev_err(rdev->dev, "Userspace still has active objects !\n");
 394         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 395                 mutex_lock(&rdev->ddev->struct_mutex);
 396                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 397                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 398                         *((unsigned long *)&bo->gem_base.refcount));
 399                 mutex_lock(&bo->rdev->gem.mutex);
 400                 list_del_init(&bo->list);
 401                 mutex_unlock(&bo->rdev->gem.mutex);
 402                 /* this should unref the ttm bo */
 403                 drm_gem_object_unreference(&bo->gem_base);
 404                 mutex_unlock(&rdev->ddev->struct_mutex);
 405         }
 406 }
 407
 408 int radeon_bo_init(struct radeon_device *rdev)
 409 {
 410         /* Add an MTRR for the VRAM */
 411         if (!rdev->fastfb_working) {
 412                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
 413                                                       rdev->mc.aper_size);
 414         }
 415         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 416                 rdev->mc.mc_vram_size >> 20,
 417                 (unsigned long long)rdev->mc.aper_size >> 20);
 418         DRM_INFO("RAM width %dbits %cDR\n",
 419                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 420         return radeon_ttm_init(rdev);
 421 }
 422
 423 void radeon_bo_fini(struct radeon_device *rdev)
 424 {
 425         radeon_ttm_fini(rdev);
 426         arch_phys_wc_del(rdev->mc.vram_mtrr);
 427 }
 428
 429 /* Returns how many bytes TTM can move per IB.
 430  */
 431 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
 432 {
 433         u64 real_vram_size = rdev->mc.real_vram_size;
 434         u64 vram_usage = atomic64_read(&rdev->vram_usage);
 435
 436         /* This function is based on the current VRAM usage.
 437          *
 438          * - If all of VRAM is free, allow relocating the number of bytes that
 439          *   is equal to 1/4 of the size of VRAM for this IB.
 440
 441          * - If more than one half of VRAM is occupied, only allow relocating
 442          *   1 MB of data for this IB.
 443          *
 444          * - From 0 to one half of used VRAM, the threshold decreases
 445          *   linearly.
 446          *         __________________
 447          * 1/4 of -|\               |
 448          * VRAM    | \              |
 449          *         |  \             |
 450          *         |   \            |
 451          *         |    \           |
 452          *         |     \          |
 453          *         |      \         |
 454          *         |       \________|1 MB
 455          *         |----------------|
 456          *    VRAM 0 %             100 %
 457          *         used            used
 458          *
 459          * Note: It's a threshold, not a limit. The threshold must be crossed
 460          * for buffer relocations to stop, so any buffer of an arbitrary size
 461          * can be moved as long as the threshold isn't crossed before
 462          * the relocation takes place. We don't want to disable buffer
 463          * relocations completely.
 464          *
 465          * The idea is that buffers should be placed in VRAM at creation time
 466          * and TTM should only do a minimum number of relocations during
 467          * command submission. In practice, you need to submit at least
 468          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 469          *
 470          * Also, things can get pretty crazy under memory pressure and actual
 471          * VRAM usage can change a lot, so playing safe even at 50% does
 472          * consistently increase performance.
 473          */
 474
 475         u64 half_vram = real_vram_size >> 1;
 476         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 477         u64 bytes_moved_threshold = half_free_vram >> 1;
 478         return max(bytes_moved_threshold, 1024*1024ull);
 479 }
 480
 481 int radeon_bo_list_validate(struct radeon_device *rdev,
 482                             struct ww_acquire_ctx *ticket,
 483                             struct list_head *head, int ring)
 484 {
 485         struct radeon_cs_reloc *lobj;
 486         struct radeon_bo *bo;
 487         int r;
 488         u64 bytes_moved = 0, initial_bytes_moved;
 489         u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
 490
 491         r = ttm_eu_reserve_buffers(ticket, head, true);
 492         if (unlikely(r != 0)) {
 493                 return r;
 494         }
 495
 496         list_for_each_entry(lobj, head, tv.head) {
 497                 bo = lobj->robj;
 498                 if (!bo->pin_count) {
 499                         u32 domain = lobj->prefered_domains;
 500                         u32 allowed = lobj->allowed_domains;
 501                         u32 current_domain =
 502                                 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
 503
 504                         /* Check if this buffer will be moved and don't move it
 505                          * if we have moved too many buffers for this IB already.
 506                          *
 507                          * Note that this allows moving at least one buffer of
 508                          * any size, because it doesn't take the current "bo"
 509                          * into account. We don't want to disallow buffer moves
 510                          * completely.
 511                          */
 512                         if ((allowed & current_domain) != 0 &&
 513                             (domain & current_domain) == 0 && /* will be moved */
 514                             bytes_moved > bytes_moved_threshold) {
 515                                 /* don't move it */
 516                                 domain = current_domain;
 517                         }
 518
 519                 retry:
 520                         radeon_ttm_placement_from_domain(bo, domain);
 521                         if (ring == R600_RING_TYPE_UVD_INDEX)
 522                                 radeon_uvd_force_into_uvd_segment(bo, allowed);
 523
 524                         initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
 525                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 526                         bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
 527                                        initial_bytes_moved;
 528
 529                         if (unlikely(r)) {
 530                                 if (r != -ERESTARTSYS &&
 531                                     domain != lobj->allowed_domains) {
 532                                         domain = lobj->allowed_domains;
 533                                         goto retry;
 534                                 }
 535                                 ttm_eu_backoff_reservation(ticket, head);
 536                                 return r;
 537                         }
 538                 }
 539                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 540                 lobj->tiling_flags = bo->tiling_flags;
 541         }
 542         return 0;
 543 }
 544
 545 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 546                              struct vm_area_struct *vma)
 547 {
 548         return ttm_fbdev_mmap(vma, &bo->tbo);
 549 }
 550
 551 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 552 {
 553         struct radeon_device *rdev = bo->rdev;
 554         struct radeon_surface_reg *reg;
 555         struct radeon_bo *old_object;
 556         int steal;
 557         int i;
 558
 559         lockdep_assert_held(&bo->tbo.resv->lock.base);
 560
 561         if (!bo->tiling_flags)
 562                 return 0;
 563
 564         if (bo->surface_reg >= 0) {
 565                 reg = &rdev->surface_regs[bo->surface_reg];
 566                 i = bo->surface_reg;
 567                 goto out;
 568         }
 569
 570         steal = -1;
 571         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 572
 573                 reg = &rdev->surface_regs[i];
 574                 if (!reg->bo)
 575                         break;
 576
 577                 old_object = reg->bo;
 578                 if (old_object->pin_count == 0)
 579                         steal = i;
 580         }
 581
 582         /* if we are all out */
 583         if (i == RADEON_GEM_MAX_SURFACES) {
 584                 if (steal == -1)
 585                         return -ENOMEM;
 586                 /* find someone with a surface reg and nuke their BO */
 587                 reg = &rdev->surface_regs[steal];
 588                 old_object = reg->bo;
 589                 /* blow away the mapping */
 590                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 591                 ttm_bo_unmap_virtual(&old_object->tbo);
 592                 old_object->surface_reg = -1;
 593                 i = steal;
 594         }
 595
 596         bo->surface_reg = i;
 597         reg->bo = bo;
 598
 599 out:
 600         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 601                                bo->tbo.mem.start << PAGE_SHIFT,
 602                                bo->tbo.num_pages << PAGE_SHIFT);
 603         return 0;
 604 }
 605
 606 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 607 {
 608         struct radeon_device *rdev = bo->rdev;
 609         struct radeon_surface_reg *reg;
 610
 611         if (bo->surface_reg == -1)
 612                 return;
 613
 614         reg = &rdev->surface_regs[bo->surface_reg];
 615         radeon_clear_surface_reg(rdev, bo->surface_reg);
 616
 617         reg->bo = NULL;
 618         bo->surface_reg = -1;
 619 }
 620
 621 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 622                                 uint32_t tiling_flags, uint32_t pitch)
 623 {
 624         struct radeon_device *rdev = bo->rdev;
 625         int r;
 626
 627         if (rdev->family >= CHIP_CEDAR) {
 628                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 629
 630                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 631                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 632                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 633                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 634                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 635                 switch (bankw) {
 636                 case 0:
 637                 case 1:
 638                 case 2:
 639                 case 4:
 640                 case 8:
 641                         break;
 642                 default:
 643                         return -EINVAL;
 644                 }
 645                 switch (bankh) {
 646                 case 0:
 647                 case 1:
 648                 case 2:
 649                 case 4:
 650                 case 8:
 651                         break;
 652                 default:
 653                         return -EINVAL;
 654                 }
 655                 switch (mtaspect) {
 656                 case 0:
 657                 case 1:
 658                 case 2:
 659                 case 4:
 660                 case 8:
 661                         break;
 662                 default:
 663                         return -EINVAL;
 664                 }
 665                 if (tilesplit > 6) {
 666                         return -EINVAL;
 667                 }
 668                 if (stilesplit > 6) {
 669                         return -EINVAL;
 670                 }
 671         }
 672         r = radeon_bo_reserve(bo, false);
 673         if (unlikely(r != 0))
 674                 return r;
 675         bo->tiling_flags = tiling_flags;
 676         bo->pitch = pitch;
 677         radeon_bo_unreserve(bo);
 678         return 0;
 679 }
 680
 681 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 682                                 uint32_t *tiling_flags,
 683                                 uint32_t *pitch)
 684 {
 685         lockdep_assert_held(&bo->tbo.resv->lock.base);
 686
 687         if (tiling_flags)
 688                 *tiling_flags = bo->tiling_flags;
 689         if (pitch)
 690                 *pitch = bo->pitch;
 691 }
 692
 693 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 694                                 bool force_drop)
 695 {
 696         if (!force_drop)
 697                 lockdep_assert_held(&bo->tbo.resv->lock.base);
 698
 699         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 700                 return 0;
 701
 702         if (force_drop) {
 703                 radeon_bo_clear_surface_reg(bo);
 704                 return 0;
 705         }
 706
 707         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 708                 if (!has_moved)
 709                         return 0;
 710
 711                 if (bo->surface_reg >= 0)
 712                         radeon_bo_clear_surface_reg(bo);
 713                 return 0;
 714         }
 715
 716         if ((bo->surface_reg >= 0) && !has_moved)
 717                 return 0;
 718
 719         return radeon_bo_get_surface_reg(bo);
 720 }
 721
 722 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 723                            struct ttm_mem_reg *new_mem)
 724 {
 725         struct radeon_bo *rbo;
 726
 727         if (!radeon_ttm_bo_is_radeon_bo(bo))
 728                 return;
 729
 730         rbo = container_of(bo, struct radeon_bo, tbo);
 731         radeon_bo_check_tiling(rbo, 0, 1);
 732         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 733
 734         /* update statistics */
 735         if (!new_mem)
 736                 return;
 737
 738         radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
 739         radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
 740 }
 741
 742 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 743 {
 744         struct radeon_device *rdev;
 745         struct radeon_bo *rbo;
 746         unsigned long offset, size;
 747         int r;
 748
 749         if (!radeon_ttm_bo_is_radeon_bo(bo))
 750                 return 0;
 751         rbo = container_of(bo, struct radeon_bo, tbo);
 752         radeon_bo_check_tiling(rbo, 0, 0);
 753         rdev = rbo->rdev;
 754         if (bo->mem.mem_type != TTM_PL_VRAM)
 755                 return 0;
 756
 757         size = bo->mem.num_pages << PAGE_SHIFT;
 758         offset = bo->mem.start << PAGE_SHIFT;
 759         if ((offset + size) <= rdev->mc.visible_vram_size)
 760                 return 0;
 761
 762         /* hurrah the memory is not visible ! */
 763         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 764         rbo->placements[0].lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 765         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 766         if (unlikely(r == -ENOMEM)) {
 767                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 768                 return ttm_bo_validate(bo, &rbo->placement, false, false);
 769         } else if (unlikely(r != 0)) {
 770                 return r;
 771         }
 772
 773         offset = bo->mem.start << PAGE_SHIFT;
 774         /* this should never happen */
 775         if ((offset + size) > rdev->mc.visible_vram_size)
 776                 return -EINVAL;
 777
 778         return 0;
 779 }
 780
 781 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 782 {
 783         int r;
 784
 785         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
 786         if (unlikely(r != 0))
 787                 return r;
 788         if (mem_type)
 789                 *mem_type = bo->tbo.mem.mem_type;
 790
 791         r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 792         ttm_bo_unreserve(&bo->tbo);
 793         return r;
 794 }