drivers/i2c/busses/i2c-imx.c

   1 /*
   2  *      Copyright (C) 2002 Motorola GSG-China
   3  *
   4  *      This program is free software; you can redistribute it and/or
   5  *      modify it under the terms of the GNU General Public License
   6  *      as published by the Free Software Foundation; either version 2
   7  *      of the License, or (at your option) any later version.
   8  *
   9  *      This program is distributed in the hope that it will be useful,
  10  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *      GNU General Public License for more details.
  13  *
  14  * Author:
  15  *      Darius Augulis, Teltonika Inc.
  16  *
  17  * Desc.:
  18  *      Implementation of I2C Adapter/Algorithm Driver
  19  *      for I2C Bus integrated in Freescale i.MX/MXC processors
  20  *
  21  *      Derived from Motorola GSG China I2C example driver
  22  *
  23  *      Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  24  *      Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  25  *      Copyright (C) 2007 RightHand Technologies, Inc.
  26  *      Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  27  *
  28  *      Copyright 2013 Freescale Semiconductor, Inc.
  29  *
  30  */
  31
  32 /** Includes *******************************************************************
  33 *******************************************************************************/
  34
  35 #include <linux/clk.h>
  36 #include <linux/completion.h>
  37 #include <linux/delay.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/dmaengine.h>
  40 #include <linux/dmapool.h>
  41 #include <linux/err.h>
  42 #include <linux/errno.h>
  43 #include <linux/i2c.h>
  44 #include <linux/init.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/kernel.h>
  48 #include <linux/module.h>
  49 #include <linux/of.h>
  50 #include <linux/of_device.h>
  51 #include <linux/of_dma.h>
  52 #include <linux/platform_data/i2c-imx.h>
  53 #include <linux/platform_device.h>
  54 #include <linux/sched.h>
  55 #include <linux/slab.h>
  56
  57 /** Defines ********************************************************************
  58 *******************************************************************************/
  59
  60 /* This will be the driver name the kernel reports */
  61 #define DRIVER_NAME "imx-i2c"
  62
  63 /* Default value */
  64 #define IMX_I2C_BIT_RATE        100000  /* 100kHz */
  65
  66 /*
  67  * Enable DMA if transfer byte size is bigger than this threshold.
  68  * As the hardware request, it must bigger than 4 bytes.\
  69  * I have set '16' here, maybe it's not the best but I think it's
  70  * the appropriate.
  71  */
  72 #define DMA_THRESHOLD   16
  73 #define DMA_TIMEOUT     1000
  74
  75 /* IMX I2C registers:
  76  * the I2C register offset is different between SoCs,
  77  * to provid support for all these chips, split the
  78  * register offset into a fixed base address and a
  79  * variable shift value, then the full register offset
  80  * will be calculated by
  81  * reg_off = ( reg_base_addr << reg_shift)
  82  */
  83 #define IMX_I2C_IADR    0x00    /* i2c slave address */
  84 #define IMX_I2C_IFDR    0x01    /* i2c frequency divider */
  85 #define IMX_I2C_I2CR    0x02    /* i2c control */
  86 #define IMX_I2C_I2SR    0x03    /* i2c status */
  87 #define IMX_I2C_I2DR    0x04    /* i2c transfer data */
  88
  89 #define IMX_I2C_REGSHIFT        2
  90 #define VF610_I2C_REGSHIFT      0
  91
  92 /* Bits of IMX I2C registers */
  93 #define I2SR_RXAK       0x01
  94 #define I2SR_IIF        0x02
  95 #define I2SR_SRW        0x04
  96 #define I2SR_IAL        0x10
  97 #define I2SR_IBB        0x20
  98 #define I2SR_IAAS       0x40
  99 #define I2SR_ICF        0x80
 100 #define I2CR_DMAEN      0x02
 101 #define I2CR_RSTA       0x04
 102 #define I2CR_TXAK       0x08
 103 #define I2CR_MTX        0x10
 104 #define I2CR_MSTA       0x20
 105 #define I2CR_IIEN       0x40
 106 #define I2CR_IEN        0x80
 107
 108 /* register bits different operating codes definition:
 109  * 1) I2SR: Interrupt flags clear operation differ between SoCs:
 110  * - write zero to clear(w0c) INT flag on i.MX,
 111  * - but write one to clear(w1c) INT flag on Vybrid.
 112  * 2) I2CR: I2C module enable operation also differ between SoCs:
 113  * - set I2CR_IEN bit enable the module on i.MX,
 114  * - but clear I2CR_IEN bit enable the module on Vybrid.
 115  */
 116 #define I2SR_CLR_OPCODE_W0C     0x0
 117 #define I2SR_CLR_OPCODE_W1C     (I2SR_IAL | I2SR_IIF)
 118 #define I2CR_IEN_OPCODE_0       0x0
 119 #define I2CR_IEN_OPCODE_1       I2CR_IEN
 120
 121 /** Variables ******************************************************************
 122 *******************************************************************************/
 123
 124 /*
 125  * sorted list of clock divider, register value pairs
 126  * taken from table 26-5, p.26-9, Freescale i.MX
 127  * Integrated Portable System Processor Reference Manual
 128  * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 129  *
 130  * Duplicated divider values removed from list
 131  */
 132 struct imx_i2c_clk_pair {
 133         u16     div;
 134         u16     val;
 135 };
 136
 137 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 138         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
 139         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
 140         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
 141         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
 142         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
 143         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
 144         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
 145         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 146         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 147         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 148         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 149         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 150         { 3072, 0x1E }, { 3840, 0x1F }
 151 };
 152
 153 /* Vybrid VF610 clock divider, register value pairs */
 154 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 155         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 156         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 157         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 158         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 159         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 160         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 161         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 162         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 163         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 164         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 165         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 166         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 167         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 168         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 169         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 170 };
 171
 172 enum imx_i2c_type {
 173         IMX1_I2C,
 174         IMX21_I2C,
 175         VF610_I2C,
 176 };
 177
 178 struct imx_i2c_hwdata {
 179         enum imx_i2c_type       devtype;
 180         unsigned                regshift;
 181         struct imx_i2c_clk_pair *clk_div;
 182         unsigned                ndivs;
 183         unsigned                i2sr_clr_opcode;
 184         unsigned                i2cr_ien_opcode;
 185 };
 186
 187 struct imx_i2c_dma {
 188         struct dma_chan         *chan_tx;
 189         struct dma_chan         *chan_rx;
 190         struct dma_chan         *chan_using;
 191         struct completion       cmd_complete;
 192         dma_addr_t              dma_buf;
 193         unsigned int            dma_len;
 194         enum dma_transfer_direction dma_transfer_dir;
 195         enum dma_data_direction dma_data_dir;
 196 };
 197
 198 struct imx_i2c_struct {
 199         struct i2c_adapter      adapter;
 200         struct clk              *clk;
 201         void __iomem            *base;
 202         wait_queue_head_t       queue;
 203         unsigned long           i2csr;
 204         unsigned int            disable_delay;
 205         int                     stopped;
 206         unsigned int            ifdr; /* IMX_I2C_IFDR */
 207         unsigned int            cur_clk;
 208         unsigned int            bitrate;
 209         const struct imx_i2c_hwdata     *hwdata;
 210
 211         struct imx_i2c_dma      *dma;
 212 };
 213
 214 static const struct imx_i2c_hwdata imx1_i2c_hwdata  = {
 215         .devtype                = IMX1_I2C,
 216         .regshift               = IMX_I2C_REGSHIFT,
 217         .clk_div                = imx_i2c_clk_div,
 218         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 219         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 220         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 221
 222 };
 223
 224 static const struct imx_i2c_hwdata imx21_i2c_hwdata  = {
 225         .devtype                = IMX21_I2C,
 226         .regshift               = IMX_I2C_REGSHIFT,
 227         .clk_div                = imx_i2c_clk_div,
 228         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 229         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 230         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 231
 232 };
 233
 234 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 235         .devtype                = VF610_I2C,
 236         .regshift               = VF610_I2C_REGSHIFT,
 237         .clk_div                = vf610_i2c_clk_div,
 238         .ndivs                  = ARRAY_SIZE(vf610_i2c_clk_div),
 239         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W1C,
 240         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_0,
 241
 242 };
 243
 244 static const struct platform_device_id imx_i2c_devtype[] = {
 245         {
 246                 .name = "imx1-i2c",
 247                 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
 248         }, {
 249                 .name = "imx21-i2c",
 250                 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
 251         }, {
 252                 /* sentinel */
 253         }
 254 };
 255 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
 256
 257 static const struct of_device_id i2c_imx_dt_ids[] = {
 258         { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 259         { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 260         { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 261         { /* sentinel */ }
 262 };
 263 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 264
 265 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 266 {
 267         return i2c_imx->hwdata->devtype == IMX1_I2C;
 268 }
 269
 270 static inline void imx_i2c_write_reg(unsigned int val,
 271                 struct imx_i2c_struct *i2c_imx, unsigned int reg)
 272 {
 273         writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 274 }
 275
 276 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 277                 unsigned int reg)
 278 {
 279         return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 280 }
 281
 282 /* Functions for DMA support */
 283 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 284                                                 dma_addr_t phy_addr)
 285 {
 286         struct imx_i2c_dma *dma;
 287         struct dma_slave_config dma_sconfig;
 288         struct device *dev = &i2c_imx->adapter.dev;
 289         int ret;
 290
 291         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 292         if (!dma)
 293                 return;
 294
 295         dma->chan_tx = dma_request_slave_channel(dev, "tx");
 296         if (!dma->chan_tx) {
 297                 dev_dbg(dev, "can't request DMA tx channel\n");
 298                 goto fail_al;
 299         }
 300
 301         dma_sconfig.dst_addr = phy_addr +
 302                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 303         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 304         dma_sconfig.dst_maxburst = 1;
 305         dma_sconfig.direction = DMA_MEM_TO_DEV;
 306         ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 307         if (ret < 0) {
 308                 dev_dbg(dev, "can't configure tx channel\n");
 309                 goto fail_tx;
 310         }
 311
 312         dma->chan_rx = dma_request_slave_channel(dev, "rx");
 313         if (!dma->chan_rx) {
 314                 dev_dbg(dev, "can't request DMA rx channel\n");
 315                 goto fail_tx;
 316         }
 317
 318         dma_sconfig.src_addr = phy_addr +
 319                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 320         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 321         dma_sconfig.src_maxburst = 1;
 322         dma_sconfig.direction = DMA_DEV_TO_MEM;
 323         ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 324         if (ret < 0) {
 325                 dev_dbg(dev, "can't configure rx channel\n");
 326                 goto fail_rx;
 327         }
 328
 329         i2c_imx->dma = dma;
 330         init_completion(&dma->cmd_complete);
 331         dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 332                 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 333
 334         return;
 335
 336 fail_rx:
 337         dma_release_channel(dma->chan_rx);
 338 fail_tx:
 339         dma_release_channel(dma->chan_tx);
 340 fail_al:
 341         devm_kfree(dev, dma);
 342         dev_info(dev, "can't use DMA\n");
 343 }
 344
 345 static void i2c_imx_dma_callback(void *arg)
 346 {
 347         struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
 348         struct imx_i2c_dma *dma = i2c_imx->dma;
 349
 350         dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
 351                         dma->dma_len, dma->dma_data_dir);
 352         complete(&dma->cmd_complete);
 353 }
 354
 355 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
 356                                         struct i2c_msg *msgs)
 357 {
 358         struct imx_i2c_dma *dma = i2c_imx->dma;
 359         struct dma_async_tx_descriptor *txdesc;
 360         struct device *dev = &i2c_imx->adapter.dev;
 361         struct device *chan_dev = dma->chan_using->device->dev;
 362
 363         dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
 364                                         dma->dma_len, dma->dma_data_dir);
 365         if (dma_mapping_error(chan_dev, dma->dma_buf)) {
 366                 dev_err(dev, "DMA mapping failed\n");
 367                 goto err_map;
 368         }
 369
 370         txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
 371                                         dma->dma_len, dma->dma_transfer_dir,
 372                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 373         if (!txdesc) {
 374                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 375                 goto err_desc;
 376         }
 377
 378         txdesc->callback = i2c_imx_dma_callback;
 379         txdesc->callback_param = i2c_imx;
 380         if (dma_submit_error(dmaengine_submit(txdesc))) {
 381                 dev_err(dev, "DMA submit failed\n");
 382                 goto err_submit;
 383         }
 384
 385         dma_async_issue_pending(dma->chan_using);
 386         return 0;
 387
 388 err_submit:
 389 err_desc:
 390         dma_unmap_single(chan_dev, dma->dma_buf,
 391                         dma->dma_len, dma->dma_data_dir);
 392 err_map:
 393         return -EINVAL;
 394 }
 395
 396 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
 397 {
 398         struct imx_i2c_dma *dma = i2c_imx->dma;
 399
 400         dma->dma_buf = 0;
 401         dma->dma_len = 0;
 402
 403         dma_release_channel(dma->chan_tx);
 404         dma->chan_tx = NULL;
 405
 406         dma_release_channel(dma->chan_rx);
 407         dma->chan_rx = NULL;
 408
 409         dma->chan_using = NULL;
 410 }
 411
 412 /** Functions for IMX I2C adapter driver ***************************************
 413 *******************************************************************************/
 414
 415 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
 416 {
 417         unsigned long orig_jiffies = jiffies;
 418         unsigned int temp;
 419
 420         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 421
 422         while (1) {
 423                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 424
 425                 /* check for arbitration lost */
 426                 if (temp & I2SR_IAL) {
 427                         temp &= ~I2SR_IAL;
 428                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 429                         return -EAGAIN;
 430                 }
 431
 432                 if (for_busy && (temp & I2SR_IBB))
 433                         break;
 434                 if (!for_busy && !(temp & I2SR_IBB))
 435                         break;
 436                 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 437                         dev_dbg(&i2c_imx->adapter.dev,
 438                                 "<%s> I2C bus is busy\n", __func__);
 439                         return -ETIMEDOUT;
 440                 }
 441                 schedule();
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
 448 {
 449         wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 450
 451         if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 452                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 453                 return -ETIMEDOUT;
 454         }
 455         dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 456         i2c_imx->i2csr = 0;
 457         return 0;
 458 }
 459
 460 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 461 {
 462         if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 463                 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 464                 return -EIO;  /* No ACK */
 465         }
 466
 467         dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 468         return 0;
 469 }
 470
 471 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
 472 {
 473         struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 474         unsigned int i2c_clk_rate;
 475         unsigned int div;
 476         int i;
 477
 478         /* Divider value calculation */
 479         i2c_clk_rate = clk_get_rate(i2c_imx->clk);
 480         if (i2c_imx->cur_clk == i2c_clk_rate)
 481                 return;
 482
 483         i2c_imx->cur_clk = i2c_clk_rate;
 484
 485         div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
 486         if (div < i2c_clk_div[0].div)
 487                 i = 0;
 488         else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 489                 i = i2c_imx->hwdata->ndivs - 1;
 490         else
 491                 for (i = 0; i2c_clk_div[i].div < div; i++)
 492                         ;
 493
 494         /* Store divider value */
 495         i2c_imx->ifdr = i2c_clk_div[i].val;
 496
 497         /*
 498          * There dummy delay is calculated.
 499          * It should be about one I2C clock period long.
 500          * This delay is used in I2C bus disable function
 501          * to fix chip hardware bug.
 502          */
 503         i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
 504                 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
 505
 506 #ifdef CONFIG_I2C_DEBUG_BUS
 507         dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 508                 i2c_clk_rate, div);
 509         dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 510                 i2c_clk_div[i].val, i2c_clk_div[i].div);
 511 #endif
 512 }
 513
 514 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
 515 {
 516         unsigned int temp = 0;
 517         int result;
 518
 519         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 520
 521         i2c_imx_set_clk(i2c_imx);
 522
 523         result = clk_prepare_enable(i2c_imx->clk);
 524         if (result)
 525                 return result;
 526         imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 527         /* Enable I2C controller */
 528         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 529         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 530
 531         /* Wait controller to be stable */
 532         udelay(50);
 533
 534         /* Start I2C transaction */
 535         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 536         temp |= I2CR_MSTA;
 537         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 538         result = i2c_imx_bus_busy(i2c_imx, 1);
 539         if (result)
 540                 return result;
 541         i2c_imx->stopped = 0;
 542
 543         temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 544         temp &= ~I2CR_DMAEN;
 545         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 546         return result;
 547 }
 548
 549 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
 550 {
 551         unsigned int temp = 0;
 552
 553         if (!i2c_imx->stopped) {
 554                 /* Stop I2C transaction */
 555                 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 556                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 557                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 558                 if (i2c_imx->dma)
 559                         temp &= ~I2CR_DMAEN;
 560                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 561         }
 562         if (is_imx1_i2c(i2c_imx)) {
 563                 /*
 564                  * This delay caused by an i.MXL hardware bug.
 565                  * If no (or too short) delay, no "STOP" bit will be generated.
 566                  */
 567                 udelay(i2c_imx->disable_delay);
 568         }
 569
 570         if (!i2c_imx->stopped) {
 571                 i2c_imx_bus_busy(i2c_imx, 0);
 572                 i2c_imx->stopped = 1;
 573         }
 574
 575         /* Disable I2C controller */
 576         temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 577         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 578         clk_disable_unprepare(i2c_imx->clk);
 579 }
 580
 581 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 582 {
 583         struct imx_i2c_struct *i2c_imx = dev_id;
 584         unsigned int temp;
 585
 586         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 587         if (temp & I2SR_IIF) {
 588                 /* save status register */
 589                 i2c_imx->i2csr = temp;
 590                 temp &= ~I2SR_IIF;
 591                 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
 592                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 593                 wake_up(&i2c_imx->queue);
 594                 return IRQ_HANDLED;
 595         }
 596
 597         return IRQ_NONE;
 598 }
 599
 600 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
 601                                         struct i2c_msg *msgs)
 602 {
 603         int result;
 604         unsigned long time_left;
 605         unsigned int temp = 0;
 606         unsigned long orig_jiffies = jiffies;
 607         struct imx_i2c_dma *dma = i2c_imx->dma;
 608         struct device *dev = &i2c_imx->adapter.dev;
 609
 610         dma->chan_using = dma->chan_tx;
 611         dma->dma_transfer_dir = DMA_MEM_TO_DEV;
 612         dma->dma_data_dir = DMA_TO_DEVICE;
 613         dma->dma_len = msgs->len - 1;
 614         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 615         if (result)
 616                 return result;
 617
 618         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 619         temp |= I2CR_DMAEN;
 620         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 621
 622         /*
 623          * Write slave address.
 624          * The first byte must be transmitted by the CPU.
 625          */
 626         imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
 627         reinit_completion(&i2c_imx->dma->cmd_complete);
 628         time_left = wait_for_completion_timeout(
 629                                 &i2c_imx->dma->cmd_complete,
 630                                 msecs_to_jiffies(DMA_TIMEOUT));
 631         if (time_left == 0) {
 632                 dmaengine_terminate_all(dma->chan_using);
 633                 return -ETIMEDOUT;
 634         }
 635
 636         /* Waiting for transfer complete. */
 637         while (1) {
 638                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 639                 if (temp & I2SR_ICF)
 640                         break;
 641                 if (time_after(jiffies, orig_jiffies +
 642                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 643                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 644                         return -ETIMEDOUT;
 645                 }
 646                 schedule();
 647         }
 648
 649         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 650         temp &= ~I2CR_DMAEN;
 651         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 652
 653         /* The last data byte must be transferred by the CPU. */
 654         imx_i2c_write_reg(msgs->buf[msgs->len-1],
 655                                 i2c_imx, IMX_I2C_I2DR);
 656         result = i2c_imx_trx_complete(i2c_imx);
 657         if (result)
 658                 return result;
 659
 660         return i2c_imx_acked(i2c_imx);
 661 }
 662
 663 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
 664                         struct i2c_msg *msgs, bool is_lastmsg)
 665 {
 666         int result;
 667         unsigned long time_left;
 668         unsigned int temp;
 669         unsigned long orig_jiffies = jiffies;
 670         struct imx_i2c_dma *dma = i2c_imx->dma;
 671         struct device *dev = &i2c_imx->adapter.dev;
 672
 673         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 674         temp |= I2CR_DMAEN;
 675         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 676
 677         dma->chan_using = dma->chan_rx;
 678         dma->dma_transfer_dir = DMA_DEV_TO_MEM;
 679         dma->dma_data_dir = DMA_FROM_DEVICE;
 680         /* The last two data bytes must be transferred by the CPU. */
 681         dma->dma_len = msgs->len - 2;
 682         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 683         if (result)
 684                 return result;
 685
 686         reinit_completion(&i2c_imx->dma->cmd_complete);
 687         time_left = wait_for_completion_timeout(
 688                                 &i2c_imx->dma->cmd_complete,
 689                                 msecs_to_jiffies(DMA_TIMEOUT));
 690         if (time_left == 0) {
 691                 dmaengine_terminate_all(dma->chan_using);
 692                 return -ETIMEDOUT;
 693         }
 694
 695         /* waiting for transfer complete. */
 696         while (1) {
 697                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 698                 if (temp & I2SR_ICF)
 699                         break;
 700                 if (time_after(jiffies, orig_jiffies +
 701                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 702                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 703                         return -ETIMEDOUT;
 704                 }
 705                 schedule();
 706         }
 707
 708         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 709         temp &= ~I2CR_DMAEN;
 710         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 711
 712         /* read n-1 byte data */
 713         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 714         temp |= I2CR_TXAK;
 715         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 716
 717         msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 718         /* read n byte data */
 719         result = i2c_imx_trx_complete(i2c_imx);
 720         if (result)
 721                 return result;
 722
 723         if (is_lastmsg) {
 724                 /*
 725                  * It must generate STOP before read I2DR to prevent
 726                  * controller from generating another clock cycle
 727                  */
 728                 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
 729                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 730                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 731                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 732                 i2c_imx_bus_busy(i2c_imx, 0);
 733                 i2c_imx->stopped = 1;
 734         } else {
 735                 /*
 736                  * For i2c master receiver repeat restart operation like:
 737                  * read -> repeat MSTA -> read/write
 738                  * The controller must set MTX before read the last byte in
 739                  * the first read operation, otherwise the first read cost
 740                  * one extra clock cycle.
 741                  */
 742                 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
 743                 temp |= I2CR_MTX;
 744                 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
 745         }
 746         msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 747
 748         return 0;
 749 }
 750
 751 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
 752 {
 753         int i, result;
 754
 755         dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
 756                 __func__, msgs->addr << 1);
 757
 758         /* write slave address */
 759         imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
 760         result = i2c_imx_trx_complete(i2c_imx);
 761         if (result)
 762                 return result;
 763         result = i2c_imx_acked(i2c_imx);
 764         if (result)
 765                 return result;
 766         dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
 767
 768         /* write data */
 769         for (i = 0; i < msgs->len; i++) {
 770                 dev_dbg(&i2c_imx->adapter.dev,
 771                         "<%s> write byte: B%d=0x%X\n",
 772                         __func__, i, msgs->buf[i]);
 773                 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
 774                 result = i2c_imx_trx_complete(i2c_imx);
 775                 if (result)
 776                         return result;
 777                 result = i2c_imx_acked(i2c_imx);
 778                 if (result)
 779                         return result;
 780         }
 781         return 0;
 782 }
 783
 784 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
 785 {
 786         int i, result;
 787         unsigned int temp;
 788         int block_data = msgs->flags & I2C_M_RECV_LEN;
 789
 790         dev_dbg(&i2c_imx->adapter.dev,
 791                 "<%s> write slave address: addr=0x%x\n",
 792                 __func__, (msgs->addr << 1) | 0x01);
 793
 794         /* write slave address */
 795         imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
 796         result = i2c_imx_trx_complete(i2c_imx);
 797         if (result)
 798                 return result;
 799         result = i2c_imx_acked(i2c_imx);
 800         if (result)
 801                 return result;
 802
 803         dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
 804
 805         /* setup bus to read data */
 806         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 807         temp &= ~I2CR_MTX;
 808
 809         /*
 810          * Reset the I2CR_TXAK flag initially for SMBus block read since the
 811          * length is unknown
 812          */
 813         if ((msgs->len - 1) || block_data)
 814                 temp &= ~I2CR_TXAK;
 815         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 816         imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
 817
 818         dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
 819
 820         if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data)
 821                 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
 822
 823         /* read data */
 824         for (i = 0; i < msgs->len; i++) {
 825                 u8 len = 0;
 826
 827                 result = i2c_imx_trx_complete(i2c_imx);
 828                 if (result)
 829                         return result;
 830                 /*
 831                  * First byte is the length of remaining packet
 832                  * in the SMBus block data read. Add it to
 833                  * msgs->len.
 834                  */
 835                 if ((!i) && block_data) {
 836                         len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 837                         if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
 838                                 return -EPROTO;
 839                         dev_dbg(&i2c_imx->adapter.dev,
 840                                 "<%s> read length: 0x%X\n",
 841                                 __func__, len);
 842                         msgs->len += len;
 843                 }
 844                 if (i == (msgs->len - 1)) {
 845                         if (is_lastmsg) {
 846                                 /*
 847                                  * It must generate STOP before read I2DR to prevent
 848                                  * controller from generating another clock cycle
 849                                  */
 850                                 dev_dbg(&i2c_imx->adapter.dev,
 851                                         "<%s> clear MSTA\n", __func__);
 852                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 853                                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 854                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 855                                 i2c_imx_bus_busy(i2c_imx, 0);
 856                                 i2c_imx->stopped = 1;
 857                         } else {
 858                                 /*
 859                                  * For i2c master receiver repeat restart operation like:
 860                                  * read -> repeat MSTA -> read/write
 861                                  * The controller must set MTX before read the last byte in
 862                                  * the first read operation, otherwise the first read cost
 863                                  * one extra clock cycle.
 864                                  */
 865                                 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
 866                                 temp |= I2CR_MTX;
 867                                 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
 868                         }
 869                 } else if (i == (msgs->len - 2)) {
 870                         dev_dbg(&i2c_imx->adapter.dev,
 871                                 "<%s> set TXAK\n", __func__);
 872                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 873                         temp |= I2CR_TXAK;
 874                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 875                 }
 876                 if ((!i) && block_data)
 877                         msgs->buf[0] = len;
 878                 else
 879                         msgs->buf[i] =  imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 880                 dev_dbg(&i2c_imx->adapter.dev,
 881                         "<%s> read byte: B%d=0x%X\n",
 882                         __func__, i, msgs->buf[i]);
 883         }
 884         return 0;
 885 }
 886
 887 static int i2c_imx_xfer(struct i2c_adapter *adapter,
 888                                                 struct i2c_msg *msgs, int num)
 889 {
 890         unsigned int i, temp;
 891         int result;
 892         bool is_lastmsg = false;
 893         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
 894
 895         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 896
 897         /* Start I2C transfer */
 898         result = i2c_imx_start(i2c_imx);
 899         if (result)
 900                 goto fail0;
 901
 902         /* read/write data */
 903         for (i = 0; i < num; i++) {
 904                 if (i == num - 1)
 905                         is_lastmsg = true;
 906
 907                 if (i) {
 908                         dev_dbg(&i2c_imx->adapter.dev,
 909                                 "<%s> repeated start\n", __func__);
 910                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 911                         temp |= I2CR_RSTA;
 912                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 913                         result =  i2c_imx_bus_busy(i2c_imx, 1);
 914                         if (result)
 915                                 goto fail0;
 916                 }
 917                 dev_dbg(&i2c_imx->adapter.dev,
 918                         "<%s> transfer message: %d\n", __func__, i);
 919                 /* write/read data */
 920 #ifdef CONFIG_I2C_DEBUG_BUS
 921                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 922                 dev_dbg(&i2c_imx->adapter.dev,
 923                         "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
 924                         __func__,
 925                         (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
 926                         (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
 927                         (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
 928                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 929                 dev_dbg(&i2c_imx->adapter.dev,
 930                         "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
 931                         __func__,
 932                         (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
 933                         (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
 934                         (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
 935                         (temp & I2SR_RXAK ? 1 : 0));
 936 #endif
 937                 if (msgs[i].flags & I2C_M_RD)
 938                         result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
 939                 else {
 940                         if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
 941                                 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
 942                         else
 943                                 result = i2c_imx_write(i2c_imx, &msgs[i]);
 944                 }
 945                 if (result)
 946                         goto fail0;
 947         }
 948
 949 fail0:
 950         /* Stop I2C transfer */
 951         i2c_imx_stop(i2c_imx);
 952
 953         dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
 954                 (result < 0) ? "error" : "success msg",
 955                         (result < 0) ? result : num);
 956         return (result < 0) ? result : num;
 957 }
 958
 959 static u32 i2c_imx_func(struct i2c_adapter *adapter)
 960 {
 961         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 962                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
 963 }
 964
 965 static struct i2c_algorithm i2c_imx_algo = {
 966         .master_xfer    = i2c_imx_xfer,
 967         .functionality  = i2c_imx_func,
 968 };
 969
 970 static int i2c_imx_probe(struct platform_device *pdev)
 971 {
 972         const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
 973                                                            &pdev->dev);
 974         struct imx_i2c_struct *i2c_imx;
 975         struct resource *res;
 976         struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
 977         void __iomem *base;
 978         int irq, ret;
 979         dma_addr_t phy_addr;
 980
 981         dev_dbg(&pdev->dev, "<%s>\n", __func__);
 982
 983         irq = platform_get_irq(pdev, 0);
 984         if (irq < 0) {
 985                 dev_err(&pdev->dev, "can't get irq number\n");
 986                 return irq;
 987         }
 988
 989         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 990         base = devm_ioremap_resource(&pdev->dev, res);
 991         if (IS_ERR(base))
 992                 return PTR_ERR(base);
 993
 994         phy_addr = (dma_addr_t)res->start;
 995         i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
 996         if (!i2c_imx)
 997                 return -ENOMEM;
 998
 999         if (of_id)
1000                 i2c_imx->hwdata = of_id->data;
1001         else
1002                 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1003                                 platform_get_device_id(pdev)->driver_data;
1004
1005         /* Setup i2c_imx driver structure */
1006         strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1007         i2c_imx->adapter.owner          = THIS_MODULE;
1008         i2c_imx->adapter.algo           = &i2c_imx_algo;
1009         i2c_imx->adapter.dev.parent     = &pdev->dev;
1010         i2c_imx->adapter.nr             = pdev->id;
1011         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
1012         i2c_imx->base                   = base;
1013
1014         /* Get I2C clock */
1015         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1016         if (IS_ERR(i2c_imx->clk)) {
1017                 dev_err(&pdev->dev, "can't get I2C clock\n");
1018                 return PTR_ERR(i2c_imx->clk);
1019         }
1020
1021         ret = clk_prepare_enable(i2c_imx->clk);
1022         if (ret) {
1023                 dev_err(&pdev->dev, "can't enable I2C clock\n");
1024                 return ret;
1025         }
1026         /* Request IRQ */
1027         ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
1028                                 pdev->name, i2c_imx);
1029         if (ret) {
1030                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1031                 goto clk_disable;
1032         }
1033
1034         /* Init queue */
1035         init_waitqueue_head(&i2c_imx->queue);
1036
1037         /* Set up adapter data */
1038         i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1039
1040         /* Set up clock divider */
1041         i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1042         ret = of_property_read_u32(pdev->dev.of_node,
1043                                    "clock-frequency", &i2c_imx->bitrate);
1044         if (ret < 0 && pdata && pdata->bitrate)
1045                 i2c_imx->bitrate = pdata->bitrate;
1046
1047         /* Set up chip registers to defaults */
1048         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1049                         i2c_imx, IMX_I2C_I2CR);
1050         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1051
1052         /* Add I2C adapter */
1053         ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1054         if (ret < 0) {
1055                 dev_err(&pdev->dev, "registration failed\n");
1056                 goto clk_disable;
1057         }
1058
1059         /* Set up platform driver data */
1060         platform_set_drvdata(pdev, i2c_imx);
1061         clk_disable_unprepare(i2c_imx->clk);
1062
1063         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1064         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1065         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1066                 i2c_imx->adapter.name);
1067         dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1068
1069         /* Init DMA config if supported */
1070         i2c_imx_dma_request(i2c_imx, phy_addr);
1071
1072         return 0;   /* Return OK */
1073
1074 clk_disable:
1075         clk_disable_unprepare(i2c_imx->clk);
1076         return ret;
1077 }
1078
1079 static int i2c_imx_remove(struct platform_device *pdev)
1080 {
1081         struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1082
1083         /* remove adapter */
1084         dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1085         i2c_del_adapter(&i2c_imx->adapter);
1086
1087         if (i2c_imx->dma)
1088                 i2c_imx_dma_free(i2c_imx);
1089
1090         /* setup chip registers to defaults */
1091         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1092         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1093         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1094         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1095
1096         return 0;
1097 }
1098
1099 static struct platform_driver i2c_imx_driver = {
1100         .probe = i2c_imx_probe,
1101         .remove = i2c_imx_remove,
1102         .driver = {
1103                 .name   = DRIVER_NAME,
1104                 .of_match_table = i2c_imx_dt_ids,
1105         },
1106         .id_table       = imx_i2c_devtype,
1107 };
1108
1109 static int __init i2c_adap_imx_init(void)
1110 {
1111         return platform_driver_register(&i2c_imx_driver);
1112 }
1113 subsys_initcall(i2c_adap_imx_init);
1114
1115 static void __exit i2c_adap_imx_exit(void)
1116 {
1117         platform_driver_unregister(&i2c_imx_driver);
1118 }
1119 module_exit(i2c_adap_imx_exit);
1120
1121 MODULE_LICENSE("GPL");
1122 MODULE_AUTHOR("Darius Augulis");
1123 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1124 MODULE_ALIAS("platform:" DRIVER_NAME);