drivers/irqchip/irq-gic-v3.c

   1 /*
   2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/percpu.h>
  26 #include <linux/slab.h>
  27
  28 #include <linux/irqchip.h>
  29 #include <linux/irqchip/arm-gic-v3.h>
  30
  31 #include <asm/cputype.h>
  32 #include <asm/exception.h>
  33 #include <asm/smp_plat.h>
  34 #include <asm/virt.h>
  35
  36 #include "irq-gic-common.h"
  37
  38 struct redist_region {
  39         void __iomem            *redist_base;
  40         phys_addr_t             phys_base;
  41 };
  42
  43 struct gic_chip_data {
  44         void __iomem            *dist_base;
  45         struct redist_region    *redist_regions;
  46         struct rdists           rdists;
  47         struct irq_domain       *domain;
  48         u64                     redist_stride;
  49         u32                     nr_redist_regions;
  50         unsigned int            irq_nr;
  51 };
  52
  53 static struct gic_chip_data gic_data __read_mostly;
  54 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
  55
  56 #define gic_data_rdist()                (this_cpu_ptr(gic_data.rdists.rdist))
  57 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
  58 #define gic_data_rdist_sgi_base()       (gic_data_rdist_rd_base() + SZ_64K)
  59
  60 /* Our default, arbitrary priority value. Linux only uses one anyway. */
  61 #define DEFAULT_PMR_VALUE       0xf0
  62
  63 static inline unsigned int gic_irq(struct irq_data *d)
  64 {
  65         return d->hwirq;
  66 }
  67
  68 static inline int gic_irq_in_rdist(struct irq_data *d)
  69 {
  70         return gic_irq(d) < 32;
  71 }
  72
  73 static inline bool forwarded_irq(struct irq_data *d)
  74 {
  75         return d->handler_data != NULL;
  76 }
  77
  78 static inline void __iomem *gic_dist_base(struct irq_data *d)
  79 {
  80         if (gic_irq_in_rdist(d))        /* SGI+PPI -> SGI_base for this CPU */
  81                 return gic_data_rdist_sgi_base();
  82
  83         if (d->hwirq <= 1023)           /* SPI -> dist_base */
  84                 return gic_data.dist_base;
  85
  86         return NULL;
  87 }
  88
  89 static void gic_do_wait_for_rwp(void __iomem *base)
  90 {
  91         u32 count = 1000000;    /* 1s! */
  92
  93         while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
  94                 count--;
  95                 if (!count) {
  96                         pr_err_ratelimited("RWP timeout, gone fishing\n");
  97                         return;
  98                 }
  99                 cpu_relax();
 100                 udelay(1);
 101         };
 102 }
 103
 104 /* Wait for completion of a distributor change */
 105 static void gic_dist_wait_for_rwp(void)
 106 {
 107         gic_do_wait_for_rwp(gic_data.dist_base);
 108 }
 109
 110 /* Wait for completion of a redistributor change */
 111 static void gic_redist_wait_for_rwp(void)
 112 {
 113         gic_do_wait_for_rwp(gic_data_rdist_rd_base());
 114 }
 115
 116 /* Low level accessors */
 117 static u64 __maybe_unused gic_read_iar(void)
 118 {
 119         u64 irqstat;
 120
 121         asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
 122         return irqstat;
 123 }
 124
 125 static void __maybe_unused gic_write_pmr(u64 val)
 126 {
 127         asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
 128 }
 129
 130 static void __maybe_unused gic_write_ctlr(u64 val)
 131 {
 132         asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
 133         isb();
 134 }
 135
 136 static void __maybe_unused gic_write_grpen1(u64 val)
 137 {
 138         asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
 139         isb();
 140 }
 141
 142 static void __maybe_unused gic_write_sgi1r(u64 val)
 143 {
 144         asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
 145 }
 146
 147 static void gic_enable_sre(void)
 148 {
 149         u64 val;
 150
 151         asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
 152         val |= ICC_SRE_EL1_SRE;
 153         asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
 154         isb();
 155
 156         /*
 157          * Need to check that the SRE bit has actually been set. If
 158          * not, it means that SRE is disabled at EL2. We're going to
 159          * die painfully, and there is nothing we can do about it.
 160          *
 161          * Kindly inform the luser.
 162          */
 163         asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
 164         if (!(val & ICC_SRE_EL1_SRE))
 165                 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
 166 }
 167
 168 static void gic_enable_redist(bool enable)
 169 {
 170         void __iomem *rbase;
 171         u32 count = 1000000;    /* 1s! */
 172         u32 val;
 173
 174         rbase = gic_data_rdist_rd_base();
 175
 176         val = readl_relaxed(rbase + GICR_WAKER);
 177         if (enable)
 178                 /* Wake up this CPU redistributor */
 179                 val &= ~GICR_WAKER_ProcessorSleep;
 180         else
 181                 val |= GICR_WAKER_ProcessorSleep;
 182         writel_relaxed(val, rbase + GICR_WAKER);
 183
 184         if (!enable) {          /* Check that GICR_WAKER is writeable */
 185                 val = readl_relaxed(rbase + GICR_WAKER);
 186                 if (!(val & GICR_WAKER_ProcessorSleep))
 187                         return; /* No PM support in this redistributor */
 188         }
 189
 190         while (count--) {
 191                 val = readl_relaxed(rbase + GICR_WAKER);
 192                 if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
 193                         break;
 194                 cpu_relax();
 195                 udelay(1);
 196         };
 197         if (!count)
 198                 pr_err_ratelimited("redistributor failed to %s...\n",
 199                                    enable ? "wakeup" : "sleep");
 200 }
 201
 202 /*
 203  * Routines to disable, enable, EOI and route interrupts
 204  */
 205 static int gic_peek_irq(struct irq_data *d, u32 offset)
 206 {
 207         u32 mask = 1 << (gic_irq(d) % 32);
 208         void __iomem *base;
 209
 210         if (gic_irq_in_rdist(d))
 211                 base = gic_data_rdist_sgi_base();
 212         else
 213                 base = gic_data.dist_base;
 214
 215         return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
 216 }
 217
 218 static void gic_poke_irq(struct irq_data *d, u32 offset)
 219 {
 220         u32 mask = 1 << (gic_irq(d) % 32);
 221         void (*rwp_wait)(void);
 222         void __iomem *base;
 223
 224         if (gic_irq_in_rdist(d)) {
 225                 base = gic_data_rdist_sgi_base();
 226                 rwp_wait = gic_redist_wait_for_rwp;
 227         } else {
 228                 base = gic_data.dist_base;
 229                 rwp_wait = gic_dist_wait_for_rwp;
 230         }
 231
 232         writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
 233         rwp_wait();
 234 }
 235
 236 static void gic_mask_irq(struct irq_data *d)
 237 {
 238         gic_poke_irq(d, GICD_ICENABLER);
 239 }
 240
 241 static void gic_eoimode1_mask_irq(struct irq_data *d)
 242 {
 243         gic_mask_irq(d);
 244         /*
 245          * When masking a forwarded interrupt, make sure it is
 246          * deactivated as well.
 247          *
 248          * This ensures that an interrupt that is getting
 249          * disabled/masked will not get "stuck", because there is
 250          * noone to deactivate it (guest is being terminated).
 251          */
 252         if (forwarded_irq(d))
 253                 gic_poke_irq(d, GICD_ICACTIVER);
 254 }
 255
 256 static void gic_unmask_irq(struct irq_data *d)
 257 {
 258         gic_poke_irq(d, GICD_ISENABLER);
 259 }
 260
 261 static int gic_irq_set_irqchip_state(struct irq_data *d,
 262                                      enum irqchip_irq_state which, bool val)
 263 {
 264         u32 reg;
 265
 266         if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
 267                 return -EINVAL;
 268
 269         switch (which) {
 270         case IRQCHIP_STATE_PENDING:
 271                 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
 272                 break;
 273
 274         case IRQCHIP_STATE_ACTIVE:
 275                 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
 276                 break;
 277
 278         case IRQCHIP_STATE_MASKED:
 279                 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
 280                 break;
 281
 282         default:
 283                 return -EINVAL;
 284         }
 285
 286         gic_poke_irq(d, reg);
 287         return 0;
 288 }
 289
 290 static int gic_irq_get_irqchip_state(struct irq_data *d,
 291                                      enum irqchip_irq_state which, bool *val)
 292 {
 293         if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
 294                 return -EINVAL;
 295
 296         switch (which) {
 297         case IRQCHIP_STATE_PENDING:
 298                 *val = gic_peek_irq(d, GICD_ISPENDR);
 299                 break;
 300
 301         case IRQCHIP_STATE_ACTIVE:
 302                 *val = gic_peek_irq(d, GICD_ISACTIVER);
 303                 break;
 304
 305         case IRQCHIP_STATE_MASKED:
 306                 *val = !gic_peek_irq(d, GICD_ISENABLER);
 307                 break;
 308
 309         default:
 310                 return -EINVAL;
 311         }
 312
 313         return 0;
 314 }
 315
 316 static void gic_eoi_irq(struct irq_data *d)
 317 {
 318         gic_write_eoir(gic_irq(d));
 319 }
 320
 321 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 322 {
 323         /*
 324          * No need to deactivate an LPI, or an interrupt that
 325          * is is getting forwarded to a vcpu.
 326          */
 327         if (gic_irq(d) >= 8192 || forwarded_irq(d))
 328                 return;
 329         gic_write_dir(gic_irq(d));
 330 }
 331
 332 static int gic_set_type(struct irq_data *d, unsigned int type)
 333 {
 334         unsigned int irq = gic_irq(d);
 335         void (*rwp_wait)(void);
 336         void __iomem *base;
 337
 338         /* Interrupt configuration for SGIs can't be changed */
 339         if (irq < 16)
 340                 return -EINVAL;
 341
 342         /* SPIs have restrictions on the supported types */
 343         if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
 344                          type != IRQ_TYPE_EDGE_RISING)
 345                 return -EINVAL;
 346
 347         if (gic_irq_in_rdist(d)) {
 348                 base = gic_data_rdist_sgi_base();
 349                 rwp_wait = gic_redist_wait_for_rwp;
 350         } else {
 351                 base = gic_data.dist_base;
 352                 rwp_wait = gic_dist_wait_for_rwp;
 353         }
 354
 355         return gic_configure_irq(irq, type, base, rwp_wait);
 356 }
 357
 358 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 359 {
 360         d->handler_data = vcpu;
 361         return 0;
 362 }
 363
 364 static u64 gic_mpidr_to_affinity(u64 mpidr)
 365 {
 366         u64 aff;
 367
 368         aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
 369                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 370                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
 371                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 372
 373         return aff;
 374 }
 375
 376 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 377 {
 378         u64 irqnr;
 379
 380         do {
 381                 irqnr = gic_read_iar();
 382
 383                 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
 384                         int err;
 385
 386                         if (static_key_true(&supports_deactivate))
 387                                 gic_write_eoir(irqnr);
 388
 389                         err = handle_domain_irq(gic_data.domain, irqnr, regs);
 390                         if (err) {
 391                                 WARN_ONCE(true, "Unexpected interrupt received!\n");
 392                                 if (static_key_true(&supports_deactivate)) {
 393                                         if (irqnr < 8192)
 394                                                 gic_write_dir(irqnr);
 395                                 } else {
 396                                         gic_write_eoir(irqnr);
 397                                 }
 398                         }
 399                         continue;
 400                 }
 401                 if (irqnr < 16) {
 402                         gic_write_eoir(irqnr);
 403                         if (static_key_true(&supports_deactivate))
 404                                 gic_write_dir(irqnr);
 405 #ifdef CONFIG_SMP
 406                         handle_IPI(irqnr, regs);
 407 #else
 408                         WARN_ONCE(true, "Unexpected SGI received!\n");
 409 #endif
 410                         continue;
 411                 }
 412         } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
 413 }
 414
 415 static void __init gic_dist_init(void)
 416 {
 417         unsigned int i;
 418         u64 affinity;
 419         void __iomem *base = gic_data.dist_base;
 420
 421         /* Disable the distributor */
 422         writel_relaxed(0, base + GICD_CTLR);
 423         gic_dist_wait_for_rwp();
 424
 425         gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
 426
 427         /* Enable distributor with ARE, Group1 */
 428         writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
 429                        base + GICD_CTLR);
 430
 431         /*
 432          * Set all global interrupts to the boot CPU only. ARE must be
 433          * enabled.
 434          */
 435         affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
 436         for (i = 32; i < gic_data.irq_nr; i++)
 437                 writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
 438 }
 439
 440 static int gic_populate_rdist(void)
 441 {
 442         u64 mpidr = cpu_logical_map(smp_processor_id());
 443         u64 typer;
 444         u32 aff;
 445         int i;
 446
 447         /*
 448          * Convert affinity to a 32bit value that can be matched to
 449          * GICR_TYPER bits [63:32].
 450          */
 451         aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
 452                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 453                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
 454                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 455
 456         for (i = 0; i < gic_data.nr_redist_regions; i++) {
 457                 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
 458                 u32 reg;
 459
 460                 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
 461                 if (reg != GIC_PIDR2_ARCH_GICv3 &&
 462                     reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
 463                         pr_warn("No redistributor present @%p\n", ptr);
 464                         break;
 465                 }
 466
 467                 do {
 468                         typer = readq_relaxed(ptr + GICR_TYPER);
 469                         if ((typer >> 32) == aff) {
 470                                 u64 offset = ptr - gic_data.redist_regions[i].redist_base;
 471                                 gic_data_rdist_rd_base() = ptr;
 472                                 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
 473                                 pr_info("CPU%d: found redistributor %llx region %d:%pa\n",
 474                                         smp_processor_id(),
 475                                         (unsigned long long)mpidr,
 476                                         i, &gic_data_rdist()->phys_base);
 477                                 return 0;
 478                         }
 479
 480                         if (gic_data.redist_stride) {
 481                                 ptr += gic_data.redist_stride;
 482                         } else {
 483                                 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
 484                                 if (typer & GICR_TYPER_VLPIS)
 485                                         ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
 486                         }
 487                 } while (!(typer & GICR_TYPER_LAST));
 488         }
 489
 490         /* We couldn't even deal with ourselves... */
 491         WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
 492              smp_processor_id(), (unsigned long long)mpidr);
 493         return -ENODEV;
 494 }
 495
 496 static void gic_cpu_sys_reg_init(void)
 497 {
 498         /* Enable system registers */
 499         gic_enable_sre();
 500
 501         /* Set priority mask register */
 502         gic_write_pmr(DEFAULT_PMR_VALUE);
 503
 504         if (static_key_true(&supports_deactivate)) {
 505                 /* EOI drops priority only (mode 1) */
 506                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
 507         } else {
 508                 /* EOI deactivates interrupt too (mode 0) */
 509                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
 510         }
 511
 512         /* ... and let's hit the road... */
 513         gic_write_grpen1(1);
 514 }
 515
 516 static int gic_dist_supports_lpis(void)
 517 {
 518         return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS);
 519 }
 520
 521 static void gic_cpu_init(void)
 522 {
 523         void __iomem *rbase;
 524
 525         /* Register ourselves with the rest of the world */
 526         if (gic_populate_rdist())
 527                 return;
 528
 529         gic_enable_redist(true);
 530
 531         rbase = gic_data_rdist_sgi_base();
 532
 533         gic_cpu_config(rbase, gic_redist_wait_for_rwp);
 534
 535         /* Give LPIs a spin */
 536         if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
 537                 its_cpu_init();
 538
 539         /* initialise system registers */
 540         gic_cpu_sys_reg_init();
 541 }
 542
 543 #ifdef CONFIG_SMP
 544 static int gic_secondary_init(struct notifier_block *nfb,
 545                               unsigned long action, void *hcpu)
 546 {
 547         if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
 548                 gic_cpu_init();
 549         return NOTIFY_OK;
 550 }
 551
 552 /*
 553  * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
 554  * priority because the GIC needs to be up before the ARM generic timers.
 555  */
 556 static struct notifier_block gic_cpu_notifier = {
 557         .notifier_call = gic_secondary_init,
 558         .priority = 100,
 559 };
 560
 561 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
 562                                    u64 cluster_id)
 563 {
 564         int cpu = *base_cpu;
 565         u64 mpidr = cpu_logical_map(cpu);
 566         u16 tlist = 0;
 567
 568         while (cpu < nr_cpu_ids) {
 569                 /*
 570                  * If we ever get a cluster of more than 16 CPUs, just
 571                  * scream and skip that CPU.
 572                  */
 573                 if (WARN_ON((mpidr & 0xff) >= 16))
 574                         goto out;
 575
 576                 tlist |= 1 << (mpidr & 0xf);
 577
 578                 cpu = cpumask_next(cpu, mask);
 579                 if (cpu >= nr_cpu_ids)
 580                         goto out;
 581
 582                 mpidr = cpu_logical_map(cpu);
 583
 584                 if (cluster_id != (mpidr & ~0xffUL)) {
 585                         cpu--;
 586                         goto out;
 587                 }
 588         }
 589 out:
 590         *base_cpu = cpu;
 591         return tlist;
 592 }
 593
 594 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
 595         (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
 596                 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
 597
 598 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
 599 {
 600         u64 val;
 601
 602         val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3)     |
 603                MPIDR_TO_SGI_AFFINITY(cluster_id, 2)     |
 604                irq << ICC_SGI1R_SGI_ID_SHIFT            |
 605                MPIDR_TO_SGI_AFFINITY(cluster_id, 1)     |
 606                tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
 607
 608         pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
 609         gic_write_sgi1r(val);
 610 }
 611
 612 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 613 {
 614         int cpu;
 615
 616         if (WARN_ON(irq >= 16))
 617                 return;
 618
 619         /*
 620          * Ensure that stores to Normal memory are visible to the
 621          * other CPUs before issuing the IPI.
 622          */
 623         smp_wmb();
 624
 625         for_each_cpu(cpu, mask) {
 626                 u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
 627                 u16 tlist;
 628
 629                 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
 630                 gic_send_sgi(cluster_id, tlist, irq);
 631         }
 632
 633         /* Force the above writes to ICC_SGI1R_EL1 to be executed */
 634         isb();
 635 }
 636
 637 static void gic_smp_init(void)
 638 {
 639         set_smp_cross_call(gic_raise_softirq);
 640         register_cpu_notifier(&gic_cpu_notifier);
 641 }
 642
 643 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 644                             bool force)
 645 {
 646         unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
 647         void __iomem *reg;
 648         int enabled;
 649         u64 val;
 650
 651         if (gic_irq_in_rdist(d))
 652                 return -EINVAL;
 653
 654         /* If interrupt was enabled, disable it first */
 655         enabled = gic_peek_irq(d, GICD_ISENABLER);
 656         if (enabled)
 657                 gic_mask_irq(d);
 658
 659         reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
 660         val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
 661
 662         writeq_relaxed(val, reg);
 663
 664         /*
 665          * If the interrupt was enabled, enabled it again. Otherwise,
 666          * just wait for the distributor to have digested our changes.
 667          */
 668         if (enabled)
 669                 gic_unmask_irq(d);
 670         else
 671                 gic_dist_wait_for_rwp();
 672
 673         return IRQ_SET_MASK_OK;
 674 }
 675 #else
 676 #define gic_set_affinity        NULL
 677 #define gic_smp_init()          do { } while(0)
 678 #endif
 679
 680 #ifdef CONFIG_CPU_PM
 681 static int gic_cpu_pm_notifier(struct notifier_block *self,
 682                                unsigned long cmd, void *v)
 683 {
 684         if (cmd == CPU_PM_EXIT) {
 685                 gic_enable_redist(true);
 686                 gic_cpu_sys_reg_init();
 687         } else if (cmd == CPU_PM_ENTER) {
 688                 gic_write_grpen1(0);
 689                 gic_enable_redist(false);
 690         }
 691         return NOTIFY_OK;
 692 }
 693
 694 static struct notifier_block gic_cpu_pm_notifier_block = {
 695         .notifier_call = gic_cpu_pm_notifier,
 696 };
 697
 698 static void gic_cpu_pm_init(void)
 699 {
 700         cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
 701 }
 702
 703 #else
 704 static inline void gic_cpu_pm_init(void) { }
 705 #endif /* CONFIG_CPU_PM */
 706
 707 static struct irq_chip gic_chip = {
 708         .name                   = "GICv3",
 709         .irq_mask               = gic_mask_irq,
 710         .irq_unmask             = gic_unmask_irq,
 711         .irq_eoi                = gic_eoi_irq,
 712         .irq_set_type           = gic_set_type,
 713         .irq_set_affinity       = gic_set_affinity,
 714         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 715         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 716         .flags                  = IRQCHIP_SET_TYPE_MASKED,
 717 };
 718
 719 static struct irq_chip gic_eoimode1_chip = {
 720         .name                   = "GICv3",
 721         .irq_mask               = gic_eoimode1_mask_irq,
 722         .irq_unmask             = gic_unmask_irq,
 723         .irq_eoi                = gic_eoimode1_eoi_irq,
 724         .irq_set_type           = gic_set_type,
 725         .irq_set_affinity       = gic_set_affinity,
 726         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 727         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 728         .irq_set_vcpu_affinity  = gic_irq_set_vcpu_affinity,
 729         .flags                  = IRQCHIP_SET_TYPE_MASKED,
 730 };
 731
 732 #define GIC_ID_NR               (1U << gic_data.rdists.id_bits)
 733
 734 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 735                               irq_hw_number_t hw)
 736 {
 737         struct irq_chip *chip = &gic_chip;
 738
 739         if (static_key_true(&supports_deactivate))
 740                 chip = &gic_eoimode1_chip;
 741
 742         /* SGIs are private to the core kernel */
 743         if (hw < 16)
 744                 return -EPERM;
 745         /* Nothing here */
 746         if (hw >= gic_data.irq_nr && hw < 8192)
 747                 return -EPERM;
 748         /* Off limits */
 749         if (hw >= GIC_ID_NR)
 750                 return -EPERM;
 751
 752         /* PPIs */
 753         if (hw < 32) {
 754                 irq_set_percpu_devid(irq);
 755                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
 756                                     handle_percpu_devid_irq, NULL, NULL);
 757                 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
 758         }
 759         /* SPIs */
 760         if (hw >= 32 && hw < gic_data.irq_nr) {
 761                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
 762                                     handle_fasteoi_irq, NULL, NULL);
 763                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 764         }
 765         /* LPIs */
 766         if (hw >= 8192 && hw < GIC_ID_NR) {
 767                 if (!gic_dist_supports_lpis())
 768                         return -EPERM;
 769                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
 770                                     handle_fasteoi_irq, NULL, NULL);
 771                 set_irq_flags(irq, IRQF_VALID);
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int gic_irq_domain_xlate(struct irq_domain *d,
 778                                 struct device_node *controller,
 779                                 const u32 *intspec, unsigned int intsize,
 780                                 unsigned long *out_hwirq, unsigned int *out_type)
 781 {
 782         if (d->of_node != controller)
 783                 return -EINVAL;
 784         if (intsize < 3)
 785                 return -EINVAL;
 786
 787         switch(intspec[0]) {
 788         case 0:                 /* SPI */
 789                 *out_hwirq = intspec[1] + 32;
 790                 break;
 791         case 1:                 /* PPI */
 792                 *out_hwirq = intspec[1] + 16;
 793                 break;
 794         case GIC_IRQ_TYPE_LPI:  /* LPI */
 795                 *out_hwirq = intspec[1];
 796                 break;
 797         default:
 798                 return -EINVAL;
 799         }
 800
 801         *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
 802         return 0;
 803 }
 804
 805 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 806                                 unsigned int nr_irqs, void *arg)
 807 {
 808         int i, ret;
 809         irq_hw_number_t hwirq;
 810         unsigned int type = IRQ_TYPE_NONE;
 811         struct of_phandle_args *irq_data = arg;
 812
 813         ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
 814                                    irq_data->args_count, &hwirq, &type);
 815         if (ret)
 816                 return ret;
 817
 818         for (i = 0; i < nr_irqs; i++)
 819                 gic_irq_domain_map(domain, virq + i, hwirq + i);
 820
 821         return 0;
 822 }
 823
 824 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
 825                                 unsigned int nr_irqs)
 826 {
 827         int i;
 828
 829         for (i = 0; i < nr_irqs; i++) {
 830                 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
 831                 irq_set_handler(virq + i, NULL);
 832                 irq_domain_reset_irq_data(d);
 833         }
 834 }
 835
 836 static const struct irq_domain_ops gic_irq_domain_ops = {
 837         .xlate = gic_irq_domain_xlate,
 838         .alloc = gic_irq_domain_alloc,
 839         .free = gic_irq_domain_free,
 840 };
 841
 842 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
 843 {
 844         void __iomem *dist_base;
 845         struct redist_region *rdist_regs;
 846         u64 redist_stride;
 847         u32 nr_redist_regions;
 848         u32 typer;
 849         u32 reg;
 850         int gic_irqs;
 851         int err;
 852         int i;
 853
 854         dist_base = of_iomap(node, 0);
 855         if (!dist_base) {
 856                 pr_err("%s: unable to map gic dist registers\n",
 857                         node->full_name);
 858                 return -ENXIO;
 859         }
 860
 861         reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
 862         if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
 863                 pr_err("%s: no distributor detected, giving up\n",
 864                         node->full_name);
 865                 err = -ENODEV;
 866                 goto out_unmap_dist;
 867         }
 868
 869         if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
 870                 nr_redist_regions = 1;
 871
 872         rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
 873         if (!rdist_regs) {
 874                 err = -ENOMEM;
 875                 goto out_unmap_dist;
 876         }
 877
 878         for (i = 0; i < nr_redist_regions; i++) {
 879                 struct resource res;
 880                 int ret;
 881
 882                 ret = of_address_to_resource(node, 1 + i, &res);
 883                 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
 884                 if (ret || !rdist_regs[i].redist_base) {
 885                         pr_err("%s: couldn't map region %d\n",
 886                                node->full_name, i);
 887                         err = -ENODEV;
 888                         goto out_unmap_rdist;
 889                 }
 890                 rdist_regs[i].phys_base = res.start;
 891         }
 892
 893         if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
 894                 redist_stride = 0;
 895
 896         if (!is_hyp_mode_available())
 897                 static_key_slow_dec(&supports_deactivate);
 898
 899         if (static_key_true(&supports_deactivate))
 900                 pr_info("GIC: Using split EOI/Deactivate mode\n");
 901
 902         gic_data.dist_base = dist_base;
 903         gic_data.redist_regions = rdist_regs;
 904         gic_data.nr_redist_regions = nr_redist_regions;
 905         gic_data.redist_stride = redist_stride;
 906
 907         /*
 908          * Find out how many interrupts are supported.
 909          * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
 910          */
 911         typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
 912         gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
 913         gic_irqs = GICD_TYPER_IRQS(typer);
 914         if (gic_irqs > 1020)
 915                 gic_irqs = 1020;
 916         gic_data.irq_nr = gic_irqs;
 917
 918         gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
 919                                               &gic_data);
 920         gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
 921
 922         if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
 923                 err = -ENOMEM;
 924                 goto out_free;
 925         }
 926
 927         set_handle_irq(gic_handle_irq);
 928
 929         if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
 930                 its_init(node, &gic_data.rdists, gic_data.domain);
 931
 932         gic_smp_init();
 933         gic_dist_init();
 934         gic_cpu_init();
 935         gic_cpu_pm_init();
 936
 937         return 0;
 938
 939 out_free:
 940         if (gic_data.domain)
 941                 irq_domain_remove(gic_data.domain);
 942         free_percpu(gic_data.rdists.rdist);
 943 out_unmap_rdist:
 944         for (i = 0; i < nr_redist_regions; i++)
 945                 if (rdist_regs[i].redist_base)
 946                         iounmap(rdist_regs[i].redist_base);
 947         kfree(rdist_regs);
 948 out_unmap_dist:
 949         iounmap(dist_base);
 950         return err;
 951 }
 952
 953 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);