drivers/media/platform/coda/coda-bit.c

   1 /*
   2  * Coda multi-standard codec IP - BIT processor functions
   3  *
   4  * Copyright (C) 2012 Vista Silicon S.L.
   5  *    Javier Martin, <javier.martin@vista-silicon.com>
   6  *    Xavier Duret
   7  * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/irqreturn.h>
  17 #include <linux/kernel.h>
  18 #include <linux/log2.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22 #include <linux/videodev2.h>
  23
  24 #include <media/v4l2-common.h>
  25 #include <media/v4l2-ctrls.h>
  26 #include <media/v4l2-fh.h>
  27 #include <media/v4l2-mem2mem.h>
  28 #include <media/videobuf2-core.h>
  29 #include <media/videobuf2-dma-contig.h>
  30 #include <media/videobuf2-vmalloc.h>
  31
  32 #include "coda.h"
  33 #define CREATE_TRACE_POINTS
  34 #include "trace.h"
  35
  36 #define CODA_PARA_BUF_SIZE      (10 * 1024)
  37 #define CODA7_PS_BUF_SIZE       0x28000
  38 #define CODA9_PS_SAVE_SIZE      (512 * 1024)
  39
  40 #define CODA_DEFAULT_GAMMA      4096
  41 #define CODA9_DEFAULT_GAMMA     24576   /* 0.75 * 32768 */
  42
  43 static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
  44
  45 static inline int coda_is_initialized(struct coda_dev *dev)
  46 {
  47         return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  48 }
  49
  50 static inline unsigned long coda_isbusy(struct coda_dev *dev)
  51 {
  52         return coda_read(dev, CODA_REG_BIT_BUSY);
  53 }
  54
  55 static int coda_wait_timeout(struct coda_dev *dev)
  56 {
  57         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  58
  59         while (coda_isbusy(dev)) {
  60                 if (time_after(jiffies, timeout))
  61                         return -ETIMEDOUT;
  62         }
  63         return 0;
  64 }
  65
  66 static void coda_command_async(struct coda_ctx *ctx, int cmd)
  67 {
  68         struct coda_dev *dev = ctx->dev;
  69
  70         if (dev->devtype->product == CODA_960 ||
  71             dev->devtype->product == CODA_7541) {
  72                 /* Restore context related registers to CODA */
  73                 coda_write(dev, ctx->bit_stream_param,
  74                                 CODA_REG_BIT_BIT_STREAM_PARAM);
  75                 coda_write(dev, ctx->frm_dis_flg,
  76                                 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  77                 coda_write(dev, ctx->frame_mem_ctrl,
  78                                 CODA_REG_BIT_FRAME_MEM_CTRL);
  79                 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  80         }
  81
  82         if (dev->devtype->product == CODA_960) {
  83                 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  84                 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  85         }
  86
  87         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  88
  89         coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  90         coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  91         coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  92
  93         trace_coda_bit_run(ctx, cmd);
  94
  95         coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  96 }
  97
  98 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  99 {
 100         struct coda_dev *dev = ctx->dev;
 101         int ret;
 102
 103         coda_command_async(ctx, cmd);
 104         ret = coda_wait_timeout(dev);
 105         trace_coda_bit_done(ctx);
 106
 107         return ret;
 108 }
 109
 110 int coda_hw_reset(struct coda_ctx *ctx)
 111 {
 112         struct coda_dev *dev = ctx->dev;
 113         unsigned long timeout;
 114         unsigned int idx;
 115         int ret;
 116
 117         if (!dev->rstc)
 118                 return -ENOENT;
 119
 120         idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
 121
 122         if (dev->devtype->product == CODA_960) {
 123                 timeout = jiffies + msecs_to_jiffies(100);
 124                 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
 125                 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
 126                         if (time_after(jiffies, timeout))
 127                                 return -ETIME;
 128                         cpu_relax();
 129                 }
 130         }
 131
 132         ret = reset_control_reset(dev->rstc);
 133         if (ret < 0)
 134                 return ret;
 135
 136         if (dev->devtype->product == CODA_960)
 137                 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
 138         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
 139         coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
 140         ret = coda_wait_timeout(dev);
 141         coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
 142
 143         return ret;
 144 }
 145
 146 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
 147 {
 148         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 149         struct coda_dev *dev = ctx->dev;
 150         u32 rd_ptr;
 151
 152         rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 153         kfifo->out = (kfifo->in & ~kfifo->mask) |
 154                       (rd_ptr - ctx->bitstream.paddr);
 155         if (kfifo->out > kfifo->in)
 156                 kfifo->out -= kfifo->mask + 1;
 157 }
 158
 159 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
 160 {
 161         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 162         struct coda_dev *dev = ctx->dev;
 163         u32 rd_ptr, wr_ptr;
 164
 165         rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
 166         coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 167         wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
 168         coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 169 }
 170
 171 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
 172 {
 173         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 174         struct coda_dev *dev = ctx->dev;
 175         u32 wr_ptr;
 176
 177         wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
 178         coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 179 }
 180
 181 static int coda_bitstream_queue(struct coda_ctx *ctx,
 182                                 struct vb2_buffer *src_buf)
 183 {
 184         u32 src_size = vb2_get_plane_payload(src_buf, 0);
 185         u32 n;
 186
 187         n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0),
 188                      src_size);
 189         if (n < src_size)
 190                 return -ENOSPC;
 191
 192         src_buf->v4l2_buf.sequence = ctx->qsequence++;
 193
 194         return 0;
 195 }
 196
 197 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
 198                                      struct vb2_buffer *src_buf)
 199 {
 200         int ret;
 201
 202         if (coda_get_bitstream_payload(ctx) +
 203             vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
 204                 return false;
 205
 206         if (vb2_plane_vaddr(src_buf, 0) == NULL) {
 207                 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
 208                 return true;
 209         }
 210
 211         ret = coda_bitstream_queue(ctx, src_buf);
 212         if (ret < 0) {
 213                 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
 214                 return false;
 215         }
 216         /* Sync read pointer to device */
 217         if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
 218                 coda_kfifo_sync_to_device_write(ctx);
 219
 220         ctx->hold = false;
 221
 222         return true;
 223 }
 224
 225 void coda_fill_bitstream(struct coda_ctx *ctx, bool streaming)
 226 {
 227         struct vb2_buffer *src_buf;
 228         struct coda_buffer_meta *meta;
 229         unsigned long flags;
 230         u32 start;
 231
 232         if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
 233                 return;
 234
 235         while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
 236                 /*
 237                  * Only queue a single JPEG into the bitstream buffer, except
 238                  * to increase payload over 512 bytes or if in hold state.
 239                  */
 240                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
 241                     (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
 242                         break;
 243
 244                 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
 245
 246                 /* Drop frames that do not start/end with a SOI/EOI markers */
 247                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
 248                     !coda_jpeg_check_buffer(ctx, src_buf)) {
 249                         v4l2_err(&ctx->dev->v4l2_dev,
 250                                  "dropping invalid JPEG frame %d\n",
 251                                  ctx->qsequence);
 252                         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 253                         v4l2_m2m_buf_done(src_buf, streaming ?
 254                                           VB2_BUF_STATE_ERROR :
 255                                           VB2_BUF_STATE_QUEUED);
 256                         continue;
 257                 }
 258
 259                 /* Dump empty buffers */
 260                 if (!vb2_get_plane_payload(src_buf, 0)) {
 261                         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 262                         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
 263                         continue;
 264                 }
 265
 266                 /* Buffer start position */
 267                 start = ctx->bitstream_fifo.kfifo.in &
 268                         ctx->bitstream_fifo.kfifo.mask;
 269
 270                 if (coda_bitstream_try_queue(ctx, src_buf)) {
 271                         /*
 272                          * Source buffer is queued in the bitstream ringbuffer;
 273                          * queue the timestamp and mark source buffer as done
 274                          */
 275                         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 276
 277                         meta = kmalloc(sizeof(*meta), GFP_KERNEL);
 278                         if (meta) {
 279                                 meta->sequence = src_buf->v4l2_buf.sequence;
 280                                 meta->timecode = src_buf->v4l2_buf.timecode;
 281                                 meta->timestamp = src_buf->v4l2_buf.timestamp;
 282                                 meta->start = start;
 283                                 meta->end = ctx->bitstream_fifo.kfifo.in &
 284                                             ctx->bitstream_fifo.kfifo.mask;
 285                                 spin_lock_irqsave(&ctx->buffer_meta_lock,
 286                                                   flags);
 287                                 list_add_tail(&meta->list,
 288                                               &ctx->buffer_meta_list);
 289                                 ctx->num_metas++;
 290                                 spin_unlock_irqrestore(&ctx->buffer_meta_lock,
 291                                                        flags);
 292
 293                                 trace_coda_bit_queue(ctx, src_buf, meta);
 294                         }
 295
 296                         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
 297                 } else {
 298                         break;
 299                 }
 300         }
 301 }
 302
 303 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
 304 {
 305         struct coda_dev *dev = ctx->dev;
 306
 307         ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
 308
 309         /* If this context is currently running, update the hardware flag */
 310         if ((dev->devtype->product == CODA_960) &&
 311             coda_isbusy(dev) &&
 312             (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
 313                 coda_write(dev, ctx->bit_stream_param,
 314                            CODA_REG_BIT_BIT_STREAM_PARAM);
 315         }
 316 }
 317
 318 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
 319 {
 320         struct coda_dev *dev = ctx->dev;
 321         u32 *p = ctx->parabuf.vaddr;
 322
 323         if (dev->devtype->product == CODA_DX6)
 324                 p[index] = value;
 325         else
 326                 p[index ^ 1] = value;
 327 }
 328
 329 static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
 330                                          struct coda_aux_buf *buf, size_t size,
 331                                          const char *name)
 332 {
 333         return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
 334 }
 335
 336
 337 static void coda_free_framebuffers(struct coda_ctx *ctx)
 338 {
 339         int i;
 340
 341         for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
 342                 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
 343 }
 344
 345 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
 346                                    struct coda_q_data *q_data, u32 fourcc)
 347 {
 348         struct coda_dev *dev = ctx->dev;
 349         int width, height;
 350         int ysize;
 351         int ret;
 352         int i;
 353
 354         if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
 355              ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
 356                 width = round_up(q_data->width, 16);
 357                 height = round_up(q_data->height, 16);
 358         } else {
 359                 width = round_up(q_data->width, 8);
 360                 height = q_data->height;
 361         }
 362         ysize = width * height;
 363
 364         /* Allocate frame buffers */
 365         for (i = 0; i < ctx->num_internal_frames; i++) {
 366                 size_t size;
 367                 char *name;
 368
 369                 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
 370                         size = round_up(ysize, 4096) + ysize / 2;
 371                 else
 372                         size = ysize + ysize / 2;
 373                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
 374                     dev->devtype->product != CODA_DX6)
 375                         size += ysize / 4;
 376                 name = kasprintf(GFP_KERNEL, "fb%d", i);
 377                 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
 378                                              size, name);
 379                 kfree(name);
 380                 if (ret < 0) {
 381                         coda_free_framebuffers(ctx);
 382                         return ret;
 383                 }
 384         }
 385
 386         /* Register frame buffers in the parameter buffer */
 387         for (i = 0; i < ctx->num_internal_frames; i++) {
 388                 u32 y, cb, cr;
 389
 390                 /* Start addresses of Y, Cb, Cr planes */
 391                 y = ctx->internal_frames[i].paddr;
 392                 cb = y + ysize;
 393                 cr = y + ysize + ysize/4;
 394                 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
 395                         cb = round_up(cb, 4096);
 396                         cr = 0;
 397                         /* Packed 20-bit MSB of base addresses */
 398                         /* YYYYYCCC, CCyyyyyc, cccc.... */
 399                         y = (y & 0xfffff000) | cb >> 20;
 400                         cb = (cb & 0x000ff000) << 12;
 401                 }
 402                 coda_parabuf_write(ctx, i * 3 + 0, y);
 403                 coda_parabuf_write(ctx, i * 3 + 1, cb);
 404                 coda_parabuf_write(ctx, i * 3 + 2, cr);
 405
 406                 /* mvcol buffer for h.264 */
 407                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
 408                     dev->devtype->product != CODA_DX6)
 409                         coda_parabuf_write(ctx, 96 + i,
 410                                            ctx->internal_frames[i].paddr +
 411                                            ysize + ysize/4 + ysize/4);
 412         }
 413
 414         /* mvcol buffer for mpeg4 */
 415         if ((dev->devtype->product != CODA_DX6) &&
 416             (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
 417                 coda_parabuf_write(ctx, 97, ctx->internal_frames[0].paddr +
 418                                             ysize + ysize/4 + ysize/4);
 419
 420         return 0;
 421 }
 422
 423 static void coda_free_context_buffers(struct coda_ctx *ctx)
 424 {
 425         struct coda_dev *dev = ctx->dev;
 426
 427         coda_free_aux_buf(dev, &ctx->slicebuf);
 428         coda_free_aux_buf(dev, &ctx->psbuf);
 429         if (dev->devtype->product != CODA_DX6)
 430                 coda_free_aux_buf(dev, &ctx->workbuf);
 431         coda_free_aux_buf(dev, &ctx->parabuf);
 432 }
 433
 434 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
 435                                       struct coda_q_data *q_data)
 436 {
 437         struct coda_dev *dev = ctx->dev;
 438         size_t size;
 439         int ret;
 440
 441         if (!ctx->parabuf.vaddr) {
 442                 ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
 443                                              CODA_PARA_BUF_SIZE, "parabuf");
 444                 if (ret < 0)
 445                         return ret;
 446         }
 447
 448         if (dev->devtype->product == CODA_DX6)
 449                 return 0;
 450
 451         if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
 452                 /* worst case slice size */
 453                 size = (DIV_ROUND_UP(q_data->width, 16) *
 454                         DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
 455                 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
 456                                              "slicebuf");
 457                 if (ret < 0)
 458                         goto err;
 459         }
 460
 461         if (!ctx->psbuf.vaddr && dev->devtype->product == CODA_7541) {
 462                 ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
 463                                              CODA7_PS_BUF_SIZE, "psbuf");
 464                 if (ret < 0)
 465                         goto err;
 466         }
 467
 468         if (!ctx->workbuf.vaddr) {
 469                 size = dev->devtype->workbuf_size;
 470                 if (dev->devtype->product == CODA_960 &&
 471                     q_data->fourcc == V4L2_PIX_FMT_H264)
 472                         size += CODA9_PS_SAVE_SIZE;
 473                 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
 474                                              "workbuf");
 475                 if (ret < 0)
 476                         goto err;
 477         }
 478
 479         return 0;
 480
 481 err:
 482         coda_free_context_buffers(ctx);
 483         return ret;
 484 }
 485
 486 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
 487                               int header_code, u8 *header, int *size)
 488 {
 489         struct coda_dev *dev = ctx->dev;
 490         size_t bufsize;
 491         int ret;
 492         int i;
 493
 494         if (dev->devtype->product == CODA_960)
 495                 memset(vb2_plane_vaddr(buf, 0), 0, 64);
 496
 497         coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
 498                    CODA_CMD_ENC_HEADER_BB_START);
 499         bufsize = vb2_plane_size(buf, 0);
 500         if (dev->devtype->product == CODA_960)
 501                 bufsize /= 1024;
 502         coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
 503         coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
 504         ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
 505         if (ret < 0) {
 506                 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
 507                 return ret;
 508         }
 509
 510         if (dev->devtype->product == CODA_960) {
 511                 for (i = 63; i > 0; i--)
 512                         if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
 513                                 break;
 514                 *size = i + 1;
 515         } else {
 516                 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
 517                         coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
 518         }
 519         memcpy(header, vb2_plane_vaddr(buf, 0), *size);
 520
 521         return 0;
 522 }
 523
 524 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
 525 {
 526         phys_addr_t ret;
 527
 528         size = round_up(size, 1024);
 529         if (size > iram->remaining)
 530                 return 0;
 531         iram->remaining -= size;
 532
 533         ret = iram->next_paddr;
 534         iram->next_paddr += size;
 535
 536         return ret;
 537 }
 538
 539 static void coda_setup_iram(struct coda_ctx *ctx)
 540 {
 541         struct coda_iram_info *iram_info = &ctx->iram_info;
 542         struct coda_dev *dev = ctx->dev;
 543         int w64, w128;
 544         int mb_width;
 545         int dbk_bits;
 546         int bit_bits;
 547         int ip_bits;
 548
 549         memset(iram_info, 0, sizeof(*iram_info));
 550         iram_info->next_paddr = dev->iram.paddr;
 551         iram_info->remaining = dev->iram.size;
 552
 553         if (!dev->iram.vaddr)
 554                 return;
 555
 556         switch (dev->devtype->product) {
 557         case CODA_7541:
 558                 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
 559                 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
 560                 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
 561                 break;
 562         case CODA_960:
 563                 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
 564                 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
 565                 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
 566                 break;
 567         default: /* CODA_DX6 */
 568                 return;
 569         }
 570
 571         if (ctx->inst_type == CODA_INST_ENCODER) {
 572                 struct coda_q_data *q_data_src;
 573
 574                 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 575                 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
 576                 w128 = mb_width * 128;
 577                 w64 = mb_width * 64;
 578
 579                 /* Prioritize in case IRAM is too small for everything */
 580                 if (dev->devtype->product == CODA_7541) {
 581                         iram_info->search_ram_size = round_up(mb_width * 16 *
 582                                                               36 + 2048, 1024);
 583                         iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
 584                                                 iram_info->search_ram_size);
 585                         if (!iram_info->search_ram_paddr) {
 586                                 pr_err("IRAM is smaller than the search ram size\n");
 587                                 goto out;
 588                         }
 589                         iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
 590                                                    CODA7_USE_ME_ENABLE;
 591                 }
 592
 593                 /* Only H.264BP and H.263P3 are considered */
 594                 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
 595                 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
 596                 if (!iram_info->buf_dbk_c_use)
 597                         goto out;
 598                 iram_info->axi_sram_use |= dbk_bits;
 599
 600                 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
 601                 if (!iram_info->buf_bit_use)
 602                         goto out;
 603                 iram_info->axi_sram_use |= bit_bits;
 604
 605                 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
 606                 if (!iram_info->buf_ip_ac_dc_use)
 607                         goto out;
 608                 iram_info->axi_sram_use |= ip_bits;
 609
 610                 /* OVL and BTP disabled for encoder */
 611         } else if (ctx->inst_type == CODA_INST_DECODER) {
 612                 struct coda_q_data *q_data_dst;
 613
 614                 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
 615                 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
 616                 w128 = mb_width * 128;
 617
 618                 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
 619                 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
 620                 if (!iram_info->buf_dbk_c_use)
 621                         goto out;
 622                 iram_info->axi_sram_use |= dbk_bits;
 623
 624                 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
 625                 if (!iram_info->buf_bit_use)
 626                         goto out;
 627                 iram_info->axi_sram_use |= bit_bits;
 628
 629                 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
 630                 if (!iram_info->buf_ip_ac_dc_use)
 631                         goto out;
 632                 iram_info->axi_sram_use |= ip_bits;
 633
 634                 /* OVL and BTP unused as there is no VC1 support yet */
 635         }
 636
 637 out:
 638         if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
 639                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 640                          "IRAM smaller than needed\n");
 641
 642         if (dev->devtype->product == CODA_7541) {
 643                 /* TODO - Enabling these causes picture errors on CODA7541 */
 644                 if (ctx->inst_type == CODA_INST_DECODER) {
 645                         /* fw 1.4.50 */
 646                         iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
 647                                                      CODA7_USE_IP_ENABLE);
 648                 } else {
 649                         /* fw 13.4.29 */
 650                         iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
 651                                                      CODA7_USE_HOST_DBK_ENABLE |
 652                                                      CODA7_USE_IP_ENABLE |
 653                                                      CODA7_USE_DBK_ENABLE);
 654                 }
 655         }
 656 }
 657
 658 static u32 coda_supported_firmwares[] = {
 659         CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
 660         CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
 661         CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
 662 };
 663
 664 static bool coda_firmware_supported(u32 vernum)
 665 {
 666         int i;
 667
 668         for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
 669                 if (vernum == coda_supported_firmwares[i])
 670                         return true;
 671         return false;
 672 }
 673
 674 int coda_check_firmware(struct coda_dev *dev)
 675 {
 676         u16 product, major, minor, release;
 677         u32 data;
 678         int ret;
 679
 680         ret = clk_prepare_enable(dev->clk_per);
 681         if (ret)
 682                 goto err_clk_per;
 683
 684         ret = clk_prepare_enable(dev->clk_ahb);
 685         if (ret)
 686                 goto err_clk_ahb;
 687
 688         coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
 689         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
 690         coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
 691         coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
 692         coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
 693         if (coda_wait_timeout(dev)) {
 694                 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
 695                 ret = -EIO;
 696                 goto err_run_cmd;
 697         }
 698
 699         if (dev->devtype->product == CODA_960) {
 700                 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
 701                 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
 702                           data);
 703         }
 704
 705         /* Check we are compatible with the loaded firmware */
 706         data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
 707         product = CODA_FIRMWARE_PRODUCT(data);
 708         major = CODA_FIRMWARE_MAJOR(data);
 709         minor = CODA_FIRMWARE_MINOR(data);
 710         release = CODA_FIRMWARE_RELEASE(data);
 711
 712         clk_disable_unprepare(dev->clk_per);
 713         clk_disable_unprepare(dev->clk_ahb);
 714
 715         if (product != dev->devtype->product) {
 716                 v4l2_err(&dev->v4l2_dev,
 717                          "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
 718                          coda_product_name(dev->devtype->product),
 719                          coda_product_name(product), major, minor, release);
 720                 return -EINVAL;
 721         }
 722
 723         v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
 724                   coda_product_name(product));
 725
 726         if (coda_firmware_supported(data)) {
 727                 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
 728                           major, minor, release);
 729         } else {
 730                 v4l2_warn(&dev->v4l2_dev,
 731                           "Unsupported firmware version: %u.%u.%u\n",
 732                           major, minor, release);
 733         }
 734
 735         return 0;
 736
 737 err_run_cmd:
 738         clk_disable_unprepare(dev->clk_ahb);
 739 err_clk_ahb:
 740         clk_disable_unprepare(dev->clk_per);
 741 err_clk_per:
 742         return ret;
 743 }
 744
 745 static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
 746 {
 747         u32 cache_size, cache_config;
 748
 749         if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
 750                 /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
 751                 cache_size = 0x20262024;
 752                 cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
 753         } else {
 754                 /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
 755                 cache_size = 0x02440243;
 756                 cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
 757         }
 758         coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
 759         if (fourcc == V4L2_PIX_FMT_NV12) {
 760                 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
 761                                 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
 762                                 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
 763         } else {
 764                 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
 765                                 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
 766                                 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
 767         }
 768         coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
 769 }
 770
 771 /*
 772  * Encoder context operations
 773  */
 774
 775 static int coda_encoder_reqbufs(struct coda_ctx *ctx,
 776                                 struct v4l2_requestbuffers *rb)
 777 {
 778         struct coda_q_data *q_data_src;
 779         int ret;
 780
 781         if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
 782                 return 0;
 783
 784         if (rb->count) {
 785                 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 786                 ret = coda_alloc_context_buffers(ctx, q_data_src);
 787                 if (ret < 0)
 788                         return ret;
 789         } else {
 790                 coda_free_context_buffers(ctx);
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int coda_start_encoding(struct coda_ctx *ctx)
 797 {
 798         struct coda_dev *dev = ctx->dev;
 799         struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
 800         struct coda_q_data *q_data_src, *q_data_dst;
 801         u32 bitstream_buf, bitstream_size;
 802         struct vb2_buffer *buf;
 803         int gamma, ret, value;
 804         u32 dst_fourcc;
 805         int num_fb;
 806         u32 stride;
 807
 808         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 809         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
 810         dst_fourcc = q_data_dst->fourcc;
 811
 812         buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
 813         bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
 814         bitstream_size = q_data_dst->sizeimage;
 815
 816         if (!coda_is_initialized(dev)) {
 817                 v4l2_err(v4l2_dev, "coda is not initialized.\n");
 818                 return -EFAULT;
 819         }
 820
 821         if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
 822                 if (!ctx->params.jpeg_qmat_tab[0])
 823                         ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
 824                 if (!ctx->params.jpeg_qmat_tab[1])
 825                         ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
 826                 coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
 827         }
 828
 829         mutex_lock(&dev->coda_mutex);
 830
 831         coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
 832         coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 833         coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 834         switch (dev->devtype->product) {
 835         case CODA_DX6:
 836                 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
 837                         CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
 838                 break;
 839         case CODA_960:
 840                 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
 841                 /* fallthrough */
 842         case CODA_7541:
 843                 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
 844                         CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
 845                 break;
 846         }
 847
 848         ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
 849                                  CODA9_FRAME_TILED2LINEAR);
 850         if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
 851                 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
 852         if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
 853                 ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
 854         coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
 855
 856         if (dev->devtype->product == CODA_DX6) {
 857                 /* Configure the coda */
 858                 coda_write(dev, dev->iram.paddr,
 859                            CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
 860         }
 861
 862         /* Could set rotation here if needed */
 863         value = 0;
 864         switch (dev->devtype->product) {
 865         case CODA_DX6:
 866                 value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
 867                         << CODADX6_PICWIDTH_OFFSET;
 868                 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
 869                          << CODA_PICHEIGHT_OFFSET;
 870                 break;
 871         case CODA_7541:
 872                 if (dst_fourcc == V4L2_PIX_FMT_H264) {
 873                         value = (round_up(q_data_src->width, 16) &
 874                                  CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
 875                         value |= (round_up(q_data_src->height, 16) &
 876                                  CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
 877                         break;
 878                 }
 879                 /* fallthrough */
 880         case CODA_960:
 881                 value = (q_data_src->width & CODA7_PICWIDTH_MASK)
 882                         << CODA7_PICWIDTH_OFFSET;
 883                 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
 884                          << CODA_PICHEIGHT_OFFSET;
 885         }
 886         coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
 887         if (dst_fourcc == V4L2_PIX_FMT_JPEG)
 888                 ctx->params.framerate = 0;
 889         coda_write(dev, ctx->params.framerate,
 890                    CODA_CMD_ENC_SEQ_SRC_F_RATE);
 891
 892         ctx->params.codec_mode = ctx->codec->mode;
 893         switch (dst_fourcc) {
 894         case V4L2_PIX_FMT_MPEG4:
 895                 if (dev->devtype->product == CODA_960)
 896                         coda_write(dev, CODA9_STD_MPEG4,
 897                                    CODA_CMD_ENC_SEQ_COD_STD);
 898                 else
 899                         coda_write(dev, CODA_STD_MPEG4,
 900                                    CODA_CMD_ENC_SEQ_COD_STD);
 901                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
 902                 break;
 903         case V4L2_PIX_FMT_H264:
 904                 if (dev->devtype->product == CODA_960)
 905                         coda_write(dev, CODA9_STD_H264,
 906                                    CODA_CMD_ENC_SEQ_COD_STD);
 907                 else
 908                         coda_write(dev, CODA_STD_H264,
 909                                    CODA_CMD_ENC_SEQ_COD_STD);
 910                 if (ctx->params.h264_deblk_enabled) {
 911                         value = ((ctx->params.h264_deblk_alpha &
 912                                   CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
 913                                  CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
 914                                 ((ctx->params.h264_deblk_beta &
 915                                   CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
 916                                  CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
 917                 } else {
 918                         value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
 919                 }
 920                 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
 921                 break;
 922         case V4L2_PIX_FMT_JPEG:
 923                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
 924                 coda_write(dev, ctx->params.jpeg_restart_interval,
 925                                 CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
 926                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
 927                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
 928                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
 929
 930                 coda_jpeg_write_tables(ctx);
 931                 break;
 932         default:
 933                 v4l2_err(v4l2_dev,
 934                          "dst format (0x%08x) invalid.\n", dst_fourcc);
 935                 ret = -EINVAL;
 936                 goto out;
 937         }
 938
 939         /*
 940          * slice mode and GOP size registers are used for thumb size/offset
 941          * in JPEG mode
 942          */
 943         if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
 944                 switch (ctx->params.slice_mode) {
 945                 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
 946                         value = 0;
 947                         break;
 948                 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
 949                         value  = (ctx->params.slice_max_mb &
 950                                   CODA_SLICING_SIZE_MASK)
 951                                  << CODA_SLICING_SIZE_OFFSET;
 952                         value |= (1 & CODA_SLICING_UNIT_MASK)
 953                                  << CODA_SLICING_UNIT_OFFSET;
 954                         value |=  1 & CODA_SLICING_MODE_MASK;
 955                         break;
 956                 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
 957                         value  = (ctx->params.slice_max_bits &
 958                                   CODA_SLICING_SIZE_MASK)
 959                                  << CODA_SLICING_SIZE_OFFSET;
 960                         value |= (0 & CODA_SLICING_UNIT_MASK)
 961                                  << CODA_SLICING_UNIT_OFFSET;
 962                         value |=  1 & CODA_SLICING_MODE_MASK;
 963                         break;
 964                 }
 965                 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
 966                 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
 967                 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
 968         }
 969
 970         if (ctx->params.bitrate) {
 971                 /* Rate control enabled */
 972                 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
 973                         << CODA_RATECONTROL_BITRATE_OFFSET;
 974                 value |=  1 & CODA_RATECONTROL_ENABLE_MASK;
 975                 value |= (ctx->params.vbv_delay &
 976                           CODA_RATECONTROL_INITIALDELAY_MASK)
 977                          << CODA_RATECONTROL_INITIALDELAY_OFFSET;
 978                 if (dev->devtype->product == CODA_960)
 979                         value |= BIT(31); /* disable autoskip */
 980         } else {
 981                 value = 0;
 982         }
 983         coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
 984
 985         coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
 986         coda_write(dev, ctx->params.intra_refresh,
 987                    CODA_CMD_ENC_SEQ_INTRA_REFRESH);
 988
 989         coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
 990         coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
 991
 992
 993         value = 0;
 994         if (dev->devtype->product == CODA_960)
 995                 gamma = CODA9_DEFAULT_GAMMA;
 996         else
 997                 gamma = CODA_DEFAULT_GAMMA;
 998         if (gamma > 0) {
 999                 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
1000                            CODA_CMD_ENC_SEQ_RC_GAMMA);
1001         }
1002
1003         if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
1004                 coda_write(dev,
1005                            ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
1006                            ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
1007                            CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
1008         }
1009         if (dev->devtype->product == CODA_960) {
1010                 if (ctx->params.h264_max_qp)
1011                         value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
1012                 if (CODA_DEFAULT_GAMMA > 0)
1013                         value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
1014         } else {
1015                 if (CODA_DEFAULT_GAMMA > 0) {
1016                         if (dev->devtype->product == CODA_DX6)
1017                                 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
1018                         else
1019                                 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
1020                 }
1021                 if (ctx->params.h264_min_qp)
1022                         value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
1023                 if (ctx->params.h264_max_qp)
1024                         value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
1025         }
1026         coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1027
1028         coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
1029
1030         coda_setup_iram(ctx);
1031
1032         if (dst_fourcc == V4L2_PIX_FMT_H264) {
1033                 switch (dev->devtype->product) {
1034                 case CODA_DX6:
1035                         value = FMO_SLICE_SAVE_BUF_SIZE << 7;
1036                         coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1037                         break;
1038                 case CODA_7541:
1039                         coda_write(dev, ctx->iram_info.search_ram_paddr,
1040                                         CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1041                         coda_write(dev, ctx->iram_info.search_ram_size,
1042                                         CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1043                         break;
1044                 case CODA_960:
1045                         coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
1046                         coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
1047                 }
1048         }
1049
1050         ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1051         if (ret < 0) {
1052                 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1053                 goto out;
1054         }
1055
1056         if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
1057                 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
1058                 ret = -EFAULT;
1059                 goto out;
1060         }
1061         ctx->initialized = 1;
1062
1063         if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
1064                 if (dev->devtype->product == CODA_960)
1065                         ctx->num_internal_frames = 4;
1066                 else
1067                         ctx->num_internal_frames = 2;
1068                 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
1069                 if (ret < 0) {
1070                         v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
1071                         goto out;
1072                 }
1073                 num_fb = 2;
1074                 stride = q_data_src->bytesperline;
1075         } else {
1076                 ctx->num_internal_frames = 0;
1077                 num_fb = 0;
1078                 stride = 0;
1079         }
1080         coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
1081         coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
1082
1083         if (dev->devtype->product == CODA_7541) {
1084                 coda_write(dev, q_data_src->bytesperline,
1085                                 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1086         }
1087         if (dev->devtype->product != CODA_DX6) {
1088                 coda_write(dev, ctx->iram_info.buf_bit_use,
1089                                 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1090                 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1091                                 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1092                 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1093                                 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1094                 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1095                                 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1096                 coda_write(dev, ctx->iram_info.buf_ovl_use,
1097                                 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1098                 if (dev->devtype->product == CODA_960) {
1099                         coda_write(dev, ctx->iram_info.buf_btp_use,
1100                                         CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1101
1102                         coda9_set_frame_cache(ctx, q_data_src->fourcc);
1103
1104                         /* FIXME */
1105                         coda_write(dev, ctx->internal_frames[2].paddr,
1106                                    CODA9_CMD_SET_FRAME_SUBSAMP_A);
1107                         coda_write(dev, ctx->internal_frames[3].paddr,
1108                                    CODA9_CMD_SET_FRAME_SUBSAMP_B);
1109                 }
1110         }
1111
1112         ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
1113         if (ret < 0) {
1114                 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1115                 goto out;
1116         }
1117
1118         /* Save stream headers */
1119         buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1120         switch (dst_fourcc) {
1121         case V4L2_PIX_FMT_H264:
1122                 /*
1123                  * Get SPS in the first frame and copy it to an
1124                  * intermediate buffer.
1125                  */
1126                 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
1127                                          &ctx->vpu_header[0][0],
1128                                          &ctx->vpu_header_size[0]);
1129                 if (ret < 0)
1130                         goto out;
1131
1132                 /*
1133                  * Get PPS in the first frame and copy it to an
1134                  * intermediate buffer.
1135                  */
1136                 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
1137                                          &ctx->vpu_header[1][0],
1138                                          &ctx->vpu_header_size[1]);
1139                 if (ret < 0)
1140                         goto out;
1141
1142                 /*
1143                  * Length of H.264 headers is variable and thus it might not be
1144                  * aligned for the coda to append the encoded frame. In that is
1145                  * the case a filler NAL must be added to header 2.
1146                  */
1147                 ctx->vpu_header_size[2] = coda_h264_padding(
1148                                         (ctx->vpu_header_size[0] +
1149                                          ctx->vpu_header_size[1]),
1150                                          ctx->vpu_header[2]);
1151                 break;
1152         case V4L2_PIX_FMT_MPEG4:
1153                 /*
1154                  * Get VOS in the first frame and copy it to an
1155                  * intermediate buffer
1156                  */
1157                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1158                                          &ctx->vpu_header[0][0],
1159                                          &ctx->vpu_header_size[0]);
1160                 if (ret < 0)
1161                         goto out;
1162
1163                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1164                                          &ctx->vpu_header[1][0],
1165                                          &ctx->vpu_header_size[1]);
1166                 if (ret < 0)
1167                         goto out;
1168
1169                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1170                                          &ctx->vpu_header[2][0],
1171                                          &ctx->vpu_header_size[2]);
1172                 if (ret < 0)
1173                         goto out;
1174                 break;
1175         default:
1176                 /* No more formats need to save headers at the moment */
1177                 break;
1178         }
1179
1180 out:
1181         mutex_unlock(&dev->coda_mutex);
1182         return ret;
1183 }
1184
1185 static int coda_prepare_encode(struct coda_ctx *ctx)
1186 {
1187         struct coda_q_data *q_data_src, *q_data_dst;
1188         struct vb2_buffer *src_buf, *dst_buf;
1189         struct coda_dev *dev = ctx->dev;
1190         int force_ipicture;
1191         int quant_param = 0;
1192         u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1193         u32 rot_mode = 0;
1194         u32 dst_fourcc;
1195         u32 reg;
1196
1197         src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1198         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1199         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1200         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1201         dst_fourcc = q_data_dst->fourcc;
1202
1203         src_buf->v4l2_buf.sequence = ctx->osequence;
1204         dst_buf->v4l2_buf.sequence = ctx->osequence;
1205         ctx->osequence++;
1206
1207         /*
1208          * Workaround coda firmware BUG that only marks the first
1209          * frame as IDR. This is a problem for some decoders that can't
1210          * recover when a frame is lost.
1211          */
1212         if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
1213                 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1214                 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1215         } else {
1216                 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1217                 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1218         }
1219
1220         if (dev->devtype->product == CODA_960)
1221                 coda_set_gdi_regs(ctx);
1222
1223         /*
1224          * Copy headers at the beginning of the first frame for H.264 only.
1225          * In MPEG4 they are already copied by the coda.
1226          */
1227         if (src_buf->v4l2_buf.sequence == 0) {
1228                 pic_stream_buffer_addr =
1229                         vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
1230                         ctx->vpu_header_size[0] +
1231                         ctx->vpu_header_size[1] +
1232                         ctx->vpu_header_size[2];
1233                 pic_stream_buffer_size = q_data_dst->sizeimage -
1234                         ctx->vpu_header_size[0] -
1235                         ctx->vpu_header_size[1] -
1236                         ctx->vpu_header_size[2];
1237                 memcpy(vb2_plane_vaddr(dst_buf, 0),
1238                        &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1239                 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
1240                        &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
1241                 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
1242                         ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
1243                         ctx->vpu_header_size[2]);
1244         } else {
1245                 pic_stream_buffer_addr =
1246                         vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1247                 pic_stream_buffer_size = q_data_dst->sizeimage;
1248         }
1249
1250         if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1251                 force_ipicture = 1;
1252                 switch (dst_fourcc) {
1253                 case V4L2_PIX_FMT_H264:
1254                         quant_param = ctx->params.h264_intra_qp;
1255                         break;
1256                 case V4L2_PIX_FMT_MPEG4:
1257                         quant_param = ctx->params.mpeg4_intra_qp;
1258                         break;
1259                 case V4L2_PIX_FMT_JPEG:
1260                         quant_param = 30;
1261                         break;
1262                 default:
1263                         v4l2_warn(&ctx->dev->v4l2_dev,
1264                                 "cannot set intra qp, fmt not supported\n");
1265                         break;
1266                 }
1267         } else {
1268                 force_ipicture = 0;
1269                 switch (dst_fourcc) {
1270                 case V4L2_PIX_FMT_H264:
1271                         quant_param = ctx->params.h264_inter_qp;
1272                         break;
1273                 case V4L2_PIX_FMT_MPEG4:
1274                         quant_param = ctx->params.mpeg4_inter_qp;
1275                         break;
1276                 default:
1277                         v4l2_warn(&ctx->dev->v4l2_dev,
1278                                 "cannot set inter qp, fmt not supported\n");
1279                         break;
1280                 }
1281         }
1282
1283         /* submit */
1284         if (ctx->params.rot_mode)
1285                 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1286         coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1287         coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1288
1289         if (dev->devtype->product == CODA_960) {
1290                 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1291                 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1292                 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1293
1294                 reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
1295         } else {
1296                 reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
1297         }
1298         coda_write_base(ctx, q_data_src, src_buf, reg);
1299
1300         coda_write(dev, force_ipicture << 1 & 0x2,
1301                    CODA_CMD_ENC_PIC_OPTION);
1302
1303         coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1304         coda_write(dev, pic_stream_buffer_size / 1024,
1305                    CODA_CMD_ENC_PIC_BB_SIZE);
1306
1307         if (!ctx->streamon_out) {
1308                 /* After streamoff on the output side, set stream end flag */
1309                 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1310                 coda_write(dev, ctx->bit_stream_param,
1311                            CODA_REG_BIT_BIT_STREAM_PARAM);
1312         }
1313
1314         if (dev->devtype->product != CODA_DX6)
1315                 coda_write(dev, ctx->iram_info.axi_sram_use,
1316                                 CODA7_REG_BIT_AXI_SRAM_USE);
1317
1318         trace_coda_enc_pic_run(ctx, src_buf);
1319
1320         coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1321
1322         return 0;
1323 }
1324
1325 static void coda_finish_encode(struct coda_ctx *ctx)
1326 {
1327         struct vb2_buffer *src_buf, *dst_buf;
1328         struct coda_dev *dev = ctx->dev;
1329         u32 wr_ptr, start_ptr;
1330
1331         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1332         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1333
1334         trace_coda_enc_pic_done(ctx, dst_buf);
1335
1336         /* Get results from the coda */
1337         start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1338         wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1339
1340         /* Calculate bytesused field */
1341         if (dst_buf->v4l2_buf.sequence == 0) {
1342                 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
1343                                         ctx->vpu_header_size[0] +
1344                                         ctx->vpu_header_size[1] +
1345                                         ctx->vpu_header_size[2]);
1346         } else {
1347                 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
1348         }
1349
1350         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1351                  wr_ptr - start_ptr);
1352
1353         coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1354         coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1355
1356         if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1357                 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1358                 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1359         } else {
1360                 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1361                 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1362         }
1363
1364         dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
1365         dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1366         dst_buf->v4l2_buf.flags |=
1367                 src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1368         dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
1369
1370         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1371
1372         dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1373         coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
1374
1375         ctx->gopcounter--;
1376         if (ctx->gopcounter < 0)
1377                 ctx->gopcounter = ctx->params.gop_size - 1;
1378
1379         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1380                 "job finished: encoding frame (%d) (%s)\n",
1381                 dst_buf->v4l2_buf.sequence,
1382                 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1383                 "KEYFRAME" : "PFRAME");
1384 }
1385
1386 static void coda_seq_end_work(struct work_struct *work)
1387 {
1388         struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1389         struct coda_dev *dev = ctx->dev;
1390
1391         mutex_lock(&ctx->buffer_mutex);
1392         mutex_lock(&dev->coda_mutex);
1393
1394         if (ctx->initialized == 0)
1395                 goto out;
1396
1397         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1398                  "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
1399                  __func__);
1400         if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1401                 v4l2_err(&dev->v4l2_dev,
1402                          "CODA_COMMAND_SEQ_END failed\n");
1403         }
1404
1405         /*
1406          * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
1407          * from the output stream after the h.264 decoder has run. Resetting the
1408          * hardware after the decoder has finished seems to help.
1409          */
1410         if (dev->devtype->product == CODA_960)
1411                 coda_hw_reset(ctx);
1412
1413         kfifo_init(&ctx->bitstream_fifo,
1414                 ctx->bitstream.vaddr, ctx->bitstream.size);
1415
1416         coda_free_framebuffers(ctx);
1417
1418         ctx->initialized = 0;
1419
1420 out:
1421         mutex_unlock(&dev->coda_mutex);
1422         mutex_unlock(&ctx->buffer_mutex);
1423 }
1424
1425 static void coda_bit_release(struct coda_ctx *ctx)
1426 {
1427         mutex_lock(&ctx->buffer_mutex);
1428         coda_free_framebuffers(ctx);
1429         coda_free_context_buffers(ctx);
1430         coda_free_bitstream_buffer(ctx);
1431         mutex_unlock(&ctx->buffer_mutex);
1432 }
1433
1434 const struct coda_context_ops coda_bit_encode_ops = {
1435         .queue_init = coda_encoder_queue_init,
1436         .reqbufs = coda_encoder_reqbufs,
1437         .start_streaming = coda_start_encoding,
1438         .prepare_run = coda_prepare_encode,
1439         .finish_run = coda_finish_encode,
1440         .seq_end_work = coda_seq_end_work,
1441         .release = coda_bit_release,
1442 };
1443
1444 /*
1445  * Decoder context operations
1446  */
1447
1448 static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
1449                                        struct coda_q_data *q_data)
1450 {
1451         if (ctx->bitstream.vaddr)
1452                 return 0;
1453
1454         ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
1455         ctx->bitstream.vaddr = dma_alloc_writecombine(
1456                         &ctx->dev->plat_dev->dev, ctx->bitstream.size,
1457                         &ctx->bitstream.paddr, GFP_KERNEL);
1458         if (!ctx->bitstream.vaddr) {
1459                 v4l2_err(&ctx->dev->v4l2_dev,
1460                          "failed to allocate bitstream ringbuffer");
1461                 return -ENOMEM;
1462         }
1463         kfifo_init(&ctx->bitstream_fifo,
1464                    ctx->bitstream.vaddr, ctx->bitstream.size);
1465
1466         return 0;
1467 }
1468
1469 static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
1470 {
1471         if (ctx->bitstream.vaddr == NULL)
1472                 return;
1473
1474         dma_free_writecombine(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
1475                               ctx->bitstream.vaddr, ctx->bitstream.paddr);
1476         ctx->bitstream.vaddr = NULL;
1477         kfifo_init(&ctx->bitstream_fifo, NULL, 0);
1478 }
1479
1480 static int coda_decoder_reqbufs(struct coda_ctx *ctx,
1481                                 struct v4l2_requestbuffers *rb)
1482 {
1483         struct coda_q_data *q_data_src;
1484         int ret;
1485
1486         if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
1487                 return 0;
1488
1489         if (rb->count) {
1490                 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1491                 ret = coda_alloc_context_buffers(ctx, q_data_src);
1492                 if (ret < 0)
1493                         return ret;
1494                 ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
1495                 if (ret < 0) {
1496                         coda_free_context_buffers(ctx);
1497                         return ret;
1498                 }
1499         } else {
1500                 coda_free_bitstream_buffer(ctx);
1501                 coda_free_context_buffers(ctx);
1502         }
1503
1504         return 0;
1505 }
1506
1507 static int __coda_start_decoding(struct coda_ctx *ctx)
1508 {
1509         struct coda_q_data *q_data_src, *q_data_dst;
1510         u32 bitstream_buf, bitstream_size;
1511         struct coda_dev *dev = ctx->dev;
1512         int width, height;
1513         u32 src_fourcc, dst_fourcc;
1514         u32 val;
1515         int ret;
1516
1517         /* Start decoding */
1518         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1519         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1520         bitstream_buf = ctx->bitstream.paddr;
1521         bitstream_size = ctx->bitstream.size;
1522         src_fourcc = q_data_src->fourcc;
1523         dst_fourcc = q_data_dst->fourcc;
1524
1525         coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1526
1527         /* Update coda bitstream read and write pointers from kfifo */
1528         coda_kfifo_sync_to_device_full(ctx);
1529
1530         ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
1531                                  CODA9_FRAME_TILED2LINEAR);
1532         if (dst_fourcc == V4L2_PIX_FMT_NV12)
1533                 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
1534         if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
1535                 ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
1536         coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
1537
1538         ctx->display_idx = -1;
1539         ctx->frm_dis_flg = 0;
1540         coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1541
1542         coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1543                         CODA_REG_BIT_BIT_STREAM_PARAM);
1544
1545         coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1546         coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1547         val = 0;
1548         if ((dev->devtype->product == CODA_7541) ||
1549             (dev->devtype->product == CODA_960))
1550                 val |= CODA_REORDER_ENABLE;
1551         if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1552                 val |= CODA_NO_INT_ENABLE;
1553         coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1554
1555         ctx->params.codec_mode = ctx->codec->mode;
1556         if (dev->devtype->product == CODA_960 &&
1557             src_fourcc == V4L2_PIX_FMT_MPEG4)
1558                 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1559         else
1560                 ctx->params.codec_mode_aux = 0;
1561         if (src_fourcc == V4L2_PIX_FMT_H264) {
1562                 if (dev->devtype->product == CODA_7541) {
1563                         coda_write(dev, ctx->psbuf.paddr,
1564                                         CODA_CMD_DEC_SEQ_PS_BB_START);
1565                         coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1566                                         CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1567                 }
1568                 if (dev->devtype->product == CODA_960) {
1569                         coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1570                         coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1571                 }
1572         }
1573         if (dev->devtype->product != CODA_960)
1574                 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1575
1576         if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1577                 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1578                 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1579                 return -ETIMEDOUT;
1580         }
1581         ctx->initialized = 1;
1582
1583         /* Update kfifo out pointer from coda bitstream read pointer */
1584         coda_kfifo_sync_from_device(ctx);
1585
1586         coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1587
1588         if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1589                 v4l2_err(&dev->v4l2_dev,
1590                         "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1591                         coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1592                 return -EAGAIN;
1593         }
1594
1595         val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1596         if (dev->devtype->product == CODA_DX6) {
1597                 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1598                 height = val & CODADX6_PICHEIGHT_MASK;
1599         } else {
1600                 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1601                 height = val & CODA7_PICHEIGHT_MASK;
1602         }
1603
1604         if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
1605                 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1606                          width, height, q_data_dst->bytesperline,
1607                          q_data_dst->height);
1608                 return -EINVAL;
1609         }
1610
1611         width = round_up(width, 16);
1612         height = round_up(height, 16);
1613
1614         v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1615                  __func__, ctx->idx, width, height);
1616
1617         ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1618         if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1619                 v4l2_err(&dev->v4l2_dev,
1620                          "not enough framebuffers to decode (%d < %d)\n",
1621                          CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1622                 return -EINVAL;
1623         }
1624
1625         if (src_fourcc == V4L2_PIX_FMT_H264) {
1626                 u32 left_right;
1627                 u32 top_bottom;
1628
1629                 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1630                 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1631
1632                 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1633                 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1634                 q_data_dst->rect.width = width - q_data_dst->rect.left -
1635                                          (left_right & 0x3ff);
1636                 q_data_dst->rect.height = height - q_data_dst->rect.top -
1637                                           (top_bottom & 0x3ff);
1638         }
1639
1640         ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1641         if (ret < 0) {
1642                 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1643                 return ret;
1644         }
1645
1646         /* Tell the decoder how many frame buffers we allocated. */
1647         coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1648         coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1649
1650         if (dev->devtype->product != CODA_DX6) {
1651                 /* Set secondary AXI IRAM */
1652                 coda_setup_iram(ctx);
1653
1654                 coda_write(dev, ctx->iram_info.buf_bit_use,
1655                                 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1656                 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1657                                 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1658                 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1659                                 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1660                 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1661                                 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1662                 coda_write(dev, ctx->iram_info.buf_ovl_use,
1663                                 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1664                 if (dev->devtype->product == CODA_960) {
1665                         coda_write(dev, ctx->iram_info.buf_btp_use,
1666                                         CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1667
1668                         coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1669                         coda9_set_frame_cache(ctx, dst_fourcc);
1670                 }
1671         }
1672
1673         if (src_fourcc == V4L2_PIX_FMT_H264) {
1674                 coda_write(dev, ctx->slicebuf.paddr,
1675                                 CODA_CMD_SET_FRAME_SLICE_BB_START);
1676                 coda_write(dev, ctx->slicebuf.size / 1024,
1677                                 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1678         }
1679
1680         if (dev->devtype->product == CODA_7541) {
1681                 int max_mb_x = 1920 / 16;
1682                 int max_mb_y = 1088 / 16;
1683                 int max_mb_num = max_mb_x * max_mb_y;
1684
1685                 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1686                                 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1687         } else if (dev->devtype->product == CODA_960) {
1688                 int max_mb_x = 1920 / 16;
1689                 int max_mb_y = 1088 / 16;
1690                 int max_mb_num = max_mb_x * max_mb_y;
1691
1692                 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1693                                 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1694         }
1695
1696         if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1697                 v4l2_err(&ctx->dev->v4l2_dev,
1698                          "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1699                 return -ETIMEDOUT;
1700         }
1701
1702         return 0;
1703 }
1704
1705 static int coda_start_decoding(struct coda_ctx *ctx)
1706 {
1707         struct coda_dev *dev = ctx->dev;
1708         int ret;
1709
1710         mutex_lock(&dev->coda_mutex);
1711         ret = __coda_start_decoding(ctx);
1712         mutex_unlock(&dev->coda_mutex);
1713
1714         return ret;
1715 }
1716
1717 static int coda_prepare_decode(struct coda_ctx *ctx)
1718 {
1719         struct vb2_buffer *dst_buf;
1720         struct coda_dev *dev = ctx->dev;
1721         struct coda_q_data *q_data_dst;
1722         struct coda_buffer_meta *meta;
1723         unsigned long flags;
1724         u32 reg_addr, reg_stride;
1725
1726         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1727         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1728
1729         /* Try to copy source buffer contents into the bitstream ringbuffer */
1730         mutex_lock(&ctx->bitstream_mutex);
1731         coda_fill_bitstream(ctx, true);
1732         mutex_unlock(&ctx->bitstream_mutex);
1733
1734         if (coda_get_bitstream_payload(ctx) < 512 &&
1735             (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1736                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1737                          "bitstream payload: %d, skipping\n",
1738                          coda_get_bitstream_payload(ctx));
1739                 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1740                 return -EAGAIN;
1741         }
1742
1743         /* Run coda_start_decoding (again) if not yet initialized */
1744         if (!ctx->initialized) {
1745                 int ret = __coda_start_decoding(ctx);
1746
1747                 if (ret < 0) {
1748                         v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1749                         v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1750                         return -EAGAIN;
1751                 } else {
1752                         ctx->initialized = 1;
1753                 }
1754         }
1755
1756         if (dev->devtype->product == CODA_960)
1757                 coda_set_gdi_regs(ctx);
1758
1759         if (dev->devtype->product == CODA_960) {
1760                 /*
1761                  * The CODA960 seems to have an internal list of buffers with
1762                  * 64 entries that includes the registered frame buffers as
1763                  * well as the rotator buffer output.
1764                  * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
1765                  */
1766                 coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
1767                                 CODA9_CMD_DEC_PIC_ROT_INDEX);
1768
1769                 reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
1770                 reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
1771         } else {
1772                 reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
1773                 reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
1774         }
1775         coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
1776         coda_write(dev, q_data_dst->bytesperline, reg_stride);
1777
1778         coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
1779                         CODA_CMD_DEC_PIC_ROT_MODE);
1780
1781         switch (dev->devtype->product) {
1782         case CODA_DX6:
1783                 /* TBD */
1784         case CODA_7541:
1785                 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1786                 break;
1787         case CODA_960:
1788                 /* 'hardcode to use interrupt disable mode'? */
1789                 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
1790                 break;
1791         }
1792
1793         coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1794
1795         coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1796         coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1797
1798         if (dev->devtype->product != CODA_DX6)
1799                 coda_write(dev, ctx->iram_info.axi_sram_use,
1800                                 CODA7_REG_BIT_AXI_SRAM_USE);
1801
1802         spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
1803         meta = list_first_entry_or_null(&ctx->buffer_meta_list,
1804                                         struct coda_buffer_meta, list);
1805
1806         if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
1807
1808                 /* If this is the last buffer in the bitstream, add padding */
1809                 if (meta->end == (ctx->bitstream_fifo.kfifo.in &
1810                                   ctx->bitstream_fifo.kfifo.mask)) {
1811                         static unsigned char buf[512];
1812                         unsigned int pad;
1813
1814                         /* Pad to multiple of 256 and then add 256 more */
1815                         pad = ((0 - meta->end) & 0xff) + 256;
1816
1817                         memset(buf, 0xff, sizeof(buf));
1818
1819                         kfifo_in(&ctx->bitstream_fifo, buf, pad);
1820                 }
1821         }
1822         spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
1823
1824         coda_kfifo_sync_to_device_full(ctx);
1825
1826         /* Clear decode success flag */
1827         coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
1828
1829         trace_coda_dec_pic_run(ctx, meta);
1830
1831         coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1832
1833         return 0;
1834 }
1835
1836 static void coda_finish_decode(struct coda_ctx *ctx)
1837 {
1838         struct coda_dev *dev = ctx->dev;
1839         struct coda_q_data *q_data_src;
1840         struct coda_q_data *q_data_dst;
1841         struct vb2_buffer *dst_buf;
1842         struct coda_buffer_meta *meta;
1843         unsigned long payload;
1844         unsigned long flags;
1845         int width, height;
1846         int decoded_idx;
1847         int display_idx;
1848         u32 src_fourcc;
1849         int success;
1850         u32 err_mb;
1851         u32 val;
1852
1853         /* Update kfifo out pointer from coda bitstream read pointer */
1854         coda_kfifo_sync_from_device(ctx);
1855
1856         /*
1857          * in stream-end mode, the read pointer can overshoot the write pointer
1858          * by up to 512 bytes
1859          */
1860         if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1861                 if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
1862                         kfifo_init(&ctx->bitstream_fifo,
1863                                 ctx->bitstream.vaddr, ctx->bitstream.size);
1864         }
1865
1866         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1867         src_fourcc = q_data_src->fourcc;
1868
1869         val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
1870         if (val != 1)
1871                 pr_err("DEC_PIC_SUCCESS = %d\n", val);
1872
1873         success = val & 0x1;
1874         if (!success)
1875                 v4l2_err(&dev->v4l2_dev, "decode failed\n");
1876
1877         if (src_fourcc == V4L2_PIX_FMT_H264) {
1878                 if (val & (1 << 3))
1879                         v4l2_err(&dev->v4l2_dev,
1880                                  "insufficient PS buffer space (%d bytes)\n",
1881                                  ctx->psbuf.size);
1882                 if (val & (1 << 2))
1883                         v4l2_err(&dev->v4l2_dev,
1884                                  "insufficient slice buffer space (%d bytes)\n",
1885                                  ctx->slicebuf.size);
1886         }
1887
1888         val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
1889         width = (val >> 16) & 0xffff;
1890         height = val & 0xffff;
1891
1892         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1893
1894         /* frame crop information */
1895         if (src_fourcc == V4L2_PIX_FMT_H264) {
1896                 u32 left_right;
1897                 u32 top_bottom;
1898
1899                 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
1900                 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
1901
1902                 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
1903                         /* Keep current crop information */
1904                 } else {
1905                         struct v4l2_rect *rect = &q_data_dst->rect;
1906
1907                         rect->left = left_right >> 16 & 0xffff;
1908                         rect->top = top_bottom >> 16 & 0xffff;
1909                         rect->width = width - rect->left -
1910                                       (left_right & 0xffff);
1911                         rect->height = height - rect->top -
1912                                        (top_bottom & 0xffff);
1913                 }
1914         } else {
1915                 /* no cropping */
1916         }
1917
1918         err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
1919         if (err_mb > 0)
1920                 v4l2_err(&dev->v4l2_dev,
1921                          "errors in %d macroblocks\n", err_mb);
1922
1923         if (dev->devtype->product == CODA_7541) {
1924                 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
1925                 if (val == 0) {
1926                         /* not enough bitstream data */
1927                         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1928                                  "prescan failed: %d\n", val);
1929                         ctx->hold = true;
1930                         return;
1931                 }
1932         }
1933
1934         ctx->frm_dis_flg = coda_read(dev,
1935                                      CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1936
1937         /*
1938          * The previous display frame was copied out by the rotator,
1939          * now it can be overwritten again
1940          */
1941         if (ctx->display_idx >= 0 &&
1942             ctx->display_idx < ctx->num_internal_frames) {
1943                 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
1944                 coda_write(dev, ctx->frm_dis_flg,
1945                                 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1946         }
1947
1948         /*
1949          * The index of the last decoded frame, not necessarily in
1950          * display order, and the index of the next display frame.
1951          * The latter could have been decoded in a previous run.
1952          */
1953         decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
1954         display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
1955
1956         if (decoded_idx == -1) {
1957                 /* no frame was decoded, but we might have a display frame */
1958                 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
1959                         ctx->sequence_offset++;
1960                 else if (ctx->display_idx < 0)
1961                         ctx->hold = true;
1962         } else if (decoded_idx == -2) {
1963                 /* no frame was decoded, we still return remaining buffers */
1964         } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
1965                 v4l2_err(&dev->v4l2_dev,
1966                          "decoded frame index out of range: %d\n", decoded_idx);
1967         } else {
1968                 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
1969                 val -= ctx->sequence_offset;
1970                 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
1971                 if (!list_empty(&ctx->buffer_meta_list)) {
1972                         meta = list_first_entry(&ctx->buffer_meta_list,
1973                                               struct coda_buffer_meta, list);
1974                         list_del(&meta->list);
1975                         ctx->num_metas--;
1976                         spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
1977                         /*
1978                          * Clamp counters to 16 bits for comparison, as the HW
1979                          * counter rolls over at this point for h.264. This
1980                          * may be different for other formats, but using 16 bits
1981                          * should be enough to detect most errors and saves us
1982                          * from doing different things based on the format.
1983                          */
1984                         if ((val & 0xffff) != (meta->sequence & 0xffff)) {
1985                                 v4l2_err(&dev->v4l2_dev,
1986                                          "sequence number mismatch (%d(%d) != %d)\n",
1987                                          val, ctx->sequence_offset,
1988                                          meta->sequence);
1989                         }
1990                         ctx->frame_metas[decoded_idx] = *meta;
1991                         kfree(meta);
1992                 } else {
1993                         spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
1994                         v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
1995                         memset(&ctx->frame_metas[decoded_idx], 0,
1996                                sizeof(struct coda_buffer_meta));
1997                         ctx->frame_metas[decoded_idx].sequence = val;
1998                         ctx->sequence_offset++;
1999                 }
2000
2001                 trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
2002
2003                 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
2004                 if (val == 0)
2005                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
2006                 else if (val == 1)
2007                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
2008                 else
2009                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
2010
2011                 ctx->frame_errors[decoded_idx] = err_mb;
2012         }
2013
2014         if (display_idx == -1) {
2015                 /*
2016                  * no more frames to be decoded, but there could still
2017                  * be rotator output to dequeue
2018                  */
2019                 ctx->hold = true;
2020         } else if (display_idx == -3) {
2021                 /* possibly prescan failure */
2022         } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
2023                 v4l2_err(&dev->v4l2_dev,
2024                          "presentation frame index out of range: %d\n",
2025                          display_idx);
2026         }
2027
2028         /* If a frame was copied out, return it */
2029         if (ctx->display_idx >= 0 &&
2030             ctx->display_idx < ctx->num_internal_frames) {
2031                 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2032                 dst_buf->v4l2_buf.sequence = ctx->osequence++;
2033
2034                 dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
2035                                              V4L2_BUF_FLAG_PFRAME |
2036                                              V4L2_BUF_FLAG_BFRAME);
2037                 dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
2038                 meta = &ctx->frame_metas[ctx->display_idx];
2039                 dst_buf->v4l2_buf.timecode = meta->timecode;
2040                 dst_buf->v4l2_buf.timestamp = meta->timestamp;
2041
2042                 trace_coda_dec_rot_done(ctx, dst_buf, meta);
2043
2044                 switch (q_data_dst->fourcc) {
2045                 case V4L2_PIX_FMT_YUV420:
2046                 case V4L2_PIX_FMT_YVU420:
2047                 case V4L2_PIX_FMT_NV12:
2048                 default:
2049                         payload = width * height * 3 / 2;
2050                         break;
2051                 case V4L2_PIX_FMT_YUV422P:
2052                         payload = width * height * 2;
2053                         break;
2054                 }
2055                 vb2_set_plane_payload(dst_buf, 0, payload);
2056
2057                 coda_m2m_buf_done(ctx, dst_buf, ctx->frame_errors[display_idx] ?
2058                                   VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
2059
2060                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2061                         "job finished: decoding frame (%d) (%s)\n",
2062                         dst_buf->v4l2_buf.sequence,
2063                         (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
2064                         "KEYFRAME" : "PFRAME");
2065         } else {
2066                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2067                         "job finished: no frame decoded\n");
2068         }
2069
2070         /* The rotator will copy the current display frame next time */
2071         ctx->display_idx = display_idx;
2072 }
2073
2074 const struct coda_context_ops coda_bit_decode_ops = {
2075         .queue_init = coda_decoder_queue_init,
2076         .reqbufs = coda_decoder_reqbufs,
2077         .start_streaming = coda_start_decoding,
2078         .prepare_run = coda_prepare_decode,
2079         .finish_run = coda_finish_decode,
2080         .seq_end_work = coda_seq_end_work,
2081         .release = coda_bit_release,
2082 };
2083
2084 irqreturn_t coda_irq_handler(int irq, void *data)
2085 {
2086         struct coda_dev *dev = data;
2087         struct coda_ctx *ctx;
2088
2089         /* read status register to attend the IRQ */
2090         coda_read(dev, CODA_REG_BIT_INT_STATUS);
2091         coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
2092                       CODA_REG_BIT_INT_CLEAR);
2093
2094         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
2095         if (ctx == NULL) {
2096                 v4l2_err(&dev->v4l2_dev,
2097                          "Instance released before the end of transaction\n");
2098                 mutex_unlock(&dev->coda_mutex);
2099                 return IRQ_HANDLED;
2100         }
2101
2102         trace_coda_bit_done(ctx);
2103
2104         if (ctx->aborting) {
2105                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2106                          "task has been aborted\n");
2107         }
2108
2109         if (coda_isbusy(ctx->dev)) {
2110                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2111                          "coda is still busy!!!!\n");
2112                 return IRQ_NONE;
2113         }
2114
2115         complete(&ctx->completion);
2116
2117         return IRQ_HANDLED;
2118 }