drivers/media/platform/exynos4-is/fimc-is.c

   1 /*
   2  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *
   6  * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
   7  *          Younghwan Joo <yhwan.joo@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  14
  15 #include <linux/device.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-contiguous.h>
  19 #include <linux/errno.h>
  20 #include <linux/firmware.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of_i2c.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/slab.h>
  31 #include <linux/types.h>
  32 #include <linux/videodev2.h>
  33 #include <media/v4l2-of.h>
  34 #include <media/videobuf2-dma-contig.h>
  35
  36 #include "media-dev.h"
  37 #include "fimc-is.h"
  38 #include "fimc-is-command.h"
  39 #include "fimc-is-errno.h"
  40 #include "fimc-is-i2c.h"
  41 #include "fimc-is-param.h"
  42 #include "fimc-is-regs.h"
  43
  44
  45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
  46         [ISS_CLK_PPMUISPX]              = "ppmuispx",
  47         [ISS_CLK_PPMUISPMX]             = "ppmuispmx",
  48         [ISS_CLK_LITE0]                 = "lite0",
  49         [ISS_CLK_LITE1]                 = "lite1",
  50         [ISS_CLK_MPLL]                  = "mpll",
  51         [ISS_CLK_SYSREG]                = "sysreg",
  52         [ISS_CLK_ISP]                   = "isp",
  53         [ISS_CLK_DRC]                   = "drc",
  54         [ISS_CLK_FD]                    = "fd",
  55         [ISS_CLK_MCUISP]                = "mcuisp",
  56         [ISS_CLK_UART]                  = "uart",
  57         [ISS_CLK_ISP_DIV0]              = "ispdiv0",
  58         [ISS_CLK_ISP_DIV1]              = "ispdiv1",
  59         [ISS_CLK_MCUISP_DIV0]           = "mcuispdiv0",
  60         [ISS_CLK_MCUISP_DIV1]           = "mcuispdiv1",
  61         [ISS_CLK_ACLK200]               = "aclk200",
  62         [ISS_CLK_ACLK200_DIV]           = "div_aclk200",
  63         [ISS_CLK_ACLK400MCUISP]         = "aclk400mcuisp",
  64         [ISS_CLK_ACLK400MCUISP_DIV]     = "div_aclk400mcuisp",
  65 };
  66
  67 static void fimc_is_put_clocks(struct fimc_is *is)
  68 {
  69         int i;
  70
  71         for (i = 0; i < ISS_CLKS_MAX; i++) {
  72                 if (IS_ERR(is->clocks[i]))
  73                         continue;
  74                 clk_unprepare(is->clocks[i]);
  75                 clk_put(is->clocks[i]);
  76                 is->clocks[i] = ERR_PTR(-EINVAL);
  77         }
  78 }
  79
  80 static int fimc_is_get_clocks(struct fimc_is *is)
  81 {
  82         int i, ret;
  83
  84         for (i = 0; i < ISS_CLKS_MAX; i++)
  85                 is->clocks[i] = ERR_PTR(-EINVAL);
  86
  87         for (i = 0; i < ISS_CLKS_MAX; i++) {
  88                 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
  89                 if (IS_ERR(is->clocks[i])) {
  90                         ret = PTR_ERR(is->clocks[i]);
  91                         goto err;
  92                 }
  93                 ret = clk_prepare(is->clocks[i]);
  94                 if (ret < 0) {
  95                         clk_put(is->clocks[i]);
  96                         is->clocks[i] = ERR_PTR(-EINVAL);
  97                         goto err;
  98                 }
  99         }
 100
 101         return 0;
 102 err:
 103         fimc_is_put_clocks(is);
 104         dev_err(&is->pdev->dev, "failed to get clock: %s\n",
 105                 fimc_is_clocks[i]);
 106         return -ENXIO;
 107 }
 108
 109 static int fimc_is_setup_clocks(struct fimc_is *is)
 110 {
 111         int ret;
 112
 113         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
 114                                         is->clocks[ISS_CLK_ACLK200_DIV]);
 115         if (ret < 0)
 116                 return ret;
 117
 118         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
 119                                         is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
 120         if (ret < 0)
 121                 return ret;
 122
 123         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
 124         if (ret < 0)
 125                 return ret;
 126
 127         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
 128         if (ret < 0)
 129                 return ret;
 130
 131         ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
 132                                         ATCLK_MCUISP_FREQUENCY);
 133         if (ret < 0)
 134                 return ret;
 135
 136         return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
 137                                         ATCLK_MCUISP_FREQUENCY);
 138 }
 139
 140 int fimc_is_enable_clocks(struct fimc_is *is)
 141 {
 142         int i, ret;
 143
 144         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
 145                 if (IS_ERR(is->clocks[i]))
 146                         continue;
 147                 ret = clk_enable(is->clocks[i]);
 148                 if (ret < 0) {
 149                         dev_err(&is->pdev->dev, "clock %s enable failed\n",
 150                                 fimc_is_clocks[i]);
 151                         for (--i; i >= 0; i--)
 152                                 clk_disable(is->clocks[i]);
 153                         return ret;
 154                 }
 155                 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
 156         }
 157         return 0;
 158 }
 159
 160 void fimc_is_disable_clocks(struct fimc_is *is)
 161 {
 162         int i;
 163
 164         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
 165                 if (!IS_ERR(is->clocks[i])) {
 166                         clk_disable(is->clocks[i]);
 167                         pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
 168                 }
 169         }
 170 }
 171
 172 static int fimc_is_parse_sensor_config(struct fimc_is_sensor *sensor,
 173                                        struct device_node *np)
 174 {
 175         u32 tmp = 0;
 176         int ret;
 177
 178         np = v4l2_of_get_next_endpoint(np, NULL);
 179         if (!np)
 180                 return -ENXIO;
 181         np = v4l2_of_get_remote_port(np);
 182         if (!np)
 183                 return -ENXIO;
 184
 185         /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
 186         ret = of_property_read_u32(np, "reg", &tmp);
 187         sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
 188
 189         return ret;
 190 }
 191
 192 static int fimc_is_register_subdevs(struct fimc_is *is)
 193 {
 194         struct device_node *adapter, *child;
 195         int ret;
 196
 197         ret = fimc_isp_subdev_create(&is->isp);
 198         if (ret < 0)
 199                 return ret;
 200
 201         for_each_compatible_node(adapter, NULL, FIMC_IS_I2C_COMPATIBLE) {
 202                 if (!of_find_device_by_node(adapter)) {
 203                         of_node_put(adapter);
 204                         return -EPROBE_DEFER;
 205                 }
 206
 207                 for_each_available_child_of_node(adapter, child) {
 208                         struct i2c_client *client;
 209                         struct v4l2_subdev *sd;
 210
 211                         client = of_find_i2c_device_by_node(child);
 212                         if (!client)
 213                                 goto e_retry;
 214
 215                         sd = i2c_get_clientdata(client);
 216                         if (!sd)
 217                                 goto e_retry;
 218
 219                         /* FIXME: Add support for multiple sensors. */
 220                         if (WARN_ON(is->sensor))
 221                                 continue;
 222
 223                         is->sensor = sd_to_fimc_is_sensor(sd);
 224
 225                         if (fimc_is_parse_sensor_config(is->sensor, child)) {
 226                                 dev_warn(&is->pdev->dev, "DT parse error: %s\n",
 227                                                          child->full_name);
 228                         }
 229                         pr_debug("%s(): registered subdev: %p\n",
 230                                  __func__, sd->name);
 231                 }
 232         }
 233         return 0;
 234
 235 e_retry:
 236         of_node_put(child);
 237         return -EPROBE_DEFER;
 238 }
 239
 240 static int fimc_is_unregister_subdevs(struct fimc_is *is)
 241 {
 242         fimc_isp_subdev_destroy(&is->isp);
 243         is->sensor = NULL;
 244         return 0;
 245 }
 246
 247 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
 248 {
 249         const struct firmware *fw;
 250         void *buf;
 251         int ret;
 252
 253         ret = request_firmware(&fw, file_name, &is->pdev->dev);
 254         if (ret < 0) {
 255                 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
 256                 return ret;
 257         }
 258         buf = is->memory.vaddr + is->setfile.base;
 259         memcpy(buf, fw->data, fw->size);
 260         fimc_is_mem_barrier();
 261         is->setfile.size = fw->size;
 262
 263         pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
 264
 265         memcpy(is->fw.setfile_info,
 266                 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
 267                 FIMC_IS_SETFILE_INFO_LEN - 1);
 268
 269         is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
 270         is->setfile.state = 1;
 271
 272         pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
 273                  is->setfile.base, fw->size);
 274
 275         release_firmware(fw);
 276         return ret;
 277 }
 278
 279 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
 280 {
 281         unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
 282
 283         if (on) {
 284                 /* Disable watchdog */
 285                 mcuctl_write(0, is, REG_WDT_ISP);
 286
 287                 /* Cortex-A5 start address setting */
 288                 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
 289
 290                 /* Enable and start Cortex-A5 */
 291                 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
 292                 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
 293         } else {
 294                 /* A5 power off */
 295                 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
 296                 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
 297
 298                 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
 299                         if (timeout == 0)
 300                                 return -ETIME;
 301                         timeout--;
 302                         udelay(1);
 303                 }
 304         }
 305
 306         return 0;
 307 }
 308
 309 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
 310 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
 311                        unsigned int state, unsigned int timeout)
 312 {
 313
 314         int ret = wait_event_timeout(is->irq_queue,
 315                                      !state ^ test_bit(bit, &is->state),
 316                                      timeout);
 317         if (ret == 0) {
 318                 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
 319                 return -ETIME;
 320         }
 321         return 0;
 322 }
 323
 324 int fimc_is_start_firmware(struct fimc_is *is)
 325 {
 326         struct device *dev = &is->pdev->dev;
 327         int ret;
 328
 329         memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
 330         wmb();
 331
 332         ret = fimc_is_cpu_set_power(is, 1);
 333         if (ret < 0)
 334                 return ret;
 335
 336         ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
 337                                  msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
 338         if (ret < 0)
 339                 dev_err(dev, "FIMC-IS CPU power on failed\n");
 340
 341         return ret;
 342 }
 343
 344 /* Allocate working memory for the FIMC-IS CPU. */
 345 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
 346 {
 347         struct device *dev = &is->pdev->dev;
 348
 349         is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
 350                                               &is->memory.paddr, GFP_KERNEL);
 351         if (is->memory.vaddr == NULL)
 352                 return -ENOMEM;
 353
 354         is->memory.size = FIMC_IS_CPU_MEM_SIZE;
 355         memset(is->memory.vaddr, 0, is->memory.size);
 356
 357         dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
 358
 359         if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
 360                 dev_err(dev, "invalid firmware memory alignment: %#x\n",
 361                         (u32)is->memory.paddr);
 362                 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
 363                                   is->memory.paddr);
 364                 return -EIO;
 365         }
 366
 367         is->is_p_region = (struct is_region *)(is->memory.vaddr +
 368                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
 369
 370         is->is_dma_p_region = is->memory.paddr +
 371                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
 372
 373         is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
 374                                 FIMC_IS_SHARED_REGION_OFFSET);
 375         return 0;
 376 }
 377
 378 static void fimc_is_free_cpu_memory(struct fimc_is *is)
 379 {
 380         struct device *dev = &is->pdev->dev;
 381
 382         dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
 383                           is->memory.paddr);
 384 }
 385
 386 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
 387 {
 388         struct fimc_is *is = context;
 389         struct device *dev = &is->pdev->dev;
 390         void *buf;
 391         int ret;
 392
 393         if (fw == NULL) {
 394                 dev_err(dev, "firmware request failed\n");
 395                 return;
 396         }
 397         mutex_lock(&is->lock);
 398
 399         if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
 400                 dev_err(dev, "wrong firmware size: %d\n", fw->size);
 401                 goto done;
 402         }
 403
 404         is->fw.size = fw->size;
 405
 406         ret = fimc_is_alloc_cpu_memory(is);
 407         if (ret < 0) {
 408                 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
 409                 goto done;
 410         }
 411
 412         memcpy(is->memory.vaddr, fw->data, fw->size);
 413         wmb();
 414
 415         /* Read firmware description. */
 416         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
 417         memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
 418         is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
 419
 420         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
 421         memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
 422         is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
 423
 424         is->fw.state = 1;
 425
 426         dev_info(dev, "loaded firmware: %s, rev. %s\n",
 427                  is->fw.info, is->fw.version);
 428         dev_dbg(dev, "FW size: %d, paddr: %#x\n", fw->size, is->memory.paddr);
 429
 430         is->is_shared_region->chip_id = 0xe4412;
 431         is->is_shared_region->chip_rev_no = 1;
 432
 433         fimc_is_mem_barrier();
 434
 435         /*
 436          * FIXME: The firmware is not being released for now, as it is
 437          * needed around for copying to the IS working memory every
 438          * time before the Cortex-A5 is restarted.
 439          */
 440         if (is->fw.f_w)
 441                 release_firmware(is->fw.f_w);
 442         is->fw.f_w = fw;
 443 done:
 444         mutex_unlock(&is->lock);
 445 }
 446
 447 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
 448 {
 449         return request_firmware_nowait(THIS_MODULE,
 450                                 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
 451                                 GFP_KERNEL, is, fimc_is_load_firmware);
 452 }
 453
 454 /* General IS interrupt handler */
 455 static void fimc_is_general_irq_handler(struct fimc_is *is)
 456 {
 457         is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
 458
 459         switch (is->i2h_cmd.cmd) {
 460         case IHC_GET_SENSOR_NUM:
 461                 fimc_is_hw_get_params(is, 1);
 462                 fimc_is_hw_wait_intmsr0_intmsd0(is);
 463                 fimc_is_hw_set_sensor_num(is);
 464                 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
 465                 break;
 466         case IHC_SET_FACE_MARK:
 467         case IHC_FRAME_DONE:
 468                 fimc_is_hw_get_params(is, 2);
 469                 break;
 470         case IHC_SET_SHOT_MARK:
 471         case IHC_AA_DONE:
 472         case IH_REPLY_DONE:
 473                 fimc_is_hw_get_params(is, 3);
 474                 break;
 475         case IH_REPLY_NOT_DONE:
 476                 fimc_is_hw_get_params(is, 4);
 477                 break;
 478         case IHC_NOT_READY:
 479                 break;
 480         default:
 481                 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
 482         }
 483
 484         fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
 485
 486         switch (is->i2h_cmd.cmd) {
 487         case IHC_GET_SENSOR_NUM:
 488                 fimc_is_hw_set_intgr0_gd0(is);
 489                 set_bit(IS_ST_A5_PWR_ON, &is->state);
 490                 break;
 491
 492         case IHC_SET_SHOT_MARK:
 493                 break;
 494
 495         case IHC_SET_FACE_MARK:
 496                 is->fd_header.count = is->i2h_cmd.args[0];
 497                 is->fd_header.index = is->i2h_cmd.args[1];
 498                 is->fd_header.offset = 0;
 499                 break;
 500
 501         case IHC_FRAME_DONE:
 502                 break;
 503
 504         case IHC_AA_DONE:
 505                 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
 506                          is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
 507                 break;
 508
 509         case IH_REPLY_DONE:
 510                 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
 511
 512                 switch (is->i2h_cmd.args[0]) {
 513                 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
 514                         /* Get CAC margin */
 515                         set_bit(IS_ST_CHANGE_MODE, &is->state);
 516                         is->isp.cac_margin_x = is->i2h_cmd.args[1];
 517                         is->isp.cac_margin_y = is->i2h_cmd.args[2];
 518                         pr_debug("CAC margin (x,y): (%d,%d)\n",
 519                                  is->isp.cac_margin_x, is->isp.cac_margin_y);
 520                         break;
 521
 522                 case HIC_STREAM_ON:
 523                         clear_bit(IS_ST_STREAM_OFF, &is->state);
 524                         set_bit(IS_ST_STREAM_ON, &is->state);
 525                         break;
 526
 527                 case HIC_STREAM_OFF:
 528                         clear_bit(IS_ST_STREAM_ON, &is->state);
 529                         set_bit(IS_ST_STREAM_OFF, &is->state);
 530                         break;
 531
 532                 case HIC_SET_PARAMETER:
 533                         is->config[is->config_index].p_region_index1 = 0;
 534                         is->config[is->config_index].p_region_index2 = 0;
 535                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
 536                         pr_debug("HIC_SET_PARAMETER\n");
 537                         break;
 538
 539                 case HIC_GET_PARAMETER:
 540                         break;
 541
 542                 case HIC_SET_TUNE:
 543                         break;
 544
 545                 case HIC_GET_STATUS:
 546                         break;
 547
 548                 case HIC_OPEN_SENSOR:
 549                         set_bit(IS_ST_OPEN_SENSOR, &is->state);
 550                         pr_debug("data lanes: %d, settle line: %d\n",
 551                                  is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
 552                         break;
 553
 554                 case HIC_CLOSE_SENSOR:
 555                         clear_bit(IS_ST_OPEN_SENSOR, &is->state);
 556                         is->sensor_index = 0;
 557                         break;
 558
 559                 case HIC_MSG_TEST:
 560                         pr_debug("config MSG level completed\n");
 561                         break;
 562
 563                 case HIC_POWER_DOWN:
 564                         clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
 565                         break;
 566
 567                 case HIC_GET_SET_FILE_ADDR:
 568                         is->setfile.base = is->i2h_cmd.args[1];
 569                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
 570                         break;
 571
 572                 case HIC_LOAD_SET_FILE:
 573                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
 574                         break;
 575                 }
 576                 break;
 577
 578         case IH_REPLY_NOT_DONE:
 579                 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
 580                        is->i2h_cmd.args[1],
 581                        fimc_is_strerr(is->i2h_cmd.args[1]));
 582
 583                 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
 584                         pr_err("IS_ERROR_TIME_OUT\n");
 585
 586                 switch (is->i2h_cmd.args[1]) {
 587                 case IS_ERROR_SET_PARAMETER:
 588                         fimc_is_mem_barrier();
 589                 }
 590
 591                 switch (is->i2h_cmd.args[0]) {
 592                 case HIC_SET_PARAMETER:
 593                         is->config[is->config_index].p_region_index1 = 0;
 594                         is->config[is->config_index].p_region_index2 = 0;
 595                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
 596                         break;
 597                 }
 598                 break;
 599
 600         case IHC_NOT_READY:
 601                 pr_err("IS control sequence error: Not Ready\n");
 602                 break;
 603         }
 604
 605         wake_up(&is->irq_queue);
 606 }
 607
 608 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
 609 {
 610         struct fimc_is *is = priv;
 611         unsigned long flags;
 612         u32 status;
 613
 614         spin_lock_irqsave(&is->slock, flags);
 615         status = mcuctl_read(is, MCUCTL_REG_INTSR1);
 616
 617         if (status & (1UL << FIMC_IS_INT_GENERAL))
 618                 fimc_is_general_irq_handler(is);
 619
 620         if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
 621                 fimc_isp_irq_handler(is);
 622
 623         spin_unlock_irqrestore(&is->slock, flags);
 624         return IRQ_HANDLED;
 625 }
 626
 627 static int fimc_is_hw_open_sensor(struct fimc_is *is,
 628                                   struct fimc_is_sensor *sensor)
 629 {
 630         struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
 631
 632         fimc_is_hw_wait_intmsr0_intmsd0(is);
 633
 634         soe->self_calibration_mode = 1;
 635         soe->actuator_type = 0;
 636         soe->mipi_lane_num = 0;
 637         soe->mclk = 0;
 638         soe->mipi_speed = 0;
 639         soe->fast_open_sensor = 0;
 640         soe->i2c_sclk = 88000000;
 641
 642         fimc_is_mem_barrier();
 643
 644         mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
 645         mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
 646         mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
 647         mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
 648         mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
 649
 650         fimc_is_hw_set_intgr0_gd0(is);
 651
 652         return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
 653                                   FIMC_IS_SENSOR_OPEN_TIMEOUT);
 654 }
 655
 656
 657 int fimc_is_hw_initialize(struct fimc_is *is)
 658 {
 659         const int config_ids[] = {
 660                 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
 661                 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
 662         };
 663         struct device *dev = &is->pdev->dev;
 664         u32 prev_id;
 665         int i, ret;
 666
 667         /* Sensor initialization. */
 668         ret = fimc_is_hw_open_sensor(is, is->sensor);
 669         if (ret < 0)
 670                 return ret;
 671
 672         /* Get the setfile address. */
 673         fimc_is_hw_get_setfile_addr(is);
 674
 675         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
 676                                  FIMC_IS_CONFIG_TIMEOUT);
 677         if (ret < 0) {
 678                 dev_err(dev, "get setfile address timed out\n");
 679                 return ret;
 680         }
 681         pr_debug("setfile.base: %#x\n", is->setfile.base);
 682
 683         /* Load the setfile. */
 684         fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
 685         clear_bit(IS_ST_SETFILE_LOADED, &is->state);
 686         fimc_is_hw_load_setfile(is);
 687         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
 688                                  FIMC_IS_CONFIG_TIMEOUT);
 689         if (ret < 0) {
 690                 dev_err(dev, "loading setfile timed out\n");
 691                 return ret;
 692         }
 693
 694         pr_debug("setfile: base: %#x, size: %d\n",
 695                  is->setfile.base, is->setfile.size);
 696         pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
 697
 698         /* Check magic number. */
 699         if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
 700             FIMC_IS_MAGIC_NUMBER) {
 701                 dev_err(dev, "magic number error!\n");
 702                 return -EIO;
 703         }
 704
 705         pr_debug("shared region: %#x, parameter region: %#x\n",
 706                  is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
 707                  is->is_dma_p_region);
 708
 709         is->setfile.sub_index = 0;
 710
 711         /* Stream off. */
 712         fimc_is_hw_stream_off(is);
 713         ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
 714                                  FIMC_IS_CONFIG_TIMEOUT);
 715         if (ret < 0) {
 716                 dev_err(dev, "stream off timeout\n");
 717                 return ret;
 718         }
 719
 720         /* Preserve previous mode. */
 721         prev_id = is->config_index;
 722
 723         /* Set initial parameter values. */
 724         for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
 725                 is->config_index = config_ids[i];
 726                 fimc_is_set_initial_params(is);
 727                 ret = fimc_is_itf_s_param(is, true);
 728                 if (ret < 0) {
 729                         is->config_index = prev_id;
 730                         return ret;
 731                 }
 732         }
 733         is->config_index = prev_id;
 734
 735         set_bit(IS_ST_INIT_DONE, &is->state);
 736         dev_info(dev, "initialization sequence completed (%d)\n",
 737                                                 is->config_index);
 738         return 0;
 739 }
 740
 741 static int fimc_is_log_show(struct seq_file *s, void *data)
 742 {
 743         struct fimc_is *is = s->private;
 744         const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
 745
 746         if (is->memory.vaddr == NULL) {
 747                 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
 748                 return -EIO;
 749         }
 750
 751         seq_printf(s, "%s\n", buf);
 752         return 0;
 753 }
 754
 755 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
 756 {
 757         return single_open(file, fimc_is_log_show, inode->i_private);
 758 }
 759
 760 static const struct file_operations fimc_is_debugfs_fops = {
 761         .open           = fimc_is_debugfs_open,
 762         .read           = seq_read,
 763         .llseek         = seq_lseek,
 764         .release        = single_release,
 765 };
 766
 767 static void fimc_is_debugfs_remove(struct fimc_is *is)
 768 {
 769         debugfs_remove_recursive(is->debugfs_entry);
 770         is->debugfs_entry = NULL;
 771 }
 772
 773 static int fimc_is_debugfs_create(struct fimc_is *is)
 774 {
 775         struct dentry *dentry;
 776
 777         is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
 778
 779         dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
 780                                      is, &fimc_is_debugfs_fops);
 781         if (!dentry)
 782                 fimc_is_debugfs_remove(is);
 783
 784         return is->debugfs_entry == NULL ? -EIO : 0;
 785 }
 786
 787 static int fimc_is_probe(struct platform_device *pdev)
 788 {
 789         struct device *dev = &pdev->dev;
 790         struct fimc_is *is;
 791         struct resource res;
 792         struct device_node *node;
 793         int ret;
 794
 795         is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
 796         if (!is)
 797                 return -ENOMEM;
 798
 799         is->pdev = pdev;
 800         is->isp.pdev = pdev;
 801
 802         init_waitqueue_head(&is->irq_queue);
 803         spin_lock_init(&is->slock);
 804         mutex_init(&is->lock);
 805
 806         ret = of_address_to_resource(dev->of_node, 0, &res);
 807         if (ret < 0)
 808                 return ret;
 809
 810         is->regs = devm_ioremap_resource(dev, &res);
 811         if (IS_ERR(is->regs))
 812                 return PTR_ERR(is->regs);
 813
 814         node = of_get_child_by_name(dev->of_node, "pmu");
 815         if (!node)
 816                 return -ENODEV;
 817
 818         is->pmu_regs = of_iomap(node, 0);
 819         if (!is->pmu_regs)
 820                 return -ENOMEM;
 821
 822         is->irq = irq_of_parse_and_map(dev->of_node, 0);
 823         if (is->irq < 0) {
 824                 dev_err(dev, "no irq found\n");
 825                 return is->irq;
 826         }
 827
 828         ret = fimc_is_get_clocks(is);
 829         if (ret < 0)
 830                 return ret;
 831
 832         platform_set_drvdata(pdev, is);
 833
 834         ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
 835         if (ret < 0) {
 836                 dev_err(dev, "irq request failed\n");
 837                 goto err_clk;
 838         }
 839         pm_runtime_enable(dev);
 840         /*
 841          * Enable only the ISP power domain, keep FIMC-IS clocks off until
 842          * the whole clock tree is configured. The ISP power domain needs
 843          * be active in order to acces any CMU_ISP clock registers.
 844          */
 845         ret = pm_runtime_get_sync(dev);
 846         if (ret < 0)
 847                 goto err_irq;
 848
 849         ret = fimc_is_setup_clocks(is);
 850         pm_runtime_put_sync(dev);
 851
 852         if (ret < 0)
 853                 goto err_irq;
 854
 855         is->clk_init = true;
 856
 857         is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
 858         if (IS_ERR(is->alloc_ctx)) {
 859                 ret = PTR_ERR(is->alloc_ctx);
 860                 goto err_irq;
 861         }
 862         /*
 863          * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
 864          * will be created within the subdev's registered() callback.
 865          */
 866         ret = fimc_is_register_subdevs(is);
 867         if (ret < 0)
 868                 goto err_vb;
 869
 870         ret = fimc_is_debugfs_create(is);
 871         if (ret < 0)
 872                 goto err_sd;
 873
 874         ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
 875         if (ret < 0)
 876                 goto err_dfs;
 877
 878         dev_dbg(dev, "FIMC-IS registered successfully\n");
 879         return 0;
 880
 881 err_dfs:
 882         fimc_is_debugfs_remove(is);
 883 err_vb:
 884         vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
 885 err_sd:
 886         fimc_is_unregister_subdevs(is);
 887 err_irq:
 888         free_irq(is->irq, is);
 889 err_clk:
 890         fimc_is_put_clocks(is);
 891         return ret;
 892 }
 893
 894 static int fimc_is_runtime_resume(struct device *dev)
 895 {
 896         struct fimc_is *is = dev_get_drvdata(dev);
 897
 898         if (!is->clk_init)
 899                 return 0;
 900
 901         return fimc_is_enable_clocks(is);
 902 }
 903
 904 static int fimc_is_runtime_suspend(struct device *dev)
 905 {
 906         struct fimc_is *is = dev_get_drvdata(dev);
 907
 908         if (is->clk_init)
 909                 fimc_is_disable_clocks(is);
 910
 911         return 0;
 912 }
 913
 914 #ifdef CONFIG_PM_SLEEP
 915 static int fimc_is_resume(struct device *dev)
 916 {
 917         /* TODO: */
 918         return 0;
 919 }
 920
 921 static int fimc_is_suspend(struct device *dev)
 922 {
 923         struct fimc_is *is = dev_get_drvdata(dev);
 924
 925         /* TODO: */
 926         if (test_bit(IS_ST_A5_PWR_ON, &is->state))
 927                 return -EBUSY;
 928
 929         return 0;
 930 }
 931 #endif /* CONFIG_PM_SLEEP */
 932
 933 static int fimc_is_remove(struct platform_device *pdev)
 934 {
 935         struct fimc_is *is = platform_get_drvdata(pdev);
 936
 937         pm_runtime_disable(&pdev->dev);
 938         pm_runtime_set_suspended(&pdev->dev);
 939         free_irq(is->irq, is);
 940         fimc_is_unregister_subdevs(is);
 941         vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
 942         fimc_is_put_clocks(is);
 943         fimc_is_debugfs_remove(is);
 944         release_firmware(is->fw.f_w);
 945         fimc_is_free_cpu_memory(is);
 946
 947         return 0;
 948 }
 949
 950 static const struct of_device_id fimc_is_of_match[] = {
 951         { .compatible = "samsung,exynos4212-fimc-is" },
 952         { /* sentinel */ },
 953 };
 954 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
 955
 956 static const struct dev_pm_ops fimc_is_pm_ops = {
 957         SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
 958         SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
 959                            NULL)
 960 };
 961
 962 static struct platform_driver fimc_is_driver = {
 963         .probe          = fimc_is_probe,
 964         .remove         = fimc_is_remove,
 965         .driver = {
 966                 .of_match_table = fimc_is_of_match,
 967                 .name           = FIMC_IS_DRV_NAME,
 968                 .owner          = THIS_MODULE,
 969                 .pm             = &fimc_is_pm_ops,
 970         }
 971 };
 972
 973 static int fimc_is_module_init(void)
 974 {
 975         int ret;
 976
 977         ret = fimc_is_register_sensor_driver();
 978         if (ret < 0)
 979                 return ret;
 980
 981         ret = fimc_is_register_i2c_driver();
 982         if (ret < 0)
 983                 goto err_sens;
 984
 985         ret = platform_driver_register(&fimc_is_driver);
 986         if (!ret)
 987                 return ret;
 988
 989         fimc_is_unregister_i2c_driver();
 990 err_sens:
 991         fimc_is_unregister_sensor_driver();
 992         return ret;
 993 }
 994
 995 static void fimc_is_module_exit(void)
 996 {
 997         fimc_is_unregister_sensor_driver();
 998         fimc_is_unregister_i2c_driver();
 999         platform_driver_unregister(&fimc_is_driver);
1000 }
1001
1002 module_init(fimc_is_module_init);
1003 module_exit(fimc_is_module_exit);
1004
1005 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
1006 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
1007 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");