3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2013-2014, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
18 #include <linux/jiffies.h>
19 #include <linux/delay.h>
20 #include <linux/kthread.h>
22 #include <linux/mei.h>
30 * mei_txe_reg_read - Reads 32bit data from the device
32 * @base_addr: registers base address
33 * @offset: register offset
36 static inline u32 mei_txe_reg_read(void __iomem *base_addr,
39 return ioread32(base_addr + offset);
43 * mei_txe_reg_write - Writes 32bit data to the device
45 * @base_addr: registers base address
46 * @offset: register offset
47 * @value: the value to write
49 static inline void mei_txe_reg_write(void __iomem *base_addr,
50 unsigned long offset, u32 value)
52 iowrite32(value, base_addr + offset);
56 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
58 * @dev: the device structure
59 * @offset: register offset
61 * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
63 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
66 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
70 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
72 * @dev: the device structure
73 * @offset: register offset
75 * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
77 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
80 WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
81 return mei_txe_sec_reg_read_silent(hw, offset);
84 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
85 * doesn't check for aliveness
87 * @dev: the device structure
88 * @offset: register offset
89 * @value: value to write
91 * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
93 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
94 unsigned long offset, u32 value)
96 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
100 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
102 * @dev: the device structure
103 * @offset: register offset
104 * @value: value to write
106 * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
108 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
109 unsigned long offset, u32 value)
111 WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
112 mei_txe_sec_reg_write_silent(hw, offset, value);
115 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
117 * @hw: the device structure
118 * @offset: offset from which to read the data
121 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
122 unsigned long offset)
124 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
128 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
130 * @hw: the device structure
131 * @offset: offset from which to write the data
132 * @value: the byte to write
134 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
135 unsigned long offset, u32 value)
137 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
141 * mei_txe_aliveness_set - request for aliveness change
143 * @dev: the device structure
144 * @req: requested aliveness value
146 * Request for aliveness change and returns true if the change is
147 * really needed and false if aliveness is already
148 * in the requested state
149 * Requires device lock to be held
151 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
154 struct mei_txe_hw *hw = to_txe_hw(dev);
155 bool do_req = hw->aliveness != req;
157 dev_dbg(&dev->pdev->dev, "Aliveness current=%d request=%d\n",
160 hw->recvd_aliveness = false;
161 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
168 * mei_txe_aliveness_req_get - get aliveness requested register value
170 * @dev: the device structure
172 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
173 * from HICR_HOST_ALIVENESS_REQ register value
175 static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
177 struct mei_txe_hw *hw = to_txe_hw(dev);
179 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
180 return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
184 * mei_txe_aliveness_get - get aliveness response register value
185 * @dev: the device structure
187 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit
188 * from HICR_HOST_ALIVENESS_RESP register value
190 static u32 mei_txe_aliveness_get(struct mei_device *dev)
192 struct mei_txe_hw *hw = to_txe_hw(dev);
194 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
195 return reg & HICR_HOST_ALIVENESS_RESP_ACK;
199 * mei_txe_aliveness_poll - waits for aliveness to settle
201 * @dev: the device structure
202 * @expected: expected aliveness value
204 * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
205 * returns > 0 if the expected value was received, -ETIME otherwise
207 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
209 struct mei_txe_hw *hw = to_txe_hw(dev);
213 hw->aliveness = mei_txe_aliveness_get(dev);
214 if (hw->aliveness == expected) {
215 dev_dbg(&dev->pdev->dev,
216 "aliveness settled after %d msecs\n", t);
219 mutex_unlock(&dev->device_lock);
220 msleep(MSEC_PER_SEC / 5);
221 mutex_lock(&dev->device_lock);
222 t += MSEC_PER_SEC / 5;
223 } while (t < SEC_ALIVENESS_WAIT_TIMEOUT);
225 dev_err(&dev->pdev->dev, "aliveness timed out\n");
230 * mei_txe_aliveness_wait - waits for aliveness to settle
232 * @dev: the device structure
233 * @expected: expected aliveness value
235 * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
236 * returns returns 0 on success and < 0 otherwise
238 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
240 struct mei_txe_hw *hw = to_txe_hw(dev);
241 const unsigned long timeout =
242 msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
246 hw->aliveness = mei_txe_aliveness_get(dev);
247 if (hw->aliveness == expected)
250 mutex_unlock(&dev->device_lock);
251 err = wait_event_timeout(hw->wait_aliveness,
252 hw->recvd_aliveness, timeout);
253 mutex_lock(&dev->device_lock);
255 hw->aliveness = mei_txe_aliveness_get(dev);
256 ret = hw->aliveness == expected ? 0 : -ETIME;
259 dev_err(&dev->pdev->dev, "aliveness timed out");
261 dev_dbg(&dev->pdev->dev, "aliveness settled after %d msecs\n",
262 jiffies_to_msecs(timeout - err));
263 hw->recvd_aliveness = false;
268 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
270 * @dev: the device structure
272 * returns returns 0 on success and < 0 otherwise
274 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
276 if (mei_txe_aliveness_set(dev, req))
277 return mei_txe_aliveness_wait(dev, req);
282 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
284 * @dev: the device structure
286 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
288 struct mei_txe_hw *hw = to_txe_hw(dev);
290 /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
291 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
292 hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
293 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
297 * mei_txe_input_doorbell_set
298 * - Sets bit 0 in SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
299 * @dev: the device structure
301 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
303 /* Clear the interrupt cause */
304 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
305 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
309 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
311 * @dev: the device structure
313 static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
315 mei_txe_br_reg_write(hw,
316 SICR_SEC_IPC_OUTPUT_STATUS_REG,
317 SEC_IPC_OUTPUT_STATUS_RDY);
321 * mei_txe_is_input_ready - check if TXE is ready for receiving data
323 * @dev: the device structure
325 static bool mei_txe_is_input_ready(struct mei_device *dev)
327 struct mei_txe_hw *hw = to_txe_hw(dev);
329 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
330 return !!(SEC_IPC_INPUT_STATUS_RDY & status);
334 * mei_txe_intr_clear - clear all interrupts
336 * @dev: the device structure
338 static inline void mei_txe_intr_clear(struct mei_device *dev)
340 struct mei_txe_hw *hw = to_txe_hw(dev);
341 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
342 SEC_IPC_HOST_INT_STATUS_PENDING);
343 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
344 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
348 * mei_txe_intr_disable - disable all interrupts
350 * @dev: the device structure
352 static void mei_txe_intr_disable(struct mei_device *dev)
354 struct mei_txe_hw *hw = to_txe_hw(dev);
355 mei_txe_br_reg_write(hw, HHIER_REG, 0);
356 mei_txe_br_reg_write(hw, HIER_REG, 0);
359 * mei_txe_intr_disable - enable all interrupts
361 * @dev: the device structure
363 static void mei_txe_intr_enable(struct mei_device *dev)
365 struct mei_txe_hw *hw = to_txe_hw(dev);
366 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
367 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
371 * mei_txe_pending_interrupts - check if there are pending interrupts
372 * only Aliveness, Input ready, and output doorbell are of relevance
374 * @dev: the device structure
376 * Checks if there are pending interrupts
377 * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
379 static bool mei_txe_pending_interrupts(struct mei_device *dev)
382 struct mei_txe_hw *hw = to_txe_hw(dev);
383 bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
389 dev_dbg(&dev->pdev->dev,
390 "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
391 !!(hw->intr_cause & TXE_INTR_IN_READY),
392 !!(hw->intr_cause & TXE_INTR_READINESS),
393 !!(hw->intr_cause & TXE_INTR_ALIVENESS),
394 !!(hw->intr_cause & TXE_INTR_OUT_DB));
400 * mei_txe_input_payload_write - write a dword to the host buffer
403 * @dev: the device structure
404 * @idx: index in the host buffer
407 static void mei_txe_input_payload_write(struct mei_device *dev,
408 unsigned long idx, u32 value)
410 struct mei_txe_hw *hw = to_txe_hw(dev);
411 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
412 (idx * sizeof(u32)), value);
416 * mei_txe_out_data_read - read dword from the device buffer
419 * @dev: the device structure
420 * @idx: index in the device buffer
422 * returns register value at index
424 static u32 mei_txe_out_data_read(const struct mei_device *dev,
427 struct mei_txe_hw *hw = to_txe_hw(dev);
428 return mei_txe_br_reg_read(hw,
429 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
435 * mei_txe_readiness_set_host_rdy
437 * @dev: the device structure
439 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
441 struct mei_txe_hw *hw = to_txe_hw(dev);
442 mei_txe_br_reg_write(hw,
443 SICR_HOST_IPC_READINESS_REQ_REG,
444 SICR_HOST_IPC_READINESS_HOST_RDY);
448 * mei_txe_readiness_clear
450 * @dev: the device structure
452 static void mei_txe_readiness_clear(struct mei_device *dev)
454 struct mei_txe_hw *hw = to_txe_hw(dev);
455 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
456 SICR_HOST_IPC_READINESS_RDY_CLR);
459 * mei_txe_readiness_get - Reads and returns
460 * the HICR_SEC_IPC_READINESS register value
462 * @dev: the device structure
464 static u32 mei_txe_readiness_get(struct mei_device *dev)
466 struct mei_txe_hw *hw = to_txe_hw(dev);
467 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
472 * mei_txe_readiness_is_sec_rdy - check readiness
473 * for HICR_SEC_IPC_READINESS_SEC_RDY
475 * @readiness - cached readiness state
477 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
479 return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
483 * mei_txe_hw_is_ready - check if the hw is ready
485 * @dev: the device structure
487 static bool mei_txe_hw_is_ready(struct mei_device *dev)
489 u32 readiness = mei_txe_readiness_get(dev);
490 return mei_txe_readiness_is_sec_rdy(readiness);
494 * mei_txe_host_is_ready - check if the host is ready
496 * @dev: the device structure
498 static inline bool mei_txe_host_is_ready(struct mei_device *dev)
500 struct mei_txe_hw *hw = to_txe_hw(dev);
501 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
502 return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
506 * mei_txe_readiness_wait - wait till readiness settles
508 * @dev: the device structure
510 * returns 0 on success and -ETIME on timeout
512 static int mei_txe_readiness_wait(struct mei_device *dev)
514 if (mei_txe_hw_is_ready(dev))
517 mutex_unlock(&dev->device_lock);
518 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
519 msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
520 mutex_lock(&dev->device_lock);
521 if (!dev->recvd_hw_ready) {
522 dev_err(&dev->pdev->dev, "wait for readiness failed\n");
526 dev->recvd_hw_ready = false;
531 * mei_txe_hw_config - configure hardware at the start of the devices
533 * @dev: the device structure
535 * Configure hardware at the start of the device should be done only
536 * once at the device probe time
538 static void mei_txe_hw_config(struct mei_device *dev)
541 struct mei_txe_hw *hw = to_txe_hw(dev);
542 /* Doesn't change in runtime */
543 dev->hbuf_depth = PAYLOAD_SIZE / 4;
545 hw->aliveness = mei_txe_aliveness_get(dev);
546 hw->readiness = mei_txe_readiness_get(dev);
548 dev_dbg(&dev->pdev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
549 hw->aliveness, hw->readiness);
554 * mei_txe_write - writes a message to device.
556 * @dev: the device structure
557 * @header: header of message
558 * @buf: message buffer will be written
559 * returns 1 if success, 0 - otherwise.
562 static int mei_txe_write(struct mei_device *dev,
563 struct mei_msg_hdr *header, unsigned char *buf)
565 struct mei_txe_hw *hw = to_txe_hw(dev);
567 unsigned long length;
568 u32 *reg_buf = (u32 *)buf;
571 if (WARN_ON(!header || !buf))
574 length = header->length;
576 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
578 if ((length + sizeof(struct mei_msg_hdr)) > PAYLOAD_SIZE) {
579 dev_err(&dev->pdev->dev, "write length exceeded = %ld > %d\n",
580 length + sizeof(struct mei_msg_hdr), PAYLOAD_SIZE);
584 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
587 /* Enable Input Ready Interrupt. */
588 mei_txe_input_ready_interrupt_enable(dev);
590 if (!mei_txe_is_input_ready(dev)) {
591 dev_err(&dev->pdev->dev, "Input is not ready");
595 mei_txe_input_payload_write(dev, 0, *((u32 *)header));
597 for (i = 0; i < length / 4; i++)
598 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]);
603 memcpy(®, &buf[length - rem], rem);
604 mei_txe_input_payload_write(dev, i + 1, reg);
607 dev->hbuf_is_ready = false;
608 /* Set Input-Doorbell */
609 mei_txe_input_doorbell_set(hw);
615 * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer
617 * @dev: the device structure
619 * returns the PAYLOAD_SIZE - 4
621 static size_t mei_txe_hbuf_max_len(const struct mei_device *dev)
623 return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr);
627 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
629 * @dev: the device structure
631 * returns always hbuf_depth
633 static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
635 return dev->hbuf_depth;
639 * mei_txe_count_full_read_slots - mimics the me device circular buffer
641 * @dev: the device structure
643 * returns always buffer size in dwords count
645 static int mei_txe_count_full_read_slots(struct mei_device *dev)
647 /* read buffers has static size */
648 return PAYLOAD_SIZE / 4;
652 * mei_txe_read_hdr - read message header which is always in 4 first bytes
654 * @dev: the device structure
656 * returns mei message header
659 static u32 mei_txe_read_hdr(const struct mei_device *dev)
661 return mei_txe_out_data_read(dev, 0);
664 * mei_txe_read - reads a message from the txe device.
666 * @dev: the device structure
667 * @buf: message buffer will be written
668 * @len: message size will be read
670 * returns -EINVAL on error wrong argument and 0 on success
672 static int mei_txe_read(struct mei_device *dev,
673 unsigned char *buf, unsigned long len)
676 struct mei_txe_hw *hw = to_txe_hw(dev);
678 u32 *reg_buf = (u32 *)buf;
681 if (WARN_ON(!buf || !len))
684 dev_dbg(&dev->pdev->dev,
685 "buffer-length = %lu buf[0]0x%08X\n",
686 len, mei_txe_out_data_read(dev, 0));
688 for (i = 0; i < len / 4; i++) {
689 /* skip header: index starts from 1 */
690 u32 reg = mei_txe_out_data_read(dev, i + 1);
691 dev_dbg(&dev->pdev->dev, "buf[%d] = 0x%08X\n", i, reg);
696 u32 reg = mei_txe_out_data_read(dev, i + 1);
697 memcpy(reg_buf, ®, rem);
700 mei_txe_output_ready_set(hw);
705 * mei_txe_hw_reset - resets host and fw.
707 * @dev: the device structure
708 * @intr_enable: if interrupt should be enabled after reset.
710 * returns 0 on success and < 0 in case of error
712 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
714 struct mei_txe_hw *hw = to_txe_hw(dev);
718 * read input doorbell to ensure consistency between Bridge and SeC
719 * return value might be garbage return
721 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
723 aliveness_req = mei_txe_aliveness_req_get(dev);
724 hw->aliveness = mei_txe_aliveness_get(dev);
726 /* Disable interrupts in this stage we will poll */
727 mei_txe_intr_disable(dev);
730 * If Aliveness Request and Aliveness Response are not equal then
731 * wait for them to be equal
732 * Since we might have interrupts disabled - poll for it
734 if (aliveness_req != hw->aliveness)
735 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
736 dev_err(&dev->pdev->dev,
737 "wait for aliveness settle failed ... bailing out\n");
742 * If Aliveness Request and Aliveness Response are set then clear them
745 mei_txe_aliveness_set(dev, 0);
746 if (mei_txe_aliveness_poll(dev, 0) < 0) {
747 dev_err(&dev->pdev->dev,
748 "wait for aliveness failed ... bailing out\n");
754 * Set rediness RDY_CLR bit
756 mei_txe_readiness_clear(dev);
762 * mei_txe_hw_start - start the hardware after reset
764 * @dev: the device structure
766 * returns 0 on success and < 0 in case of error
768 static int mei_txe_hw_start(struct mei_device *dev)
770 struct mei_txe_hw *hw = to_txe_hw(dev);
775 /* bring back interrupts */
776 mei_txe_intr_enable(dev);
778 ret = mei_txe_readiness_wait(dev);
780 dev_err(&dev->pdev->dev, "wating for readiness failed\n");
785 * If HISR.INT2_STS interrupt status bit is set then clear it.
787 hisr = mei_txe_br_reg_read(hw, HISR_REG);
788 if (hisr & HISR_INT_2_STS)
789 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
791 /* Clear the interrupt cause of OutputDoorbell */
792 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
794 ret = mei_txe_aliveness_set_sync(dev, 1);
796 dev_err(&dev->pdev->dev, "wait for aliveness failed ... bailing out\n");
800 /* enable input ready interrupts:
801 * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
803 mei_txe_input_ready_interrupt_enable(dev);
806 /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
807 mei_txe_output_ready_set(hw);
809 /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
811 mei_txe_readiness_set_host_rdy(dev);
817 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
818 * single bit mask and acknowledge the interrupts
820 * @dev: the device structure
821 * @do_ack: acknowledge interrupts
823 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
825 struct mei_txe_hw *hw = to_txe_hw(dev);
832 /* read interrupt registers */
833 hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
834 generated = (hhisr & IPC_HHIER_MSK);
838 hisr = mei_txe_br_reg_read(hw, HISR_REG);
840 aliveness = mei_txe_aliveness_get(dev);
841 if (hhisr & IPC_HHIER_SEC && aliveness)
842 ipc_isr = mei_txe_sec_reg_read_silent(hw,
843 SEC_IPC_HOST_INT_STATUS_REG);
847 generated = generated ||
848 (hisr & HISR_INT_STS_MSK) ||
849 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
851 if (generated && do_ack) {
852 /* Save the interrupt causes */
853 hw->intr_cause |= hisr & HISR_INT_STS_MSK;
854 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
855 hw->intr_cause |= TXE_INTR_IN_READY;
858 mei_txe_intr_disable(dev);
859 /* Clear the interrupts in hierarchy:
860 * IPC and Bridge, than the High Level */
861 mei_txe_sec_reg_write_silent(hw,
862 SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
863 mei_txe_br_reg_write(hw, HISR_REG, hisr);
864 mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
872 * mei_txe_irq_quick_handler - The ISR of the MEI device
874 * @irq: The irq number
875 * @dev_id: pointer to the device structure
877 * returns irqreturn_t
879 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
881 struct mei_device *dev = dev_id;
883 if (mei_txe_check_and_ack_intrs(dev, true))
884 return IRQ_WAKE_THREAD;
890 * mei_txe_irq_thread_handler - txe interrupt thread
892 * @irq: The irq number
893 * @dev_id: pointer to the device structure
895 * returns irqreturn_t
898 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
900 struct mei_device *dev = (struct mei_device *) dev_id;
901 struct mei_txe_hw *hw = to_txe_hw(dev);
902 struct mei_cl_cb complete_list;
906 dev_dbg(&dev->pdev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
907 mei_txe_br_reg_read(hw, HHISR_REG),
908 mei_txe_br_reg_read(hw, HISR_REG),
909 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
912 /* initialize our complete list */
913 mutex_lock(&dev->device_lock);
914 mei_io_list_init(&complete_list);
916 if (pci_dev_msi_enabled(dev->pdev))
917 mei_txe_check_and_ack_intrs(dev, true);
919 /* show irq events */
920 mei_txe_pending_interrupts(dev);
922 hw->aliveness = mei_txe_aliveness_get(dev);
923 hw->readiness = mei_txe_readiness_get(dev);
926 * Detection of TXE driver going through reset
927 * or TXE driver resetting the HECI interface.
929 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
930 dev_dbg(&dev->pdev->dev, "Readiness Interrupt was received...\n");
932 /* Check if SeC is going through reset */
933 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
934 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
935 dev->recvd_hw_ready = true;
937 dev->recvd_hw_ready = false;
938 if (dev->dev_state != MEI_DEV_RESETTING) {
940 dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n");
941 schedule_work(&dev->reset_work);
946 wake_up(&dev->wait_hw_ready);
949 /************************************************************/
950 /* Check interrupt cause:
951 * Aliveness: Detection of SeC acknowledge of host request that
952 * it remain alive or host cancellation of that request.
955 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
956 /* Clear the interrupt cause */
957 dev_dbg(&dev->pdev->dev,
958 "Aliveness Interrupt: Status: %d\n", hw->aliveness);
959 hw->recvd_aliveness = true;
960 if (waitqueue_active(&hw->wait_aliveness))
961 wake_up(&hw->wait_aliveness);
966 * Detection of SeC having sent output to host
968 slots = mei_count_full_read_slots(dev);
969 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
971 rets = mei_irq_read_handler(dev, &complete_list, &slots);
972 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
973 dev_err(&dev->pdev->dev,
974 "mei_irq_read_handler ret = %d.\n", rets);
976 schedule_work(&dev->reset_work);
980 /* Input Ready: Detection if host can write to SeC */
981 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause))
982 dev->hbuf_is_ready = true;
984 if (hw->aliveness && dev->hbuf_is_ready) {
985 /* if SeC did not complete reading the written data by host */
986 if (!mei_txe_is_input_ready(dev)) {
987 dev_dbg(&dev->pdev->dev, "got Input Ready Int, but SEC_IPC_INPUT_STATUS_RDY is 0.\n");
991 rets = mei_irq_write_handler(dev, &complete_list);
993 dev_err(&dev->pdev->dev,
994 "mei_irq_write_handler ret = %d.\n", rets);
999 mei_irq_compl_handler(dev, &complete_list);
1002 dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets);
1004 mutex_unlock(&dev->device_lock);
1006 mei_enable_interrupts(dev);
1010 static const struct mei_hw_ops mei_txe_hw_ops = {
1012 .host_is_ready = mei_txe_host_is_ready,
1014 .hw_is_ready = mei_txe_hw_is_ready,
1015 .hw_reset = mei_txe_hw_reset,
1016 .hw_config = mei_txe_hw_config,
1017 .hw_start = mei_txe_hw_start,
1019 .intr_clear = mei_txe_intr_clear,
1020 .intr_enable = mei_txe_intr_enable,
1021 .intr_disable = mei_txe_intr_disable,
1023 .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1024 .hbuf_is_ready = mei_txe_is_input_ready,
1025 .hbuf_max_len = mei_txe_hbuf_max_len,
1027 .write = mei_txe_write,
1029 .rdbuf_full_slots = mei_txe_count_full_read_slots,
1030 .read_hdr = mei_txe_read_hdr,
1032 .read = mei_txe_read,
1037 * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1039 * @pdev - pci device
1040 * returns struct mei_device * on success or NULL;
1043 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1045 struct mei_device *dev;
1046 struct mei_txe_hw *hw;
1048 dev = kzalloc(sizeof(struct mei_device) +
1049 sizeof(struct mei_txe_hw), GFP_KERNEL);
1053 mei_device_init(dev);
1055 hw = to_txe_hw(dev);
1057 init_waitqueue_head(&hw->wait_aliveness);
1059 dev->ops = &mei_txe_hw_ops;
1066 * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1068 * @dev: the device structure
1069 * @addr: physical address start of the range
1070 * @range: physical range size
1072 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1074 struct mei_txe_hw *hw = to_txe_hw(dev);
1076 u32 lo32 = lower_32_bits(addr);
1077 u32 hi32 = upper_32_bits(addr);
1080 /* SATT is limited to 36 Bits */
1084 /* SATT has to be 16Byte aligned */
1088 /* SATT range has to be 4Bytes aligned */
1092 /* SATT is limited to 32 MB range*/
1093 if (range > SATT_RANGE_MAX)
1096 ctrl = SATT2_CTRL_VALID_MSK;
1097 ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1099 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1100 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1101 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1102 dev_dbg(&dev->pdev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",