drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include "sdhci.h"
  35
  36 #define DRIVER_NAME "sdhci"
  37
  38 #define DBG(f, x...) \
  39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  40
  41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  42         defined(CONFIG_MMC_SDHCI_MODULE))
  43 #define SDHCI_USE_LEDS_CLASS
  44 #endif
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_finish_data(struct sdhci_host *);
  52
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
  57                                         struct mmc_data *data);
  58 static int sdhci_do_get_cd(struct sdhci_host *host);
  59
  60 #ifdef CONFIG_PM
  61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  65 #else
  66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  67 {
  68         return 0;
  69 }
  70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  71 {
  72         return 0;
  73 }
  74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  75 {
  76 }
  77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  78 {
  79 }
  80 #endif
  81
  82 static void sdhci_dumpregs(struct sdhci_host *host)
  83 {
  84         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  85                 mmc_hostname(host->mmc));
  86
  87         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  88                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  89                 sdhci_readw(host, SDHCI_HOST_VERSION));
  90         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  91                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  92                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  93         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_ARGUMENT),
  95                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  96         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  98                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  99         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 100                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 101                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 102         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 103                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 104                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 105         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 106                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 107                 sdhci_readl(host, SDHCI_INT_STATUS));
 108         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 109                 sdhci_readl(host, SDHCI_INT_ENABLE),
 110                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 111         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 112                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 113                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 114         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 115                 sdhci_readl(host, SDHCI_CAPABILITIES),
 116                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 117         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_COMMAND),
 119                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 120         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 121                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 122
 123         if (host->flags & SDHCI_USE_ADMA) {
 124                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 125                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 126                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 127                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 128                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 129                 else
 130                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 131                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 132                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 133         }
 134
 135         pr_debug(DRIVER_NAME ": ===========================================\n");
 136 }
 137
 138 /*****************************************************************************\
 139  *                                                                           *
 140  * Low level functions                                                       *
 141  *                                                                           *
 142 \*****************************************************************************/
 143
 144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 145 {
 146         u32 present;
 147
 148         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 149             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 150                 return;
 151
 152         if (enable) {
 153                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                                       SDHCI_CARD_PRESENT;
 155
 156                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 157                                        SDHCI_INT_CARD_INSERT;
 158         } else {
 159                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 160         }
 161
 162         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 163         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 164 }
 165
 166 static void sdhci_enable_card_detection(struct sdhci_host *host)
 167 {
 168         sdhci_set_card_detection(host, true);
 169 }
 170
 171 static void sdhci_disable_card_detection(struct sdhci_host *host)
 172 {
 173         sdhci_set_card_detection(host, false);
 174 }
 175
 176 void sdhci_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         unsigned long timeout;
 179
 180         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 181
 182         if (mask & SDHCI_RESET_ALL) {
 183                 host->clock = 0;
 184                 /* Reset-all turns off SD Bus Power */
 185                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 186                         sdhci_runtime_pm_bus_off(host);
 187         }
 188
 189         /* Wait max 100 ms */
 190         timeout = 100;
 191
 192         /* hw clears the bit when it's done */
 193         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 194                 if (timeout == 0) {
 195                         pr_err("%s: Reset 0x%x never completed.\n",
 196                                 mmc_hostname(host->mmc), (int)mask);
 197                         sdhci_dumpregs(host);
 198                         return;
 199                 }
 200                 timeout--;
 201                 mdelay(1);
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(sdhci_reset);
 205
 206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 207 {
 208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 209                 if (!sdhci_do_get_cd(host))
 210                         return;
 211         }
 212
 213         host->ops->reset(host, mask);
 214
 215         if (mask & SDHCI_RESET_ALL) {
 216                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 217                         if (host->ops->enable_dma)
 218                                 host->ops->enable_dma(host);
 219                 }
 220
 221                 /* Resetting the controller clears many */
 222                 host->preset_enabled = false;
 223         }
 224 }
 225
 226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 227
 228 static void sdhci_init(struct sdhci_host *host, int soft)
 229 {
 230         if (soft)
 231                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 232         else
 233                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 234
 235         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 236                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 237                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 238                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 239                     SDHCI_INT_RESPONSE;
 240
 241         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 242         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 243
 244         if (soft) {
 245                 /* force clock reconfiguration */
 246                 host->clock = 0;
 247                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 248         }
 249 }
 250
 251 static void sdhci_reinit(struct sdhci_host *host)
 252 {
 253         sdhci_init(host, 0);
 254         sdhci_enable_card_detection(host);
 255 }
 256
 257 static void sdhci_activate_led(struct sdhci_host *host)
 258 {
 259         u8 ctrl;
 260
 261         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 262         ctrl |= SDHCI_CTRL_LED;
 263         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 264 }
 265
 266 static void sdhci_deactivate_led(struct sdhci_host *host)
 267 {
 268         u8 ctrl;
 269
 270         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 271         ctrl &= ~SDHCI_CTRL_LED;
 272         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 273 }
 274
 275 #ifdef SDHCI_USE_LEDS_CLASS
 276 static void sdhci_led_control(struct led_classdev *led,
 277         enum led_brightness brightness)
 278 {
 279         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 280         unsigned long flags;
 281
 282         spin_lock_irqsave(&host->lock, flags);
 283
 284         if (host->runtime_suspended)
 285                 goto out;
 286
 287         if (brightness == LED_OFF)
 288                 sdhci_deactivate_led(host);
 289         else
 290                 sdhci_activate_led(host);
 291 out:
 292         spin_unlock_irqrestore(&host->lock, flags);
 293 }
 294 #endif
 295
 296 /*****************************************************************************\
 297  *                                                                           *
 298  * Core functions                                                            *
 299  *                                                                           *
 300 \*****************************************************************************/
 301
 302 static void sdhci_read_block_pio(struct sdhci_host *host)
 303 {
 304         unsigned long flags;
 305         size_t blksize, len, chunk;
 306         u32 uninitialized_var(scratch);
 307         u8 *buf;
 308
 309         DBG("PIO reading\n");
 310
 311         blksize = host->data->blksz;
 312         chunk = 0;
 313
 314         local_irq_save(flags);
 315
 316         while (blksize) {
 317                 BUG_ON(!sg_miter_next(&host->sg_miter));
 318
 319                 len = min(host->sg_miter.length, blksize);
 320
 321                 blksize -= len;
 322                 host->sg_miter.consumed = len;
 323
 324                 buf = host->sg_miter.addr;
 325
 326                 while (len) {
 327                         if (chunk == 0) {
 328                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 329                                 chunk = 4;
 330                         }
 331
 332                         *buf = scratch & 0xFF;
 333
 334                         buf++;
 335                         scratch >>= 8;
 336                         chunk--;
 337                         len--;
 338                 }
 339         }
 340
 341         sg_miter_stop(&host->sg_miter);
 342
 343         local_irq_restore(flags);
 344 }
 345
 346 static void sdhci_write_block_pio(struct sdhci_host *host)
 347 {
 348         unsigned long flags;
 349         size_t blksize, len, chunk;
 350         u32 scratch;
 351         u8 *buf;
 352
 353         DBG("PIO writing\n");
 354
 355         blksize = host->data->blksz;
 356         chunk = 0;
 357         scratch = 0;
 358
 359         local_irq_save(flags);
 360
 361         while (blksize) {
 362                 BUG_ON(!sg_miter_next(&host->sg_miter));
 363
 364                 len = min(host->sg_miter.length, blksize);
 365
 366                 blksize -= len;
 367                 host->sg_miter.consumed = len;
 368
 369                 buf = host->sg_miter.addr;
 370
 371                 while (len) {
 372                         scratch |= (u32)*buf << (chunk * 8);
 373
 374                         buf++;
 375                         chunk++;
 376                         len--;
 377
 378                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 379                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 380                                 chunk = 0;
 381                                 scratch = 0;
 382                         }
 383                 }
 384         }
 385
 386         sg_miter_stop(&host->sg_miter);
 387
 388         local_irq_restore(flags);
 389 }
 390
 391 static void sdhci_transfer_pio(struct sdhci_host *host)
 392 {
 393         u32 mask;
 394
 395         BUG_ON(!host->data);
 396
 397         if (host->blocks == 0)
 398                 return;
 399
 400         if (host->data->flags & MMC_DATA_READ)
 401                 mask = SDHCI_DATA_AVAILABLE;
 402         else
 403                 mask = SDHCI_SPACE_AVAILABLE;
 404
 405         /*
 406          * Some controllers (JMicron JMB38x) mess up the buffer bits
 407          * for transfers < 4 bytes. As long as it is just one block,
 408          * we can ignore the bits.
 409          */
 410         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 411                 (host->data->blocks == 1))
 412                 mask = ~0;
 413
 414         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 415                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 416                         udelay(100);
 417
 418                 if (host->data->flags & MMC_DATA_READ)
 419                         sdhci_read_block_pio(host);
 420                 else
 421                         sdhci_write_block_pio(host);
 422
 423                 host->blocks--;
 424                 if (host->blocks == 0)
 425                         break;
 426         }
 427
 428         DBG("PIO transfer complete.\n");
 429 }
 430
 431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 432 {
 433         local_irq_save(*flags);
 434         return kmap_atomic(sg_page(sg)) + sg->offset;
 435 }
 436
 437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 438 {
 439         kunmap_atomic(buffer);
 440         local_irq_restore(*flags);
 441 }
 442
 443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 444                                   dma_addr_t addr, int len, unsigned cmd)
 445 {
 446         struct sdhci_adma2_64_desc *dma_desc = desc;
 447
 448         /* 32-bit and 64-bit descriptors have these members in same position */
 449         dma_desc->cmd = cpu_to_le16(cmd);
 450         dma_desc->len = cpu_to_le16(len);
 451         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 452
 453         if (host->flags & SDHCI_USE_64_BIT_DMA)
 454                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 455 }
 456
 457 static void sdhci_adma_mark_end(void *desc)
 458 {
 459         struct sdhci_adma2_64_desc *dma_desc = desc;
 460
 461         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 462         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 463 }
 464
 465 static int sdhci_adma_table_pre(struct sdhci_host *host,
 466         struct mmc_data *data)
 467 {
 468         int direction;
 469
 470         void *desc;
 471         void *align;
 472         dma_addr_t addr;
 473         dma_addr_t align_addr;
 474         int len, offset;
 475
 476         struct scatterlist *sg;
 477         int i;
 478         char *buffer;
 479         unsigned long flags;
 480
 481         /*
 482          * The spec does not specify endianness of descriptor table.
 483          * We currently guess that it is LE.
 484          */
 485
 486         if (data->flags & MMC_DATA_READ)
 487                 direction = DMA_FROM_DEVICE;
 488         else
 489                 direction = DMA_TO_DEVICE;
 490
 491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 492                 host->align_buffer, host->align_buffer_sz, direction);
 493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 494                 goto fail;
 495         BUG_ON(host->align_addr & host->align_mask);
 496
 497         host->sg_count = sdhci_pre_dma_transfer(host, data);
 498         if (host->sg_count < 0)
 499                 goto unmap_align;
 500
 501         desc = host->adma_table;
 502         align = host->align_buffer;
 503
 504         align_addr = host->align_addr;
 505
 506         for_each_sg(data->sg, sg, host->sg_count, i) {
 507                 addr = sg_dma_address(sg);
 508                 len = sg_dma_len(sg);
 509
 510                 /*
 511                  * The SDHCI specification states that ADMA
 512                  * addresses must be 32-bit aligned. If they
 513                  * aren't, then we use a bounce buffer for
 514                  * the (up to three) bytes that screw up the
 515                  * alignment.
 516                  */
 517                 offset = (host->align_sz - (addr & host->align_mask)) &
 518                          host->align_mask;
 519                 if (offset) {
 520                         if (data->flags & MMC_DATA_WRITE) {
 521                                 buffer = sdhci_kmap_atomic(sg, &flags);
 522                                 memcpy(align, buffer, offset);
 523                                 sdhci_kunmap_atomic(buffer, &flags);
 524                         }
 525
 526                         /* tran, valid */
 527                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 528                                               ADMA2_TRAN_VALID);
 529
 530                         BUG_ON(offset > 65536);
 531
 532                         align += host->align_sz;
 533                         align_addr += host->align_sz;
 534
 535                         desc += host->desc_sz;
 536
 537                         addr += offset;
 538                         len -= offset;
 539                 }
 540
 541                 BUG_ON(len > 65536);
 542
 543                 /* tran, valid */
 544                 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
 545                 desc += host->desc_sz;
 546
 547                 /*
 548                  * If this triggers then we have a calculation bug
 549                  * somewhere. :/
 550                  */
 551                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 552         }
 553
 554         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 555                 /*
 556                 * Mark the last descriptor as the terminating descriptor
 557                 */
 558                 if (desc != host->adma_table) {
 559                         desc -= host->desc_sz;
 560                         sdhci_adma_mark_end(desc);
 561                 }
 562         } else {
 563                 /*
 564                 * Add a terminating entry.
 565                 */
 566
 567                 /* nop, end, valid */
 568                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 569         }
 570
 571         /*
 572          * Resync align buffer as we might have changed it.
 573          */
 574         if (data->flags & MMC_DATA_WRITE) {
 575                 dma_sync_single_for_device(mmc_dev(host->mmc),
 576                         host->align_addr, host->align_buffer_sz, direction);
 577         }
 578
 579         return 0;
 580
 581 unmap_align:
 582         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 583                 host->align_buffer_sz, direction);
 584 fail:
 585         return -EINVAL;
 586 }
 587
 588 static void sdhci_adma_table_post(struct sdhci_host *host,
 589         struct mmc_data *data)
 590 {
 591         int direction;
 592
 593         struct scatterlist *sg;
 594         int i, size;
 595         void *align;
 596         char *buffer;
 597         unsigned long flags;
 598         bool has_unaligned;
 599
 600         if (data->flags & MMC_DATA_READ)
 601                 direction = DMA_FROM_DEVICE;
 602         else
 603                 direction = DMA_TO_DEVICE;
 604
 605         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 606                 host->align_buffer_sz, direction);
 607
 608         /* Do a quick scan of the SG list for any unaligned mappings */
 609         has_unaligned = false;
 610         for_each_sg(data->sg, sg, host->sg_count, i)
 611                 if (sg_dma_address(sg) & host->align_mask) {
 612                         has_unaligned = true;
 613                         break;
 614                 }
 615
 616         if (has_unaligned && data->flags & MMC_DATA_READ) {
 617                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 618                         data->sg_len, direction);
 619
 620                 align = host->align_buffer;
 621
 622                 for_each_sg(data->sg, sg, host->sg_count, i) {
 623                         if (sg_dma_address(sg) & host->align_mask) {
 624                                 size = host->align_sz -
 625                                        (sg_dma_address(sg) & host->align_mask);
 626
 627                                 buffer = sdhci_kmap_atomic(sg, &flags);
 628                                 memcpy(buffer, align, size);
 629                                 sdhci_kunmap_atomic(buffer, &flags);
 630
 631                                 align += host->align_sz;
 632                         }
 633                 }
 634         }
 635
 636         if (data->host_cookie == COOKIE_MAPPED) {
 637                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 638                         data->sg_len, direction);
 639                 data->host_cookie = COOKIE_UNMAPPED;
 640         }
 641 }
 642
 643 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 644 {
 645         u8 count;
 646         struct mmc_data *data = cmd->data;
 647         unsigned target_timeout, current_timeout;
 648
 649         /*
 650          * If the host controller provides us with an incorrect timeout
 651          * value, just skip the check and use 0xE.  The hardware may take
 652          * longer to time out, but that's much better than having a too-short
 653          * timeout value.
 654          */
 655         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 656                 return 0xE;
 657
 658         /* Unspecified timeout, assume max */
 659         if (!data && !cmd->busy_timeout)
 660                 return 0xE;
 661
 662         /* timeout in us */
 663         if (!data)
 664                 target_timeout = cmd->busy_timeout * 1000;
 665         else {
 666                 target_timeout = data->timeout_ns / 1000;
 667                 if (host->clock)
 668                         target_timeout += data->timeout_clks / host->clock;
 669         }
 670
 671         /*
 672          * Figure out needed cycles.
 673          * We do this in steps in order to fit inside a 32 bit int.
 674          * The first step is the minimum timeout, which will have a
 675          * minimum resolution of 6 bits:
 676          * (1) 2^13*1000 > 2^22,
 677          * (2) host->timeout_clk < 2^16
 678          *     =>
 679          *     (1) / (2) > 2^6
 680          */
 681         count = 0;
 682         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 683         while (current_timeout < target_timeout) {
 684                 count++;
 685                 current_timeout <<= 1;
 686                 if (count >= 0xF)
 687                         break;
 688         }
 689
 690         if (count >= 0xF) {
 691                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 692                     mmc_hostname(host->mmc), count, cmd->opcode);
 693                 count = 0xE;
 694         }
 695
 696         return count;
 697 }
 698
 699 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 700 {
 701         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 702         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 703
 704         if (host->flags & SDHCI_REQ_USE_DMA)
 705                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 706         else
 707                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 708
 709         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 710         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 711 }
 712
 713 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 714 {
 715         u8 count;
 716
 717         if (host->ops->set_timeout) {
 718                 host->ops->set_timeout(host, cmd);
 719         } else {
 720                 count = sdhci_calc_timeout(host, cmd);
 721                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 722         }
 723 }
 724
 725 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 726 {
 727         u8 ctrl;
 728         struct mmc_data *data = cmd->data;
 729         int ret;
 730
 731         WARN_ON(host->data);
 732
 733         if (data || (cmd->flags & MMC_RSP_BUSY))
 734                 sdhci_set_timeout(host, cmd);
 735
 736         if (!data)
 737                 return;
 738
 739         /* Sanity checks */
 740         BUG_ON(data->blksz * data->blocks > 524288);
 741         BUG_ON(data->blksz > host->mmc->max_blk_size);
 742         BUG_ON(data->blocks > 65535);
 743
 744         host->data = data;
 745         host->data_early = 0;
 746         host->data->bytes_xfered = 0;
 747
 748         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 749                 host->flags |= SDHCI_REQ_USE_DMA;
 750
 751         /*
 752          * FIXME: This doesn't account for merging when mapping the
 753          * scatterlist.
 754          */
 755         if (host->flags & SDHCI_REQ_USE_DMA) {
 756                 int broken, i;
 757                 struct scatterlist *sg;
 758
 759                 broken = 0;
 760                 if (host->flags & SDHCI_USE_ADMA) {
 761                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 762                                 broken = 1;
 763                 } else {
 764                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 765                                 broken = 1;
 766                 }
 767
 768                 if (unlikely(broken)) {
 769                         for_each_sg(data->sg, sg, data->sg_len, i) {
 770                                 if (sg->length & 0x3) {
 771                                         DBG("Reverting to PIO because of "
 772                                                 "transfer size (%d)\n",
 773                                                 sg->length);
 774                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 775                                         break;
 776                                 }
 777                         }
 778                 }
 779         }
 780
 781         /*
 782          * The assumption here being that alignment is the same after
 783          * translation to device address space.
 784          */
 785         if (host->flags & SDHCI_REQ_USE_DMA) {
 786                 int broken, i;
 787                 struct scatterlist *sg;
 788
 789                 broken = 0;
 790                 if (host->flags & SDHCI_USE_ADMA) {
 791                         /*
 792                          * As we use 3 byte chunks to work around
 793                          * alignment problems, we need to check this
 794                          * quirk.
 795                          */
 796                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 797                                 broken = 1;
 798                 } else {
 799                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 800                                 broken = 1;
 801                 }
 802
 803                 if (unlikely(broken)) {
 804                         for_each_sg(data->sg, sg, data->sg_len, i) {
 805                                 if (sg->offset & 0x3) {
 806                                         DBG("Reverting to PIO because of "
 807                                                 "bad alignment\n");
 808                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 809                                         break;
 810                                 }
 811                         }
 812                 }
 813         }
 814
 815         if (host->flags & SDHCI_REQ_USE_DMA) {
 816                 if (host->flags & SDHCI_USE_ADMA) {
 817                         ret = sdhci_adma_table_pre(host, data);
 818                         if (ret) {
 819                                 /*
 820                                  * This only happens when someone fed
 821                                  * us an invalid request.
 822                                  */
 823                                 WARN_ON(1);
 824                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 825                         } else {
 826                                 sdhci_writel(host, host->adma_addr,
 827                                         SDHCI_ADMA_ADDRESS);
 828                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 829                                         sdhci_writel(host,
 830                                                      (u64)host->adma_addr >> 32,
 831                                                      SDHCI_ADMA_ADDRESS_HI);
 832                         }
 833                 } else {
 834                         int sg_cnt;
 835
 836                         sg_cnt = sdhci_pre_dma_transfer(host, data);
 837                         if (sg_cnt <= 0) {
 838                                 /*
 839                                  * This only happens when someone fed
 840                                  * us an invalid request.
 841                                  */
 842                                 WARN_ON(1);
 843                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 844                         } else {
 845                                 WARN_ON(sg_cnt != 1);
 846                                 sdhci_writel(host, sg_dma_address(data->sg),
 847                                         SDHCI_DMA_ADDRESS);
 848                         }
 849                 }
 850         }
 851
 852         /*
 853          * Always adjust the DMA selection as some controllers
 854          * (e.g. JMicron) can't do PIO properly when the selection
 855          * is ADMA.
 856          */
 857         if (host->version >= SDHCI_SPEC_200) {
 858                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 859                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 860                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 861                         (host->flags & SDHCI_USE_ADMA)) {
 862                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 863                                 ctrl |= SDHCI_CTRL_ADMA64;
 864                         else
 865                                 ctrl |= SDHCI_CTRL_ADMA32;
 866                 } else {
 867                         ctrl |= SDHCI_CTRL_SDMA;
 868                 }
 869                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 870         }
 871
 872         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 873                 int flags;
 874
 875                 flags = SG_MITER_ATOMIC;
 876                 if (host->data->flags & MMC_DATA_READ)
 877                         flags |= SG_MITER_TO_SG;
 878                 else
 879                         flags |= SG_MITER_FROM_SG;
 880                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 881                 host->blocks = data->blocks;
 882         }
 883
 884         sdhci_set_transfer_irqs(host);
 885
 886         /* Set the DMA boundary value and block size */
 887         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 888                 data->blksz), SDHCI_BLOCK_SIZE);
 889         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 890 }
 891
 892 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 893         struct mmc_command *cmd)
 894 {
 895         u16 mode = 0;
 896         struct mmc_data *data = cmd->data;
 897
 898         if (data == NULL) {
 899                 if (host->quirks2 &
 900                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 901                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 902                 } else {
 903                 /* clear Auto CMD settings for no data CMDs */
 904                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 905                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 906                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 907                 }
 908                 return;
 909         }
 910
 911         WARN_ON(!host->data);
 912
 913         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 914                 mode = SDHCI_TRNS_BLK_CNT_EN;
 915
 916         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 917                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 918                 /*
 919                  * If we are sending CMD23, CMD12 never gets sent
 920                  * on successful completion (so no Auto-CMD12).
 921                  */
 922                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 923                     (cmd->opcode != SD_IO_RW_EXTENDED))
 924                         mode |= SDHCI_TRNS_AUTO_CMD12;
 925                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 926                         mode |= SDHCI_TRNS_AUTO_CMD23;
 927                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 928                 }
 929         }
 930
 931         if (data->flags & MMC_DATA_READ)
 932                 mode |= SDHCI_TRNS_READ;
 933         if (host->flags & SDHCI_REQ_USE_DMA)
 934                 mode |= SDHCI_TRNS_DMA;
 935
 936         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 937 }
 938
 939 static void sdhci_finish_data(struct sdhci_host *host)
 940 {
 941         struct mmc_data *data;
 942
 943         BUG_ON(!host->data);
 944
 945         data = host->data;
 946         host->data = NULL;
 947
 948         if (host->flags & SDHCI_REQ_USE_DMA) {
 949                 if (host->flags & SDHCI_USE_ADMA)
 950                         sdhci_adma_table_post(host, data);
 951                 else {
 952                         if (data->host_cookie == COOKIE_MAPPED) {
 953                                 dma_unmap_sg(mmc_dev(host->mmc),
 954                                         data->sg, data->sg_len,
 955                                         (data->flags & MMC_DATA_READ) ?
 956                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 957                                 data->host_cookie = COOKIE_UNMAPPED;
 958                         }
 959                 }
 960         }
 961
 962         /*
 963          * The specification states that the block count register must
 964          * be updated, but it does not specify at what point in the
 965          * data flow. That makes the register entirely useless to read
 966          * back so we have to assume that nothing made it to the card
 967          * in the event of an error.
 968          */
 969         if (data->error)
 970                 data->bytes_xfered = 0;
 971         else
 972                 data->bytes_xfered = data->blksz * data->blocks;
 973
 974         /*
 975          * Need to send CMD12 if -
 976          * a) open-ended multiblock transfer (no CMD23)
 977          * b) error in multiblock transfer
 978          */
 979         if (data->stop &&
 980             (data->error ||
 981              !host->mrq->sbc)) {
 982
 983                 /*
 984                  * The controller needs a reset of internal state machines
 985                  * upon error conditions.
 986                  */
 987                 if (data->error) {
 988                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 989                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 990                 }
 991
 992                 sdhci_send_command(host, data->stop);
 993         } else
 994                 tasklet_schedule(&host->finish_tasklet);
 995 }
 996
 997 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 998 {
 999         int flags;
1000         u32 mask;
1001         unsigned long timeout;
1002
1003         WARN_ON(host->cmd);
1004
1005         /* Wait max 10 ms */
1006         timeout = 10;
1007
1008         mask = SDHCI_CMD_INHIBIT;
1009         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1010                 mask |= SDHCI_DATA_INHIBIT;
1011
1012         /* We shouldn't wait for data inihibit for stop commands, even
1013            though they might use busy signaling */
1014         if (host->mrq->data && (cmd == host->mrq->data->stop))
1015                 mask &= ~SDHCI_DATA_INHIBIT;
1016
1017         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1018                 if (timeout == 0) {
1019                         pr_err("%s: Controller never released "
1020                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1021                         sdhci_dumpregs(host);
1022                         cmd->error = -EIO;
1023                         tasklet_schedule(&host->finish_tasklet);
1024                         return;
1025                 }
1026                 timeout--;
1027                 mdelay(1);
1028         }
1029
1030         timeout = jiffies;
1031         if (!cmd->data && cmd->busy_timeout > 9000)
1032                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1033         else
1034                 timeout += 10 * HZ;
1035         mod_timer(&host->timer, timeout);
1036
1037         host->cmd = cmd;
1038         host->busy_handle = 0;
1039
1040         sdhci_prepare_data(host, cmd);
1041
1042         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1043
1044         sdhci_set_transfer_mode(host, cmd);
1045
1046         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1047                 pr_err("%s: Unsupported response type!\n",
1048                         mmc_hostname(host->mmc));
1049                 cmd->error = -EINVAL;
1050                 tasklet_schedule(&host->finish_tasklet);
1051                 return;
1052         }
1053
1054         if (!(cmd->flags & MMC_RSP_PRESENT))
1055                 flags = SDHCI_CMD_RESP_NONE;
1056         else if (cmd->flags & MMC_RSP_136)
1057                 flags = SDHCI_CMD_RESP_LONG;
1058         else if (cmd->flags & MMC_RSP_BUSY)
1059                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1060         else
1061                 flags = SDHCI_CMD_RESP_SHORT;
1062
1063         if (cmd->flags & MMC_RSP_CRC)
1064                 flags |= SDHCI_CMD_CRC;
1065         if (cmd->flags & MMC_RSP_OPCODE)
1066                 flags |= SDHCI_CMD_INDEX;
1067
1068         /* CMD19 is special in that the Data Present Select should be set */
1069         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1070             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1071                 flags |= SDHCI_CMD_DATA;
1072
1073         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1074 }
1075 EXPORT_SYMBOL_GPL(sdhci_send_command);
1076
1077 static void sdhci_finish_command(struct sdhci_host *host)
1078 {
1079         int i;
1080
1081         BUG_ON(host->cmd == NULL);
1082
1083         if (host->cmd->flags & MMC_RSP_PRESENT) {
1084                 if (host->cmd->flags & MMC_RSP_136) {
1085                         /* CRC is stripped so we need to do some shifting. */
1086                         for (i = 0;i < 4;i++) {
1087                                 host->cmd->resp[i] = sdhci_readl(host,
1088                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1089                                 if (i != 3)
1090                                         host->cmd->resp[i] |=
1091                                                 sdhci_readb(host,
1092                                                 SDHCI_RESPONSE + (3-i)*4-1);
1093                         }
1094                 } else {
1095                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1096                 }
1097         }
1098
1099         host->cmd->error = 0;
1100
1101         /* Finished CMD23, now send actual command. */
1102         if (host->cmd == host->mrq->sbc) {
1103                 host->cmd = NULL;
1104                 sdhci_send_command(host, host->mrq->cmd);
1105         } else {
1106
1107                 /* Processed actual command. */
1108                 if (host->data && host->data_early)
1109                         sdhci_finish_data(host);
1110
1111                 if (!host->cmd->data)
1112                         tasklet_schedule(&host->finish_tasklet);
1113
1114                 host->cmd = NULL;
1115         }
1116 }
1117
1118 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1119 {
1120         u16 preset = 0;
1121
1122         switch (host->timing) {
1123         case MMC_TIMING_UHS_SDR12:
1124                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1125                 break;
1126         case MMC_TIMING_UHS_SDR25:
1127                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1128                 break;
1129         case MMC_TIMING_UHS_SDR50:
1130                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1131                 break;
1132         case MMC_TIMING_UHS_SDR104:
1133         case MMC_TIMING_MMC_HS200:
1134                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1135                 break;
1136         case MMC_TIMING_UHS_DDR50:
1137         case MMC_TIMING_MMC_DDR52:
1138                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1139                 break;
1140         case MMC_TIMING_MMC_HS400:
1141                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1142                 break;
1143         default:
1144                 pr_warn("%s: Invalid UHS-I mode selected\n",
1145                         mmc_hostname(host->mmc));
1146                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1147                 break;
1148         }
1149         return preset;
1150 }
1151
1152 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1153 {
1154         int div = 0; /* Initialized for compiler warning */
1155         int real_div = div, clk_mul = 1;
1156         u16 clk = 0;
1157         unsigned long timeout;
1158         bool switch_base_clk = false;
1159
1160         host->mmc->actual_clock = 0;
1161
1162         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1163         if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1164                 mdelay(1);
1165
1166         if (clock == 0)
1167                 return;
1168
1169         if (host->version >= SDHCI_SPEC_300) {
1170                 if (host->preset_enabled) {
1171                         u16 pre_val;
1172
1173                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1174                         pre_val = sdhci_get_preset_value(host);
1175                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1176                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1177                         if (host->clk_mul &&
1178                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1179                                 clk = SDHCI_PROG_CLOCK_MODE;
1180                                 real_div = div + 1;
1181                                 clk_mul = host->clk_mul;
1182                         } else {
1183                                 real_div = max_t(int, 1, div << 1);
1184                         }
1185                         goto clock_set;
1186                 }
1187
1188                 /*
1189                  * Check if the Host Controller supports Programmable Clock
1190                  * Mode.
1191                  */
1192                 if (host->clk_mul) {
1193                         for (div = 1; div <= 1024; div++) {
1194                                 if ((host->max_clk * host->clk_mul / div)
1195                                         <= clock)
1196                                         break;
1197                         }
1198                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1199                                 /*
1200                                  * Set Programmable Clock Mode in the Clock
1201                                  * Control register.
1202                                  */
1203                                 clk = SDHCI_PROG_CLOCK_MODE;
1204                                 real_div = div;
1205                                 clk_mul = host->clk_mul;
1206                                 div--;
1207                         } else {
1208                                 /*
1209                                  * Divisor can be too small to reach clock
1210                                  * speed requirement. Then use the base clock.
1211                                  */
1212                                 switch_base_clk = true;
1213                         }
1214                 }
1215
1216                 if (!host->clk_mul || switch_base_clk) {
1217                         /* Version 3.00 divisors must be a multiple of 2. */
1218                         if (host->max_clk <= clock)
1219                                 div = 1;
1220                         else {
1221                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1222                                      div += 2) {
1223                                         if ((host->max_clk / div) <= clock)
1224                                                 break;
1225                                 }
1226                         }
1227                         real_div = div;
1228                         div >>= 1;
1229                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1230                                 && !div && host->max_clk <= 25000000)
1231                                 div = 1;
1232                 }
1233         } else {
1234                 /* Version 2.00 divisors must be a power of 2. */
1235                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1236                         if ((host->max_clk / div) <= clock)
1237                                 break;
1238                 }
1239                 real_div = div;
1240                 div >>= 1;
1241         }
1242
1243 clock_set:
1244         if (real_div)
1245                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1246         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1247         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1248                 << SDHCI_DIVIDER_HI_SHIFT;
1249         clk |= SDHCI_CLOCK_INT_EN;
1250         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1251
1252         /* Wait max 20 ms */
1253         timeout = 20;
1254         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1255                 & SDHCI_CLOCK_INT_STABLE)) {
1256                 if (timeout == 0) {
1257                         pr_err("%s: Internal clock never "
1258                                 "stabilised.\n", mmc_hostname(host->mmc));
1259                         sdhci_dumpregs(host);
1260                         return;
1261                 }
1262                 timeout--;
1263                 mdelay(1);
1264         }
1265
1266         clk |= SDHCI_CLOCK_CARD_EN;
1267         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1268 }
1269 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1270
1271 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1272                             unsigned short vdd)
1273 {
1274         struct mmc_host *mmc = host->mmc;
1275         u8 pwr = 0;
1276
1277         if (!IS_ERR(mmc->supply.vmmc)) {
1278                 spin_unlock_irq(&host->lock);
1279                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1280                 spin_lock_irq(&host->lock);
1281
1282                 if (mode != MMC_POWER_OFF)
1283                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1284                 else
1285                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1286
1287                 return;
1288         }
1289
1290         if (mode != MMC_POWER_OFF) {
1291                 switch (1 << vdd) {
1292                 case MMC_VDD_165_195:
1293                         pwr = SDHCI_POWER_180;
1294                         break;
1295                 case MMC_VDD_29_30:
1296                 case MMC_VDD_30_31:
1297                         pwr = SDHCI_POWER_300;
1298                         break;
1299                 case MMC_VDD_32_33:
1300                 case MMC_VDD_33_34:
1301                         pwr = SDHCI_POWER_330;
1302                         break;
1303                 default:
1304                         BUG();
1305                 }
1306         }
1307
1308         if (host->pwr == pwr)
1309                 return;
1310
1311         host->pwr = pwr;
1312
1313         if (pwr == 0) {
1314                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1315                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1316                         sdhci_runtime_pm_bus_off(host);
1317                 vdd = 0;
1318         } else {
1319                 /*
1320                  * Spec says that we should clear the power reg before setting
1321                  * a new value. Some controllers don't seem to like this though.
1322                  */
1323                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1324                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1325
1326                 /*
1327                  * At least the Marvell CaFe chip gets confused if we set the
1328                  * voltage and set turn on power at the same time, so set the
1329                  * voltage first.
1330                  */
1331                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1332                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1333
1334                 pwr |= SDHCI_POWER_ON;
1335
1336                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1337
1338                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1339                         sdhci_runtime_pm_bus_on(host);
1340
1341                 /*
1342                  * Some controllers need an extra 10ms delay of 10ms before
1343                  * they can apply clock after applying power
1344                  */
1345                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1346                         mdelay(10);
1347         }
1348 }
1349
1350 /*****************************************************************************\
1351  *                                                                           *
1352  * MMC callbacks                                                             *
1353  *                                                                           *
1354 \*****************************************************************************/
1355
1356 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1357 {
1358         struct sdhci_host *host;
1359         int present;
1360         unsigned long flags;
1361
1362         host = mmc_priv(mmc);
1363
1364         sdhci_runtime_pm_get(host);
1365
1366         /* Firstly check card presence */
1367         present = sdhci_do_get_cd(host);
1368
1369         spin_lock_irqsave(&host->lock, flags);
1370
1371         WARN_ON(host->mrq != NULL);
1372
1373 #ifndef SDHCI_USE_LEDS_CLASS
1374         sdhci_activate_led(host);
1375 #endif
1376
1377         /*
1378          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1379          * requests if Auto-CMD12 is enabled.
1380          */
1381         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1382                 if (mrq->stop) {
1383                         mrq->data->stop = NULL;
1384                         mrq->stop = NULL;
1385                 }
1386         }
1387
1388         host->mrq = mrq;
1389
1390         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1391                 host->mrq->cmd->error = -ENOMEDIUM;
1392                 tasklet_schedule(&host->finish_tasklet);
1393         } else {
1394                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1395                         sdhci_send_command(host, mrq->sbc);
1396                 else
1397                         sdhci_send_command(host, mrq->cmd);
1398         }
1399
1400         mmiowb();
1401         spin_unlock_irqrestore(&host->lock, flags);
1402 }
1403
1404 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1405 {
1406         u8 ctrl;
1407
1408         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1409         if (width == MMC_BUS_WIDTH_8) {
1410                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1411                 if (host->version >= SDHCI_SPEC_300)
1412                         ctrl |= SDHCI_CTRL_8BITBUS;
1413         } else {
1414                 if (host->version >= SDHCI_SPEC_300)
1415                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1416                 if (width == MMC_BUS_WIDTH_4)
1417                         ctrl |= SDHCI_CTRL_4BITBUS;
1418                 else
1419                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1420         }
1421         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1422 }
1423 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1424
1425 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1426 {
1427         u16 ctrl_2;
1428
1429         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1430         /* Select Bus Speed Mode for host */
1431         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1432         if ((timing == MMC_TIMING_MMC_HS200) ||
1433             (timing == MMC_TIMING_UHS_SDR104))
1434                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1435         else if (timing == MMC_TIMING_UHS_SDR12)
1436                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1437         else if (timing == MMC_TIMING_UHS_SDR25)
1438                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1439         else if (timing == MMC_TIMING_UHS_SDR50)
1440                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1441         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1442                  (timing == MMC_TIMING_MMC_DDR52))
1443                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1444         else if (timing == MMC_TIMING_MMC_HS400)
1445                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1446         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1447 }
1448 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1449
1450 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1451 {
1452         unsigned long flags;
1453         u8 ctrl;
1454         struct mmc_host *mmc = host->mmc;
1455
1456         spin_lock_irqsave(&host->lock, flags);
1457
1458         if (host->flags & SDHCI_DEVICE_DEAD) {
1459                 spin_unlock_irqrestore(&host->lock, flags);
1460                 if (!IS_ERR(mmc->supply.vmmc) &&
1461                     ios->power_mode == MMC_POWER_OFF)
1462                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1463                 return;
1464         }
1465
1466         /*
1467          * Reset the chip on each power off.
1468          * Should clear out any weird states.
1469          */
1470         if (ios->power_mode == MMC_POWER_OFF) {
1471                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1472                 sdhci_reinit(host);
1473         }
1474
1475         if (host->version >= SDHCI_SPEC_300 &&
1476                 (ios->power_mode == MMC_POWER_UP) &&
1477                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1478                 sdhci_enable_preset_value(host, false);
1479
1480         if (!ios->clock || ios->clock != host->clock) {
1481                 host->ops->set_clock(host, ios->clock);
1482                 host->clock = ios->clock;
1483
1484                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1485                     host->clock) {
1486                         host->timeout_clk = host->mmc->actual_clock ?
1487                                                 host->mmc->actual_clock / 1000 :
1488                                                 host->clock / 1000;
1489                         host->mmc->max_busy_timeout =
1490                                 host->ops->get_max_timeout_count ?
1491                                 host->ops->get_max_timeout_count(host) :
1492                                 1 << 27;
1493                         host->mmc->max_busy_timeout /= host->timeout_clk;
1494                 }
1495         }
1496
1497         sdhci_set_power(host, ios->power_mode, ios->vdd);
1498
1499         if (host->ops->platform_send_init_74_clocks)
1500                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1501
1502         host->ops->set_bus_width(host, ios->bus_width);
1503
1504         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1505
1506         if ((ios->timing == MMC_TIMING_SD_HS ||
1507              ios->timing == MMC_TIMING_MMC_HS)
1508             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1509                 ctrl |= SDHCI_CTRL_HISPD;
1510         else
1511                 ctrl &= ~SDHCI_CTRL_HISPD;
1512
1513         if (host->version >= SDHCI_SPEC_300) {
1514                 u16 clk, ctrl_2;
1515
1516                 /* In case of UHS-I modes, set High Speed Enable */
1517                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1518                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1519                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1520                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1521                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1522                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1523                     (ios->timing == MMC_TIMING_UHS_SDR25))
1524                         ctrl |= SDHCI_CTRL_HISPD;
1525
1526                 if (!host->preset_enabled) {
1527                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1528                         /*
1529                          * We only need to set Driver Strength if the
1530                          * preset value enable is not set.
1531                          */
1532                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1533                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1534                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1535                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1536                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1537                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1538                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1539                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1540                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1541                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1542                         else {
1543                                 pr_warn("%s: invalid driver type, default to "
1544                                         "driver type B\n", mmc_hostname(mmc));
1545                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1546                         }
1547
1548                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1549                 } else {
1550                         /*
1551                          * According to SDHC Spec v3.00, if the Preset Value
1552                          * Enable in the Host Control 2 register is set, we
1553                          * need to reset SD Clock Enable before changing High
1554                          * Speed Enable to avoid generating clock gliches.
1555                          */
1556
1557                         /* Reset SD Clock Enable */
1558                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1559                         clk &= ~SDHCI_CLOCK_CARD_EN;
1560                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1561
1562                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1563
1564                         /* Re-enable SD Clock */
1565                         host->ops->set_clock(host, host->clock);
1566                 }
1567
1568                 /* Reset SD Clock Enable */
1569                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1570                 clk &= ~SDHCI_CLOCK_CARD_EN;
1571                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1572
1573                 host->ops->set_uhs_signaling(host, ios->timing);
1574                 host->timing = ios->timing;
1575
1576                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1577                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1578                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1579                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1580                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1581                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1582                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1583                         u16 preset;
1584
1585                         sdhci_enable_preset_value(host, true);
1586                         preset = sdhci_get_preset_value(host);
1587                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1588                                 >> SDHCI_PRESET_DRV_SHIFT;
1589                 }
1590
1591                 /* Re-enable SD Clock */
1592                 host->ops->set_clock(host, host->clock);
1593         } else
1594                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1595
1596         /*
1597          * Some (ENE) controllers go apeshit on some ios operation,
1598          * signalling timeout and CRC errors even on CMD0. Resetting
1599          * it on each ios seems to solve the problem.
1600          */
1601         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1602                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1603
1604         mmiowb();
1605         spin_unlock_irqrestore(&host->lock, flags);
1606 }
1607
1608 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1609 {
1610         struct sdhci_host *host = mmc_priv(mmc);
1611
1612         sdhci_runtime_pm_get(host);
1613         sdhci_do_set_ios(host, ios);
1614         sdhci_runtime_pm_put(host);
1615 }
1616
1617 static int sdhci_do_get_cd(struct sdhci_host *host)
1618 {
1619         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1620
1621         if (host->flags & SDHCI_DEVICE_DEAD)
1622                 return 0;
1623
1624         /* If nonremovable, assume that the card is always present. */
1625         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1626                 return 1;
1627
1628         /*
1629          * Try slot gpio detect, if defined it take precedence
1630          * over build in controller functionality
1631          */
1632         if (!IS_ERR_VALUE(gpio_cd))
1633                 return !!gpio_cd;
1634
1635         /* If polling, assume that the card is always present. */
1636         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1637                 return 1;
1638
1639         /* Host native card detect */
1640         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1641 }
1642
1643 static int sdhci_get_cd(struct mmc_host *mmc)
1644 {
1645         struct sdhci_host *host = mmc_priv(mmc);
1646         int ret;
1647
1648         sdhci_runtime_pm_get(host);
1649         ret = sdhci_do_get_cd(host);
1650         sdhci_runtime_pm_put(host);
1651         return ret;
1652 }
1653
1654 static int sdhci_check_ro(struct sdhci_host *host)
1655 {
1656         unsigned long flags;
1657         int is_readonly;
1658
1659         spin_lock_irqsave(&host->lock, flags);
1660
1661         if (host->flags & SDHCI_DEVICE_DEAD)
1662                 is_readonly = 0;
1663         else if (host->ops->get_ro)
1664                 is_readonly = host->ops->get_ro(host);
1665         else
1666                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1667                                 & SDHCI_WRITE_PROTECT);
1668
1669         spin_unlock_irqrestore(&host->lock, flags);
1670
1671         /* This quirk needs to be replaced by a callback-function later */
1672         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1673                 !is_readonly : is_readonly;
1674 }
1675
1676 #define SAMPLE_COUNT    5
1677
1678 static int sdhci_do_get_ro(struct sdhci_host *host)
1679 {
1680         int i, ro_count;
1681
1682         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1683                 return sdhci_check_ro(host);
1684
1685         ro_count = 0;
1686         for (i = 0; i < SAMPLE_COUNT; i++) {
1687                 if (sdhci_check_ro(host)) {
1688                         if (++ro_count > SAMPLE_COUNT / 2)
1689                                 return 1;
1690                 }
1691                 msleep(30);
1692         }
1693         return 0;
1694 }
1695
1696 static void sdhci_hw_reset(struct mmc_host *mmc)
1697 {
1698         struct sdhci_host *host = mmc_priv(mmc);
1699
1700         if (host->ops && host->ops->hw_reset)
1701                 host->ops->hw_reset(host);
1702 }
1703
1704 static int sdhci_get_ro(struct mmc_host *mmc)
1705 {
1706         struct sdhci_host *host = mmc_priv(mmc);
1707         int ret;
1708
1709         sdhci_runtime_pm_get(host);
1710         ret = sdhci_do_get_ro(host);
1711         sdhci_runtime_pm_put(host);
1712         return ret;
1713 }
1714
1715 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1716 {
1717         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1718                 if (enable)
1719                         host->ier |= SDHCI_INT_CARD_INT;
1720                 else
1721                         host->ier &= ~SDHCI_INT_CARD_INT;
1722
1723                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1724                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1725                 mmiowb();
1726         }
1727 }
1728
1729 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1730 {
1731         struct sdhci_host *host = mmc_priv(mmc);
1732         unsigned long flags;
1733
1734         sdhci_runtime_pm_get(host);
1735
1736         spin_lock_irqsave(&host->lock, flags);
1737         if (enable)
1738                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1739         else
1740                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1741
1742         sdhci_enable_sdio_irq_nolock(host, enable);
1743         spin_unlock_irqrestore(&host->lock, flags);
1744
1745         sdhci_runtime_pm_put(host);
1746 }
1747
1748 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1749                                                 struct mmc_ios *ios)
1750 {
1751         struct mmc_host *mmc = host->mmc;
1752         u16 ctrl;
1753         int ret;
1754
1755         /*
1756          * Signal Voltage Switching is only applicable for Host Controllers
1757          * v3.00 and above.
1758          */
1759         if (host->version < SDHCI_SPEC_300)
1760                 return 0;
1761
1762         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1763
1764         switch (ios->signal_voltage) {
1765         case MMC_SIGNAL_VOLTAGE_330:
1766                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1767                 ctrl &= ~SDHCI_CTRL_VDD_180;
1768                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1769
1770                 if (!IS_ERR(mmc->supply.vqmmc)) {
1771                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1772                                                     3600000);
1773                         if (ret) {
1774                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1775                                         mmc_hostname(mmc));
1776                                 return -EIO;
1777                         }
1778                 }
1779                 /* Wait for 5ms */
1780                 usleep_range(5000, 5500);
1781
1782                 /* 3.3V regulator output should be stable within 5 ms */
1783                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1784                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1785                         return 0;
1786
1787                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1788                         mmc_hostname(mmc));
1789
1790                 return -EAGAIN;
1791         case MMC_SIGNAL_VOLTAGE_180:
1792                 if (!IS_ERR(mmc->supply.vqmmc)) {
1793                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1794                                         1700000, 1950000);
1795                         if (ret) {
1796                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1797                                         mmc_hostname(mmc));
1798                                 return -EIO;
1799                         }
1800                 }
1801
1802                 /*
1803                  * Enable 1.8V Signal Enable in the Host Control2
1804                  * register
1805                  */
1806                 ctrl |= SDHCI_CTRL_VDD_180;
1807                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1808
1809                 /* Some controller need to do more when switching */
1810                 if (host->ops->voltage_switch)
1811                         host->ops->voltage_switch(host);
1812
1813                 /* 1.8V regulator output should be stable within 5 ms */
1814                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1815                 if (ctrl & SDHCI_CTRL_VDD_180)
1816                         return 0;
1817
1818                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1819                         mmc_hostname(mmc));
1820
1821                 return -EAGAIN;
1822         case MMC_SIGNAL_VOLTAGE_120:
1823                 if (!IS_ERR(mmc->supply.vqmmc)) {
1824                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1825                                                     1300000);
1826                         if (ret) {
1827                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1828                                         mmc_hostname(mmc));
1829                                 return -EIO;
1830                         }
1831                 }
1832                 return 0;
1833         default:
1834                 /* No signal voltage switch required */
1835                 return 0;
1836         }
1837 }
1838
1839 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1840         struct mmc_ios *ios)
1841 {
1842         struct sdhci_host *host = mmc_priv(mmc);
1843         int err;
1844
1845         if (host->version < SDHCI_SPEC_300)
1846                 return 0;
1847         sdhci_runtime_pm_get(host);
1848         err = sdhci_do_start_signal_voltage_switch(host, ios);
1849         sdhci_runtime_pm_put(host);
1850         return err;
1851 }
1852
1853 static int sdhci_card_busy(struct mmc_host *mmc)
1854 {
1855         struct sdhci_host *host = mmc_priv(mmc);
1856         u32 present_state;
1857
1858         sdhci_runtime_pm_get(host);
1859         /* Check whether DAT[3:0] is 0000 */
1860         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1861         sdhci_runtime_pm_put(host);
1862
1863         return !(present_state & SDHCI_DATA_LVL_MASK);
1864 }
1865
1866 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1867 {
1868         struct sdhci_host *host = mmc_priv(mmc);
1869         unsigned long flags;
1870
1871         spin_lock_irqsave(&host->lock, flags);
1872         host->flags |= SDHCI_HS400_TUNING;
1873         spin_unlock_irqrestore(&host->lock, flags);
1874
1875         return 0;
1876 }
1877
1878 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1879 {
1880         struct sdhci_host *host = mmc_priv(mmc);
1881         u16 ctrl;
1882         int tuning_loop_counter = MAX_TUNING_LOOP;
1883         int err = 0;
1884         unsigned long flags;
1885         unsigned int tuning_count = 0;
1886         bool hs400_tuning;
1887
1888         sdhci_runtime_pm_get(host);
1889         spin_lock_irqsave(&host->lock, flags);
1890
1891         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1892         host->flags &= ~SDHCI_HS400_TUNING;
1893
1894         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1895                 tuning_count = host->tuning_count;
1896
1897         /*
1898          * The Host Controller needs tuning only in case of SDR104 mode
1899          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1900          * Capabilities register.
1901          * If the Host Controller supports the HS200 mode then the
1902          * tuning function has to be executed.
1903          */
1904         switch (host->timing) {
1905         /* HS400 tuning is done in HS200 mode */
1906         case MMC_TIMING_MMC_HS400:
1907                 err = -EINVAL;
1908                 goto out_unlock;
1909
1910         case MMC_TIMING_MMC_HS200:
1911                 /*
1912                  * Periodic re-tuning for HS400 is not expected to be needed, so
1913                  * disable it here.
1914                  */
1915                 if (hs400_tuning)
1916                         tuning_count = 0;
1917                 break;
1918
1919         case MMC_TIMING_UHS_SDR104:
1920                 break;
1921
1922         case MMC_TIMING_UHS_SDR50:
1923                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1924                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1925                         break;
1926                 /* FALLTHROUGH */
1927
1928         default:
1929                 goto out_unlock;
1930         }
1931
1932         if (host->ops->platform_execute_tuning) {
1933                 spin_unlock_irqrestore(&host->lock, flags);
1934                 err = host->ops->platform_execute_tuning(host, opcode);
1935                 sdhci_runtime_pm_put(host);
1936                 return err;
1937         }
1938
1939         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1940         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1941         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1942                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1943         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1944
1945         /*
1946          * As per the Host Controller spec v3.00, tuning command
1947          * generates Buffer Read Ready interrupt, so enable that.
1948          *
1949          * Note: The spec clearly says that when tuning sequence
1950          * is being performed, the controller does not generate
1951          * interrupts other than Buffer Read Ready interrupt. But
1952          * to make sure we don't hit a controller bug, we _only_
1953          * enable Buffer Read Ready interrupt here.
1954          */
1955         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1956         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1957
1958         /*
1959          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1960          * of loops reaches 40 times or a timeout of 150ms occurs.
1961          */
1962         do {
1963                 struct mmc_command cmd = {0};
1964                 struct mmc_request mrq = {NULL};
1965
1966                 cmd.opcode = opcode;
1967                 cmd.arg = 0;
1968                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1969                 cmd.retries = 0;
1970                 cmd.data = NULL;
1971                 cmd.error = 0;
1972
1973                 if (tuning_loop_counter-- == 0)
1974                         break;
1975
1976                 mrq.cmd = &cmd;
1977                 host->mrq = &mrq;
1978
1979                 /*
1980                  * In response to CMD19, the card sends 64 bytes of tuning
1981                  * block to the Host Controller. So we set the block size
1982                  * to 64 here.
1983                  */
1984                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1985                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1986                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1987                                              SDHCI_BLOCK_SIZE);
1988                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1989                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1990                                              SDHCI_BLOCK_SIZE);
1991                 } else {
1992                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1993                                      SDHCI_BLOCK_SIZE);
1994                 }
1995
1996                 /*
1997                  * The tuning block is sent by the card to the host controller.
1998                  * So we set the TRNS_READ bit in the Transfer Mode register.
1999                  * This also takes care of setting DMA Enable and Multi Block
2000                  * Select in the same register to 0.
2001                  */
2002                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2003
2004                 sdhci_send_command(host, &cmd);
2005
2006                 host->cmd = NULL;
2007                 host->mrq = NULL;
2008
2009                 spin_unlock_irqrestore(&host->lock, flags);
2010                 /* Wait for Buffer Read Ready interrupt */
2011                 wait_event_interruptible_timeout(host->buf_ready_int,
2012                                         (host->tuning_done == 1),
2013                                         msecs_to_jiffies(50));
2014                 spin_lock_irqsave(&host->lock, flags);
2015
2016                 if (!host->tuning_done) {
2017                         pr_info(DRIVER_NAME ": Timeout waiting for "
2018                                 "Buffer Read Ready interrupt during tuning "
2019                                 "procedure, falling back to fixed sampling "
2020                                 "clock\n");
2021                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2022                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2023                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2024                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2025
2026                         err = -EIO;
2027                         goto out;
2028                 }
2029
2030                 host->tuning_done = 0;
2031
2032                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2033
2034                 /* eMMC spec does not require a delay between tuning cycles */
2035                 if (opcode == MMC_SEND_TUNING_BLOCK)
2036                         mdelay(1);
2037         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2038
2039         /*
2040          * The Host Driver has exhausted the maximum number of loops allowed,
2041          * so use fixed sampling frequency.
2042          */
2043         if (tuning_loop_counter < 0) {
2044                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2045                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2046         }
2047         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2048                 pr_info(DRIVER_NAME ": Tuning procedure"
2049                         " failed, falling back to fixed sampling"
2050                         " clock\n");
2051                 err = -EIO;
2052         }
2053
2054 out:
2055         if (tuning_count) {
2056                 /*
2057                  * In case tuning fails, host controllers which support
2058                  * re-tuning can try tuning again at a later time, when the
2059                  * re-tuning timer expires.  So for these controllers, we
2060                  * return 0. Since there might be other controllers who do not
2061                  * have this capability, we return error for them.
2062                  */
2063                 err = 0;
2064         }
2065
2066         host->mmc->retune_period = err ? 0 : tuning_count;
2067
2068         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2069         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2070 out_unlock:
2071         spin_unlock_irqrestore(&host->lock, flags);
2072         sdhci_runtime_pm_put(host);
2073
2074         return err;
2075 }
2076
2077 static int sdhci_select_drive_strength(struct mmc_card *card,
2078                                        unsigned int max_dtr, int host_drv,
2079                                        int card_drv, int *drv_type)
2080 {
2081         struct sdhci_host *host = mmc_priv(card->host);
2082
2083         if (!host->ops->select_drive_strength)
2084                 return 0;
2085
2086         return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2087                                                 card_drv, drv_type);
2088 }
2089
2090 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2091 {
2092         /* Host Controller v3.00 defines preset value registers */
2093         if (host->version < SDHCI_SPEC_300)
2094                 return;
2095
2096         /*
2097          * We only enable or disable Preset Value if they are not already
2098          * enabled or disabled respectively. Otherwise, we bail out.
2099          */
2100         if (host->preset_enabled != enable) {
2101                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2102
2103                 if (enable)
2104                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2105                 else
2106                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2107
2108                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2109
2110                 if (enable)
2111                         host->flags |= SDHCI_PV_ENABLED;
2112                 else
2113                         host->flags &= ~SDHCI_PV_ENABLED;
2114
2115                 host->preset_enabled = enable;
2116         }
2117 }
2118
2119 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2120                                 int err)
2121 {
2122         struct sdhci_host *host = mmc_priv(mmc);
2123         struct mmc_data *data = mrq->data;
2124
2125         if (host->flags & SDHCI_REQ_USE_DMA) {
2126                 if (data->host_cookie == COOKIE_GIVEN ||
2127                                 data->host_cookie == COOKIE_MAPPED)
2128                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2129                                          data->flags & MMC_DATA_WRITE ?
2130                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2131                 data->host_cookie = COOKIE_UNMAPPED;
2132         }
2133 }
2134
2135 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2136                                        struct mmc_data *data)
2137 {
2138         int sg_count;
2139
2140         if (data->host_cookie == COOKIE_MAPPED) {
2141                 data->host_cookie = COOKIE_GIVEN;
2142                 return data->sg_count;
2143         }
2144
2145         WARN_ON(data->host_cookie == COOKIE_GIVEN);
2146
2147         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2148                                 data->flags & MMC_DATA_WRITE ?
2149                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2150
2151         if (sg_count == 0)
2152                 return -ENOSPC;
2153
2154         data->sg_count = sg_count;
2155         data->host_cookie = COOKIE_MAPPED;
2156
2157         return sg_count;
2158 }
2159
2160 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2161                                bool is_first_req)
2162 {
2163         struct sdhci_host *host = mmc_priv(mmc);
2164
2165         mrq->data->host_cookie = COOKIE_UNMAPPED;
2166
2167         if (host->flags & SDHCI_REQ_USE_DMA)
2168                 sdhci_pre_dma_transfer(host, mrq->data);
2169 }
2170
2171 static void sdhci_card_event(struct mmc_host *mmc)
2172 {
2173         struct sdhci_host *host = mmc_priv(mmc);
2174         unsigned long flags;
2175         int present;
2176
2177         /* First check if client has provided their own card event */
2178         if (host->ops->card_event)
2179                 host->ops->card_event(host);
2180
2181         present = sdhci_do_get_cd(host);
2182
2183         spin_lock_irqsave(&host->lock, flags);
2184
2185         /* Check host->mrq first in case we are runtime suspended */
2186         if (host->mrq && !present) {
2187                 pr_err("%s: Card removed during transfer!\n",
2188                         mmc_hostname(host->mmc));
2189                 pr_err("%s: Resetting controller.\n",
2190                         mmc_hostname(host->mmc));
2191
2192                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2193                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2194
2195                 host->mrq->cmd->error = -ENOMEDIUM;
2196                 tasklet_schedule(&host->finish_tasklet);
2197         }
2198
2199         spin_unlock_irqrestore(&host->lock, flags);
2200 }
2201
2202 static const struct mmc_host_ops sdhci_ops = {
2203         .request        = sdhci_request,
2204         .post_req       = sdhci_post_req,
2205         .pre_req        = sdhci_pre_req,
2206         .set_ios        = sdhci_set_ios,
2207         .get_cd         = sdhci_get_cd,
2208         .get_ro         = sdhci_get_ro,
2209         .hw_reset       = sdhci_hw_reset,
2210         .enable_sdio_irq = sdhci_enable_sdio_irq,
2211         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2212         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2213         .execute_tuning                 = sdhci_execute_tuning,
2214         .select_drive_strength          = sdhci_select_drive_strength,
2215         .card_event                     = sdhci_card_event,
2216         .card_busy      = sdhci_card_busy,
2217 };
2218
2219 /*****************************************************************************\
2220  *                                                                           *
2221  * Tasklets                                                                  *
2222  *                                                                           *
2223 \*****************************************************************************/
2224
2225 static void sdhci_tasklet_finish(unsigned long param)
2226 {
2227         struct sdhci_host *host;
2228         unsigned long flags;
2229         struct mmc_request *mrq;
2230
2231         host = (struct sdhci_host*)param;
2232
2233         spin_lock_irqsave(&host->lock, flags);
2234
2235         /*
2236          * If this tasklet gets rescheduled while running, it will
2237          * be run again afterwards but without any active request.
2238          */
2239         if (!host->mrq) {
2240                 spin_unlock_irqrestore(&host->lock, flags);
2241                 return;
2242         }
2243
2244         del_timer(&host->timer);
2245
2246         mrq = host->mrq;
2247
2248         /*
2249          * The controller needs a reset of internal state machines
2250          * upon error conditions.
2251          */
2252         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2253             ((mrq->cmd && mrq->cmd->error) ||
2254              (mrq->sbc && mrq->sbc->error) ||
2255              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2256                             (mrq->data->stop && mrq->data->stop->error))) ||
2257              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2258
2259                 /* Some controllers need this kick or reset won't work here */
2260                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2261                         /* This is to force an update */
2262                         host->ops->set_clock(host, host->clock);
2263
2264                 /* Spec says we should do both at the same time, but Ricoh
2265                    controllers do not like that. */
2266                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2267                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2268         }
2269
2270         host->mrq = NULL;
2271         host->cmd = NULL;
2272         host->data = NULL;
2273
2274 #ifndef SDHCI_USE_LEDS_CLASS
2275         sdhci_deactivate_led(host);
2276 #endif
2277
2278         mmiowb();
2279         spin_unlock_irqrestore(&host->lock, flags);
2280
2281         mmc_request_done(host->mmc, mrq);
2282         sdhci_runtime_pm_put(host);
2283 }
2284
2285 static void sdhci_timeout_timer(unsigned long data)
2286 {
2287         struct sdhci_host *host;
2288         unsigned long flags;
2289
2290         host = (struct sdhci_host*)data;
2291
2292         spin_lock_irqsave(&host->lock, flags);
2293
2294         if (host->mrq) {
2295                 pr_err("%s: Timeout waiting for hardware "
2296                         "interrupt.\n", mmc_hostname(host->mmc));
2297                 sdhci_dumpregs(host);
2298
2299                 if (host->data) {
2300                         host->data->error = -ETIMEDOUT;
2301                         sdhci_finish_data(host);
2302                 } else {
2303                         if (host->cmd)
2304                                 host->cmd->error = -ETIMEDOUT;
2305                         else
2306                                 host->mrq->cmd->error = -ETIMEDOUT;
2307
2308                         tasklet_schedule(&host->finish_tasklet);
2309                 }
2310         }
2311
2312         mmiowb();
2313         spin_unlock_irqrestore(&host->lock, flags);
2314 }
2315
2316 /*****************************************************************************\
2317  *                                                                           *
2318  * Interrupt handling                                                        *
2319  *                                                                           *
2320 \*****************************************************************************/
2321
2322 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2323 {
2324         BUG_ON(intmask == 0);
2325
2326         if (!host->cmd) {
2327                 pr_err("%s: Got command interrupt 0x%08x even "
2328                         "though no command operation was in progress.\n",
2329                         mmc_hostname(host->mmc), (unsigned)intmask);
2330                 sdhci_dumpregs(host);
2331                 return;
2332         }
2333
2334         if (intmask & SDHCI_INT_TIMEOUT)
2335                 host->cmd->error = -ETIMEDOUT;
2336         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2337                         SDHCI_INT_INDEX))
2338                 host->cmd->error = -EILSEQ;
2339
2340         if (host->cmd->error) {
2341                 tasklet_schedule(&host->finish_tasklet);
2342                 return;
2343         }
2344
2345         /*
2346          * The host can send and interrupt when the busy state has
2347          * ended, allowing us to wait without wasting CPU cycles.
2348          * Unfortunately this is overloaded on the "data complete"
2349          * interrupt, so we need to take some care when handling
2350          * it.
2351          *
2352          * Note: The 1.0 specification is a bit ambiguous about this
2353          *       feature so there might be some problems with older
2354          *       controllers.
2355          */
2356         if (host->cmd->flags & MMC_RSP_BUSY) {
2357                 if (host->cmd->data)
2358                         DBG("Cannot wait for busy signal when also "
2359                                 "doing a data transfer");
2360                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2361                                 && !host->busy_handle) {
2362                         /* Mark that command complete before busy is ended */
2363                         host->busy_handle = 1;
2364                         return;
2365                 }
2366
2367                 /* The controller does not support the end-of-busy IRQ,
2368                  * fall through and take the SDHCI_INT_RESPONSE */
2369         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2370                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2371                 *mask &= ~SDHCI_INT_DATA_END;
2372         }
2373
2374         if (intmask & SDHCI_INT_RESPONSE)
2375                 sdhci_finish_command(host);
2376 }
2377
2378 #ifdef CONFIG_MMC_DEBUG
2379 static void sdhci_adma_show_error(struct sdhci_host *host)
2380 {
2381         const char *name = mmc_hostname(host->mmc);
2382         void *desc = host->adma_table;
2383
2384         sdhci_dumpregs(host);
2385
2386         while (true) {
2387                 struct sdhci_adma2_64_desc *dma_desc = desc;
2388
2389                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2390                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2391                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2392                             le32_to_cpu(dma_desc->addr_lo),
2393                             le16_to_cpu(dma_desc->len),
2394                             le16_to_cpu(dma_desc->cmd));
2395                 else
2396                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2397                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2398                             le16_to_cpu(dma_desc->len),
2399                             le16_to_cpu(dma_desc->cmd));
2400
2401                 desc += host->desc_sz;
2402
2403                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2404                         break;
2405         }
2406 }
2407 #else
2408 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2409 #endif
2410
2411 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2412 {
2413         u32 command;
2414         BUG_ON(intmask == 0);
2415
2416         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2417         if (intmask & SDHCI_INT_DATA_AVAIL) {
2418                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2419                 if (command == MMC_SEND_TUNING_BLOCK ||
2420                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2421                         host->tuning_done = 1;
2422                         wake_up(&host->buf_ready_int);
2423                         return;
2424                 }
2425         }
2426
2427         if (!host->data) {
2428                 /*
2429                  * The "data complete" interrupt is also used to
2430                  * indicate that a busy state has ended. See comment
2431                  * above in sdhci_cmd_irq().
2432                  */
2433                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2434                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2435                                 host->cmd->error = -ETIMEDOUT;
2436                                 tasklet_schedule(&host->finish_tasklet);
2437                                 return;
2438                         }
2439                         if (intmask & SDHCI_INT_DATA_END) {
2440                                 /*
2441                                  * Some cards handle busy-end interrupt
2442                                  * before the command completed, so make
2443                                  * sure we do things in the proper order.
2444                                  */
2445                                 if (host->busy_handle)
2446                                         sdhci_finish_command(host);
2447                                 else
2448                                         host->busy_handle = 1;
2449                                 return;
2450                         }
2451                 }
2452
2453                 pr_err("%s: Got data interrupt 0x%08x even "
2454                         "though no data operation was in progress.\n",
2455                         mmc_hostname(host->mmc), (unsigned)intmask);
2456                 sdhci_dumpregs(host);
2457
2458                 return;
2459         }
2460
2461         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2462                 host->data->error = -ETIMEDOUT;
2463         else if (intmask & SDHCI_INT_DATA_END_BIT)
2464                 host->data->error = -EILSEQ;
2465         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2466                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2467                         != MMC_BUS_TEST_R)
2468                 host->data->error = -EILSEQ;
2469         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2470                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2471                 sdhci_adma_show_error(host);
2472                 host->data->error = -EIO;
2473                 if (host->ops->adma_workaround)
2474                         host->ops->adma_workaround(host, intmask);
2475         }
2476
2477         if (host->data->error)
2478                 sdhci_finish_data(host);
2479         else {
2480                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2481                         sdhci_transfer_pio(host);
2482
2483                 /*
2484                  * We currently don't do anything fancy with DMA
2485                  * boundaries, but as we can't disable the feature
2486                  * we need to at least restart the transfer.
2487                  *
2488                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2489                  * should return a valid address to continue from, but as
2490                  * some controllers are faulty, don't trust them.
2491                  */
2492                 if (intmask & SDHCI_INT_DMA_END) {
2493                         u32 dmastart, dmanow;
2494                         dmastart = sg_dma_address(host->data->sg);
2495                         dmanow = dmastart + host->data->bytes_xfered;
2496                         /*
2497                          * Force update to the next DMA block boundary.
2498                          */
2499                         dmanow = (dmanow &
2500                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2501                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2502                         host->data->bytes_xfered = dmanow - dmastart;
2503                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2504                                 " next 0x%08x\n",
2505                                 mmc_hostname(host->mmc), dmastart,
2506                                 host->data->bytes_xfered, dmanow);
2507                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2508                 }
2509
2510                 if (intmask & SDHCI_INT_DATA_END) {
2511                         if (host->cmd) {
2512                                 /*
2513                                  * Data managed to finish before the
2514                                  * command completed. Make sure we do
2515                                  * things in the proper order.
2516                                  */
2517                                 host->data_early = 1;
2518                         } else {
2519                                 sdhci_finish_data(host);
2520                         }
2521                 }
2522         }
2523 }
2524
2525 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2526 {
2527         irqreturn_t result = IRQ_NONE;
2528         struct sdhci_host *host = dev_id;
2529         u32 intmask, mask, unexpected = 0;
2530         int max_loops = 16;
2531
2532         spin_lock(&host->lock);
2533
2534         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2535                 spin_unlock(&host->lock);
2536                 return IRQ_NONE;
2537         }
2538
2539         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2540         if (!intmask || intmask == 0xffffffff) {
2541                 result = IRQ_NONE;
2542                 goto out;
2543         }
2544
2545         do {
2546                 /* Clear selected interrupts. */
2547                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2548                                   SDHCI_INT_BUS_POWER);
2549                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2550
2551                 DBG("*** %s got interrupt: 0x%08x\n",
2552                         mmc_hostname(host->mmc), intmask);
2553
2554                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2555                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2556                                       SDHCI_CARD_PRESENT;
2557
2558                         /*
2559                          * There is a observation on i.mx esdhc.  INSERT
2560                          * bit will be immediately set again when it gets
2561                          * cleared, if a card is inserted.  We have to mask
2562                          * the irq to prevent interrupt storm which will
2563                          * freeze the system.  And the REMOVE gets the
2564                          * same situation.
2565                          *
2566                          * More testing are needed here to ensure it works
2567                          * for other platforms though.
2568                          */
2569                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2570                                        SDHCI_INT_CARD_REMOVE);
2571                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2572                                                SDHCI_INT_CARD_INSERT;
2573                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2574                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2575
2576                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2577                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2578
2579                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2580                                                        SDHCI_INT_CARD_REMOVE);
2581                         result = IRQ_WAKE_THREAD;
2582                 }
2583
2584                 if (intmask & SDHCI_INT_CMD_MASK)
2585                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2586                                       &intmask);
2587
2588                 if (intmask & SDHCI_INT_DATA_MASK)
2589                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2590
2591                 if (intmask & SDHCI_INT_BUS_POWER)
2592                         pr_err("%s: Card is consuming too much power!\n",
2593                                 mmc_hostname(host->mmc));
2594
2595                 if (intmask & SDHCI_INT_CARD_INT) {
2596                         sdhci_enable_sdio_irq_nolock(host, false);
2597                         host->thread_isr |= SDHCI_INT_CARD_INT;
2598                         result = IRQ_WAKE_THREAD;
2599                 }
2600
2601                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2602                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2603                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2604                              SDHCI_INT_CARD_INT);
2605
2606                 if (intmask) {
2607                         unexpected |= intmask;
2608                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2609                 }
2610
2611                 if (result == IRQ_NONE)
2612                         result = IRQ_HANDLED;
2613
2614                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2615         } while (intmask && --max_loops);
2616 out:
2617         spin_unlock(&host->lock);
2618
2619         if (unexpected) {
2620                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2621                            mmc_hostname(host->mmc), unexpected);
2622                 sdhci_dumpregs(host);
2623         }
2624
2625         return result;
2626 }
2627
2628 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2629 {
2630         struct sdhci_host *host = dev_id;
2631         unsigned long flags;
2632         u32 isr;
2633
2634         spin_lock_irqsave(&host->lock, flags);
2635         isr = host->thread_isr;
2636         host->thread_isr = 0;
2637         spin_unlock_irqrestore(&host->lock, flags);
2638
2639         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2640                 sdhci_card_event(host->mmc);
2641                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2642         }
2643
2644         if (isr & SDHCI_INT_CARD_INT) {
2645                 sdio_run_irqs(host->mmc);
2646
2647                 spin_lock_irqsave(&host->lock, flags);
2648                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2649                         sdhci_enable_sdio_irq_nolock(host, true);
2650                 spin_unlock_irqrestore(&host->lock, flags);
2651         }
2652
2653         return isr ? IRQ_HANDLED : IRQ_NONE;
2654 }
2655
2656 /*****************************************************************************\
2657  *                                                                           *
2658  * Suspend/resume                                                            *
2659  *                                                                           *
2660 \*****************************************************************************/
2661
2662 #ifdef CONFIG_PM
2663 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2664 {
2665         u8 val;
2666         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2667                         | SDHCI_WAKE_ON_INT;
2668
2669         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2670         val |= mask ;
2671         /* Avoid fake wake up */
2672         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2673                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2674         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2675 }
2676 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2677
2678 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2679 {
2680         u8 val;
2681         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2682                         | SDHCI_WAKE_ON_INT;
2683
2684         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2685         val &= ~mask;
2686         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2687 }
2688
2689 int sdhci_suspend_host(struct sdhci_host *host)
2690 {
2691         sdhci_disable_card_detection(host);
2692
2693         mmc_retune_timer_stop(host->mmc);
2694         mmc_retune_needed(host->mmc);
2695
2696         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2697                 host->ier = 0;
2698                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2699                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2700                 free_irq(host->irq, host);
2701         } else {
2702                 sdhci_enable_irq_wakeups(host);
2703                 enable_irq_wake(host->irq);
2704         }
2705         return 0;
2706 }
2707
2708 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2709
2710 int sdhci_resume_host(struct sdhci_host *host)
2711 {
2712         int ret = 0;
2713
2714         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2715                 if (host->ops->enable_dma)
2716                         host->ops->enable_dma(host);
2717         }
2718
2719         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2720                 ret = request_threaded_irq(host->irq, sdhci_irq,
2721                                            sdhci_thread_irq, IRQF_SHARED,
2722                                            mmc_hostname(host->mmc), host);
2723                 if (ret)
2724                         return ret;
2725         } else {
2726                 sdhci_disable_irq_wakeups(host);
2727                 disable_irq_wake(host->irq);
2728         }
2729
2730         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2731             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2732                 /* Card keeps power but host controller does not */
2733                 sdhci_init(host, 0);
2734                 host->pwr = 0;
2735                 host->clock = 0;
2736                 sdhci_do_set_ios(host, &host->mmc->ios);
2737         } else {
2738                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2739                 mmiowb();
2740         }
2741
2742         sdhci_enable_card_detection(host);
2743
2744         return ret;
2745 }
2746
2747 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2748
2749 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2750 {
2751         return pm_runtime_get_sync(host->mmc->parent);
2752 }
2753
2754 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2755 {
2756         pm_runtime_mark_last_busy(host->mmc->parent);
2757         return pm_runtime_put_autosuspend(host->mmc->parent);
2758 }
2759
2760 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2761 {
2762         if (host->runtime_suspended || host->bus_on)
2763                 return;
2764         host->bus_on = true;
2765         pm_runtime_get_noresume(host->mmc->parent);
2766 }
2767
2768 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2769 {
2770         if (host->runtime_suspended || !host->bus_on)
2771                 return;
2772         host->bus_on = false;
2773         pm_runtime_put_noidle(host->mmc->parent);
2774 }
2775
2776 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2777 {
2778         unsigned long flags;
2779
2780         mmc_retune_timer_stop(host->mmc);
2781         mmc_retune_needed(host->mmc);
2782
2783         spin_lock_irqsave(&host->lock, flags);
2784         host->ier &= SDHCI_INT_CARD_INT;
2785         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2786         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2787         spin_unlock_irqrestore(&host->lock, flags);
2788
2789         synchronize_hardirq(host->irq);
2790
2791         spin_lock_irqsave(&host->lock, flags);
2792         host->runtime_suspended = true;
2793         spin_unlock_irqrestore(&host->lock, flags);
2794
2795         return 0;
2796 }
2797 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2798
2799 int sdhci_runtime_resume_host(struct sdhci_host *host)
2800 {
2801         unsigned long flags;
2802         int host_flags = host->flags;
2803
2804         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2805                 if (host->ops->enable_dma)
2806                         host->ops->enable_dma(host);
2807         }
2808
2809         sdhci_init(host, 0);
2810
2811         /* Force clock and power re-program */
2812         host->pwr = 0;
2813         host->clock = 0;
2814         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2815         sdhci_do_set_ios(host, &host->mmc->ios);
2816
2817         if ((host_flags & SDHCI_PV_ENABLED) &&
2818                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2819                 spin_lock_irqsave(&host->lock, flags);
2820                 sdhci_enable_preset_value(host, true);
2821                 spin_unlock_irqrestore(&host->lock, flags);
2822         }
2823
2824         spin_lock_irqsave(&host->lock, flags);
2825
2826         host->runtime_suspended = false;
2827
2828         /* Enable SDIO IRQ */
2829         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2830                 sdhci_enable_sdio_irq_nolock(host, true);
2831
2832         /* Enable Card Detection */
2833         sdhci_enable_card_detection(host);
2834
2835         spin_unlock_irqrestore(&host->lock, flags);
2836
2837         return 0;
2838 }
2839 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2840
2841 #endif /* CONFIG_PM */
2842
2843 /*****************************************************************************\
2844  *                                                                           *
2845  * Device allocation/registration                                            *
2846  *                                                                           *
2847 \*****************************************************************************/
2848
2849 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2850         size_t priv_size)
2851 {
2852         struct mmc_host *mmc;
2853         struct sdhci_host *host;
2854
2855         WARN_ON(dev == NULL);
2856
2857         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2858         if (!mmc)
2859                 return ERR_PTR(-ENOMEM);
2860
2861         host = mmc_priv(mmc);
2862         host->mmc = mmc;
2863
2864         return host;
2865 }
2866
2867 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2868
2869 int sdhci_add_host(struct sdhci_host *host)
2870 {
2871         struct mmc_host *mmc;
2872         u32 caps[2] = {0, 0};
2873         u32 max_current_caps;
2874         unsigned int ocr_avail;
2875         unsigned int override_timeout_clk;
2876         u32 max_clk;
2877         int ret;
2878
2879         WARN_ON(host == NULL);
2880         if (host == NULL)
2881                 return -EINVAL;
2882
2883         mmc = host->mmc;
2884
2885         if (debug_quirks)
2886                 host->quirks = debug_quirks;
2887         if (debug_quirks2)
2888                 host->quirks2 = debug_quirks2;
2889
2890         override_timeout_clk = host->timeout_clk;
2891
2892         sdhci_do_reset(host, SDHCI_RESET_ALL);
2893
2894         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2895         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2896                                 >> SDHCI_SPEC_VER_SHIFT;
2897         if (host->version > SDHCI_SPEC_300) {
2898                 pr_err("%s: Unknown controller version (%d). "
2899                         "You may experience problems.\n", mmc_hostname(mmc),
2900                         host->version);
2901         }
2902
2903         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2904                 sdhci_readl(host, SDHCI_CAPABILITIES);
2905
2906         if (host->version >= SDHCI_SPEC_300)
2907                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2908                         host->caps1 :
2909                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2910
2911         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2912                 host->flags |= SDHCI_USE_SDMA;
2913         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2914                 DBG("Controller doesn't have SDMA capability\n");
2915         else
2916                 host->flags |= SDHCI_USE_SDMA;
2917
2918         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2919                 (host->flags & SDHCI_USE_SDMA)) {
2920                 DBG("Disabling DMA as it is marked broken\n");
2921                 host->flags &= ~SDHCI_USE_SDMA;
2922         }
2923
2924         if ((host->version >= SDHCI_SPEC_200) &&
2925                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2926                 host->flags |= SDHCI_USE_ADMA;
2927
2928         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2929                 (host->flags & SDHCI_USE_ADMA)) {
2930                 DBG("Disabling ADMA as it is marked broken\n");
2931                 host->flags &= ~SDHCI_USE_ADMA;
2932         }
2933
2934         /*
2935          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2936          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2937          * that during the first call to ->enable_dma().  Similarly
2938          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2939          * implement.
2940          */
2941         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2942                 host->flags |= SDHCI_USE_64_BIT_DMA;
2943
2944         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2945                 if (host->ops->enable_dma) {
2946                         if (host->ops->enable_dma(host)) {
2947                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2948                                         mmc_hostname(mmc));
2949                                 host->flags &=
2950                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2951                         }
2952                 }
2953         }
2954
2955         /* SDMA does not support 64-bit DMA */
2956         if (host->flags & SDHCI_USE_64_BIT_DMA)
2957                 host->flags &= ~SDHCI_USE_SDMA;
2958
2959         if (host->flags & SDHCI_USE_ADMA) {
2960                 /*
2961                  * The DMA descriptor table size is calculated as the maximum
2962                  * number of segments times 2, to allow for an alignment
2963                  * descriptor for each segment, plus 1 for a nop end descriptor,
2964                  * all multipled by the descriptor size.
2965                  */
2966                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2967                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2968                                               SDHCI_ADMA2_64_DESC_SZ;
2969                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2970                                                 SDHCI_ADMA2_64_ALIGN;
2971                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2972                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
2973                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2974                 } else {
2975                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2976                                               SDHCI_ADMA2_32_DESC_SZ;
2977                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2978                                                 SDHCI_ADMA2_32_ALIGN;
2979                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2980                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
2981                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2982                 }
2983                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2984                                                       host->adma_table_sz,
2985                                                       &host->adma_addr,
2986                                                       GFP_KERNEL);
2987                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2988                 if (!host->adma_table || !host->align_buffer) {
2989                         if (host->adma_table)
2990                                 dma_free_coherent(mmc_dev(mmc),
2991                                                   host->adma_table_sz,
2992                                                   host->adma_table,
2993                                                   host->adma_addr);
2994                         kfree(host->align_buffer);
2995                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2996                                 mmc_hostname(mmc));
2997                         host->flags &= ~SDHCI_USE_ADMA;
2998                         host->adma_table = NULL;
2999                         host->align_buffer = NULL;
3000                 } else if (host->adma_addr & host->align_mask) {
3001                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3002                                 mmc_hostname(mmc));
3003                         host->flags &= ~SDHCI_USE_ADMA;
3004                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3005                                           host->adma_table, host->adma_addr);
3006                         kfree(host->align_buffer);
3007                         host->adma_table = NULL;
3008                         host->align_buffer = NULL;
3009                 }
3010         }
3011
3012         /*
3013          * If we use DMA, then it's up to the caller to set the DMA
3014          * mask, but PIO does not need the hw shim so we set a new
3015          * mask here in that case.
3016          */
3017         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3018                 host->dma_mask = DMA_BIT_MASK(64);
3019                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3020         }
3021
3022         if (host->version >= SDHCI_SPEC_300)
3023                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3024                         >> SDHCI_CLOCK_BASE_SHIFT;
3025         else
3026                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3027                         >> SDHCI_CLOCK_BASE_SHIFT;
3028
3029         host->max_clk *= 1000000;
3030         if (host->max_clk == 0 || host->quirks &
3031                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3032                 if (!host->ops->get_max_clock) {
3033                         pr_err("%s: Hardware doesn't specify base clock "
3034                                "frequency.\n", mmc_hostname(mmc));
3035                         return -ENODEV;
3036                 }
3037                 host->max_clk = host->ops->get_max_clock(host);
3038         }
3039
3040         /*
3041          * In case of Host Controller v3.00, find out whether clock
3042          * multiplier is supported.
3043          */
3044         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3045                         SDHCI_CLOCK_MUL_SHIFT;
3046
3047         /*
3048          * In case the value in Clock Multiplier is 0, then programmable
3049          * clock mode is not supported, otherwise the actual clock
3050          * multiplier is one more than the value of Clock Multiplier
3051          * in the Capabilities Register.
3052          */
3053         if (host->clk_mul)
3054                 host->clk_mul += 1;
3055
3056         /*
3057          * Set host parameters.
3058          */
3059         mmc->ops = &sdhci_ops;
3060         max_clk = host->max_clk;
3061
3062         if (host->ops->get_min_clock)
3063                 mmc->f_min = host->ops->get_min_clock(host);
3064         else if (host->version >= SDHCI_SPEC_300) {
3065                 if (host->clk_mul) {
3066                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3067                         max_clk = host->max_clk * host->clk_mul;
3068                 } else
3069                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3070         } else
3071                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3072
3073         if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3074                 mmc->f_max = max_clk;
3075
3076         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3077                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3078                                         SDHCI_TIMEOUT_CLK_SHIFT;
3079                 if (host->timeout_clk == 0) {
3080                         if (host->ops->get_timeout_clock) {
3081                                 host->timeout_clk =
3082                                         host->ops->get_timeout_clock(host);
3083                         } else {
3084                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3085                                         mmc_hostname(mmc));
3086                                 return -ENODEV;
3087                         }
3088                 }
3089
3090                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3091                         host->timeout_clk *= 1000;
3092
3093                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3094                         host->ops->get_max_timeout_count(host) : 1 << 27;
3095                 mmc->max_busy_timeout /= host->timeout_clk;
3096         }
3097
3098         if (override_timeout_clk)
3099                 host->timeout_clk = override_timeout_clk;
3100
3101         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3102         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3103
3104         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3105                 host->flags |= SDHCI_AUTO_CMD12;
3106
3107         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3108         if ((host->version >= SDHCI_SPEC_300) &&
3109             ((host->flags & SDHCI_USE_ADMA) ||
3110              !(host->flags & SDHCI_USE_SDMA)) &&
3111              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3112                 host->flags |= SDHCI_AUTO_CMD23;
3113                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3114         } else {
3115                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3116         }
3117
3118         /*
3119          * A controller may support 8-bit width, but the board itself
3120          * might not have the pins brought out.  Boards that support
3121          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3122          * their platform code before calling sdhci_add_host(), and we
3123          * won't assume 8-bit width for hosts without that CAP.
3124          */
3125         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3126                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3127
3128         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3129                 mmc->caps &= ~MMC_CAP_CMD23;
3130
3131         if (caps[0] & SDHCI_CAN_DO_HISPD)
3132                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3133
3134         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3135             !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3136             IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3137                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3138
3139         /* If there are external regulators, get them */
3140         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3141                 return -EPROBE_DEFER;
3142
3143         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3144         if (!IS_ERR(mmc->supply.vqmmc)) {
3145                 ret = regulator_enable(mmc->supply.vqmmc);
3146                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3147                                                     1950000))
3148                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3149                                         SDHCI_SUPPORT_SDR50 |
3150                                         SDHCI_SUPPORT_DDR50);
3151                 if (ret) {
3152                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3153                                 mmc_hostname(mmc), ret);
3154                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3155                 }
3156         }
3157
3158         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3159                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3160                        SDHCI_SUPPORT_DDR50);
3161
3162         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3163         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3164                        SDHCI_SUPPORT_DDR50))
3165                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3166
3167         /* SDR104 supports also implies SDR50 support */
3168         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3169                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3170                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3171                  * field can be promoted to support HS200.
3172                  */
3173                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3174                         mmc->caps2 |= MMC_CAP2_HS200;
3175         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3176                 mmc->caps |= MMC_CAP_UHS_SDR50;
3177
3178         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3179             (caps[1] & SDHCI_SUPPORT_HS400))
3180                 mmc->caps2 |= MMC_CAP2_HS400;
3181
3182         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3183             (IS_ERR(mmc->supply.vqmmc) ||
3184              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3185                                              1300000)))
3186                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3187
3188         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3189                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3190                 mmc->caps |= MMC_CAP_UHS_DDR50;
3191
3192         /* Does the host need tuning for SDR50? */
3193         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3194                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3195
3196         /* Does the host need tuning for SDR104 / HS200? */
3197         if (mmc->caps2 & MMC_CAP2_HS200)
3198                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3199
3200         /* Driver Type(s) (A, C, D) supported by the host */
3201         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3202                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3203         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3204                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3205         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3206                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3207
3208         /* Initial value for re-tuning timer count */
3209         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3210                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3211
3212         /*
3213          * In case Re-tuning Timer is not disabled, the actual value of
3214          * re-tuning timer will be 2 ^ (n - 1).
3215          */
3216         if (host->tuning_count)
3217                 host->tuning_count = 1 << (host->tuning_count - 1);
3218
3219         /* Re-tuning mode supported by the Host Controller */
3220         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3221                              SDHCI_RETUNING_MODE_SHIFT;
3222
3223         ocr_avail = 0;
3224
3225         /*
3226          * According to SD Host Controller spec v3.00, if the Host System
3227          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3228          * the value is meaningful only if Voltage Support in the Capabilities
3229          * register is set. The actual current value is 4 times the register
3230          * value.
3231          */
3232         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3233         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3234                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3235                 if (curr > 0) {
3236
3237                         /* convert to SDHCI_MAX_CURRENT format */
3238                         curr = curr/1000;  /* convert to mA */
3239                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3240
3241                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3242                         max_current_caps =
3243                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3244                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3245                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3246                 }
3247         }
3248
3249         if (caps[0] & SDHCI_CAN_VDD_330) {
3250                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3251
3252                 mmc->max_current_330 = ((max_current_caps &
3253                                    SDHCI_MAX_CURRENT_330_MASK) >>
3254                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3255                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3256         }
3257         if (caps[0] & SDHCI_CAN_VDD_300) {
3258                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3259
3260                 mmc->max_current_300 = ((max_current_caps &
3261                                    SDHCI_MAX_CURRENT_300_MASK) >>
3262                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3263                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3264         }
3265         if (caps[0] & SDHCI_CAN_VDD_180) {
3266                 ocr_avail |= MMC_VDD_165_195;
3267
3268                 mmc->max_current_180 = ((max_current_caps &
3269                                    SDHCI_MAX_CURRENT_180_MASK) >>
3270                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3271                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3272         }
3273
3274         /* If OCR set by host, use it instead. */
3275         if (host->ocr_mask)
3276                 ocr_avail = host->ocr_mask;
3277
3278         /* If OCR set by external regulators, give it highest prio. */
3279         if (mmc->ocr_avail)
3280                 ocr_avail = mmc->ocr_avail;
3281
3282         mmc->ocr_avail = ocr_avail;
3283         mmc->ocr_avail_sdio = ocr_avail;
3284         if (host->ocr_avail_sdio)
3285                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3286         mmc->ocr_avail_sd = ocr_avail;
3287         if (host->ocr_avail_sd)
3288                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3289         else /* normal SD controllers don't support 1.8V */
3290                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3291         mmc->ocr_avail_mmc = ocr_avail;
3292         if (host->ocr_avail_mmc)
3293                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3294
3295         if (mmc->ocr_avail == 0) {
3296                 pr_err("%s: Hardware doesn't report any "
3297                         "support voltages.\n", mmc_hostname(mmc));
3298                 return -ENODEV;
3299         }
3300
3301         spin_lock_init(&host->lock);
3302
3303         /*
3304          * Maximum number of segments. Depends on if the hardware
3305          * can do scatter/gather or not.
3306          */
3307         if (host->flags & SDHCI_USE_ADMA)
3308                 mmc->max_segs = SDHCI_MAX_SEGS;
3309         else if (host->flags & SDHCI_USE_SDMA)
3310                 mmc->max_segs = 1;
3311         else /* PIO */
3312                 mmc->max_segs = SDHCI_MAX_SEGS;
3313
3314         /*
3315          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3316          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3317          * is less anyway.
3318          */
3319         mmc->max_req_size = 524288;
3320
3321         /*
3322          * Maximum segment size. Could be one segment with the maximum number
3323          * of bytes. When doing hardware scatter/gather, each entry cannot
3324          * be larger than 64 KiB though.
3325          */
3326         if (host->flags & SDHCI_USE_ADMA) {
3327                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3328                         mmc->max_seg_size = 65535;
3329                 else
3330                         mmc->max_seg_size = 65536;
3331         } else {
3332                 mmc->max_seg_size = mmc->max_req_size;
3333         }
3334
3335         /*
3336          * Maximum block size. This varies from controller to controller and
3337          * is specified in the capabilities register.
3338          */
3339         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3340                 mmc->max_blk_size = 2;
3341         } else {
3342                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3343                                 SDHCI_MAX_BLOCK_SHIFT;
3344                 if (mmc->max_blk_size >= 3) {
3345                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3346                                 mmc_hostname(mmc));
3347                         mmc->max_blk_size = 0;
3348                 }
3349         }
3350
3351         mmc->max_blk_size = 512 << mmc->max_blk_size;
3352
3353         /*
3354          * Maximum block count.
3355          */
3356         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3357
3358         /*
3359          * Init tasklets.
3360          */
3361         tasklet_init(&host->finish_tasklet,
3362                 sdhci_tasklet_finish, (unsigned long)host);
3363
3364         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3365
3366         init_waitqueue_head(&host->buf_ready_int);
3367
3368         sdhci_init(host, 0);
3369
3370         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3371                                    IRQF_SHARED, mmc_hostname(mmc), host);
3372         if (ret) {
3373                 pr_err("%s: Failed to request IRQ %d: %d\n",
3374                        mmc_hostname(mmc), host->irq, ret);
3375                 goto untasklet;
3376         }
3377
3378 #ifdef CONFIG_MMC_DEBUG
3379         sdhci_dumpregs(host);
3380 #endif
3381
3382 #ifdef SDHCI_USE_LEDS_CLASS
3383         snprintf(host->led_name, sizeof(host->led_name),
3384                 "%s::", mmc_hostname(mmc));
3385         host->led.name = host->led_name;
3386         host->led.brightness = LED_OFF;
3387         host->led.default_trigger = mmc_hostname(mmc);
3388         host->led.brightness_set = sdhci_led_control;
3389
3390         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3391         if (ret) {
3392                 pr_err("%s: Failed to register LED device: %d\n",
3393                        mmc_hostname(mmc), ret);
3394                 goto reset;
3395         }
3396 #endif
3397
3398         mmiowb();
3399
3400         mmc_add_host(mmc);
3401
3402         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3403                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3404                 (host->flags & SDHCI_USE_ADMA) ?
3405                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3406                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3407
3408         sdhci_enable_card_detection(host);
3409
3410         return 0;
3411
3412 #ifdef SDHCI_USE_LEDS_CLASS
3413 reset:
3414         sdhci_do_reset(host, SDHCI_RESET_ALL);
3415         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3416         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3417         free_irq(host->irq, host);
3418 #endif
3419 untasklet:
3420         tasklet_kill(&host->finish_tasklet);
3421
3422         return ret;
3423 }
3424
3425 EXPORT_SYMBOL_GPL(sdhci_add_host);
3426
3427 void sdhci_remove_host(struct sdhci_host *host, int dead)
3428 {
3429         struct mmc_host *mmc = host->mmc;
3430         unsigned long flags;
3431
3432         if (dead) {
3433                 spin_lock_irqsave(&host->lock, flags);
3434
3435                 host->flags |= SDHCI_DEVICE_DEAD;
3436
3437                 if (host->mrq) {
3438                         pr_err("%s: Controller removed during "
3439                                 " transfer!\n", mmc_hostname(mmc));
3440
3441                         host->mrq->cmd->error = -ENOMEDIUM;
3442                         tasklet_schedule(&host->finish_tasklet);
3443                 }
3444
3445                 spin_unlock_irqrestore(&host->lock, flags);
3446         }
3447
3448         sdhci_disable_card_detection(host);
3449
3450         mmc_remove_host(mmc);
3451
3452 #ifdef SDHCI_USE_LEDS_CLASS
3453         led_classdev_unregister(&host->led);
3454 #endif
3455
3456         if (!dead)
3457                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3458
3459         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3460         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3461         free_irq(host->irq, host);
3462
3463         del_timer_sync(&host->timer);
3464
3465         tasklet_kill(&host->finish_tasklet);
3466
3467         if (!IS_ERR(mmc->supply.vqmmc))
3468                 regulator_disable(mmc->supply.vqmmc);
3469
3470         if (host->adma_table)
3471                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3472                                   host->adma_table, host->adma_addr);
3473         kfree(host->align_buffer);
3474
3475         host->adma_table = NULL;
3476         host->align_buffer = NULL;
3477 }
3478
3479 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3480
3481 void sdhci_free_host(struct sdhci_host *host)
3482 {
3483         mmc_free_host(host->mmc);
3484 }
3485
3486 EXPORT_SYMBOL_GPL(sdhci_free_host);
3487
3488 /*****************************************************************************\
3489  *                                                                           *
3490  * Driver init/exit                                                          *
3491  *                                                                           *
3492 \*****************************************************************************/
3493
3494 static int __init sdhci_drv_init(void)
3495 {
3496         pr_info(DRIVER_NAME
3497                 ": Secure Digital Host Controller Interface driver\n");
3498         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3499
3500         return 0;
3501 }
3502
3503 static void __exit sdhci_drv_exit(void)
3504 {
3505 }
3506
3507 module_init(sdhci_drv_init);
3508 module_exit(sdhci_drv_exit);
3509
3510 module_param(debug_quirks, uint, 0444);
3511 module_param(debug_quirks2, uint, 0444);
3512
3513 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3514 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3515 MODULE_LICENSE("GPL");
3516
3517 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3518 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");