drivers/mtd/nand/sunxi_nand.c

   1 /*
   2  * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
   3  *
   4  * Derived from:
   5  *      https://github.com/yuq/sunxi-nfc-mtd
   6  *      Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
   7  *
   8  *      https://github.com/hno/Allwinner-Info
   9  *      Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  10  *
  11  *      Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  12  *      Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/of_mtd.h>
  34 #include <linux/mtd/mtd.h>
  35 #include <linux/mtd/nand.h>
  36 #include <linux/mtd/partitions.h>
  37 #include <linux/clk.h>
  38 #include <linux/delay.h>
  39 #include <linux/dmaengine.h>
  40 #include <linux/gpio.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/io.h>
  43
  44 #define NFC_REG_CTL             0x0000
  45 #define NFC_REG_ST              0x0004
  46 #define NFC_REG_INT             0x0008
  47 #define NFC_REG_TIMING_CTL      0x000C
  48 #define NFC_REG_TIMING_CFG      0x0010
  49 #define NFC_REG_ADDR_LOW        0x0014
  50 #define NFC_REG_ADDR_HIGH       0x0018
  51 #define NFC_REG_SECTOR_NUM      0x001C
  52 #define NFC_REG_CNT             0x0020
  53 #define NFC_REG_CMD             0x0024
  54 #define NFC_REG_RCMD_SET        0x0028
  55 #define NFC_REG_WCMD_SET        0x002C
  56 #define NFC_REG_IO_DATA         0x0030
  57 #define NFC_REG_ECC_CTL         0x0034
  58 #define NFC_REG_ECC_ST          0x0038
  59 #define NFC_REG_DEBUG           0x003C
  60 #define NFC_REG_ECC_ERR_CNT(x)  ((0x0040 + (x)) & ~0x3)
  61 #define NFC_REG_USER_DATA(x)    (0x0050 + ((x) * 4))
  62 #define NFC_REG_SPARE_AREA      0x00A0
  63 #define NFC_RAM0_BASE           0x0400
  64 #define NFC_RAM1_BASE           0x0800
  65
  66 /* define bit use in NFC_CTL */
  67 #define NFC_EN                  BIT(0)
  68 #define NFC_RESET               BIT(1)
  69 #define NFC_BUS_WIDTH_MSK       BIT(2)
  70 #define NFC_BUS_WIDTH_8         (0 << 2)
  71 #define NFC_BUS_WIDTH_16        (1 << 2)
  72 #define NFC_RB_SEL_MSK          BIT(3)
  73 #define NFC_RB_SEL(x)           ((x) << 3)
  74 #define NFC_CE_SEL_MSK          GENMASK(26, 24)
  75 #define NFC_CE_SEL(x)           ((x) << 24)
  76 #define NFC_CE_CTL              BIT(6)
  77 #define NFC_PAGE_SHIFT_MSK      GENMASK(11, 8)
  78 #define NFC_PAGE_SHIFT(x)       (((x) < 10 ? 0 : (x) - 10) << 8)
  79 #define NFC_SAM                 BIT(12)
  80 #define NFC_RAM_METHOD          BIT(14)
  81 #define NFC_DEBUG_CTL           BIT(31)
  82
  83 /* define bit use in NFC_ST */
  84 #define NFC_RB_B2R              BIT(0)
  85 #define NFC_CMD_INT_FLAG        BIT(1)
  86 #define NFC_DMA_INT_FLAG        BIT(2)
  87 #define NFC_CMD_FIFO_STATUS     BIT(3)
  88 #define NFC_STA                 BIT(4)
  89 #define NFC_NATCH_INT_FLAG      BIT(5)
  90 #define NFC_RB_STATE(x)         BIT(x + 8)
  91
  92 /* define bit use in NFC_INT */
  93 #define NFC_B2R_INT_ENABLE      BIT(0)
  94 #define NFC_CMD_INT_ENABLE      BIT(1)
  95 #define NFC_DMA_INT_ENABLE      BIT(2)
  96 #define NFC_INT_MASK            (NFC_B2R_INT_ENABLE | \
  97                                  NFC_CMD_INT_ENABLE | \
  98                                  NFC_DMA_INT_ENABLE)
  99
 100 /* define bit use in NFC_TIMING_CTL */
 101 #define NFC_TIMING_CTL_EDO      BIT(8)
 102
 103 /* define NFC_TIMING_CFG register layout */
 104 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD)             \
 105         (((tWB) & 0x3) | (((tADL) & 0x3) << 2) |                \
 106         (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) |         \
 107         (((tCAD) & 0x7) << 8))
 108
 109 /* define bit use in NFC_CMD */
 110 #define NFC_CMD_LOW_BYTE_MSK    GENMASK(7, 0)
 111 #define NFC_CMD_HIGH_BYTE_MSK   GENMASK(15, 8)
 112 #define NFC_CMD(x)              (x)
 113 #define NFC_ADR_NUM_MSK         GENMASK(18, 16)
 114 #define NFC_ADR_NUM(x)          (((x) - 1) << 16)
 115 #define NFC_SEND_ADR            BIT(19)
 116 #define NFC_ACCESS_DIR          BIT(20)
 117 #define NFC_DATA_TRANS          BIT(21)
 118 #define NFC_SEND_CMD1           BIT(22)
 119 #define NFC_WAIT_FLAG           BIT(23)
 120 #define NFC_SEND_CMD2           BIT(24)
 121 #define NFC_SEQ                 BIT(25)
 122 #define NFC_DATA_SWAP_METHOD    BIT(26)
 123 #define NFC_ROW_AUTO_INC        BIT(27)
 124 #define NFC_SEND_CMD3           BIT(28)
 125 #define NFC_SEND_CMD4           BIT(29)
 126 #define NFC_CMD_TYPE_MSK        GENMASK(31, 30)
 127 #define NFC_NORMAL_OP           (0 << 30)
 128 #define NFC_ECC_OP              (1 << 30)
 129 #define NFC_PAGE_OP             (2 << 30)
 130
 131 /* define bit use in NFC_RCMD_SET */
 132 #define NFC_READ_CMD_MSK        GENMASK(7, 0)
 133 #define NFC_RND_READ_CMD0_MSK   GENMASK(15, 8)
 134 #define NFC_RND_READ_CMD1_MSK   GENMASK(23, 16)
 135
 136 /* define bit use in NFC_WCMD_SET */
 137 #define NFC_PROGRAM_CMD_MSK     GENMASK(7, 0)
 138 #define NFC_RND_WRITE_CMD_MSK   GENMASK(15, 8)
 139 #define NFC_READ_CMD0_MSK       GENMASK(23, 16)
 140 #define NFC_READ_CMD1_MSK       GENMASK(31, 24)
 141
 142 /* define bit use in NFC_ECC_CTL */
 143 #define NFC_ECC_EN              BIT(0)
 144 #define NFC_ECC_PIPELINE        BIT(3)
 145 #define NFC_ECC_EXCEPTION       BIT(4)
 146 #define NFC_ECC_BLOCK_SIZE_MSK  BIT(5)
 147 #define NFC_RANDOM_EN           BIT(9)
 148 #define NFC_RANDOM_DIRECTION    BIT(10)
 149 #define NFC_ECC_MODE_MSK        GENMASK(15, 12)
 150 #define NFC_ECC_MODE(x)         ((x) << 12)
 151 #define NFC_RANDOM_SEED_MSK     GENMASK(30, 16)
 152 #define NFC_RANDOM_SEED(x)      ((x) << 16)
 153
 154 /* define bit use in NFC_ECC_ST */
 155 #define NFC_ECC_ERR(x)          BIT(x)
 156 #define NFC_ECC_PAT_FOUND(x)    BIT(x + 16)
 157 #define NFC_ECC_ERR_CNT(b, x)   (((x) >> ((b) * 8)) & 0xff)
 158
 159 #define NFC_DEFAULT_TIMEOUT_MS  1000
 160
 161 #define NFC_SRAM_SIZE           1024
 162
 163 #define NFC_MAX_CS              7
 164
 165 /*
 166  * Ready/Busy detection type: describes the Ready/Busy detection modes
 167  *
 168  * @RB_NONE:    no external detection available, rely on STATUS command
 169  *              and software timeouts
 170  * @RB_NATIVE:  use sunxi NAND controller Ready/Busy support. The Ready/Busy
 171  *              pin of the NAND flash chip must be connected to one of the
 172  *              native NAND R/B pins (those which can be muxed to the NAND
 173  *              Controller)
 174  * @RB_GPIO:    use a simple GPIO to handle Ready/Busy status. The Ready/Busy
 175  *              pin of the NAND flash chip must be connected to a GPIO capable
 176  *              pin.
 177  */
 178 enum sunxi_nand_rb_type {
 179         RB_NONE,
 180         RB_NATIVE,
 181         RB_GPIO,
 182 };
 183
 184 /*
 185  * Ready/Busy structure: stores information related to Ready/Busy detection
 186  *
 187  * @type:       the Ready/Busy detection mode
 188  * @info:       information related to the R/B detection mode. Either a gpio
 189  *              id or a native R/B id (those supported by the NAND controller).
 190  */
 191 struct sunxi_nand_rb {
 192         enum sunxi_nand_rb_type type;
 193         union {
 194                 int gpio;
 195                 int nativeid;
 196         } info;
 197 };
 198
 199 /*
 200  * Chip Select structure: stores information related to NAND Chip Select
 201  *
 202  * @cs:         the NAND CS id used to communicate with a NAND Chip
 203  * @rb:         the Ready/Busy description
 204  */
 205 struct sunxi_nand_chip_sel {
 206         u8 cs;
 207         struct sunxi_nand_rb rb;
 208 };
 209
 210 /*
 211  * sunxi HW ECC infos: stores information related to HW ECC support
 212  *
 213  * @mode:       the sunxi ECC mode field deduced from ECC requirements
 214  * @layout:     the OOB layout depending on the ECC requirements and the
 215  *              selected ECC mode
 216  */
 217 struct sunxi_nand_hw_ecc {
 218         int mode;
 219         struct nand_ecclayout layout;
 220 };
 221
 222 /*
 223  * NAND chip structure: stores NAND chip device related information
 224  *
 225  * @node:               used to store NAND chips into a list
 226  * @nand:               base NAND chip structure
 227  * @mtd:                base MTD structure
 228  * @clk_rate:           clk_rate required for this NAND chip
 229  * @timing_cfg          TIMING_CFG register value for this NAND chip
 230  * @selected:           current active CS
 231  * @nsels:              number of CS lines required by the NAND chip
 232  * @sels:               array of CS lines descriptions
 233  */
 234 struct sunxi_nand_chip {
 235         struct list_head node;
 236         struct nand_chip nand;
 237         struct mtd_info mtd;
 238         unsigned long clk_rate;
 239         u32 timing_cfg;
 240         u32 timing_ctl;
 241         int selected;
 242         int nsels;
 243         struct sunxi_nand_chip_sel sels[0];
 244 };
 245
 246 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
 247 {
 248         return container_of(nand, struct sunxi_nand_chip, nand);
 249 }
 250
 251 /*
 252  * NAND Controller structure: stores sunxi NAND controller information
 253  *
 254  * @controller:         base controller structure
 255  * @dev:                parent device (used to print error messages)
 256  * @regs:               NAND controller registers
 257  * @ahb_clk:            NAND Controller AHB clock
 258  * @mod_clk:            NAND Controller mod clock
 259  * @assigned_cs:        bitmask describing already assigned CS lines
 260  * @clk_rate:           NAND controller current clock rate
 261  * @chips:              a list containing all the NAND chips attached to
 262  *                      this NAND controller
 263  * @complete:           a completion object used to wait for NAND
 264  *                      controller events
 265  */
 266 struct sunxi_nfc {
 267         struct nand_hw_control controller;
 268         struct device *dev;
 269         void __iomem *regs;
 270         struct clk *ahb_clk;
 271         struct clk *mod_clk;
 272         unsigned long assigned_cs;
 273         unsigned long clk_rate;
 274         struct list_head chips;
 275         struct completion complete;
 276 };
 277
 278 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
 279 {
 280         return container_of(ctrl, struct sunxi_nfc, controller);
 281 }
 282
 283 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
 284 {
 285         struct sunxi_nfc *nfc = dev_id;
 286         u32 st = readl(nfc->regs + NFC_REG_ST);
 287         u32 ien = readl(nfc->regs + NFC_REG_INT);
 288
 289         if (!(ien & st))
 290                 return IRQ_NONE;
 291
 292         if ((ien & st) == ien)
 293                 complete(&nfc->complete);
 294
 295         writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
 296         writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
 297
 298         return IRQ_HANDLED;
 299 }
 300
 301 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
 302                               unsigned int timeout_ms)
 303 {
 304         init_completion(&nfc->complete);
 305
 306         writel(flags, nfc->regs + NFC_REG_INT);
 307
 308         if (!timeout_ms)
 309                 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
 310
 311         if (!wait_for_completion_timeout(&nfc->complete,
 312                                          msecs_to_jiffies(timeout_ms))) {
 313                 dev_err(nfc->dev, "wait interrupt timedout\n");
 314                 return -ETIMEDOUT;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
 321 {
 322         unsigned long timeout = jiffies +
 323                                 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
 324
 325         do {
 326                 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
 327                         return 0;
 328         } while (time_before(jiffies, timeout));
 329
 330         dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
 331         return -ETIMEDOUT;
 332 }
 333
 334 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
 335 {
 336         unsigned long timeout = jiffies +
 337                                 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
 338
 339         writel(0, nfc->regs + NFC_REG_ECC_CTL);
 340         writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
 341
 342         do {
 343                 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
 344                         return 0;
 345         } while (time_before(jiffies, timeout));
 346
 347         dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
 348         return -ETIMEDOUT;
 349 }
 350
 351 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
 352 {
 353         struct nand_chip *nand = mtd->priv;
 354         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 355         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 356         struct sunxi_nand_rb *rb;
 357         unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
 358         int ret;
 359
 360         if (sunxi_nand->selected < 0)
 361                 return 0;
 362
 363         rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
 364
 365         switch (rb->type) {
 366         case RB_NATIVE:
 367                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 368                          NFC_RB_STATE(rb->info.nativeid));
 369                 if (ret)
 370                         break;
 371
 372                 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
 373                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 374                          NFC_RB_STATE(rb->info.nativeid));
 375                 break;
 376         case RB_GPIO:
 377                 ret = gpio_get_value(rb->info.gpio);
 378                 break;
 379         case RB_NONE:
 380         default:
 381                 ret = 0;
 382                 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
 383                 break;
 384         }
 385
 386         return ret;
 387 }
 388
 389 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
 390 {
 391         struct nand_chip *nand = mtd->priv;
 392         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 393         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 394         struct sunxi_nand_chip_sel *sel;
 395         u32 ctl;
 396
 397         if (chip > 0 && chip >= sunxi_nand->nsels)
 398                 return;
 399
 400         if (chip == sunxi_nand->selected)
 401                 return;
 402
 403         ctl = readl(nfc->regs + NFC_REG_CTL) &
 404               ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
 405
 406         if (chip >= 0) {
 407                 sel = &sunxi_nand->sels[chip];
 408
 409                 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
 410                        NFC_PAGE_SHIFT(nand->page_shift - 10);
 411                 if (sel->rb.type == RB_NONE) {
 412                         nand->dev_ready = NULL;
 413                 } else {
 414                         nand->dev_ready = sunxi_nfc_dev_ready;
 415                         if (sel->rb.type == RB_NATIVE)
 416                                 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
 417                 }
 418
 419                 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
 420
 421                 if (nfc->clk_rate != sunxi_nand->clk_rate) {
 422                         clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
 423                         nfc->clk_rate = sunxi_nand->clk_rate;
 424                 }
 425         }
 426
 427         writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
 428         writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
 429         writel(ctl, nfc->regs + NFC_REG_CTL);
 430
 431         sunxi_nand->selected = chip;
 432 }
 433
 434 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 435 {
 436         struct nand_chip *nand = mtd->priv;
 437         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 438         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 439         int ret;
 440         int cnt;
 441         int offs = 0;
 442         u32 tmp;
 443
 444         while (len > offs) {
 445                 cnt = min(len - offs, NFC_SRAM_SIZE);
 446
 447                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 448                 if (ret)
 449                         break;
 450
 451                 writel(cnt, nfc->regs + NFC_REG_CNT);
 452                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
 453                 writel(tmp, nfc->regs + NFC_REG_CMD);
 454
 455                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 456                 if (ret)
 457                         break;
 458
 459                 if (buf)
 460                         memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
 461                                       cnt);
 462                 offs += cnt;
 463         }
 464 }
 465
 466 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 467                                 int len)
 468 {
 469         struct nand_chip *nand = mtd->priv;
 470         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 471         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 472         int ret;
 473         int cnt;
 474         int offs = 0;
 475         u32 tmp;
 476
 477         while (len > offs) {
 478                 cnt = min(len - offs, NFC_SRAM_SIZE);
 479
 480                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 481                 if (ret)
 482                         break;
 483
 484                 writel(cnt, nfc->regs + NFC_REG_CNT);
 485                 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
 486                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 487                       NFC_ACCESS_DIR;
 488                 writel(tmp, nfc->regs + NFC_REG_CMD);
 489
 490                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 491                 if (ret)
 492                         break;
 493
 494                 offs += cnt;
 495         }
 496 }
 497
 498 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
 499 {
 500         uint8_t ret;
 501
 502         sunxi_nfc_read_buf(mtd, &ret, 1);
 503
 504         return ret;
 505 }
 506
 507 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
 508                                unsigned int ctrl)
 509 {
 510         struct nand_chip *nand = mtd->priv;
 511         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 512         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 513         int ret;
 514         u32 tmp;
 515
 516         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 517         if (ret)
 518                 return;
 519
 520         if (ctrl & NAND_CTRL_CHANGE) {
 521                 tmp = readl(nfc->regs + NFC_REG_CTL);
 522                 if (ctrl & NAND_NCE)
 523                         tmp |= NFC_CE_CTL;
 524                 else
 525                         tmp &= ~NFC_CE_CTL;
 526                 writel(tmp, nfc->regs + NFC_REG_CTL);
 527         }
 528
 529         if (dat == NAND_CMD_NONE)
 530                 return;
 531
 532         if (ctrl & NAND_CLE) {
 533                 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
 534         } else {
 535                 writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
 536                 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
 537         }
 538
 539         sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 540 }
 541
 542 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
 543 {
 544         struct nand_chip *nand = mtd->priv;
 545         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 546         struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
 547         u32 ecc_ctl;
 548
 549         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 550         ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
 551                      NFC_ECC_BLOCK_SIZE_MSK);
 552         ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
 553
 554         writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
 555 }
 556
 557 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
 558 {
 559         struct nand_chip *nand = mtd->priv;
 560         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 561
 562         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
 563                nfc->regs + NFC_REG_ECC_CTL);
 564 }
 565
 566 static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
 567 {
 568         buf[0] = user_data;
 569         buf[1] = user_data >> 8;
 570         buf[2] = user_data >> 16;
 571         buf[3] = user_data >> 24;
 572 }
 573
 574 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
 575                                        u8 *data, int data_off,
 576                                        u8 *oob, int oob_off,
 577                                        int *cur_off,
 578                                        unsigned int *max_bitflips)
 579 {
 580         struct nand_chip *nand = mtd->priv;
 581         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 582         struct nand_ecc_ctrl *ecc = &nand->ecc;
 583         u32 status;
 584         int ret;
 585
 586         if (*cur_off != data_off)
 587                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 588
 589         sunxi_nfc_read_buf(mtd, data, ecc->size);
 590
 591         if (data_off + ecc->size != oob_off)
 592                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 593
 594         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 595         if (ret)
 596                 return ret;
 597
 598         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
 599                nfc->regs + NFC_REG_CMD);
 600
 601         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 602         if (ret)
 603                 return ret;
 604
 605         status = readl(nfc->regs + NFC_REG_ECC_ST);
 606         ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
 607
 608         memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
 609
 610         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 611         sunxi_nfc_read_buf(mtd, oob, ecc->bytes + 4);
 612
 613         if (status & NFC_ECC_ERR(0)) {
 614                 ret = nand_check_erased_ecc_chunk(data, ecc->size,
 615                                                   oob, ecc->bytes + 4,
 616                                                   NULL, 0, ecc->strength);
 617         } else {
 618                 /*
 619                  * The engine protects 4 bytes of OOB data per chunk.
 620                  * Retrieve the corrected OOB bytes.
 621                  */
 622                 sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(0)),
 623                                            oob);
 624         }
 625
 626         if (ret < 0) {
 627                 mtd->ecc_stats.failed++;
 628         } else {
 629                 mtd->ecc_stats.corrected += ret;
 630                 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
 631         }
 632
 633         *cur_off = oob_off + ecc->bytes + 4;
 634
 635         return 0;
 636 }
 637
 638 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
 639                                             u8 *oob, int *cur_off)
 640 {
 641         struct nand_chip *nand = mtd->priv;
 642         struct nand_ecc_ctrl *ecc = &nand->ecc;
 643         int offset = ((ecc->bytes + 4) * ecc->steps);
 644         int len = mtd->oobsize - offset;
 645
 646         if (len <= 0)
 647                 return;
 648
 649         if (*cur_off != offset)
 650                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
 651                               offset + mtd->writesize, -1);
 652
 653         sunxi_nfc_read_buf(mtd, oob + offset, len);
 654
 655         *cur_off = mtd->oobsize + mtd->writesize;
 656 }
 657
 658 static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
 659 {
 660         return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
 661 }
 662
 663 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
 664                                         const u8 *data, int data_off,
 665                                         const u8 *oob, int oob_off,
 666                                         int *cur_off)
 667 {
 668         struct nand_chip *nand = mtd->priv;
 669         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 670         struct nand_ecc_ctrl *ecc = &nand->ecc;
 671         int ret;
 672
 673         if (data_off != *cur_off)
 674                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
 675
 676         sunxi_nfc_write_buf(mtd, data, ecc->size);
 677
 678         /* Fill OOB data in */
 679         writel(sunxi_nfc_buf_to_user_data(oob),
 680                nfc->regs + NFC_REG_USER_DATA(0));
 681
 682         if (data_off + ecc->size != oob_off)
 683                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
 684
 685         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 686         if (ret)
 687                 return ret;
 688
 689         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 690                NFC_ACCESS_DIR | NFC_ECC_OP,
 691                nfc->regs + NFC_REG_CMD);
 692
 693         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 694         if (ret)
 695                 return ret;
 696
 697         *cur_off = oob_off + ecc->bytes + 4;
 698
 699         return 0;
 700 }
 701
 702 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
 703                                              u8 *oob, int *cur_off)
 704 {
 705         struct nand_chip *nand = mtd->priv;
 706         struct nand_ecc_ctrl *ecc = &nand->ecc;
 707         int offset = ((ecc->bytes + 4) * ecc->steps);
 708         int len = mtd->oobsize - offset;
 709
 710         if (len <= 0)
 711                 return;
 712
 713         if (*cur_off != offset)
 714                 nand->cmdfunc(mtd, NAND_CMD_RNDIN,
 715                               offset + mtd->writesize, -1);
 716
 717         sunxi_nfc_write_buf(mtd, oob + offset, len);
 718
 719         *cur_off = mtd->oobsize + mtd->writesize;
 720 }
 721
 722 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
 723                                       struct nand_chip *chip, uint8_t *buf,
 724                                       int oob_required, int page)
 725 {
 726         struct nand_ecc_ctrl *ecc = &chip->ecc;
 727         unsigned int max_bitflips = 0;
 728         int ret, i, cur_off = 0;
 729
 730         sunxi_nfc_hw_ecc_enable(mtd);
 731
 732         for (i = 0; i < ecc->steps; i++) {
 733                 int data_off = i * ecc->size;
 734                 int oob_off = i * (ecc->bytes + 4);
 735                 u8 *data = buf + data_off;
 736                 u8 *oob = chip->oob_poi + oob_off;
 737
 738                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
 739                                                   oob_off + mtd->writesize,
 740                                                   &cur_off, &max_bitflips);
 741                 if (ret)
 742                         return ret;
 743         }
 744
 745         if (oob_required)
 746                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off);
 747
 748         sunxi_nfc_hw_ecc_disable(mtd);
 749
 750         return max_bitflips;
 751 }
 752
 753 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
 754                                        struct nand_chip *chip,
 755                                        const uint8_t *buf, int oob_required,
 756                                        int page)
 757 {
 758         struct nand_ecc_ctrl *ecc = &chip->ecc;
 759         int ret, i, cur_off = 0;
 760
 761         sunxi_nfc_hw_ecc_enable(mtd);
 762
 763         for (i = 0; i < ecc->steps; i++) {
 764                 int data_off = i * ecc->size;
 765                 int oob_off = i * (ecc->bytes + 4);
 766                 const u8 *data = buf + data_off;
 767                 const u8 *oob = chip->oob_poi + oob_off;
 768
 769                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
 770                                                    oob_off + mtd->writesize,
 771                                                    &cur_off);
 772                 if (ret)
 773                         return ret;
 774         }
 775
 776         if (oob_required)
 777                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, &cur_off);
 778
 779         sunxi_nfc_hw_ecc_disable(mtd);
 780
 781         return 0;
 782 }
 783
 784 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
 785                                                struct nand_chip *chip,
 786                                                uint8_t *buf, int oob_required,
 787                                                int page)
 788 {
 789         struct nand_ecc_ctrl *ecc = &chip->ecc;
 790         unsigned int max_bitflips = 0;
 791         int ret, i, cur_off = 0;
 792
 793         sunxi_nfc_hw_ecc_enable(mtd);
 794
 795         for (i = 0; i < ecc->steps; i++) {
 796                 int data_off = i * (ecc->size + ecc->bytes + 4);
 797                 int oob_off = data_off + ecc->size;
 798                 u8 *data = buf + (i * ecc->size);
 799                 u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
 800
 801                 ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
 802                                                   oob_off, &cur_off,
 803                                                   &max_bitflips);
 804                 if (ret)
 805                         return ret;
 806         }
 807
 808         if (oob_required)
 809                 sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off);
 810
 811         sunxi_nfc_hw_ecc_disable(mtd);
 812
 813         return max_bitflips;
 814 }
 815
 816 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
 817                                                 struct nand_chip *chip,
 818                                                 const uint8_t *buf,
 819                                                 int oob_required, int page)
 820 {
 821         struct nand_ecc_ctrl *ecc = &chip->ecc;
 822         int ret, i, cur_off = 0;
 823
 824         sunxi_nfc_hw_ecc_enable(mtd);
 825
 826         for (i = 0; i < ecc->steps; i++) {
 827                 int data_off = i * (ecc->size + ecc->bytes + 4);
 828                 int oob_off = data_off + ecc->size;
 829                 const u8 *data = buf + (i * ecc->size);
 830                 const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
 831
 832                 ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
 833                                                    oob, oob_off, &cur_off);
 834                 if (ret)
 835                         return ret;
 836         }
 837
 838         if (oob_required)
 839                 sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, &cur_off);
 840
 841         sunxi_nfc_hw_ecc_disable(mtd);
 842
 843         return 0;
 844 }
 845
 846 static const s32 tWB_lut[] = {6, 12, 16, 20};
 847 static const s32 tRHW_lut[] = {4, 8, 12, 20};
 848
 849 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
 850                 u32 clk_period)
 851 {
 852         u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
 853         int i;
 854
 855         for (i = 0; i < lut_size; i++) {
 856                 if (clk_cycles <= lut[i])
 857                         return i;
 858         }
 859
 860         /* Doesn't fit */
 861         return -EINVAL;
 862 }
 863
 864 #define sunxi_nand_lookup_timing(l, p, c) \
 865                         _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
 866
 867 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
 868                                        const struct nand_sdr_timings *timings)
 869 {
 870         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
 871         u32 min_clk_period = 0;
 872         s32 tWB, tADL, tWHR, tRHW, tCAD;
 873
 874         /* T1 <=> tCLS */
 875         if (timings->tCLS_min > min_clk_period)
 876                 min_clk_period = timings->tCLS_min;
 877
 878         /* T2 <=> tCLH */
 879         if (timings->tCLH_min > min_clk_period)
 880                 min_clk_period = timings->tCLH_min;
 881
 882         /* T3 <=> tCS */
 883         if (timings->tCS_min > min_clk_period)
 884                 min_clk_period = timings->tCS_min;
 885
 886         /* T4 <=> tCH */
 887         if (timings->tCH_min > min_clk_period)
 888                 min_clk_period = timings->tCH_min;
 889
 890         /* T5 <=> tWP */
 891         if (timings->tWP_min > min_clk_period)
 892                 min_clk_period = timings->tWP_min;
 893
 894         /* T6 <=> tWH */
 895         if (timings->tWH_min > min_clk_period)
 896                 min_clk_period = timings->tWH_min;
 897
 898         /* T7 <=> tALS */
 899         if (timings->tALS_min > min_clk_period)
 900                 min_clk_period = timings->tALS_min;
 901
 902         /* T8 <=> tDS */
 903         if (timings->tDS_min > min_clk_period)
 904                 min_clk_period = timings->tDS_min;
 905
 906         /* T9 <=> tDH */
 907         if (timings->tDH_min > min_clk_period)
 908                 min_clk_period = timings->tDH_min;
 909
 910         /* T10 <=> tRR */
 911         if (timings->tRR_min > (min_clk_period * 3))
 912                 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
 913
 914         /* T11 <=> tALH */
 915         if (timings->tALH_min > min_clk_period)
 916                 min_clk_period = timings->tALH_min;
 917
 918         /* T12 <=> tRP */
 919         if (timings->tRP_min > min_clk_period)
 920                 min_clk_period = timings->tRP_min;
 921
 922         /* T13 <=> tREH */
 923         if (timings->tREH_min > min_clk_period)
 924                 min_clk_period = timings->tREH_min;
 925
 926         /* T14 <=> tRC */
 927         if (timings->tRC_min > (min_clk_period * 2))
 928                 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
 929
 930         /* T15 <=> tWC */
 931         if (timings->tWC_min > (min_clk_period * 2))
 932                 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
 933
 934         /* T16 - T19 + tCAD */
 935         tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
 936                                         min_clk_period);
 937         if (tWB < 0) {
 938                 dev_err(nfc->dev, "unsupported tWB\n");
 939                 return tWB;
 940         }
 941
 942         tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
 943         if (tADL > 3) {
 944                 dev_err(nfc->dev, "unsupported tADL\n");
 945                 return -EINVAL;
 946         }
 947
 948         tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
 949         if (tWHR > 3) {
 950                 dev_err(nfc->dev, "unsupported tWHR\n");
 951                 return -EINVAL;
 952         }
 953
 954         tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
 955                                         min_clk_period);
 956         if (tRHW < 0) {
 957                 dev_err(nfc->dev, "unsupported tRHW\n");
 958                 return tRHW;
 959         }
 960
 961         /*
 962          * TODO: according to ONFI specs this value only applies for DDR NAND,
 963          * but Allwinner seems to set this to 0x7. Mimic them for now.
 964          */
 965         tCAD = 0x7;
 966
 967         /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
 968         chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
 969
 970         /*
 971          * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
 972          * output cycle timings shall be used if the host drives tRC less than
 973          * 30 ns.
 974          */
 975         chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
 976
 977         /* Convert min_clk_period from picoseconds to nanoseconds */
 978         min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
 979
 980         /*
 981          * Convert min_clk_period into a clk frequency, then get the
 982          * appropriate rate for the NAND controller IP given this formula
 983          * (specified in the datasheet):
 984          * nand clk_rate = 2 * min_clk_rate
 985          */
 986         chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
 987
 988         return 0;
 989 }
 990
 991 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
 992                                         struct device_node *np)
 993 {
 994         const struct nand_sdr_timings *timings;
 995         int ret;
 996         int mode;
 997
 998         mode = onfi_get_async_timing_mode(&chip->nand);
 999         if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1000                 mode = chip->nand.onfi_timing_mode_default;
1001         } else {
1002                 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1003                 int i;
1004
1005                 mode = fls(mode) - 1;
1006                 if (mode < 0)
1007                         mode = 0;
1008
1009                 feature[0] = mode;
1010                 for (i = 0; i < chip->nsels; i++) {
1011                         chip->nand.select_chip(&chip->mtd, i);
1012                         ret = chip->nand.onfi_set_features(&chip->mtd,
1013                                                 &chip->nand,
1014                                                 ONFI_FEATURE_ADDR_TIMING_MODE,
1015                                                 feature);
1016                         chip->nand.select_chip(&chip->mtd, -1);
1017                         if (ret)
1018                                 return ret;
1019                 }
1020         }
1021
1022         timings = onfi_async_timing_mode_to_sdr_timings(mode);
1023         if (IS_ERR(timings))
1024                 return PTR_ERR(timings);
1025
1026         return sunxi_nand_chip_set_timings(chip, timings);
1027 }
1028
1029 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1030                                               struct nand_ecc_ctrl *ecc,
1031                                               struct device_node *np)
1032 {
1033         static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1034         struct nand_chip *nand = mtd->priv;
1035         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1036         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1037         struct sunxi_nand_hw_ecc *data;
1038         struct nand_ecclayout *layout;
1039         int nsectors;
1040         int ret;
1041         int i;
1042
1043         data = kzalloc(sizeof(*data), GFP_KERNEL);
1044         if (!data)
1045                 return -ENOMEM;
1046
1047         /* Add ECC info retrieval from DT */
1048         for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1049                 if (ecc->strength <= strengths[i])
1050                         break;
1051         }
1052
1053         if (i >= ARRAY_SIZE(strengths)) {
1054                 dev_err(nfc->dev, "unsupported strength\n");
1055                 ret = -ENOTSUPP;
1056                 goto err;
1057         }
1058
1059         data->mode = i;
1060
1061         /* HW ECC always request ECC bytes for 1024 bytes blocks */
1062         ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1063
1064         /* HW ECC always work with even numbers of ECC bytes */
1065         ecc->bytes = ALIGN(ecc->bytes, 2);
1066
1067         layout = &data->layout;
1068         nsectors = mtd->writesize / ecc->size;
1069
1070         if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1071                 ret = -EINVAL;
1072                 goto err;
1073         }
1074
1075         layout->eccbytes = (ecc->bytes * nsectors);
1076
1077         ecc->layout = layout;
1078         ecc->priv = data;
1079
1080         return 0;
1081
1082 err:
1083         kfree(data);
1084
1085         return ret;
1086 }
1087
1088 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1089 {
1090         kfree(ecc->priv);
1091 }
1092
1093 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1094                                        struct nand_ecc_ctrl *ecc,
1095                                        struct device_node *np)
1096 {
1097         struct nand_ecclayout *layout;
1098         int nsectors;
1099         int i, j;
1100         int ret;
1101
1102         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1103         if (ret)
1104                 return ret;
1105
1106         ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1107         ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1108         layout = ecc->layout;
1109         nsectors = mtd->writesize / ecc->size;
1110
1111         for (i = 0; i < nsectors; i++) {
1112                 if (i) {
1113                         layout->oobfree[i].offset =
1114                                 layout->oobfree[i - 1].offset +
1115                                 layout->oobfree[i - 1].length +
1116                                 ecc->bytes;
1117                         layout->oobfree[i].length = 4;
1118                 } else {
1119                         /*
1120                          * The first 2 bytes are used for BB markers, hence we
1121                          * only have 2 bytes available in the first user data
1122                          * section.
1123                          */
1124                         layout->oobfree[i].length = 2;
1125                         layout->oobfree[i].offset = 2;
1126                 }
1127
1128                 for (j = 0; j < ecc->bytes; j++)
1129                         layout->eccpos[(ecc->bytes * i) + j] =
1130                                         layout->oobfree[i].offset +
1131                                         layout->oobfree[i].length + j;
1132         }
1133
1134         if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1135                 layout->oobfree[nsectors].offset =
1136                                 layout->oobfree[nsectors - 1].offset +
1137                                 layout->oobfree[nsectors - 1].length +
1138                                 ecc->bytes;
1139                 layout->oobfree[nsectors].length = mtd->oobsize -
1140                                 ((ecc->bytes + 4) * nsectors);
1141         }
1142
1143         return 0;
1144 }
1145
1146 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1147                                                 struct nand_ecc_ctrl *ecc,
1148                                                 struct device_node *np)
1149 {
1150         struct nand_ecclayout *layout;
1151         int nsectors;
1152         int i;
1153         int ret;
1154
1155         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1156         if (ret)
1157                 return ret;
1158
1159         ecc->prepad = 4;
1160         ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1161         ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1162
1163         layout = ecc->layout;
1164         nsectors = mtd->writesize / ecc->size;
1165
1166         for (i = 0; i < (ecc->bytes * nsectors); i++)
1167                 layout->eccpos[i] = i;
1168
1169         layout->oobfree[0].length = mtd->oobsize - i;
1170         layout->oobfree[0].offset = i;
1171
1172         return 0;
1173 }
1174
1175 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1176 {
1177         switch (ecc->mode) {
1178         case NAND_ECC_HW:
1179         case NAND_ECC_HW_SYNDROME:
1180                 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1181                 break;
1182         case NAND_ECC_NONE:
1183                 kfree(ecc->layout);
1184         default:
1185                 break;
1186         }
1187 }
1188
1189 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1190                                struct device_node *np)
1191 {
1192         struct nand_chip *nand = mtd->priv;
1193         int ret;
1194
1195         if (!ecc->size) {
1196                 ecc->size = nand->ecc_step_ds;
1197                 ecc->strength = nand->ecc_strength_ds;
1198         }
1199
1200         if (!ecc->size || !ecc->strength)
1201                 return -EINVAL;
1202
1203         switch (ecc->mode) {
1204         case NAND_ECC_SOFT_BCH:
1205                 break;
1206         case NAND_ECC_HW:
1207                 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1208                 if (ret)
1209                         return ret;
1210                 break;
1211         case NAND_ECC_HW_SYNDROME:
1212                 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1213                 if (ret)
1214                         return ret;
1215                 break;
1216         case NAND_ECC_NONE:
1217                 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1218                 if (!ecc->layout)
1219                         return -ENOMEM;
1220                 ecc->layout->oobfree[0].length = mtd->oobsize;
1221         case NAND_ECC_SOFT:
1222                 break;
1223         default:
1224                 return -EINVAL;
1225         }
1226
1227         return 0;
1228 }
1229
1230 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1231                                 struct device_node *np)
1232 {
1233         const struct nand_sdr_timings *timings;
1234         struct sunxi_nand_chip *chip;
1235         struct mtd_part_parser_data ppdata;
1236         struct mtd_info *mtd;
1237         struct nand_chip *nand;
1238         int nsels;
1239         int ret;
1240         int i;
1241         u32 tmp;
1242
1243         if (!of_get_property(np, "reg", &nsels))
1244                 return -EINVAL;
1245
1246         nsels /= sizeof(u32);
1247         if (!nsels) {
1248                 dev_err(dev, "invalid reg property size\n");
1249                 return -EINVAL;
1250         }
1251
1252         chip = devm_kzalloc(dev,
1253                             sizeof(*chip) +
1254                             (nsels * sizeof(struct sunxi_nand_chip_sel)),
1255                             GFP_KERNEL);
1256         if (!chip) {
1257                 dev_err(dev, "could not allocate chip\n");
1258                 return -ENOMEM;
1259         }
1260
1261         chip->nsels = nsels;
1262         chip->selected = -1;
1263
1264         for (i = 0; i < nsels; i++) {
1265                 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1266                 if (ret) {
1267                         dev_err(dev, "could not retrieve reg property: %d\n",
1268                                 ret);
1269                         return ret;
1270                 }
1271
1272                 if (tmp > NFC_MAX_CS) {
1273                         dev_err(dev,
1274                                 "invalid reg value: %u (max CS = 7)\n",
1275                                 tmp);
1276                         return -EINVAL;
1277                 }
1278
1279                 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1280                         dev_err(dev, "CS %d already assigned\n", tmp);
1281                         return -EINVAL;
1282                 }
1283
1284                 chip->sels[i].cs = tmp;
1285
1286                 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1287                     tmp < 2) {
1288                         chip->sels[i].rb.type = RB_NATIVE;
1289                         chip->sels[i].rb.info.nativeid = tmp;
1290                 } else {
1291                         ret = of_get_named_gpio(np, "rb-gpios", i);
1292                         if (ret >= 0) {
1293                                 tmp = ret;
1294                                 chip->sels[i].rb.type = RB_GPIO;
1295                                 chip->sels[i].rb.info.gpio = tmp;
1296                                 ret = devm_gpio_request(dev, tmp, "nand-rb");
1297                                 if (ret)
1298                                         return ret;
1299
1300                                 ret = gpio_direction_input(tmp);
1301                                 if (ret)
1302                                         return ret;
1303                         } else {
1304                                 chip->sels[i].rb.type = RB_NONE;
1305                         }
1306                 }
1307         }
1308
1309         timings = onfi_async_timing_mode_to_sdr_timings(0);
1310         if (IS_ERR(timings)) {
1311                 ret = PTR_ERR(timings);
1312                 dev_err(dev,
1313                         "could not retrieve timings for ONFI mode 0: %d\n",
1314                         ret);
1315                 return ret;
1316         }
1317
1318         ret = sunxi_nand_chip_set_timings(chip, timings);
1319         if (ret) {
1320                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1321                 return ret;
1322         }
1323
1324         nand = &chip->nand;
1325         /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1326         nand->chip_delay = 200;
1327         nand->controller = &nfc->controller;
1328         /*
1329          * Set the ECC mode to the default value in case nothing is specified
1330          * in the DT.
1331          */
1332         nand->ecc.mode = NAND_ECC_HW;
1333         nand->flash_node = np;
1334         nand->select_chip = sunxi_nfc_select_chip;
1335         nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1336         nand->read_buf = sunxi_nfc_read_buf;
1337         nand->write_buf = sunxi_nfc_write_buf;
1338         nand->read_byte = sunxi_nfc_read_byte;
1339
1340         mtd = &chip->mtd;
1341         mtd->dev.parent = dev;
1342         mtd->priv = nand;
1343
1344         ret = nand_scan_ident(mtd, nsels, NULL);
1345         if (ret)
1346                 return ret;
1347
1348         if (nand->bbt_options & NAND_BBT_USE_FLASH)
1349                 nand->bbt_options |= NAND_BBT_NO_OOB;
1350
1351         ret = sunxi_nand_chip_init_timings(chip, np);
1352         if (ret) {
1353                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1354                 return ret;
1355         }
1356
1357         ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1358         if (ret) {
1359                 dev_err(dev, "ECC init failed: %d\n", ret);
1360                 return ret;
1361         }
1362
1363         ret = nand_scan_tail(mtd);
1364         if (ret) {
1365                 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1366                 return ret;
1367         }
1368
1369         ppdata.of_node = np;
1370         ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1371         if (ret) {
1372                 dev_err(dev, "failed to register mtd device: %d\n", ret);
1373                 nand_release(mtd);
1374                 return ret;
1375         }
1376
1377         list_add_tail(&chip->node, &nfc->chips);
1378
1379         return 0;
1380 }
1381
1382 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1383 {
1384         struct device_node *np = dev->of_node;
1385         struct device_node *nand_np;
1386         int nchips = of_get_child_count(np);
1387         int ret;
1388
1389         if (nchips > 8) {
1390                 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1391                 return -EINVAL;
1392         }
1393
1394         for_each_child_of_node(np, nand_np) {
1395                 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1396                 if (ret)
1397                         return ret;
1398         }
1399
1400         return 0;
1401 }
1402
1403 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1404 {
1405         struct sunxi_nand_chip *chip;
1406
1407         while (!list_empty(&nfc->chips)) {
1408                 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1409                                         node);
1410                 nand_release(&chip->mtd);
1411                 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1412                 list_del(&chip->node);
1413         }
1414 }
1415
1416 static int sunxi_nfc_probe(struct platform_device *pdev)
1417 {
1418         struct device *dev = &pdev->dev;
1419         struct resource *r;
1420         struct sunxi_nfc *nfc;
1421         int irq;
1422         int ret;
1423
1424         nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1425         if (!nfc)
1426                 return -ENOMEM;
1427
1428         nfc->dev = dev;
1429         spin_lock_init(&nfc->controller.lock);
1430         init_waitqueue_head(&nfc->controller.wq);
1431         INIT_LIST_HEAD(&nfc->chips);
1432
1433         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1434         nfc->regs = devm_ioremap_resource(dev, r);
1435         if (IS_ERR(nfc->regs))
1436                 return PTR_ERR(nfc->regs);
1437
1438         irq = platform_get_irq(pdev, 0);
1439         if (irq < 0) {
1440                 dev_err(dev, "failed to retrieve irq\n");
1441                 return irq;
1442         }
1443
1444         nfc->ahb_clk = devm_clk_get(dev, "ahb");
1445         if (IS_ERR(nfc->ahb_clk)) {
1446                 dev_err(dev, "failed to retrieve ahb clk\n");
1447                 return PTR_ERR(nfc->ahb_clk);
1448         }
1449
1450         ret = clk_prepare_enable(nfc->ahb_clk);
1451         if (ret)
1452                 return ret;
1453
1454         nfc->mod_clk = devm_clk_get(dev, "mod");
1455         if (IS_ERR(nfc->mod_clk)) {
1456                 dev_err(dev, "failed to retrieve mod clk\n");
1457                 ret = PTR_ERR(nfc->mod_clk);
1458                 goto out_ahb_clk_unprepare;
1459         }
1460
1461         ret = clk_prepare_enable(nfc->mod_clk);
1462         if (ret)
1463                 goto out_ahb_clk_unprepare;
1464
1465         ret = sunxi_nfc_rst(nfc);
1466         if (ret)
1467                 goto out_mod_clk_unprepare;
1468
1469         writel(0, nfc->regs + NFC_REG_INT);
1470         ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1471                                0, "sunxi-nand", nfc);
1472         if (ret)
1473                 goto out_mod_clk_unprepare;
1474
1475         platform_set_drvdata(pdev, nfc);
1476
1477         ret = sunxi_nand_chips_init(dev, nfc);
1478         if (ret) {
1479                 dev_err(dev, "failed to init nand chips\n");
1480                 goto out_mod_clk_unprepare;
1481         }
1482
1483         return 0;
1484
1485 out_mod_clk_unprepare:
1486         clk_disable_unprepare(nfc->mod_clk);
1487 out_ahb_clk_unprepare:
1488         clk_disable_unprepare(nfc->ahb_clk);
1489
1490         return ret;
1491 }
1492
1493 static int sunxi_nfc_remove(struct platform_device *pdev)
1494 {
1495         struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1496
1497         sunxi_nand_chips_cleanup(nfc);
1498
1499         return 0;
1500 }
1501
1502 static const struct of_device_id sunxi_nfc_ids[] = {
1503         { .compatible = "allwinner,sun4i-a10-nand" },
1504         { /* sentinel */ }
1505 };
1506 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1507
1508 static struct platform_driver sunxi_nfc_driver = {
1509         .driver = {
1510                 .name = "sunxi_nand",
1511                 .of_match_table = sunxi_nfc_ids,
1512         },
1513         .probe = sunxi_nfc_probe,
1514         .remove = sunxi_nfc_remove,
1515 };
1516 module_platform_driver(sunxi_nfc_driver);
1517
1518 MODULE_LICENSE("GPL v2");
1519 MODULE_AUTHOR("Boris BREZILLON");
1520 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1521 MODULE_ALIAS("platform:sunxi_nand");