2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
18 #include "mv88e6xxx.h"
20 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
21 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
22 * will be directly accessible on some {device address,register address}
23 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
24 * will only respond to SMI transactions to that specific address, and
25 * an indirect addressing mechanism needs to be used to access its
28 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
33 for (i = 0; i < 16; i++) {
34 ret = mdiobus_read(bus, sw_addr, 0);
38 if ((ret & 0x8000) == 0)
45 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
50 return mdiobus_read(bus, addr, reg);
52 /* Wait for the bus to become free. */
53 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
57 /* Transmit the read command. */
58 ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
62 /* Wait for the read command to complete. */
63 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
68 ret = mdiobus_read(bus, sw_addr, 1);
75 /* Must be called with SMI mutex held */
76 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
78 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
84 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
88 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
94 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
96 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
99 mutex_lock(&ps->smi_mutex);
100 ret = _mv88e6xxx_reg_read(ds, addr, reg);
101 mutex_unlock(&ps->smi_mutex);
106 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
112 return mdiobus_write(bus, addr, reg, val);
114 /* Wait for the bus to become free. */
115 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
119 /* Transmit the data to write. */
120 ret = mdiobus_write(bus, sw_addr, 1, val);
124 /* Transmit the write command. */
125 ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
129 /* Wait for the write command to complete. */
130 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
137 /* Must be called with SMI mutex held */
138 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
141 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
146 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
149 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
152 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
154 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
157 mutex_lock(&ps->smi_mutex);
158 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
159 mutex_unlock(&ps->smi_mutex);
164 int mv88e6xxx_config_prio(struct dsa_switch *ds)
166 /* Configure the IP ToS mapping registers. */
167 REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
168 REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
169 REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
170 REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
171 REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
172 REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
173 REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
174 REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
176 /* Configure the IEEE 802.1p priority mapping register. */
177 REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
182 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
184 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
185 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
186 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
191 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
196 for (i = 0; i < 6; i++) {
199 /* Write the MAC address byte. */
200 REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
202 /* Wait for the write to complete. */
203 for (j = 0; j < 16; j++) {
204 ret = REG_READ(REG_GLOBAL2, 0x0d);
205 if ((ret & 0x8000) == 0)
215 int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
218 return mv88e6xxx_reg_read(ds, addr, regnum);
222 int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
225 return mv88e6xxx_reg_write(ds, addr, regnum, val);
229 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
230 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
233 unsigned long timeout;
235 ret = REG_READ(REG_GLOBAL, 0x04);
236 REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
238 timeout = jiffies + 1 * HZ;
239 while (time_before(jiffies, timeout)) {
240 ret = REG_READ(REG_GLOBAL, 0x00);
241 usleep_range(1000, 2000);
242 if ((ret & 0xc000) != 0xc000)
249 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
252 unsigned long timeout;
254 ret = REG_READ(REG_GLOBAL, 0x04);
255 REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
257 timeout = jiffies + 1 * HZ;
258 while (time_before(jiffies, timeout)) {
259 ret = REG_READ(REG_GLOBAL, 0x00);
260 usleep_range(1000, 2000);
261 if ((ret & 0xc000) == 0xc000)
268 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
270 struct mv88e6xxx_priv_state *ps;
272 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
273 if (mutex_trylock(&ps->ppu_mutex)) {
274 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
276 if (mv88e6xxx_ppu_enable(ds) == 0)
277 ps->ppu_disabled = 0;
278 mutex_unlock(&ps->ppu_mutex);
282 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
284 struct mv88e6xxx_priv_state *ps = (void *)_ps;
286 schedule_work(&ps->ppu_work);
289 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
291 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
294 mutex_lock(&ps->ppu_mutex);
296 /* If the PHY polling unit is enabled, disable it so that
297 * we can access the PHY registers. If it was already
298 * disabled, cancel the timer that is going to re-enable
301 if (!ps->ppu_disabled) {
302 ret = mv88e6xxx_ppu_disable(ds);
304 mutex_unlock(&ps->ppu_mutex);
307 ps->ppu_disabled = 1;
309 del_timer(&ps->ppu_timer);
316 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
318 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
320 /* Schedule a timer to re-enable the PHY polling unit. */
321 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
322 mutex_unlock(&ps->ppu_mutex);
325 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
327 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
329 mutex_init(&ps->ppu_mutex);
330 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
331 init_timer(&ps->ppu_timer);
332 ps->ppu_timer.data = (unsigned long)ps;
333 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
336 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
340 ret = mv88e6xxx_ppu_access_get(ds);
342 ret = mv88e6xxx_reg_read(ds, addr, regnum);
343 mv88e6xxx_ppu_access_put(ds);
349 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
354 ret = mv88e6xxx_ppu_access_get(ds);
356 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
357 mv88e6xxx_ppu_access_put(ds);
364 void mv88e6xxx_poll_link(struct dsa_switch *ds)
368 for (i = 0; i < DSA_MAX_PORTS; i++) {
369 struct net_device *dev;
370 int uninitialized_var(port_status);
381 if (dev->flags & IFF_UP) {
382 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
386 link = !!(port_status & 0x0800);
390 if (netif_carrier_ok(dev)) {
391 netdev_info(dev, "link down\n");
392 netif_carrier_off(dev);
397 switch (port_status & 0x0300) {
411 duplex = (port_status & 0x0400) ? 1 : 0;
412 fc = (port_status & 0x8000) ? 1 : 0;
414 if (!netif_carrier_ok(dev)) {
416 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
418 duplex ? "full" : "half",
420 netif_carrier_on(dev);
425 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
430 for (i = 0; i < 10; i++) {
431 ret = REG_READ(REG_GLOBAL, 0x1d);
432 if ((ret & 0x8000) == 0)
439 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
443 /* Snapshot the hardware statistics counters for this port. */
444 REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
446 /* Wait for the snapshotting to complete. */
447 ret = mv88e6xxx_stats_wait(ds);
454 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
461 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
465 ret = mv88e6xxx_stats_wait(ds);
469 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
475 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
482 void mv88e6xxx_get_strings(struct dsa_switch *ds,
483 int nr_stats, struct mv88e6xxx_hw_stat *stats,
484 int port, uint8_t *data)
488 for (i = 0; i < nr_stats; i++) {
489 memcpy(data + i * ETH_GSTRING_LEN,
490 stats[i].string, ETH_GSTRING_LEN);
494 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
495 int nr_stats, struct mv88e6xxx_hw_stat *stats,
496 int port, uint64_t *data)
498 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
502 mutex_lock(&ps->stats_mutex);
504 ret = mv88e6xxx_stats_snapshot(ds, port);
506 mutex_unlock(&ps->stats_mutex);
510 /* Read each of the counters. */
511 for (i = 0; i < nr_stats; i++) {
512 struct mv88e6xxx_hw_stat *s = stats + i;
516 if (s->reg >= 0x100) {
519 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
524 if (s->sizeof_stat == 4) {
525 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
531 data[i] = (((u64)high) << 16) | low;
534 mv88e6xxx_stats_read(ds, s->reg, &low);
535 if (s->sizeof_stat == 8)
536 mv88e6xxx_stats_read(ds, s->reg + 1, &high);
538 data[i] = (((u64)high) << 32) | low;
541 mutex_unlock(&ps->stats_mutex);
544 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
546 return 32 * sizeof(u16);
549 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
550 struct ethtool_regs *regs, void *_p)
557 memset(p, 0xff, 32 * sizeof(u16));
559 for (i = 0; i < 32; i++) {
562 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
568 #ifdef CONFIG_NET_DSA_HWMON
570 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
572 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
578 mutex_lock(&ps->phy_mutex);
580 ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
584 /* Enable temperature sensor */
585 ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
589 ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
593 /* Wait for temperature to stabilize */
594 usleep_range(10000, 12000);
596 val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
602 /* Disable temperature sensor */
603 ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
607 *temp = ((val & 0x1f) - 5) * 5;
610 mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
611 mutex_unlock(&ps->phy_mutex);
614 #endif /* CONFIG_NET_DSA_HWMON */
616 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
618 unsigned long timeout = jiffies + HZ / 10;
620 while (time_before(jiffies, timeout)) {
623 ret = REG_READ(reg, offset);
627 usleep_range(1000, 2000);
632 int mv88e6xxx_phy_wait(struct dsa_switch *ds)
634 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x18, 0x8000);
637 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
639 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x0800);
642 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
644 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x8000);
647 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum)
651 REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);
653 ret = mv88e6xxx_phy_wait(ds);
657 return REG_READ(REG_GLOBAL2, 0x19);
660 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
663 REG_WRITE(REG_GLOBAL2, 0x19, val);
664 REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);
666 return mv88e6xxx_phy_wait(ds);
669 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
673 reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
677 e->eee_enabled = !!(reg & 0x0200);
678 e->tx_lpi_enabled = !!(reg & 0x0100);
680 reg = REG_READ(REG_PORT(port), 0);
681 e->eee_active = !!(reg & 0x0040);
686 static int mv88e6xxx_eee_enable_set(struct dsa_switch *ds, int port,
687 bool eee_enabled, bool tx_lpi_enabled)
691 reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
695 nreg = reg & ~0x0300;
702 return mv88e6xxx_phy_write_indirect(ds, port, 16, nreg);
707 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
708 struct phy_device *phydev, struct ethtool_eee *e)
712 ret = mv88e6xxx_eee_enable_set(ds, port, e->eee_enabled,
720 int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
722 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
725 mutex_lock(&ps->smi_mutex);
727 /* Port Control 1: disable trunking, disable sending
728 * learning messages to this port.
730 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x05, 0x0000);
734 /* Port based VLAN map: give each port its own address
735 * database, allow the CPU port to talk to each of the 'real'
736 * ports, and allow each of the 'real' ports to only talk to
739 reg = (port & 0xf) << 12;
740 if (dsa_is_cpu_port(ds, port))
741 reg |= ds->phys_port_mask;
743 reg |= 1 << dsa_upstream_port(ds);
745 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x06, reg);
749 /* Default VLAN ID and priority: don't set a default VLAN
750 * ID, and set the default packet priority to zero.
752 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
754 mutex_unlock(&ps->smi_mutex);
758 int mv88e6xxx_setup_common(struct dsa_switch *ds)
760 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
762 mutex_init(&ps->smi_mutex);
763 mutex_init(&ps->stats_mutex);
764 mutex_init(&ps->phy_mutex);
769 static int __init mv88e6xxx_init(void)
771 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
772 register_switch_driver(&mv88e6131_switch_driver);
774 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
775 register_switch_driver(&mv88e6123_61_65_switch_driver);
777 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
778 register_switch_driver(&mv88e6352_switch_driver);
780 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
781 register_switch_driver(&mv88e6171_switch_driver);
785 module_init(mv88e6xxx_init);
787 static void __exit mv88e6xxx_cleanup(void)
789 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
790 unregister_switch_driver(&mv88e6171_switch_driver);
792 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
793 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
795 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
796 unregister_switch_driver(&mv88e6131_switch_driver);
799 module_exit(mv88e6xxx_cleanup);
801 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
802 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
803 MODULE_LICENSE("GPL");