drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/crash_dump.h>
  45 #include <net/ip.h>
  46 #include <net/ipv6.h>
  47 #include <net/tcp.h>
  48 #include <net/checksum.h>
  49 #include <net/ip6_checksum.h>
  50 #include <linux/workqueue.h>
  51 #include <linux/crc32.h>
  52 #include <linux/crc32c.h>
  53 #include <linux/prefetch.h>
  54 #include <linux/zlib.h>
  55 #include <linux/io.h>
  56 #include <linux/semaphore.h>
  57 #include <linux/stringify.h>
  58 #include <linux/vmalloc.h>
  59
  60 #include "bnx2x.h"
  61 #include "bnx2x_init.h"
  62 #include "bnx2x_init_ops.h"
  63 #include "bnx2x_cmn.h"
  64 #include "bnx2x_vfpf.h"
  65 #include "bnx2x_dcb.h"
  66 #include "bnx2x_sp.h"
  67 #include <linux/firmware.h>
  68 #include "bnx2x_fw_file_hdr.h"
  69 /* FW files */
  70 #define FW_FILE_VERSION                                 \
  71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  78
  79 /* Time in jiffies before concluding the transmitter is hung */
  80 #define TX_TIMEOUT              (5*HZ)
  81
  82 static char version[] =
  83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  85
  86 MODULE_AUTHOR("Eliezer Tamir");
  87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  88                    "BCM57710/57711/57711E/"
  89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  90                    "57840/57840_MF Driver");
  91 MODULE_LICENSE("GPL");
  92 MODULE_VERSION(DRV_MODULE_VERSION);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  96
  97 int bnx2x_num_queues;
  98 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, S_IRUGO);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 static int int_mode;
 107 module_param(int_mode, int, S_IRUGO);
 108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 109                                 "(1 INT#x; 2 MSI)");
 110
 111 static int dropless_fc;
 112 module_param(dropless_fc, int, S_IRUGO);
 113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 114
 115 static int mrrs = -1;
 116 module_param(mrrs, int, S_IRUGO);
 117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 118
 119 static int debug;
 120 module_param(debug, int, S_IRUGO);
 121 MODULE_PARM_DESC(debug, " Default debug msglevel");
 122
 123 static struct workqueue_struct *bnx2x_wq;
 124 struct workqueue_struct *bnx2x_iov_wq;
 125
 126 struct bnx2x_mac_vals {
 127         u32 xmac_addr;
 128         u32 xmac_val;
 129         u32 emac_addr;
 130         u32 emac_val;
 131         u32 umac_addr;
 132         u32 umac_val;
 133         u32 bmac_addr;
 134         u32 bmac_val[2];
 135 };
 136
 137 enum bnx2x_board_type {
 138         BCM57710 = 0,
 139         BCM57711,
 140         BCM57711E,
 141         BCM57712,
 142         BCM57712_MF,
 143         BCM57712_VF,
 144         BCM57800,
 145         BCM57800_MF,
 146         BCM57800_VF,
 147         BCM57810,
 148         BCM57810_MF,
 149         BCM57810_VF,
 150         BCM57840_4_10,
 151         BCM57840_2_20,
 152         BCM57840_MF,
 153         BCM57840_VF,
 154         BCM57811,
 155         BCM57811_MF,
 156         BCM57840_O,
 157         BCM57840_MFO,
 158         BCM57811_VF
 159 };
 160
 161 /* indexed by board_type, above */
 162 static struct {
 163         char *name;
 164 } board_info[] = {
 165         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 166         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 167         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 168         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 169         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 170         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 171         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 172         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 173         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 175         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 176         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 178         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 179         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 180         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 181         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 182         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 183         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 184         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 185         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 186 };
 187
 188 #ifndef PCI_DEVICE_ID_NX2_57710
 189 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 190 #endif
 191 #ifndef PCI_DEVICE_ID_NX2_57711
 192 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711E
 195 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57712
 198 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 201 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 204 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57800
 207 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 210 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 213 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57810
 216 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 219 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57840_O
 222 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 225 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 228 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 231 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 234 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 237 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 240 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57811
 243 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 246 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 249 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 250 #endif
 251
 252 static const struct pci_device_id bnx2x_pci_tbl[] = {
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 274         { 0 }
 275 };
 276
 277 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 278
 279 /* Global resources for unloading a previously loaded device */
 280 #define BNX2X_PREV_WAIT_NEEDED 1
 281 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 282 static LIST_HEAD(bnx2x_prev_list);
 283
 284 /* Forward declaration */
 285 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 286 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 287 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 288
 289 /****************************************************************************
 290 * General service functions
 291 ****************************************************************************/
 292
 293 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 294
 295 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 296                                        u32 addr, dma_addr_t mapping)
 297 {
 298         REG_WR(bp,  addr, U64_LO(mapping));
 299         REG_WR(bp,  addr + 4, U64_HI(mapping));
 300 }
 301
 302 static void storm_memset_spq_addr(struct bnx2x *bp,
 303                                   dma_addr_t mapping, u16 abs_fid)
 304 {
 305         u32 addr = XSEM_REG_FAST_MEMORY +
 306                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 307
 308         __storm_memset_dma_mapping(bp, addr, mapping);
 309 }
 310
 311 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 312                                   u16 pf_id)
 313 {
 314         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 315                 pf_id);
 316         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 317                 pf_id);
 318         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 319                 pf_id);
 320         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 321                 pf_id);
 322 }
 323
 324 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 325                                  u8 enable)
 326 {
 327         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 328                 enable);
 329         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 330                 enable);
 331         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 332                 enable);
 333         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 334                 enable);
 335 }
 336
 337 static void storm_memset_eq_data(struct bnx2x *bp,
 338                                  struct event_ring_data *eq_data,
 339                                 u16 pfid)
 340 {
 341         size_t size = sizeof(struct event_ring_data);
 342
 343         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 344
 345         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 346 }
 347
 348 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 349                                  u16 pfid)
 350 {
 351         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 352         REG_WR16(bp, addr, eq_prod);
 353 }
 354
 355 /* used only at init
 356  * locking is done by mcp
 357  */
 358 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 359 {
 360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 363                                PCICFG_VENDOR_ID_OFFSET);
 364 }
 365
 366 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 367 {
 368         u32 val;
 369
 370         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 371         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 372         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 373                                PCICFG_VENDOR_ID_OFFSET);
 374
 375         return val;
 376 }
 377
 378 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 379 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 380 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 381 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 382 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 383
 384 static void bnx2x_dp_dmae(struct bnx2x *bp,
 385                           struct dmae_command *dmae, int msglvl)
 386 {
 387         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 388         int i;
 389
 390         switch (dmae->opcode & DMAE_COMMAND_DST) {
 391         case DMAE_CMD_DST_PCI:
 392                 if (src_type == DMAE_CMD_SRC_PCI)
 393                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 394                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 395                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 396                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 397                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 398                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 399                            dmae->comp_val);
 400                 else
 401                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 402                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 403                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 404                            dmae->opcode, dmae->src_addr_lo >> 2,
 405                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 406                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 407                            dmae->comp_val);
 408                 break;
 409         case DMAE_CMD_DST_GRC:
 410                 if (src_type == DMAE_CMD_SRC_PCI)
 411                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 412                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 413                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 414                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 415                            dmae->len, dmae->dst_addr_lo >> 2,
 416                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 417                            dmae->comp_val);
 418                 else
 419                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 420                            "src [%08x], len [%d*4], dst [%08x]\n"
 421                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 422                            dmae->opcode, dmae->src_addr_lo >> 2,
 423                            dmae->len, dmae->dst_addr_lo >> 2,
 424                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 425                            dmae->comp_val);
 426                 break;
 427         default:
 428                 if (src_type == DMAE_CMD_SRC_PCI)
 429                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 430                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 431                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 432                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 433                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 434                            dmae->comp_val);
 435                 else
 436                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 437                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 438                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 439                            dmae->opcode, dmae->src_addr_lo >> 2,
 440                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 441                            dmae->comp_val);
 442                 break;
 443         }
 444
 445         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 446                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 447                    i, *(((u32 *)dmae) + i));
 448 }
 449
 450 /* copy command into DMAE command memory and set DMAE command go */
 451 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 452 {
 453         u32 cmd_offset;
 454         int i;
 455
 456         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 457         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 458                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 459         }
 460         REG_WR(bp, dmae_reg_go_c[idx], 1);
 461 }
 462
 463 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 464 {
 465         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 466                            DMAE_CMD_C_ENABLE);
 467 }
 468
 469 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 470 {
 471         return opcode & ~DMAE_CMD_SRC_RESET;
 472 }
 473
 474 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 475                              bool with_comp, u8 comp_type)
 476 {
 477         u32 opcode = 0;
 478
 479         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 480                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 481
 482         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 483
 484         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 485         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 486                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 487         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 488
 489 #ifdef __BIG_ENDIAN
 490         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 491 #else
 492         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 493 #endif
 494         if (with_comp)
 495                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 496         return opcode;
 497 }
 498
 499 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 500                                       struct dmae_command *dmae,
 501                                       u8 src_type, u8 dst_type)
 502 {
 503         memset(dmae, 0, sizeof(struct dmae_command));
 504
 505         /* set the opcode */
 506         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 507                                          true, DMAE_COMP_PCI);
 508
 509         /* fill in the completion parameters */
 510         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 511         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 512         dmae->comp_val = DMAE_COMP_VAL;
 513 }
 514
 515 /* issue a dmae command over the init-channel and wait for completion */
 516 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 517                                u32 *comp)
 518 {
 519         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 520         int rc = 0;
 521
 522         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 523
 524         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 525          * as long as this code is called both from syscall context and
 526          * from ndo_set_rx_mode() flow that may be called from BH.
 527          */
 528
 529         spin_lock_bh(&bp->dmae_lock);
 530
 531         /* reset completion */
 532         *comp = 0;
 533
 534         /* post the command on the channel used for initializations */
 535         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 536
 537         /* wait for completion */
 538         udelay(5);
 539         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 540
 541                 if (!cnt ||
 542                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 543                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 544                         BNX2X_ERR("DMAE timeout!\n");
 545                         rc = DMAE_TIMEOUT;
 546                         goto unlock;
 547                 }
 548                 cnt--;
 549                 udelay(50);
 550         }
 551         if (*comp & DMAE_PCI_ERR_FLAG) {
 552                 BNX2X_ERR("DMAE PCI error!\n");
 553                 rc = DMAE_PCI_ERROR;
 554         }
 555
 556 unlock:
 557
 558         spin_unlock_bh(&bp->dmae_lock);
 559
 560         return rc;
 561 }
 562
 563 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 564                       u32 len32)
 565 {
 566         int rc;
 567         struct dmae_command dmae;
 568
 569         if (!bp->dmae_ready) {
 570                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 571
 572                 if (CHIP_IS_E1(bp))
 573                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 574                 else
 575                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 576                 return;
 577         }
 578
 579         /* set opcode and fixed command fields */
 580         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 581
 582         /* fill in addresses and len */
 583         dmae.src_addr_lo = U64_LO(dma_addr);
 584         dmae.src_addr_hi = U64_HI(dma_addr);
 585         dmae.dst_addr_lo = dst_addr >> 2;
 586         dmae.dst_addr_hi = 0;
 587         dmae.len = len32;
 588
 589         /* issue the command and wait for completion */
 590         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 591         if (rc) {
 592                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 593 #ifdef BNX2X_STOP_ON_ERROR
 594                 bnx2x_panic();
 595 #endif
 596         }
 597 }
 598
 599 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 600 {
 601         int rc;
 602         struct dmae_command dmae;
 603
 604         if (!bp->dmae_ready) {
 605                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 606                 int i;
 607
 608                 if (CHIP_IS_E1(bp))
 609                         for (i = 0; i < len32; i++)
 610                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 611                 else
 612                         for (i = 0; i < len32; i++)
 613                                 data[i] = REG_RD(bp, src_addr + i*4);
 614
 615                 return;
 616         }
 617
 618         /* set opcode and fixed command fields */
 619         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 620
 621         /* fill in addresses and len */
 622         dmae.src_addr_lo = src_addr >> 2;
 623         dmae.src_addr_hi = 0;
 624         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 625         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 626         dmae.len = len32;
 627
 628         /* issue the command and wait for completion */
 629         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 630         if (rc) {
 631                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 632 #ifdef BNX2X_STOP_ON_ERROR
 633                 bnx2x_panic();
 634 #endif
 635         }
 636 }
 637
 638 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 639                                       u32 addr, u32 len)
 640 {
 641         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 642         int offset = 0;
 643
 644         while (len > dmae_wr_max) {
 645                 bnx2x_write_dmae(bp, phys_addr + offset,
 646                                  addr + offset, dmae_wr_max);
 647                 offset += dmae_wr_max * 4;
 648                 len -= dmae_wr_max;
 649         }
 650
 651         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 652 }
 653
 654 enum storms {
 655            XSTORM,
 656            TSTORM,
 657            CSTORM,
 658            USTORM,
 659            MAX_STORMS
 660 };
 661
 662 #define STORMS_NUM 4
 663 #define REGS_IN_ENTRY 4
 664
 665 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 666                                               enum storms storm,
 667                                               int entry)
 668 {
 669         switch (storm) {
 670         case XSTORM:
 671                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 672         case TSTORM:
 673                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 674         case CSTORM:
 675                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 676         case USTORM:
 677                 return USTORM_ASSERT_LIST_OFFSET(entry);
 678         case MAX_STORMS:
 679         default:
 680                 BNX2X_ERR("unknown storm\n");
 681         }
 682         return -EINVAL;
 683 }
 684
 685 static int bnx2x_mc_assert(struct bnx2x *bp)
 686 {
 687         char last_idx;
 688         int i, j, rc = 0;
 689         enum storms storm;
 690         u32 regs[REGS_IN_ENTRY];
 691         u32 bar_storm_intmem[STORMS_NUM] = {
 692                 BAR_XSTRORM_INTMEM,
 693                 BAR_TSTRORM_INTMEM,
 694                 BAR_CSTRORM_INTMEM,
 695                 BAR_USTRORM_INTMEM
 696         };
 697         u32 storm_assert_list_index[STORMS_NUM] = {
 698                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 699                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 700                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 701                 USTORM_ASSERT_LIST_INDEX_OFFSET
 702         };
 703         char *storms_string[STORMS_NUM] = {
 704                 "XSTORM",
 705                 "TSTORM",
 706                 "CSTORM",
 707                 "USTORM"
 708         };
 709
 710         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 711                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 712                                    storm_assert_list_index[storm]);
 713                 if (last_idx)
 714                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 715                                   storms_string[storm], last_idx);
 716
 717                 /* print the asserts */
 718                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 719                         /* read a single assert entry */
 720                         for (j = 0; j < REGS_IN_ENTRY; j++)
 721                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 722                                           bnx2x_get_assert_list_entry(bp,
 723                                                                       storm,
 724                                                                       i) +
 725                                           sizeof(u32) * j);
 726
 727                         /* log entry if it contains a valid assert */
 728                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 729                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 730                                           storms_string[storm], i, regs[3],
 731                                           regs[2], regs[1], regs[0]);
 732                                 rc++;
 733                         } else {
 734                                 break;
 735                         }
 736                 }
 737         }
 738
 739         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 740                   CHIP_IS_E1(bp) ? "everest1" :
 741                   CHIP_IS_E1H(bp) ? "everest1h" :
 742                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 743                   BCM_5710_FW_MAJOR_VERSION,
 744                   BCM_5710_FW_MINOR_VERSION,
 745                   BCM_5710_FW_REVISION_VERSION);
 746
 747         return rc;
 748 }
 749
 750 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 751 #define SCRATCH_BUFFER_SIZE(bp) \
 752         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 753
 754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 755 {
 756         u32 addr, val;
 757         u32 mark, offset;
 758         __be32 data[9];
 759         int word;
 760         u32 trace_shmem_base;
 761         if (BP_NOMCP(bp)) {
 762                 BNX2X_ERR("NO MCP - can not dump\n");
 763                 return;
 764         }
 765         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 766                 (bp->common.bc_ver & 0xff0000) >> 16,
 767                 (bp->common.bc_ver & 0xff00) >> 8,
 768                 (bp->common.bc_ver & 0xff));
 769
 770         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 771         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 772                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 773
 774         if (BP_PATH(bp) == 0)
 775                 trace_shmem_base = bp->common.shmem_base;
 776         else
 777                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 778
 779         /* sanity */
 780         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 781             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 782                                 SCRATCH_BUFFER_SIZE(bp)) {
 783                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 784                           trace_shmem_base);
 785                 return;
 786         }
 787
 788         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 789
 790         /* validate TRCB signature */
 791         mark = REG_RD(bp, addr);
 792         if (mark != MFW_TRACE_SIGNATURE) {
 793                 BNX2X_ERR("Trace buffer signature is missing.");
 794                 return ;
 795         }
 796
 797         /* read cyclic buffer pointer */
 798         addr += 4;
 799         mark = REG_RD(bp, addr);
 800         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 801         if (mark >= trace_shmem_base || mark < addr + 4) {
 802                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 803                 return;
 804         }
 805         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 806
 807         printk("%s", lvl);
 808
 809         /* dump buffer after the mark */
 810         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 811                 for (word = 0; word < 8; word++)
 812                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 813                 data[8] = 0x0;
 814                 pr_cont("%s", (char *)data);
 815         }
 816
 817         /* dump buffer before the mark */
 818         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 819                 for (word = 0; word < 8; word++)
 820                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 821                 data[8] = 0x0;
 822                 pr_cont("%s", (char *)data);
 823         }
 824         printk("%s" "end of fw dump\n", lvl);
 825 }
 826
 827 static void bnx2x_fw_dump(struct bnx2x *bp)
 828 {
 829         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 830 }
 831
 832 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 833 {
 834         int port = BP_PORT(bp);
 835         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 836         u32 val = REG_RD(bp, addr);
 837
 838         /* in E1 we must use only PCI configuration space to disable
 839          * MSI/MSIX capability
 840          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 841          */
 842         if (CHIP_IS_E1(bp)) {
 843                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 844                  * Use mask register to prevent from HC sending interrupts
 845                  * after we exit the function
 846                  */
 847                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 848
 849                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 850                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 851                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 852         } else
 853                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 854                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 855                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 856                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 857
 858         DP(NETIF_MSG_IFDOWN,
 859            "write %x to HC %d (addr 0x%x)\n",
 860            val, port, addr);
 861
 862         /* flush all outstanding writes */
 863         mmiowb();
 864
 865         REG_WR(bp, addr, val);
 866         if (REG_RD(bp, addr) != val)
 867                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 868 }
 869
 870 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 871 {
 872         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 873
 874         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 875                  IGU_PF_CONF_INT_LINE_EN |
 876                  IGU_PF_CONF_ATTN_BIT_EN);
 877
 878         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 879
 880         /* flush all outstanding writes */
 881         mmiowb();
 882
 883         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 884         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 885                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 886 }
 887
 888 static void bnx2x_int_disable(struct bnx2x *bp)
 889 {
 890         if (bp->common.int_block == INT_BLOCK_HC)
 891                 bnx2x_hc_int_disable(bp);
 892         else
 893                 bnx2x_igu_int_disable(bp);
 894 }
 895
 896 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 897 {
 898         int i;
 899         u16 j;
 900         struct hc_sp_status_block_data sp_sb_data;
 901         int func = BP_FUNC(bp);
 902 #ifdef BNX2X_STOP_ON_ERROR
 903         u16 start = 0, end = 0;
 904         u8 cos;
 905 #endif
 906         if (IS_PF(bp) && disable_int)
 907                 bnx2x_int_disable(bp);
 908
 909         bp->stats_state = STATS_STATE_DISABLED;
 910         bp->eth_stats.unrecoverable_error++;
 911         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 912
 913         BNX2X_ERR("begin crash dump -----------------\n");
 914
 915         /* Indices */
 916         /* Common */
 917         if (IS_PF(bp)) {
 918                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 919                 int data_size, cstorm_offset;
 920
 921                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 922                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 923                           bp->spq_prod_idx, bp->stats_counter);
 924                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 925                           def_sb->atten_status_block.attn_bits,
 926                           def_sb->atten_status_block.attn_bits_ack,
 927                           def_sb->atten_status_block.status_block_id,
 928                           def_sb->atten_status_block.attn_bits_index);
 929                 BNX2X_ERR("     def (");
 930                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 931                         pr_cont("0x%x%s",
 932                                 def_sb->sp_sb.index_values[i],
 933                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 934
 935                 data_size = sizeof(struct hc_sp_status_block_data) /
 936                             sizeof(u32);
 937                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 938                 for (i = 0; i < data_size; i++)
 939                         *((u32 *)&sp_sb_data + i) =
 940                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 941                                            i * sizeof(u32));
 942
 943                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 944                         sp_sb_data.igu_sb_id,
 945                         sp_sb_data.igu_seg_id,
 946                         sp_sb_data.p_func.pf_id,
 947                         sp_sb_data.p_func.vnic_id,
 948                         sp_sb_data.p_func.vf_id,
 949                         sp_sb_data.p_func.vf_valid,
 950                         sp_sb_data.state);
 951         }
 952
 953         for_each_eth_queue(bp, i) {
 954                 struct bnx2x_fastpath *fp = &bp->fp[i];
 955                 int loop;
 956                 struct hc_status_block_data_e2 sb_data_e2;
 957                 struct hc_status_block_data_e1x sb_data_e1x;
 958                 struct hc_status_block_sm  *hc_sm_p =
 959                         CHIP_IS_E1x(bp) ?
 960                         sb_data_e1x.common.state_machine :
 961                         sb_data_e2.common.state_machine;
 962                 struct hc_index_data *hc_index_p =
 963                         CHIP_IS_E1x(bp) ?
 964                         sb_data_e1x.index_data :
 965                         sb_data_e2.index_data;
 966                 u8 data_size, cos;
 967                 u32 *sb_data_p;
 968                 struct bnx2x_fp_txdata txdata;
 969
 970                 if (!bp->fp)
 971                         break;
 972
 973                 if (!fp->rx_cons_sb)
 974                         continue;
 975
 976                 /* Rx */
 977                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 978                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 979                           fp->rx_comp_prod,
 980                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 981                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 982                           fp->rx_sge_prod, fp->last_max_sge,
 983                           le16_to_cpu(fp->fp_hc_idx));
 984
 985                 /* Tx */
 986                 for_each_cos_in_tx_queue(fp, cos)
 987                 {
 988                         if (!fp->txdata_ptr[cos])
 989                                 break;
 990
 991                         txdata = *fp->txdata_ptr[cos];
 992
 993                         if (!txdata.tx_cons_sb)
 994                                 continue;
 995
 996                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 997                                   i, txdata.tx_pkt_prod,
 998                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 999                                   txdata.tx_bd_cons,
1000                                   le16_to_cpu(*txdata.tx_cons_sb));
1001                 }
1002
1003                 loop = CHIP_IS_E1x(bp) ?
1004                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1005
1006                 /* host sb data */
1007
1008                 if (IS_FCOE_FP(fp))
1009                         continue;
1010
1011                 BNX2X_ERR("     run indexes (");
1012                 for (j = 0; j < HC_SB_MAX_SM; j++)
1013                         pr_cont("0x%x%s",
1014                                fp->sb_running_index[j],
1015                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1016
1017                 BNX2X_ERR("     indexes (");
1018                 for (j = 0; j < loop; j++)
1019                         pr_cont("0x%x%s",
1020                                fp->sb_index_values[j],
1021                                (j == loop - 1) ? ")" : " ");
1022
1023                 /* VF cannot access FW refelection for status block */
1024                 if (IS_VF(bp))
1025                         continue;
1026
1027                 /* fw sb data */
1028                 data_size = CHIP_IS_E1x(bp) ?
1029                         sizeof(struct hc_status_block_data_e1x) :
1030                         sizeof(struct hc_status_block_data_e2);
1031                 data_size /= sizeof(u32);
1032                 sb_data_p = CHIP_IS_E1x(bp) ?
1033                         (u32 *)&sb_data_e1x :
1034                         (u32 *)&sb_data_e2;
1035                 /* copy sb data in here */
1036                 for (j = 0; j < data_size; j++)
1037                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1038                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1039                                 j * sizeof(u32));
1040
1041                 if (!CHIP_IS_E1x(bp)) {
1042                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1043                                 sb_data_e2.common.p_func.pf_id,
1044                                 sb_data_e2.common.p_func.vf_id,
1045                                 sb_data_e2.common.p_func.vf_valid,
1046                                 sb_data_e2.common.p_func.vnic_id,
1047                                 sb_data_e2.common.same_igu_sb_1b,
1048                                 sb_data_e2.common.state);
1049                 } else {
1050                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1051                                 sb_data_e1x.common.p_func.pf_id,
1052                                 sb_data_e1x.common.p_func.vf_id,
1053                                 sb_data_e1x.common.p_func.vf_valid,
1054                                 sb_data_e1x.common.p_func.vnic_id,
1055                                 sb_data_e1x.common.same_igu_sb_1b,
1056                                 sb_data_e1x.common.state);
1057                 }
1058
1059                 /* SB_SMs data */
1060                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1061                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1062                                 j, hc_sm_p[j].__flags,
1063                                 hc_sm_p[j].igu_sb_id,
1064                                 hc_sm_p[j].igu_seg_id,
1065                                 hc_sm_p[j].time_to_expire,
1066                                 hc_sm_p[j].timer_value);
1067                 }
1068
1069                 /* Indices data */
1070                 for (j = 0; j < loop; j++) {
1071                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1072                                hc_index_p[j].flags,
1073                                hc_index_p[j].timeout);
1074                 }
1075         }
1076
1077 #ifdef BNX2X_STOP_ON_ERROR
1078         if (IS_PF(bp)) {
1079                 /* event queue */
1080                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1081                 for (i = 0; i < NUM_EQ_DESC; i++) {
1082                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1083
1084                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1085                                   i, bp->eq_ring[i].message.opcode,
1086                                   bp->eq_ring[i].message.error);
1087                         BNX2X_ERR("data: %x %x %x\n",
1088                                   data[0], data[1], data[2]);
1089                 }
1090         }
1091
1092         /* Rings */
1093         /* Rx */
1094         for_each_valid_rx_queue(bp, i) {
1095                 struct bnx2x_fastpath *fp = &bp->fp[i];
1096
1097                 if (!bp->fp)
1098                         break;
1099
1100                 if (!fp->rx_cons_sb)
1101                         continue;
1102
1103                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1104                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1105                 for (j = start; j != end; j = RX_BD(j + 1)) {
1106                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1107                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1108
1109                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1110                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1111                 }
1112
1113                 start = RX_SGE(fp->rx_sge_prod);
1114                 end = RX_SGE(fp->last_max_sge);
1115                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1116                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1117                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1118
1119                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1120                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1121                 }
1122
1123                 start = RCQ_BD(fp->rx_comp_cons - 10);
1124                 end = RCQ_BD(fp->rx_comp_cons + 503);
1125                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1126                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1127
1128                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1129                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1130                 }
1131         }
1132
1133         /* Tx */
1134         for_each_valid_tx_queue(bp, i) {
1135                 struct bnx2x_fastpath *fp = &bp->fp[i];
1136
1137                 if (!bp->fp)
1138                         break;
1139
1140                 for_each_cos_in_tx_queue(fp, cos) {
1141                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1142
1143                         if (!fp->txdata_ptr[cos])
1144                                 break;
1145
1146                         if (!txdata->tx_cons_sb)
1147                                 continue;
1148
1149                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1150                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1151                         for (j = start; j != end; j = TX_BD(j + 1)) {
1152                                 struct sw_tx_bd *sw_bd =
1153                                         &txdata->tx_buf_ring[j];
1154
1155                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1156                                           i, cos, j, sw_bd->skb,
1157                                           sw_bd->first_bd);
1158                         }
1159
1160                         start = TX_BD(txdata->tx_bd_cons - 10);
1161                         end = TX_BD(txdata->tx_bd_cons + 254);
1162                         for (j = start; j != end; j = TX_BD(j + 1)) {
1163                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1164
1165                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1166                                           i, cos, j, tx_bd[0], tx_bd[1],
1167                                           tx_bd[2], tx_bd[3]);
1168                         }
1169                 }
1170         }
1171 #endif
1172         if (IS_PF(bp)) {
1173                 bnx2x_fw_dump(bp);
1174                 bnx2x_mc_assert(bp);
1175         }
1176         BNX2X_ERR("end crash dump -----------------\n");
1177 }
1178
1179 /*
1180  * FLR Support for E2
1181  *
1182  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1183  * initialization.
1184  */
1185 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1186 #define FLR_WAIT_INTERVAL       50      /* usec */
1187 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1188
1189 struct pbf_pN_buf_regs {
1190         int pN;
1191         u32 init_crd;
1192         u32 crd;
1193         u32 crd_freed;
1194 };
1195
1196 struct pbf_pN_cmd_regs {
1197         int pN;
1198         u32 lines_occup;
1199         u32 lines_freed;
1200 };
1201
1202 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1203                                      struct pbf_pN_buf_regs *regs,
1204                                      u32 poll_count)
1205 {
1206         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1207         u32 cur_cnt = poll_count;
1208
1209         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1210         crd = crd_start = REG_RD(bp, regs->crd);
1211         init_crd = REG_RD(bp, regs->init_crd);
1212
1213         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1214         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1215         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1216
1217         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1218                (init_crd - crd_start))) {
1219                 if (cur_cnt--) {
1220                         udelay(FLR_WAIT_INTERVAL);
1221                         crd = REG_RD(bp, regs->crd);
1222                         crd_freed = REG_RD(bp, regs->crd_freed);
1223                 } else {
1224                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1225                            regs->pN);
1226                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1227                            regs->pN, crd);
1228                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1229                            regs->pN, crd_freed);
1230                         break;
1231                 }
1232         }
1233         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1234            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1235 }
1236
1237 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1238                                      struct pbf_pN_cmd_regs *regs,
1239                                      u32 poll_count)
1240 {
1241         u32 occup, to_free, freed, freed_start;
1242         u32 cur_cnt = poll_count;
1243
1244         occup = to_free = REG_RD(bp, regs->lines_occup);
1245         freed = freed_start = REG_RD(bp, regs->lines_freed);
1246
1247         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1248         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1249
1250         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1251                 if (cur_cnt--) {
1252                         udelay(FLR_WAIT_INTERVAL);
1253                         occup = REG_RD(bp, regs->lines_occup);
1254                         freed = REG_RD(bp, regs->lines_freed);
1255                 } else {
1256                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1257                            regs->pN);
1258                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1259                            regs->pN, occup);
1260                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1261                            regs->pN, freed);
1262                         break;
1263                 }
1264         }
1265         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1266            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1267 }
1268
1269 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1270                                     u32 expected, u32 poll_count)
1271 {
1272         u32 cur_cnt = poll_count;
1273         u32 val;
1274
1275         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1276                 udelay(FLR_WAIT_INTERVAL);
1277
1278         return val;
1279 }
1280
1281 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1282                                     char *msg, u32 poll_cnt)
1283 {
1284         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1285         if (val != 0) {
1286                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1287                 return 1;
1288         }
1289         return 0;
1290 }
1291
1292 /* Common routines with VF FLR cleanup */
1293 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1294 {
1295         /* adjust polling timeout */
1296         if (CHIP_REV_IS_EMUL(bp))
1297                 return FLR_POLL_CNT * 2000;
1298
1299         if (CHIP_REV_IS_FPGA(bp))
1300                 return FLR_POLL_CNT * 120;
1301
1302         return FLR_POLL_CNT;
1303 }
1304
1305 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1306 {
1307         struct pbf_pN_cmd_regs cmd_regs[] = {
1308                 {0, (CHIP_IS_E3B0(bp)) ?
1309                         PBF_REG_TQ_OCCUPANCY_Q0 :
1310                         PBF_REG_P0_TQ_OCCUPANCY,
1311                     (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1313                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1314                 {1, (CHIP_IS_E3B0(bp)) ?
1315                         PBF_REG_TQ_OCCUPANCY_Q1 :
1316                         PBF_REG_P1_TQ_OCCUPANCY,
1317                     (CHIP_IS_E3B0(bp)) ?
1318                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1319                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1320                 {4, (CHIP_IS_E3B0(bp)) ?
1321                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1322                         PBF_REG_P4_TQ_OCCUPANCY,
1323                     (CHIP_IS_E3B0(bp)) ?
1324                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1325                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1326         };
1327
1328         struct pbf_pN_buf_regs buf_regs[] = {
1329                 {0, (CHIP_IS_E3B0(bp)) ?
1330                         PBF_REG_INIT_CRD_Q0 :
1331                         PBF_REG_P0_INIT_CRD ,
1332                     (CHIP_IS_E3B0(bp)) ?
1333                         PBF_REG_CREDIT_Q0 :
1334                         PBF_REG_P0_CREDIT,
1335                     (CHIP_IS_E3B0(bp)) ?
1336                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1337                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1338                 {1, (CHIP_IS_E3B0(bp)) ?
1339                         PBF_REG_INIT_CRD_Q1 :
1340                         PBF_REG_P1_INIT_CRD,
1341                     (CHIP_IS_E3B0(bp)) ?
1342                         PBF_REG_CREDIT_Q1 :
1343                         PBF_REG_P1_CREDIT,
1344                     (CHIP_IS_E3B0(bp)) ?
1345                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1346                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1347                 {4, (CHIP_IS_E3B0(bp)) ?
1348                         PBF_REG_INIT_CRD_LB_Q :
1349                         PBF_REG_P4_INIT_CRD,
1350                     (CHIP_IS_E3B0(bp)) ?
1351                         PBF_REG_CREDIT_LB_Q :
1352                         PBF_REG_P4_CREDIT,
1353                     (CHIP_IS_E3B0(bp)) ?
1354                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1355                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1356         };
1357
1358         int i;
1359
1360         /* Verify the command queues are flushed P0, P1, P4 */
1361         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1362                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1363
1364         /* Verify the transmission buffers are flushed P0, P1, P4 */
1365         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1366                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1367 }
1368
1369 #define OP_GEN_PARAM(param) \
1370         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1371
1372 #define OP_GEN_TYPE(type) \
1373         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1374
1375 #define OP_GEN_AGG_VECT(index) \
1376         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1377
1378 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1379 {
1380         u32 op_gen_command = 0;
1381         u32 comp_addr = BAR_CSTRORM_INTMEM +
1382                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1383         int ret = 0;
1384
1385         if (REG_RD(bp, comp_addr)) {
1386                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1387                 return 1;
1388         }
1389
1390         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1391         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1392         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1393         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1394
1395         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1396         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1397
1398         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1399                 BNX2X_ERR("FW final cleanup did not succeed\n");
1400                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1401                    (REG_RD(bp, comp_addr)));
1402                 bnx2x_panic();
1403                 return 1;
1404         }
1405         /* Zero completion for next FLR */
1406         REG_WR(bp, comp_addr, 0);
1407
1408         return ret;
1409 }
1410
1411 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1412 {
1413         u16 status;
1414
1415         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1416         return status & PCI_EXP_DEVSTA_TRPND;
1417 }
1418
1419 /* PF FLR specific routines
1420 */
1421 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1422 {
1423         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1424         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1426                         "CFC PF usage counter timed out",
1427                         poll_cnt))
1428                 return 1;
1429
1430         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1431         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432                         DORQ_REG_PF_USAGE_CNT,
1433                         "DQ PF usage counter timed out",
1434                         poll_cnt))
1435                 return 1;
1436
1437         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1438         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1439                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1440                         "QM PF usage counter timed out",
1441                         poll_cnt))
1442                 return 1;
1443
1444         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1445         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1446                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1447                         "Timers VNIC usage counter timed out",
1448                         poll_cnt))
1449                 return 1;
1450         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1451                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1452                         "Timers NUM_SCANS usage counter timed out",
1453                         poll_cnt))
1454                 return 1;
1455
1456         /* Wait DMAE PF usage counter to zero */
1457         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1458                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1459                         "DMAE command register timed out",
1460                         poll_cnt))
1461                 return 1;
1462
1463         return 0;
1464 }
1465
1466 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1467 {
1468         u32 val;
1469
1470         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1471         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1472
1473         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1474         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1475
1476         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1477         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1478
1479         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1480         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1481
1482         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1483         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1484
1485         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1486         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1487
1488         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1489         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1490
1491         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1492         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1493            val);
1494 }
1495
1496 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1497 {
1498         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1499
1500         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1501
1502         /* Re-enable PF target read access */
1503         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1504
1505         /* Poll HW usage counters */
1506         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1507         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1508                 return -EBUSY;
1509
1510         /* Zero the igu 'trailing edge' and 'leading edge' */
1511
1512         /* Send the FW cleanup command */
1513         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1514                 return -EBUSY;
1515
1516         /* ATC cleanup */
1517
1518         /* Verify TX hw is flushed */
1519         bnx2x_tx_hw_flushed(bp, poll_cnt);
1520
1521         /* Wait 100ms (not adjusted according to platform) */
1522         msleep(100);
1523
1524         /* Verify no pending pci transactions */
1525         if (bnx2x_is_pcie_pending(bp->pdev))
1526                 BNX2X_ERR("PCIE Transactions still pending\n");
1527
1528         /* Debug */
1529         bnx2x_hw_enable_status(bp);
1530
1531         /*
1532          * Master enable - Due to WB DMAE writes performed before this
1533          * register is re-initialized as part of the regular function init
1534          */
1535         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1536
1537         return 0;
1538 }
1539
1540 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1541 {
1542         int port = BP_PORT(bp);
1543         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1544         u32 val = REG_RD(bp, addr);
1545         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1546         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1547         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1548
1549         if (msix) {
1550                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1551                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1552                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1553                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1554                 if (single_msix)
1555                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1556         } else if (msi) {
1557                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1558                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1559                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1560                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1561         } else {
1562                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1565                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1566
1567                 if (!CHIP_IS_E1(bp)) {
1568                         DP(NETIF_MSG_IFUP,
1569                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1570
1571                         REG_WR(bp, addr, val);
1572
1573                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1574                 }
1575         }
1576
1577         if (CHIP_IS_E1(bp))
1578                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1579
1580         DP(NETIF_MSG_IFUP,
1581            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1582            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1583
1584         REG_WR(bp, addr, val);
1585         /*
1586          * Ensure that HC_CONFIG is written before leading/trailing edge config
1587          */
1588         mmiowb();
1589         barrier();
1590
1591         if (!CHIP_IS_E1(bp)) {
1592                 /* init leading/trailing edge */
1593                 if (IS_MF(bp)) {
1594                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1595                         if (bp->port.pmf)
1596                                 /* enable nig and gpio3 attention */
1597                                 val |= 0x1100;
1598                 } else
1599                         val = 0xffff;
1600
1601                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1602                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1603         }
1604
1605         /* Make sure that interrupts are indeed enabled from here on */
1606         mmiowb();
1607 }
1608
1609 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1610 {
1611         u32 val;
1612         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1613         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1614         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1615
1616         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1617
1618         if (msix) {
1619                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1620                          IGU_PF_CONF_SINGLE_ISR_EN);
1621                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1622                         IGU_PF_CONF_ATTN_BIT_EN);
1623
1624                 if (single_msix)
1625                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1626         } else if (msi) {
1627                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1628                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1629                         IGU_PF_CONF_ATTN_BIT_EN |
1630                         IGU_PF_CONF_SINGLE_ISR_EN);
1631         } else {
1632                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1633                 val |= (IGU_PF_CONF_INT_LINE_EN |
1634                         IGU_PF_CONF_ATTN_BIT_EN |
1635                         IGU_PF_CONF_SINGLE_ISR_EN);
1636         }
1637
1638         /* Clean previous status - need to configure igu prior to ack*/
1639         if ((!msix) || single_msix) {
1640                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641                 bnx2x_ack_int(bp);
1642         }
1643
1644         val |= IGU_PF_CONF_FUNC_EN;
1645
1646         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1647            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1648
1649         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650
1651         if (val & IGU_PF_CONF_INT_LINE_EN)
1652                 pci_intx(bp->pdev, true);
1653
1654         barrier();
1655
1656         /* init leading/trailing edge */
1657         if (IS_MF(bp)) {
1658                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1659                 if (bp->port.pmf)
1660                         /* enable nig and gpio3 attention */
1661                         val |= 0x1100;
1662         } else
1663                 val = 0xffff;
1664
1665         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1666         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1667
1668         /* Make sure that interrupts are indeed enabled from here on */
1669         mmiowb();
1670 }
1671
1672 void bnx2x_int_enable(struct bnx2x *bp)
1673 {
1674         if (bp->common.int_block == INT_BLOCK_HC)
1675                 bnx2x_hc_int_enable(bp);
1676         else
1677                 bnx2x_igu_int_enable(bp);
1678 }
1679
1680 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1681 {
1682         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1683         int i, offset;
1684
1685         if (disable_hw)
1686                 /* prevent the HW from sending interrupts */
1687                 bnx2x_int_disable(bp);
1688
1689         /* make sure all ISRs are done */
1690         if (msix) {
1691                 synchronize_irq(bp->msix_table[0].vector);
1692                 offset = 1;
1693                 if (CNIC_SUPPORT(bp))
1694                         offset++;
1695                 for_each_eth_queue(bp, i)
1696                         synchronize_irq(bp->msix_table[offset++].vector);
1697         } else
1698                 synchronize_irq(bp->pdev->irq);
1699
1700         /* make sure sp_task is not running */
1701         cancel_delayed_work(&bp->sp_task);
1702         cancel_delayed_work(&bp->period_task);
1703         flush_workqueue(bnx2x_wq);
1704 }
1705
1706 /* fast path */
1707
1708 /*
1709  * General service functions
1710  */
1711
1712 /* Return true if succeeded to acquire the lock */
1713 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1714 {
1715         u32 lock_status;
1716         u32 resource_bit = (1 << resource);
1717         int func = BP_FUNC(bp);
1718         u32 hw_lock_control_reg;
1719
1720         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1721            "Trying to take a lock on resource %d\n", resource);
1722
1723         /* Validating that the resource is within range */
1724         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1725                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1726                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1727                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1728                 return false;
1729         }
1730
1731         if (func <= 5)
1732                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1733         else
1734                 hw_lock_control_reg =
1735                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1736
1737         /* Try to acquire the lock */
1738         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1739         lock_status = REG_RD(bp, hw_lock_control_reg);
1740         if (lock_status & resource_bit)
1741                 return true;
1742
1743         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1744            "Failed to get a lock on resource %d\n", resource);
1745         return false;
1746 }
1747
1748 /**
1749  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1750  *
1751  * @bp: driver handle
1752  *
1753  * Returns the recovery leader resource id according to the engine this function
1754  * belongs to. Currently only only 2 engines is supported.
1755  */
1756 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1757 {
1758         if (BP_PATH(bp))
1759                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1760         else
1761                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1762 }
1763
1764 /**
1765  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1766  *
1767  * @bp: driver handle
1768  *
1769  * Tries to acquire a leader lock for current engine.
1770  */
1771 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1772 {
1773         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1774 }
1775
1776 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1777
1778 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1779 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1780 {
1781         /* Set the interrupt occurred bit for the sp-task to recognize it
1782          * must ack the interrupt and transition according to the IGU
1783          * state machine.
1784          */
1785         atomic_set(&bp->interrupt_occurred, 1);
1786
1787         /* The sp_task must execute only after this bit
1788          * is set, otherwise we will get out of sync and miss all
1789          * further interrupts. Hence, the barrier.
1790          */
1791         smp_wmb();
1792
1793         /* schedule sp_task to workqueue */
1794         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795 }
1796
1797 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1798 {
1799         struct bnx2x *bp = fp->bp;
1800         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1801         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1803         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1804
1805         DP(BNX2X_MSG_SP,
1806            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1807            fp->index, cid, command, bp->state,
1808            rr_cqe->ramrod_cqe.ramrod_type);
1809
1810         /* If cid is within VF range, replace the slowpath object with the
1811          * one corresponding to this VF
1812          */
1813         if (cid >= BNX2X_FIRST_VF_CID  &&
1814             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1815                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1816
1817         switch (command) {
1818         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1819                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1820                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1821                 break;
1822
1823         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1824                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1825                 drv_cmd = BNX2X_Q_CMD_SETUP;
1826                 break;
1827
1828         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1829                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1830                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1831                 break;
1832
1833         case (RAMROD_CMD_ID_ETH_HALT):
1834                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1835                 drv_cmd = BNX2X_Q_CMD_HALT;
1836                 break;
1837
1838         case (RAMROD_CMD_ID_ETH_TERMINATE):
1839                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1840                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1841                 break;
1842
1843         case (RAMROD_CMD_ID_ETH_EMPTY):
1844                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1845                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1846                 break;
1847
1848         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1849                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1850                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1851                 break;
1852
1853         default:
1854                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1855                           command, fp->index);
1856                 return;
1857         }
1858
1859         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1860             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1861                 /* q_obj->complete_cmd() failure means that this was
1862                  * an unexpected completion.
1863                  *
1864                  * In this case we don't want to increase the bp->spq_left
1865                  * because apparently we haven't sent this command the first
1866                  * place.
1867                  */
1868 #ifdef BNX2X_STOP_ON_ERROR
1869                 bnx2x_panic();
1870 #else
1871                 return;
1872 #endif
1873
1874         smp_mb__before_atomic();
1875         atomic_inc(&bp->cq_spq_left);
1876         /* push the change in bp->spq_left and towards the memory */
1877         smp_mb__after_atomic();
1878
1879         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1880
1881         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1882             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1883                 /* if Q update ramrod is completed for last Q in AFEX vif set
1884                  * flow, then ACK MCP at the end
1885                  *
1886                  * mark pending ACK to MCP bit.
1887                  * prevent case that both bits are cleared.
1888                  * At the end of load/unload driver checks that
1889                  * sp_state is cleared, and this order prevents
1890                  * races
1891                  */
1892                 smp_mb__before_atomic();
1893                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1894                 wmb();
1895                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1896                 smp_mb__after_atomic();
1897
1898                 /* schedule the sp task as mcp ack is required */
1899                 bnx2x_schedule_sp_task(bp);
1900         }
1901
1902         return;
1903 }
1904
1905 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1906 {
1907         struct bnx2x *bp = netdev_priv(dev_instance);
1908         u16 status = bnx2x_ack_int(bp);
1909         u16 mask;
1910         int i;
1911         u8 cos;
1912
1913         /* Return here if interrupt is shared and it's not for us */
1914         if (unlikely(status == 0)) {
1915                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1916                 return IRQ_NONE;
1917         }
1918         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1919
1920 #ifdef BNX2X_STOP_ON_ERROR
1921         if (unlikely(bp->panic))
1922                 return IRQ_HANDLED;
1923 #endif
1924
1925         for_each_eth_queue(bp, i) {
1926                 struct bnx2x_fastpath *fp = &bp->fp[i];
1927
1928                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1929                 if (status & mask) {
1930                         /* Handle Rx or Tx according to SB id */
1931                         for_each_cos_in_tx_queue(fp, cos)
1932                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1933                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1934                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1935                         status &= ~mask;
1936                 }
1937         }
1938
1939         if (CNIC_SUPPORT(bp)) {
1940                 mask = 0x2;
1941                 if (status & (mask | 0x1)) {
1942                         struct cnic_ops *c_ops = NULL;
1943
1944                         rcu_read_lock();
1945                         c_ops = rcu_dereference(bp->cnic_ops);
1946                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1947                                       CNIC_DRV_STATE_HANDLES_IRQ))
1948                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1949                         rcu_read_unlock();
1950
1951                         status &= ~mask;
1952                 }
1953         }
1954
1955         if (unlikely(status & 0x1)) {
1956
1957                 /* schedule sp task to perform default status block work, ack
1958                  * attentions and enable interrupts.
1959                  */
1960                 bnx2x_schedule_sp_task(bp);
1961
1962                 status &= ~0x1;
1963                 if (!status)
1964                         return IRQ_HANDLED;
1965         }
1966
1967         if (unlikely(status))
1968                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1969                    status);
1970
1971         return IRQ_HANDLED;
1972 }
1973
1974 /* Link */
1975
1976 /*
1977  * General service functions
1978  */
1979
1980 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1981 {
1982         u32 lock_status;
1983         u32 resource_bit = (1 << resource);
1984         int func = BP_FUNC(bp);
1985         u32 hw_lock_control_reg;
1986         int cnt;
1987
1988         /* Validating that the resource is within range */
1989         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1990                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1991                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1992                 return -EINVAL;
1993         }
1994
1995         if (func <= 5) {
1996                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1997         } else {
1998                 hw_lock_control_reg =
1999                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2000         }
2001
2002         /* Validating that the resource is not already taken */
2003         lock_status = REG_RD(bp, hw_lock_control_reg);
2004         if (lock_status & resource_bit) {
2005                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2006                    lock_status, resource_bit);
2007                 return -EEXIST;
2008         }
2009
2010         /* Try for 5 second every 5ms */
2011         for (cnt = 0; cnt < 1000; cnt++) {
2012                 /* Try to acquire the lock */
2013                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2014                 lock_status = REG_RD(bp, hw_lock_control_reg);
2015                 if (lock_status & resource_bit)
2016                         return 0;
2017
2018                 usleep_range(5000, 10000);
2019         }
2020         BNX2X_ERR("Timeout\n");
2021         return -EAGAIN;
2022 }
2023
2024 int bnx2x_release_leader_lock(struct bnx2x *bp)
2025 {
2026         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2027 }
2028
2029 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2030 {
2031         u32 lock_status;
2032         u32 resource_bit = (1 << resource);
2033         int func = BP_FUNC(bp);
2034         u32 hw_lock_control_reg;
2035
2036         /* Validating that the resource is within range */
2037         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2038                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2039                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2040                 return -EINVAL;
2041         }
2042
2043         if (func <= 5) {
2044                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2045         } else {
2046                 hw_lock_control_reg =
2047                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2048         }
2049
2050         /* Validating that the resource is currently taken */
2051         lock_status = REG_RD(bp, hw_lock_control_reg);
2052         if (!(lock_status & resource_bit)) {
2053                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2054                           lock_status, resource_bit);
2055                 return -EFAULT;
2056         }
2057
2058         REG_WR(bp, hw_lock_control_reg, resource_bit);
2059         return 0;
2060 }
2061
2062 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2063 {
2064         /* The GPIO should be swapped if swap register is set and active */
2065         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2066                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2067         int gpio_shift = gpio_num +
2068                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2069         u32 gpio_mask = (1 << gpio_shift);
2070         u32 gpio_reg;
2071         int value;
2072
2073         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2074                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2075                 return -EINVAL;
2076         }
2077
2078         /* read GPIO value */
2079         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2080
2081         /* get the requested pin value */
2082         if ((gpio_reg & gpio_mask) == gpio_mask)
2083                 value = 1;
2084         else
2085                 value = 0;
2086
2087         return value;
2088 }
2089
2090 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2091 {
2092         /* The GPIO should be swapped if swap register is set and active */
2093         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2094                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2095         int gpio_shift = gpio_num +
2096                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2097         u32 gpio_mask = (1 << gpio_shift);
2098         u32 gpio_reg;
2099
2100         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2101                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2102                 return -EINVAL;
2103         }
2104
2105         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2106         /* read GPIO and mask except the float bits */
2107         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2108
2109         switch (mode) {
2110         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2111                 DP(NETIF_MSG_LINK,
2112                    "Set GPIO %d (shift %d) -> output low\n",
2113                    gpio_num, gpio_shift);
2114                 /* clear FLOAT and set CLR */
2115                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2116                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2117                 break;
2118
2119         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2120                 DP(NETIF_MSG_LINK,
2121                    "Set GPIO %d (shift %d) -> output high\n",
2122                    gpio_num, gpio_shift);
2123                 /* clear FLOAT and set SET */
2124                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2125                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2126                 break;
2127
2128         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2129                 DP(NETIF_MSG_LINK,
2130                    "Set GPIO %d (shift %d) -> input\n",
2131                    gpio_num, gpio_shift);
2132                 /* set FLOAT */
2133                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2134                 break;
2135
2136         default:
2137                 break;
2138         }
2139
2140         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2141         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2142
2143         return 0;
2144 }
2145
2146 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2147 {
2148         u32 gpio_reg = 0;
2149         int rc = 0;
2150
2151         /* Any port swapping should be handled by caller. */
2152
2153         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2154         /* read GPIO and mask except the float bits */
2155         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2156         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2159
2160         switch (mode) {
2161         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2162                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2163                 /* set CLR */
2164                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2165                 break;
2166
2167         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2168                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2169                 /* set SET */
2170                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2171                 break;
2172
2173         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2174                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2175                 /* set FLOAT */
2176                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2177                 break;
2178
2179         default:
2180                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2181                 rc = -EINVAL;
2182                 break;
2183         }
2184
2185         if (rc == 0)
2186                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2187
2188         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2189
2190         return rc;
2191 }
2192
2193 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2194 {
2195         /* The GPIO should be swapped if swap register is set and active */
2196         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2197                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2198         int gpio_shift = gpio_num +
2199                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2200         u32 gpio_mask = (1 << gpio_shift);
2201         u32 gpio_reg;
2202
2203         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2204                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2205                 return -EINVAL;
2206         }
2207
2208         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2209         /* read GPIO int */
2210         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2211
2212         switch (mode) {
2213         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2214                 DP(NETIF_MSG_LINK,
2215                    "Clear GPIO INT %d (shift %d) -> output low\n",
2216                    gpio_num, gpio_shift);
2217                 /* clear SET and set CLR */
2218                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2220                 break;
2221
2222         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2223                 DP(NETIF_MSG_LINK,
2224                    "Set GPIO INT %d (shift %d) -> output high\n",
2225                    gpio_num, gpio_shift);
2226                 /* clear CLR and set SET */
2227                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229                 break;
2230
2231         default:
2232                 break;
2233         }
2234
2235         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2236         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2237
2238         return 0;
2239 }
2240
2241 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2242 {
2243         u32 spio_reg;
2244
2245         /* Only 2 SPIOs are configurable */
2246         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2247                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2248                 return -EINVAL;
2249         }
2250
2251         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2252         /* read SPIO and mask except the float bits */
2253         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2254
2255         switch (mode) {
2256         case MISC_SPIO_OUTPUT_LOW:
2257                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2258                 /* clear FLOAT and set CLR */
2259                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2260                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2261                 break;
2262
2263         case MISC_SPIO_OUTPUT_HIGH:
2264                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2265                 /* clear FLOAT and set SET */
2266                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2267                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2268                 break;
2269
2270         case MISC_SPIO_INPUT_HI_Z:
2271                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2272                 /* set FLOAT */
2273                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2274                 break;
2275
2276         default:
2277                 break;
2278         }
2279
2280         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2281         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2282
2283         return 0;
2284 }
2285
2286 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2287 {
2288         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2289         switch (bp->link_vars.ieee_fc &
2290                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2291         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2292                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2293                                                    ADVERTISED_Pause);
2294                 break;
2295
2296         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2297                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2298                                                   ADVERTISED_Pause);
2299                 break;
2300
2301         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2302                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2303                 break;
2304
2305         default:
2306                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2307                                                    ADVERTISED_Pause);
2308                 break;
2309         }
2310 }
2311
2312 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2313 {
2314         /* Initialize link parameters structure variables
2315          * It is recommended to turn off RX FC for jumbo frames
2316          *  for better performance
2317          */
2318         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2319                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2320         else
2321                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2322 }
2323
2324 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2325 {
2326         u32 pause_enabled = 0;
2327
2328         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2329                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2330                         pause_enabled = 1;
2331
2332                 REG_WR(bp, BAR_USTRORM_INTMEM +
2333                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2334                        pause_enabled);
2335         }
2336
2337         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2338            pause_enabled ? "enabled" : "disabled");
2339 }
2340
2341 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2342 {
2343         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2344         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2345
2346         if (!BP_NOMCP(bp)) {
2347                 bnx2x_set_requested_fc(bp);
2348                 bnx2x_acquire_phy_lock(bp);
2349
2350                 if (load_mode == LOAD_DIAG) {
2351                         struct link_params *lp = &bp->link_params;
2352                         lp->loopback_mode = LOOPBACK_XGXS;
2353                         /* do PHY loopback at 10G speed, if possible */
2354                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2355                                 if (lp->speed_cap_mask[cfx_idx] &
2356                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2357                                         lp->req_line_speed[cfx_idx] =
2358                                         SPEED_10000;
2359                                 else
2360                                         lp->req_line_speed[cfx_idx] =
2361                                         SPEED_1000;
2362                         }
2363                 }
2364
2365                 if (load_mode == LOAD_LOOPBACK_EXT) {
2366                         struct link_params *lp = &bp->link_params;
2367                         lp->loopback_mode = LOOPBACK_EXT;
2368                 }
2369
2370                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2371
2372                 bnx2x_release_phy_lock(bp);
2373
2374                 bnx2x_init_dropless_fc(bp);
2375
2376                 bnx2x_calc_fc_adv(bp);
2377
2378                 if (bp->link_vars.link_up) {
2379                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2380                         bnx2x_link_report(bp);
2381                 }
2382                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2383                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2384                 return rc;
2385         }
2386         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2387         return -EINVAL;
2388 }
2389
2390 void bnx2x_link_set(struct bnx2x *bp)
2391 {
2392         if (!BP_NOMCP(bp)) {
2393                 bnx2x_acquire_phy_lock(bp);
2394                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2395                 bnx2x_release_phy_lock(bp);
2396
2397                 bnx2x_init_dropless_fc(bp);
2398
2399                 bnx2x_calc_fc_adv(bp);
2400         } else
2401                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2402 }
2403
2404 static void bnx2x__link_reset(struct bnx2x *bp)
2405 {
2406         if (!BP_NOMCP(bp)) {
2407                 bnx2x_acquire_phy_lock(bp);
2408                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2409                 bnx2x_release_phy_lock(bp);
2410         } else
2411                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2412 }
2413
2414 void bnx2x_force_link_reset(struct bnx2x *bp)
2415 {
2416         bnx2x_acquire_phy_lock(bp);
2417         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2418         bnx2x_release_phy_lock(bp);
2419 }
2420
2421 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2422 {
2423         u8 rc = 0;
2424
2425         if (!BP_NOMCP(bp)) {
2426                 bnx2x_acquire_phy_lock(bp);
2427                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2428                                      is_serdes);
2429                 bnx2x_release_phy_lock(bp);
2430         } else
2431                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2432
2433         return rc;
2434 }
2435
2436 /* Calculates the sum of vn_min_rates.
2437    It's needed for further normalizing of the min_rates.
2438    Returns:
2439      sum of vn_min_rates.
2440        or
2441      0 - if all the min_rates are 0.
2442      In the later case fairness algorithm should be deactivated.
2443      If not all min_rates are zero then those that are zeroes will be set to 1.
2444  */
2445 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2446                                       struct cmng_init_input *input)
2447 {
2448         int all_zero = 1;
2449         int vn;
2450
2451         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452                 u32 vn_cfg = bp->mf_config[vn];
2453                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2454                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2455
2456                 /* Skip hidden vns */
2457                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2458                         vn_min_rate = 0;
2459                 /* If min rate is zero - set it to 1 */
2460                 else if (!vn_min_rate)
2461                         vn_min_rate = DEF_MIN_RATE;
2462                 else
2463                         all_zero = 0;
2464
2465                 input->vnic_min_rate[vn] = vn_min_rate;
2466         }
2467
2468         /* if ETS or all min rates are zeros - disable fairness */
2469         if (BNX2X_IS_ETS_ENABLED(bp)) {
2470                 input->flags.cmng_enables &=
2471                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2472                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2473         } else if (all_zero) {
2474                 input->flags.cmng_enables &=
2475                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476                 DP(NETIF_MSG_IFUP,
2477                    "All MIN values are zeroes fairness will be disabled\n");
2478         } else
2479                 input->flags.cmng_enables |=
2480                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2481 }
2482
2483 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2484                                     struct cmng_init_input *input)
2485 {
2486         u16 vn_max_rate;
2487         u32 vn_cfg = bp->mf_config[vn];
2488
2489         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2490                 vn_max_rate = 0;
2491         else {
2492                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2493
2494                 if (IS_MF_SI(bp)) {
2495                         /* maxCfg in percents of linkspeed */
2496                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2497                 } else /* SD modes */
2498                         /* maxCfg is absolute in 100Mb units */
2499                         vn_max_rate = maxCfg * 100;
2500         }
2501
2502         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2503
2504         input->vnic_max_rate[vn] = vn_max_rate;
2505 }
2506
2507 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2508 {
2509         if (CHIP_REV_IS_SLOW(bp))
2510                 return CMNG_FNS_NONE;
2511         if (IS_MF(bp))
2512                 return CMNG_FNS_MINMAX;
2513
2514         return CMNG_FNS_NONE;
2515 }
2516
2517 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2518 {
2519         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2520
2521         if (BP_NOMCP(bp))
2522                 return; /* what should be the default value in this case */
2523
2524         /* For 2 port configuration the absolute function number formula
2525          * is:
2526          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2527          *
2528          *      and there are 4 functions per port
2529          *
2530          * For 4 port configuration it is
2531          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2532          *
2533          *      and there are 2 functions per port
2534          */
2535         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2536                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2537
2538                 if (func >= E1H_FUNC_MAX)
2539                         break;
2540
2541                 bp->mf_config[vn] =
2542                         MF_CFG_RD(bp, func_mf_config[func].config);
2543         }
2544         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2545                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2546                 bp->flags |= MF_FUNC_DIS;
2547         } else {
2548                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2549                 bp->flags &= ~MF_FUNC_DIS;
2550         }
2551 }
2552
2553 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2554 {
2555         struct cmng_init_input input;
2556         memset(&input, 0, sizeof(struct cmng_init_input));
2557
2558         input.port_rate = bp->link_vars.line_speed;
2559
2560         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2561                 int vn;
2562
2563                 /* read mf conf from shmem */
2564                 if (read_cfg)
2565                         bnx2x_read_mf_cfg(bp);
2566
2567                 /* vn_weight_sum and enable fairness if not 0 */
2568                 bnx2x_calc_vn_min(bp, &input);
2569
2570                 /* calculate and set min-max rate for each vn */
2571                 if (bp->port.pmf)
2572                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2573                                 bnx2x_calc_vn_max(bp, vn, &input);
2574
2575                 /* always enable rate shaping and fairness */
2576                 input.flags.cmng_enables |=
2577                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2578
2579                 bnx2x_init_cmng(&input, &bp->cmng);
2580                 return;
2581         }
2582
2583         /* rate shaping and fairness are disabled */
2584         DP(NETIF_MSG_IFUP,
2585            "rate shaping and fairness are disabled\n");
2586 }
2587
2588 static void storm_memset_cmng(struct bnx2x *bp,
2589                               struct cmng_init *cmng,
2590                               u8 port)
2591 {
2592         int vn;
2593         size_t size = sizeof(struct cmng_struct_per_port);
2594
2595         u32 addr = BAR_XSTRORM_INTMEM +
2596                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2597
2598         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2599
2600         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2601                 int func = func_by_vn(bp, vn);
2602
2603                 addr = BAR_XSTRORM_INTMEM +
2604                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2605                 size = sizeof(struct rate_shaping_vars_per_vn);
2606                 __storm_memset_struct(bp, addr, size,
2607                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2608
2609                 addr = BAR_XSTRORM_INTMEM +
2610                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2611                 size = sizeof(struct fairness_vars_per_vn);
2612                 __storm_memset_struct(bp, addr, size,
2613                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2614         }
2615 }
2616
2617 /* init cmng mode in HW according to local configuration */
2618 void bnx2x_set_local_cmng(struct bnx2x *bp)
2619 {
2620         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2621
2622         if (cmng_fns != CMNG_FNS_NONE) {
2623                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2624                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2625         } else {
2626                 /* rate shaping and fairness are disabled */
2627                 DP(NETIF_MSG_IFUP,
2628                    "single function mode without fairness\n");
2629         }
2630 }
2631
2632 /* This function is called upon link interrupt */
2633 static void bnx2x_link_attn(struct bnx2x *bp)
2634 {
2635         /* Make sure that we are synced with the current statistics */
2636         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2637
2638         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2639
2640         bnx2x_init_dropless_fc(bp);
2641
2642         if (bp->link_vars.link_up) {
2643
2644                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2645                         struct host_port_stats *pstats;
2646
2647                         pstats = bnx2x_sp(bp, port_stats);
2648                         /* reset old mac stats */
2649                         memset(&(pstats->mac_stx[0]), 0,
2650                                sizeof(struct mac_stx));
2651                 }
2652                 if (bp->state == BNX2X_STATE_OPEN)
2653                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2654         }
2655
2656         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2657                 bnx2x_set_local_cmng(bp);
2658
2659         __bnx2x_link_report(bp);
2660
2661         if (IS_MF(bp))
2662                 bnx2x_link_sync_notify(bp);
2663 }
2664
2665 void bnx2x__link_status_update(struct bnx2x *bp)
2666 {
2667         if (bp->state != BNX2X_STATE_OPEN)
2668                 return;
2669
2670         /* read updated dcb configuration */
2671         if (IS_PF(bp)) {
2672                 bnx2x_dcbx_pmf_update(bp);
2673                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2674                 if (bp->link_vars.link_up)
2675                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2676                 else
2677                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2678                         /* indicate link status */
2679                 bnx2x_link_report(bp);
2680
2681         } else { /* VF */
2682                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2683                                           SUPPORTED_10baseT_Full |
2684                                           SUPPORTED_100baseT_Half |
2685                                           SUPPORTED_100baseT_Full |
2686                                           SUPPORTED_1000baseT_Full |
2687                                           SUPPORTED_2500baseX_Full |
2688                                           SUPPORTED_10000baseT_Full |
2689                                           SUPPORTED_TP |
2690                                           SUPPORTED_FIBRE |
2691                                           SUPPORTED_Autoneg |
2692                                           SUPPORTED_Pause |
2693                                           SUPPORTED_Asym_Pause);
2694                 bp->port.advertising[0] = bp->port.supported[0];
2695
2696                 bp->link_params.bp = bp;
2697                 bp->link_params.port = BP_PORT(bp);
2698                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2699                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2700                 bp->link_params.req_line_speed[0] = SPEED_10000;
2701                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2702                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2703                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2704                 bp->link_vars.line_speed = SPEED_10000;
2705                 bp->link_vars.link_status =
2706                         (LINK_STATUS_LINK_UP |
2707                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2708                 bp->link_vars.link_up = 1;
2709                 bp->link_vars.duplex = DUPLEX_FULL;
2710                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2711                 __bnx2x_link_report(bp);
2712
2713                 bnx2x_sample_bulletin(bp);
2714
2715                 /* if bulletin board did not have an update for link status
2716                  * __bnx2x_link_report will report current status
2717                  * but it will NOT duplicate report in case of already reported
2718                  * during sampling bulletin board.
2719                  */
2720                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2721         }
2722 }
2723
2724 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2725                                   u16 vlan_val, u8 allowed_prio)
2726 {
2727         struct bnx2x_func_state_params func_params = {NULL};
2728         struct bnx2x_func_afex_update_params *f_update_params =
2729                 &func_params.params.afex_update;
2730
2731         func_params.f_obj = &bp->func_obj;
2732         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2733
2734         /* no need to wait for RAMROD completion, so don't
2735          * set RAMROD_COMP_WAIT flag
2736          */
2737
2738         f_update_params->vif_id = vifid;
2739         f_update_params->afex_default_vlan = vlan_val;
2740         f_update_params->allowed_priorities = allowed_prio;
2741
2742         /* if ramrod can not be sent, response to MCP immediately */
2743         if (bnx2x_func_state_change(bp, &func_params) < 0)
2744                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2745
2746         return 0;
2747 }
2748
2749 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2750                                           u16 vif_index, u8 func_bit_map)
2751 {
2752         struct bnx2x_func_state_params func_params = {NULL};
2753         struct bnx2x_func_afex_viflists_params *update_params =
2754                 &func_params.params.afex_viflists;
2755         int rc;
2756         u32 drv_msg_code;
2757
2758         /* validate only LIST_SET and LIST_GET are received from switch */
2759         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2760                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2761                           cmd_type);
2762
2763         func_params.f_obj = &bp->func_obj;
2764         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2765
2766         /* set parameters according to cmd_type */
2767         update_params->afex_vif_list_command = cmd_type;
2768         update_params->vif_list_index = vif_index;
2769         update_params->func_bit_map =
2770                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2771         update_params->func_to_clear = 0;
2772         drv_msg_code =
2773                 (cmd_type == VIF_LIST_RULE_GET) ?
2774                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2775                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2776
2777         /* if ramrod can not be sent, respond to MCP immediately for
2778          * SET and GET requests (other are not triggered from MCP)
2779          */
2780         rc = bnx2x_func_state_change(bp, &func_params);
2781         if (rc < 0)
2782                 bnx2x_fw_command(bp, drv_msg_code, 0);
2783
2784         return 0;
2785 }
2786
2787 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2788 {
2789         struct afex_stats afex_stats;
2790         u32 func = BP_ABS_FUNC(bp);
2791         u32 mf_config;
2792         u16 vlan_val;
2793         u32 vlan_prio;
2794         u16 vif_id;
2795         u8 allowed_prio;
2796         u8 vlan_mode;
2797         u32 addr_to_write, vifid, addrs, stats_type, i;
2798
2799         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2800                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2801                 DP(BNX2X_MSG_MCP,
2802                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2803                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2804         }
2805
2806         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2807                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2808                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2809                 DP(BNX2X_MSG_MCP,
2810                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2811                    vifid, addrs);
2812                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2813                                                addrs);
2814         }
2815
2816         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2817                 addr_to_write = SHMEM2_RD(bp,
2818                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2819                 stats_type = SHMEM2_RD(bp,
2820                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2821
2822                 DP(BNX2X_MSG_MCP,
2823                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2824                    addr_to_write);
2825
2826                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2827
2828                 /* write response to scratchpad, for MCP */
2829                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2830                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2831                                *(((u32 *)(&afex_stats))+i));
2832
2833                 /* send ack message to MCP */
2834                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2835         }
2836
2837         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2838                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2839                 bp->mf_config[BP_VN(bp)] = mf_config;
2840                 DP(BNX2X_MSG_MCP,
2841                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2842                    mf_config);
2843
2844                 /* if VIF_SET is "enabled" */
2845                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2846                         /* set rate limit directly to internal RAM */
2847                         struct cmng_init_input cmng_input;
2848                         struct rate_shaping_vars_per_vn m_rs_vn;
2849                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2850                         u32 addr = BAR_XSTRORM_INTMEM +
2851                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2852
2853                         bp->mf_config[BP_VN(bp)] = mf_config;
2854
2855                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2856                         m_rs_vn.vn_counter.rate =
2857                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2858                         m_rs_vn.vn_counter.quota =
2859                                 (m_rs_vn.vn_counter.rate *
2860                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2861
2862                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2863
2864                         /* read relevant values from mf_cfg struct in shmem */
2865                         vif_id =
2866                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2867                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2868                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2869                         vlan_val =
2870                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2872                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2873                         vlan_prio = (mf_config &
2874                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2875                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2876                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2877                         vlan_mode =
2878                                 (MF_CFG_RD(bp,
2879                                            func_mf_config[func].afex_config) &
2880                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2881                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2882                         allowed_prio =
2883                                 (MF_CFG_RD(bp,
2884                                            func_mf_config[func].afex_config) &
2885                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2886                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2887
2888                         /* send ramrod to FW, return in case of failure */
2889                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2890                                                    allowed_prio))
2891                                 return;
2892
2893                         bp->afex_def_vlan_tag = vlan_val;
2894                         bp->afex_vlan_mode = vlan_mode;
2895                 } else {
2896                         /* notify link down because BP->flags is disabled */
2897                         bnx2x_link_report(bp);
2898
2899                         /* send INVALID VIF ramrod to FW */
2900                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2901
2902                         /* Reset the default afex VLAN */
2903                         bp->afex_def_vlan_tag = -1;
2904                 }
2905         }
2906 }
2907
2908 static void bnx2x_pmf_update(struct bnx2x *bp)
2909 {
2910         int port = BP_PORT(bp);
2911         u32 val;
2912
2913         bp->port.pmf = 1;
2914         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2915
2916         /*
2917          * We need the mb() to ensure the ordering between the writing to
2918          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2919          */
2920         smp_mb();
2921
2922         /* queue a periodic task */
2923         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2924
2925         bnx2x_dcbx_pmf_update(bp);
2926
2927         /* enable nig attention */
2928         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2929         if (bp->common.int_block == INT_BLOCK_HC) {
2930                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2931                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2932         } else if (!CHIP_IS_E1x(bp)) {
2933                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2934                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2935         }
2936
2937         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2938 }
2939
2940 /* end of Link */
2941
2942 /* slow path */
2943
2944 /*
2945  * General service functions
2946  */
2947
2948 /* send the MCP a request, block until there is a reply */
2949 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2950 {
2951         int mb_idx = BP_FW_MB_IDX(bp);
2952         u32 seq;
2953         u32 rc = 0;
2954         u32 cnt = 1;
2955         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2956
2957         mutex_lock(&bp->fw_mb_mutex);
2958         seq = ++bp->fw_seq;
2959         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2960         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2961
2962         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2963                         (command | seq), param);
2964
2965         do {
2966                 /* let the FW do it's magic ... */
2967                 msleep(delay);
2968
2969                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2970
2971                 /* Give the FW up to 5 second (500*10ms) */
2972         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2973
2974         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2975            cnt*delay, rc, seq);
2976
2977         /* is this a reply to our command? */
2978         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2979                 rc &= FW_MSG_CODE_MASK;
2980         else {
2981                 /* FW BUG! */
2982                 BNX2X_ERR("FW failed to respond!\n");
2983                 bnx2x_fw_dump(bp);
2984                 rc = 0;
2985         }
2986         mutex_unlock(&bp->fw_mb_mutex);
2987
2988         return rc;
2989 }
2990
2991 static void storm_memset_func_cfg(struct bnx2x *bp,
2992                                  struct tstorm_eth_function_common_config *tcfg,
2993                                  u16 abs_fid)
2994 {
2995         size_t size = sizeof(struct tstorm_eth_function_common_config);
2996
2997         u32 addr = BAR_TSTRORM_INTMEM +
2998                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2999
3000         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3001 }
3002
3003 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3004 {
3005         if (CHIP_IS_E1x(bp)) {
3006                 struct tstorm_eth_function_common_config tcfg = {0};
3007
3008                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3009         }
3010
3011         /* Enable the function in the FW */
3012         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3013         storm_memset_func_en(bp, p->func_id, 1);
3014
3015         /* spq */
3016         if (p->func_flgs & FUNC_FLG_SPQ) {
3017                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3018                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3019                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3020         }
3021 }
3022
3023 /**
3024  * bnx2x_get_common_flags - Return common flags
3025  *
3026  * @bp          device handle
3027  * @fp          queue handle
3028  * @zero_stats  TRUE if statistics zeroing is needed
3029  *
3030  * Return the flags that are common for the Tx-only and not normal connections.
3031  */
3032 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3033                                             struct bnx2x_fastpath *fp,
3034                                             bool zero_stats)
3035 {
3036         unsigned long flags = 0;
3037
3038         /* PF driver will always initialize the Queue to an ACTIVE state */
3039         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3040
3041         /* tx only connections collect statistics (on the same index as the
3042          * parent connection). The statistics are zeroed when the parent
3043          * connection is initialized.
3044          */
3045
3046         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3047         if (zero_stats)
3048                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3049
3050         if (bp->flags & TX_SWITCHING)
3051                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3052
3053         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3054         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3055
3056 #ifdef BNX2X_STOP_ON_ERROR
3057         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3058 #endif
3059
3060         return flags;
3061 }
3062
3063 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3064                                        struct bnx2x_fastpath *fp,
3065                                        bool leading)
3066 {
3067         unsigned long flags = 0;
3068
3069         /* calculate other queue flags */
3070         if (IS_MF_SD(bp))
3071                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3072
3073         if (IS_FCOE_FP(fp)) {
3074                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3075                 /* For FCoE - force usage of default priority (for afex) */
3076                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3077         }
3078
3079         if (!fp->disable_tpa) {
3080                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3081                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3082                 if (fp->mode == TPA_MODE_GRO)
3083                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3084         }
3085
3086         if (leading) {
3087                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3088                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3089         }
3090
3091         /* Always set HW VLAN stripping */
3092         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3093
3094         /* configure silent vlan removal */
3095         if (IS_MF_AFEX(bp))
3096                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3097
3098         return flags | bnx2x_get_common_flags(bp, fp, true);
3099 }
3100
3101 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3102         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3103         u8 cos)
3104 {
3105         gen_init->stat_id = bnx2x_stats_id(fp);
3106         gen_init->spcl_id = fp->cl_id;
3107
3108         /* Always use mini-jumbo MTU for FCoE L2 ring */
3109         if (IS_FCOE_FP(fp))
3110                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3111         else
3112                 gen_init->mtu = bp->dev->mtu;
3113
3114         gen_init->cos = cos;
3115 }
3116
3117 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3118         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3119         struct bnx2x_rxq_setup_params *rxq_init)
3120 {
3121         u8 max_sge = 0;
3122         u16 sge_sz = 0;
3123         u16 tpa_agg_size = 0;
3124
3125         if (!fp->disable_tpa) {
3126                 pause->sge_th_lo = SGE_TH_LO(bp);
3127                 pause->sge_th_hi = SGE_TH_HI(bp);
3128
3129                 /* validate SGE ring has enough to cross high threshold */
3130                 WARN_ON(bp->dropless_fc &&
3131                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3132                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3133
3134                 tpa_agg_size = TPA_AGG_SIZE;
3135                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3136                         SGE_PAGE_SHIFT;
3137                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3138                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3139                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3140         }
3141
3142         /* pause - not for e1 */
3143         if (!CHIP_IS_E1(bp)) {
3144                 pause->bd_th_lo = BD_TH_LO(bp);
3145                 pause->bd_th_hi = BD_TH_HI(bp);
3146
3147                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3148                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3149                 /*
3150                  * validate that rings have enough entries to cross
3151                  * high thresholds
3152                  */
3153                 WARN_ON(bp->dropless_fc &&
3154                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3155                                 bp->rx_ring_size);
3156                 WARN_ON(bp->dropless_fc &&
3157                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3158                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3159
3160                 pause->pri_map = 1;
3161         }
3162
3163         /* rxq setup */
3164         rxq_init->dscr_map = fp->rx_desc_mapping;
3165         rxq_init->sge_map = fp->rx_sge_mapping;
3166         rxq_init->rcq_map = fp->rx_comp_mapping;
3167         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3168
3169         /* This should be a maximum number of data bytes that may be
3170          * placed on the BD (not including paddings).
3171          */
3172         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3173                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3174
3175         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3176         rxq_init->tpa_agg_sz = tpa_agg_size;
3177         rxq_init->sge_buf_sz = sge_sz;
3178         rxq_init->max_sges_pkt = max_sge;
3179         rxq_init->rss_engine_id = BP_FUNC(bp);
3180         rxq_init->mcast_engine_id = BP_FUNC(bp);
3181
3182         /* Maximum number or simultaneous TPA aggregation for this Queue.
3183          *
3184          * For PF Clients it should be the maximum available number.
3185          * VF driver(s) may want to define it to a smaller value.
3186          */
3187         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3188
3189         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3190         rxq_init->fw_sb_id = fp->fw_sb_id;
3191
3192         if (IS_FCOE_FP(fp))
3193                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3194         else
3195                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3196         /* configure silent vlan removal
3197          * if multi function mode is afex, then mask default vlan
3198          */
3199         if (IS_MF_AFEX(bp)) {
3200                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3201                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3202         }
3203 }
3204
3205 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3206         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3207         u8 cos)
3208 {
3209         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3210         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3211         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3212         txq_init->fw_sb_id = fp->fw_sb_id;
3213
3214         /*
3215          * set the tss leading client id for TX classification ==
3216          * leading RSS client id
3217          */
3218         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3219
3220         if (IS_FCOE_FP(fp)) {
3221                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3222                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3223         }
3224 }
3225
3226 static void bnx2x_pf_init(struct bnx2x *bp)
3227 {
3228         struct bnx2x_func_init_params func_init = {0};
3229         struct event_ring_data eq_data = { {0} };
3230         u16 flags;
3231
3232         if (!CHIP_IS_E1x(bp)) {
3233                 /* reset IGU PF statistics: MSIX + ATTN */
3234                 /* PF */
3235                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3236                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3237                            (CHIP_MODE_IS_4_PORT(bp) ?
3238                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3239                 /* ATTN */
3240                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3241                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3242                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3243                            (CHIP_MODE_IS_4_PORT(bp) ?
3244                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3245         }
3246
3247         /* function setup flags */
3248         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3249
3250         /* This flag is relevant for E1x only.
3251          * E2 doesn't have a TPA configuration in a function level.
3252          */
3253         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3254
3255         func_init.func_flgs = flags;
3256         func_init.pf_id = BP_FUNC(bp);
3257         func_init.func_id = BP_FUNC(bp);
3258         func_init.spq_map = bp->spq_mapping;
3259         func_init.spq_prod = bp->spq_prod_idx;
3260
3261         bnx2x_func_init(bp, &func_init);
3262
3263         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3264
3265         /*
3266          * Congestion management values depend on the link rate
3267          * There is no active link so initial link rate is set to 10 Gbps.
3268          * When the link comes up The congestion management values are
3269          * re-calculated according to the actual link rate.
3270          */
3271         bp->link_vars.line_speed = SPEED_10000;
3272         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3273
3274         /* Only the PMF sets the HW */
3275         if (bp->port.pmf)
3276                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3277
3278         /* init Event Queue - PCI bus guarantees correct endianity*/
3279         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3280         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3281         eq_data.producer = bp->eq_prod;
3282         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3283         eq_data.sb_id = DEF_SB_ID;
3284         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3285 }
3286
3287 static void bnx2x_e1h_disable(struct bnx2x *bp)
3288 {
3289         int port = BP_PORT(bp);
3290
3291         bnx2x_tx_disable(bp);
3292
3293         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3294 }
3295
3296 static void bnx2x_e1h_enable(struct bnx2x *bp)
3297 {
3298         int port = BP_PORT(bp);
3299
3300         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3301
3302         /* Tx queue should be only re-enabled */
3303         netif_tx_wake_all_queues(bp->dev);
3304
3305         /*
3306          * Should not call netif_carrier_on since it will be called if the link
3307          * is up when checking for link state
3308          */
3309 }
3310
3311 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3312
3313 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3314 {
3315         struct eth_stats_info *ether_stat =
3316                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3317         struct bnx2x_vlan_mac_obj *mac_obj =
3318                 &bp->sp_objs->mac_obj;
3319         int i;
3320
3321         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3322                 ETH_STAT_INFO_VERSION_LEN);
3323
3324         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3325          * mac_local field in ether_stat struct. The base address is offset by 2
3326          * bytes to account for the field being 8 bytes but a mac address is
3327          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3328          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3329          * allocated by the ether_stat struct, so the macs will land in their
3330          * proper positions.
3331          */
3332         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3333                 memset(ether_stat->mac_local + i, 0,
3334                        sizeof(ether_stat->mac_local[0]));
3335         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3336                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3337                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3338                                 ETH_ALEN);
3339         ether_stat->mtu_size = bp->dev->mtu;
3340         if (bp->dev->features & NETIF_F_RXCSUM)
3341                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3342         if (bp->dev->features & NETIF_F_TSO)
3343                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3344         ether_stat->feature_flags |= bp->common.boot_mode;
3345
3346         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3347
3348         ether_stat->txq_size = bp->tx_ring_size;
3349         ether_stat->rxq_size = bp->rx_ring_size;
3350
3351 #ifdef CONFIG_BNX2X_SRIOV
3352         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3353 #endif
3354 }
3355
3356 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3357 {
3358         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3359         struct fcoe_stats_info *fcoe_stat =
3360                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3361
3362         if (!CNIC_LOADED(bp))
3363                 return;
3364
3365         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3366
3367         fcoe_stat->qos_priority =
3368                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3369
3370         /* insert FCoE stats from ramrod response */
3371         if (!NO_FCOE(bp)) {
3372                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3373                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3374                         tstorm_queue_statistics;
3375
3376                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3377                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3378                         xstorm_queue_statistics;
3379
3380                 struct fcoe_statistics_params *fw_fcoe_stat =
3381                         &bp->fw_stats_data->fcoe;
3382
3383                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3384                           fcoe_stat->rx_bytes_lo,
3385                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3386
3387                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3388                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3389                           fcoe_stat->rx_bytes_lo,
3390                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3391
3392                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3393                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3394                           fcoe_stat->rx_bytes_lo,
3395                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3396
3397                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3398                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3399                           fcoe_stat->rx_bytes_lo,
3400                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3401
3402                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3403                           fcoe_stat->rx_frames_lo,
3404                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3405
3406                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3407                           fcoe_stat->rx_frames_lo,
3408                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3409
3410                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3411                           fcoe_stat->rx_frames_lo,
3412                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3413
3414                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3415                           fcoe_stat->rx_frames_lo,
3416                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3417
3418                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3419                           fcoe_stat->tx_bytes_lo,
3420                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3421
3422                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3423                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3424                           fcoe_stat->tx_bytes_lo,
3425                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3426
3427                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3428                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3429                           fcoe_stat->tx_bytes_lo,
3430                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3431
3432                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3433                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3434                           fcoe_stat->tx_bytes_lo,
3435                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3436
3437                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3438                           fcoe_stat->tx_frames_lo,
3439                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3440
3441                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3442                           fcoe_stat->tx_frames_lo,
3443                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3444
3445                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3446                           fcoe_stat->tx_frames_lo,
3447                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3448
3449                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3450                           fcoe_stat->tx_frames_lo,
3451                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3452         }
3453
3454         /* ask L5 driver to add data to the struct */
3455         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3456 }
3457
3458 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3459 {
3460         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3461         struct iscsi_stats_info *iscsi_stat =
3462                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3463
3464         if (!CNIC_LOADED(bp))
3465                 return;
3466
3467         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3468                ETH_ALEN);
3469
3470         iscsi_stat->qos_priority =
3471                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3472
3473         /* ask L5 driver to add data to the struct */
3474         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3475 }
3476
3477 /* called due to MCP event (on pmf):
3478  *      reread new bandwidth configuration
3479  *      configure FW
3480  *      notify others function about the change
3481  */
3482 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3483 {
3484         if (bp->link_vars.link_up) {
3485                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3486                 bnx2x_link_sync_notify(bp);
3487         }
3488         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3489 }
3490
3491 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3492 {
3493         bnx2x_config_mf_bw(bp);
3494         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3495 }
3496
3497 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3498 {
3499         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3500         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3501 }
3502
3503 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3504 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3505
3506 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3507 {
3508         enum drv_info_opcode op_code;
3509         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3510         bool release = false;
3511         int wait;
3512
3513         /* if drv_info version supported by MFW doesn't match - send NACK */
3514         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3515                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3516                 return;
3517         }
3518
3519         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3520                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3521
3522         /* Must prevent other flows from accessing drv_info_to_mcp */
3523         mutex_lock(&bp->drv_info_mutex);
3524
3525         memset(&bp->slowpath->drv_info_to_mcp, 0,
3526                sizeof(union drv_info_to_mcp));
3527
3528         switch (op_code) {
3529         case ETH_STATS_OPCODE:
3530                 bnx2x_drv_info_ether_stat(bp);
3531                 break;
3532         case FCOE_STATS_OPCODE:
3533                 bnx2x_drv_info_fcoe_stat(bp);
3534                 break;
3535         case ISCSI_STATS_OPCODE:
3536                 bnx2x_drv_info_iscsi_stat(bp);
3537                 break;
3538         default:
3539                 /* if op code isn't supported - send NACK */
3540                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3541                 goto out;
3542         }
3543
3544         /* if we got drv_info attn from MFW then these fields are defined in
3545          * shmem2 for sure
3546          */
3547         SHMEM2_WR(bp, drv_info_host_addr_lo,
3548                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3549         SHMEM2_WR(bp, drv_info_host_addr_hi,
3550                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3551
3552         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3553
3554         /* Since possible management wants both this and get_driver_version
3555          * need to wait until management notifies us it finished utilizing
3556          * the buffer.
3557          */
3558         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3559                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3560         } else if (!bp->drv_info_mng_owner) {
3561                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3562
3563                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3564                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3565
3566                         /* Management is done; need to clear indication */
3567                         if (indication & bit) {
3568                                 SHMEM2_WR(bp, mfw_drv_indication,
3569                                           indication & ~bit);
3570                                 release = true;
3571                                 break;
3572                         }
3573
3574                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3575                 }
3576         }
3577         if (!release) {
3578                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3579                 bp->drv_info_mng_owner = true;
3580         }
3581
3582 out:
3583         mutex_unlock(&bp->drv_info_mutex);
3584 }
3585
3586 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3587 {
3588         u8 vals[4];
3589         int i = 0;
3590
3591         if (bnx2x_format) {
3592                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3593                            &vals[0], &vals[1], &vals[2], &vals[3]);
3594                 if (i > 0)
3595                         vals[0] -= '0';
3596         } else {
3597                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3598                            &vals[0], &vals[1], &vals[2], &vals[3]);
3599         }
3600
3601         while (i < 4)
3602                 vals[i++] = 0;
3603
3604         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3605 }
3606
3607 void bnx2x_update_mng_version(struct bnx2x *bp)
3608 {
3609         u32 iscsiver = DRV_VER_NOT_LOADED;
3610         u32 fcoever = DRV_VER_NOT_LOADED;
3611         u32 ethver = DRV_VER_NOT_LOADED;
3612         int idx = BP_FW_MB_IDX(bp);
3613         u8 *version;
3614
3615         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3616                 return;
3617
3618         mutex_lock(&bp->drv_info_mutex);
3619         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3620         if (bp->drv_info_mng_owner)
3621                 goto out;
3622
3623         if (bp->state != BNX2X_STATE_OPEN)
3624                 goto out;
3625
3626         /* Parse ethernet driver version */
3627         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3628         if (!CNIC_LOADED(bp))
3629                 goto out;
3630
3631         /* Try getting storage driver version via cnic */
3632         memset(&bp->slowpath->drv_info_to_mcp, 0,
3633                sizeof(union drv_info_to_mcp));
3634         bnx2x_drv_info_iscsi_stat(bp);
3635         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3636         iscsiver = bnx2x_update_mng_version_utility(version, false);
3637
3638         memset(&bp->slowpath->drv_info_to_mcp, 0,
3639                sizeof(union drv_info_to_mcp));
3640         bnx2x_drv_info_fcoe_stat(bp);
3641         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3642         fcoever = bnx2x_update_mng_version_utility(version, false);
3643
3644 out:
3645         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3646         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3647         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3648
3649         mutex_unlock(&bp->drv_info_mutex);
3650
3651         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3652            ethver, iscsiver, fcoever);
3653 }
3654
3655 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3656 {
3657         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3658
3659         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3660
3661                 /*
3662                  * This is the only place besides the function initialization
3663                  * where the bp->flags can change so it is done without any
3664                  * locks
3665                  */
3666                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3667                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3668                         bp->flags |= MF_FUNC_DIS;
3669
3670                         bnx2x_e1h_disable(bp);
3671                 } else {
3672                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3673                         bp->flags &= ~MF_FUNC_DIS;
3674
3675                         bnx2x_e1h_enable(bp);
3676                 }
3677                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3678         }
3679         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3680                 bnx2x_config_mf_bw(bp);
3681                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3682         }
3683
3684         /* Report results to MCP */
3685         if (dcc_event)
3686                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3687         else
3688                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3689 }
3690
3691 /* must be called under the spq lock */
3692 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3693 {
3694         struct eth_spe *next_spe = bp->spq_prod_bd;
3695
3696         if (bp->spq_prod_bd == bp->spq_last_bd) {
3697                 bp->spq_prod_bd = bp->spq;
3698                 bp->spq_prod_idx = 0;
3699                 DP(BNX2X_MSG_SP, "end of spq\n");
3700         } else {
3701                 bp->spq_prod_bd++;
3702                 bp->spq_prod_idx++;
3703         }
3704         return next_spe;
3705 }
3706
3707 /* must be called under the spq lock */
3708 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3709 {
3710         int func = BP_FUNC(bp);
3711
3712         /*
3713          * Make sure that BD data is updated before writing the producer:
3714          * BD data is written to the memory, the producer is read from the
3715          * memory, thus we need a full memory barrier to ensure the ordering.
3716          */
3717         mb();
3718
3719         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3720                  bp->spq_prod_idx);
3721         mmiowb();
3722 }
3723
3724 /**
3725  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3726  *
3727  * @cmd:        command to check
3728  * @cmd_type:   command type
3729  */
3730 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3731 {
3732         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3733             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3734             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3735             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3736             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3737             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3738             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3739                 return true;
3740         else
3741                 return false;
3742 }
3743
3744 /**
3745  * bnx2x_sp_post - place a single command on an SP ring
3746  *
3747  * @bp:         driver handle
3748  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3749  * @cid:        SW CID the command is related to
3750  * @data_hi:    command private data address (high 32 bits)
3751  * @data_lo:    command private data address (low 32 bits)
3752  * @cmd_type:   command type (e.g. NONE, ETH)
3753  *
3754  * SP data is handled as if it's always an address pair, thus data fields are
3755  * not swapped to little endian in upper functions. Instead this function swaps
3756  * data as if it's two u32 fields.
3757  */
3758 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3759                   u32 data_hi, u32 data_lo, int cmd_type)
3760 {
3761         struct eth_spe *spe;
3762         u16 type;
3763         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3764
3765 #ifdef BNX2X_STOP_ON_ERROR
3766         if (unlikely(bp->panic)) {
3767                 BNX2X_ERR("Can't post SP when there is panic\n");
3768                 return -EIO;
3769         }
3770 #endif
3771
3772         spin_lock_bh(&bp->spq_lock);
3773
3774         if (common) {
3775                 if (!atomic_read(&bp->eq_spq_left)) {
3776                         BNX2X_ERR("BUG! EQ ring full!\n");
3777                         spin_unlock_bh(&bp->spq_lock);
3778                         bnx2x_panic();
3779                         return -EBUSY;
3780                 }
3781         } else if (!atomic_read(&bp->cq_spq_left)) {
3782                         BNX2X_ERR("BUG! SPQ ring full!\n");
3783                         spin_unlock_bh(&bp->spq_lock);
3784                         bnx2x_panic();
3785                         return -EBUSY;
3786         }
3787
3788         spe = bnx2x_sp_get_next(bp);
3789
3790         /* CID needs port number to be encoded int it */
3791         spe->hdr.conn_and_cmd_data =
3792                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3793                                     HW_CID(bp, cid));
3794
3795         /* In some cases, type may already contain the func-id
3796          * mainly in SRIOV related use cases, so we add it here only
3797          * if it's not already set.
3798          */
3799         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3800                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3801                         SPE_HDR_CONN_TYPE;
3802                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3803                          SPE_HDR_FUNCTION_ID);
3804         } else {
3805                 type = cmd_type;
3806         }
3807
3808         spe->hdr.type = cpu_to_le16(type);
3809
3810         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3811         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3812
3813         /*
3814          * It's ok if the actual decrement is issued towards the memory
3815          * somewhere between the spin_lock and spin_unlock. Thus no
3816          * more explicit memory barrier is needed.
3817          */
3818         if (common)
3819                 atomic_dec(&bp->eq_spq_left);
3820         else
3821                 atomic_dec(&bp->cq_spq_left);
3822
3823         DP(BNX2X_MSG_SP,
3824            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3825            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3826            (u32)(U64_LO(bp->spq_mapping) +
3827            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3828            HW_CID(bp, cid), data_hi, data_lo, type,
3829            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3830
3831         bnx2x_sp_prod_update(bp);
3832         spin_unlock_bh(&bp->spq_lock);
3833         return 0;
3834 }
3835
3836 /* acquire split MCP access lock register */
3837 static int bnx2x_acquire_alr(struct bnx2x *bp)
3838 {
3839         u32 j, val;
3840         int rc = 0;
3841
3842         might_sleep();
3843         for (j = 0; j < 1000; j++) {
3844                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3845                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3846                 if (val & MCPR_ACCESS_LOCK_LOCK)
3847                         break;
3848
3849                 usleep_range(5000, 10000);
3850         }
3851         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3852                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3853                 rc = -EBUSY;
3854         }
3855
3856         return rc;
3857 }
3858
3859 /* release split MCP access lock register */
3860 static void bnx2x_release_alr(struct bnx2x *bp)
3861 {
3862         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3863 }
3864
3865 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3866 #define BNX2X_DEF_SB_IDX        0x0002
3867
3868 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3869 {
3870         struct host_sp_status_block *def_sb = bp->def_status_blk;
3871         u16 rc = 0;
3872
3873         barrier(); /* status block is written to by the chip */
3874         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3875                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3876                 rc |= BNX2X_DEF_SB_ATT_IDX;
3877         }
3878
3879         if (bp->def_idx != def_sb->sp_sb.running_index) {
3880                 bp->def_idx = def_sb->sp_sb.running_index;
3881                 rc |= BNX2X_DEF_SB_IDX;
3882         }
3883
3884         /* Do not reorder: indices reading should complete before handling */
3885         barrier();
3886         return rc;
3887 }
3888
3889 /*
3890  * slow path service functions
3891  */
3892
3893 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3894 {
3895         int port = BP_PORT(bp);
3896         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3897                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3898         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3899                                        NIG_REG_MASK_INTERRUPT_PORT0;
3900         u32 aeu_mask;
3901         u32 nig_mask = 0;
3902         u32 reg_addr;
3903
3904         if (bp->attn_state & asserted)
3905                 BNX2X_ERR("IGU ERROR\n");
3906
3907         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3908         aeu_mask = REG_RD(bp, aeu_addr);
3909
3910         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3911            aeu_mask, asserted);
3912         aeu_mask &= ~(asserted & 0x3ff);
3913         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3914
3915         REG_WR(bp, aeu_addr, aeu_mask);
3916         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3917
3918         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3919         bp->attn_state |= asserted;
3920         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3921
3922         if (asserted & ATTN_HARD_WIRED_MASK) {
3923                 if (asserted & ATTN_NIG_FOR_FUNC) {
3924
3925                         bnx2x_acquire_phy_lock(bp);
3926
3927                         /* save nig interrupt mask */
3928                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3929
3930                         /* If nig_mask is not set, no need to call the update
3931                          * function.
3932                          */
3933                         if (nig_mask) {
3934                                 REG_WR(bp, nig_int_mask_addr, 0);
3935
3936                                 bnx2x_link_attn(bp);
3937                         }
3938
3939                         /* handle unicore attn? */
3940                 }
3941                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3942                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3943
3944                 if (asserted & GPIO_2_FUNC)
3945                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3946
3947                 if (asserted & GPIO_3_FUNC)
3948                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3949
3950                 if (asserted & GPIO_4_FUNC)
3951                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3952
3953                 if (port == 0) {
3954                         if (asserted & ATTN_GENERAL_ATTN_1) {
3955                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3956                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3957                         }
3958                         if (asserted & ATTN_GENERAL_ATTN_2) {
3959                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3960                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3961                         }
3962                         if (asserted & ATTN_GENERAL_ATTN_3) {
3963                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3964                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3965                         }
3966                 } else {
3967                         if (asserted & ATTN_GENERAL_ATTN_4) {
3968                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3969                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3970                         }
3971                         if (asserted & ATTN_GENERAL_ATTN_5) {
3972                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3973                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3974                         }
3975                         if (asserted & ATTN_GENERAL_ATTN_6) {
3976                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3977                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3978                         }
3979                 }
3980
3981         } /* if hardwired */
3982
3983         if (bp->common.int_block == INT_BLOCK_HC)
3984                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3985                             COMMAND_REG_ATTN_BITS_SET);
3986         else
3987                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3988
3989         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3990            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3991         REG_WR(bp, reg_addr, asserted);
3992
3993         /* now set back the mask */
3994         if (asserted & ATTN_NIG_FOR_FUNC) {
3995                 /* Verify that IGU ack through BAR was written before restoring
3996                  * NIG mask. This loop should exit after 2-3 iterations max.
3997                  */
3998                 if (bp->common.int_block != INT_BLOCK_HC) {
3999                         u32 cnt = 0, igu_acked;
4000                         do {
4001                                 igu_acked = REG_RD(bp,
4002                                                    IGU_REG_ATTENTION_ACK_BITS);
4003                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4004                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4005                         if (!igu_acked)
4006                                 DP(NETIF_MSG_HW,
4007                                    "Failed to verify IGU ack on time\n");
4008                         barrier();
4009                 }
4010                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4011                 bnx2x_release_phy_lock(bp);
4012         }
4013 }
4014
4015 static void bnx2x_fan_failure(struct bnx2x *bp)
4016 {
4017         int port = BP_PORT(bp);
4018         u32 ext_phy_config;
4019         /* mark the failure */
4020         ext_phy_config =
4021                 SHMEM_RD(bp,
4022                          dev_info.port_hw_config[port].external_phy_config);
4023
4024         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4025         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4026         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4027                  ext_phy_config);
4028
4029         /* log the failure */
4030         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4031                             "Please contact OEM Support for assistance\n");
4032
4033         /* Schedule device reset (unload)
4034          * This is due to some boards consuming sufficient power when driver is
4035          * up to overheat if fan fails.
4036          */
4037         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4038 }
4039
4040 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4041 {
4042         int port = BP_PORT(bp);
4043         int reg_offset;
4044         u32 val;
4045
4046         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4047                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4048
4049         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4050
4051                 val = REG_RD(bp, reg_offset);
4052                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4053                 REG_WR(bp, reg_offset, val);
4054
4055                 BNX2X_ERR("SPIO5 hw attention\n");
4056
4057                 /* Fan failure attention */
4058                 bnx2x_hw_reset_phy(&bp->link_params);
4059                 bnx2x_fan_failure(bp);
4060         }
4061
4062         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4063                 bnx2x_acquire_phy_lock(bp);
4064                 bnx2x_handle_module_detect_int(&bp->link_params);
4065                 bnx2x_release_phy_lock(bp);
4066         }
4067
4068         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4069
4070                 val = REG_RD(bp, reg_offset);
4071                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4072                 REG_WR(bp, reg_offset, val);
4073
4074                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4075                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4076                 bnx2x_panic();
4077         }
4078 }
4079
4080 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4081 {
4082         u32 val;
4083
4084         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4085
4086                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4087                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4088                 /* DORQ discard attention */
4089                 if (val & 0x2)
4090                         BNX2X_ERR("FATAL error from DORQ\n");
4091         }
4092
4093         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4094
4095                 int port = BP_PORT(bp);
4096                 int reg_offset;
4097
4098                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4099                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4100
4101                 val = REG_RD(bp, reg_offset);
4102                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4103                 REG_WR(bp, reg_offset, val);
4104
4105                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4106                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4107                 bnx2x_panic();
4108         }
4109 }
4110
4111 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4112 {
4113         u32 val;
4114
4115         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4116
4117                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4118                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4119                 /* CFC error attention */
4120                 if (val & 0x2)
4121                         BNX2X_ERR("FATAL error from CFC\n");
4122         }
4123
4124         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4125                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4126                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4127                 /* RQ_USDMDP_FIFO_OVERFLOW */
4128                 if (val & 0x18000)
4129                         BNX2X_ERR("FATAL error from PXP\n");
4130
4131                 if (!CHIP_IS_E1x(bp)) {
4132                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4133                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4134                 }
4135         }
4136
4137         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4138
4139                 int port = BP_PORT(bp);
4140                 int reg_offset;
4141
4142                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4143                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4144
4145                 val = REG_RD(bp, reg_offset);
4146                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4147                 REG_WR(bp, reg_offset, val);
4148
4149                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4150                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4151                 bnx2x_panic();
4152         }
4153 }
4154
4155 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4156 {
4157         u32 val;
4158
4159         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4160
4161                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4162                         int func = BP_FUNC(bp);
4163
4164                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4165                         bnx2x_read_mf_cfg(bp);
4166                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4167                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4168                         val = SHMEM_RD(bp,
4169                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4170                         if (val & DRV_STATUS_DCC_EVENT_MASK)
4171                                 bnx2x_dcc_event(bp,
4172                                             (val & DRV_STATUS_DCC_EVENT_MASK));
4173
4174                         if (val & DRV_STATUS_SET_MF_BW)
4175                                 bnx2x_set_mf_bw(bp);
4176
4177                         if (val & DRV_STATUS_DRV_INFO_REQ)
4178                                 bnx2x_handle_drv_info_req(bp);
4179
4180                         if (val & DRV_STATUS_VF_DISABLED)
4181                                 bnx2x_schedule_iov_task(bp,
4182                                                         BNX2X_IOV_HANDLE_FLR);
4183
4184                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4185                                 bnx2x_pmf_update(bp);
4186
4187                         if (bp->port.pmf &&
4188                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4189                                 bp->dcbx_enabled > 0)
4190                                 /* start dcbx state machine */
4191                                 bnx2x_dcbx_set_params(bp,
4192                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4193                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4194                                 bnx2x_handle_afex_cmd(bp,
4195                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4196                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4197                                 bnx2x_handle_eee_event(bp);
4198                         if (bp->link_vars.periodic_flags &
4199                             PERIODIC_FLAGS_LINK_EVENT) {
4200                                 /*  sync with link */
4201                                 bnx2x_acquire_phy_lock(bp);
4202                                 bp->link_vars.periodic_flags &=
4203                                         ~PERIODIC_FLAGS_LINK_EVENT;
4204                                 bnx2x_release_phy_lock(bp);
4205                                 if (IS_MF(bp))
4206                                         bnx2x_link_sync_notify(bp);
4207                                 bnx2x_link_report(bp);
4208                         }
4209                         /* Always call it here: bnx2x_link_report() will
4210                          * prevent the link indication duplication.
4211                          */
4212                         bnx2x__link_status_update(bp);
4213                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4214
4215                         BNX2X_ERR("MC assert!\n");
4216                         bnx2x_mc_assert(bp);
4217                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4218                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4219                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4220                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4221                         bnx2x_panic();
4222
4223                 } else if (attn & BNX2X_MCP_ASSERT) {
4224
4225                         BNX2X_ERR("MCP assert!\n");
4226                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4227                         bnx2x_fw_dump(bp);
4228
4229                 } else
4230                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4231         }
4232
4233         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4234                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4235                 if (attn & BNX2X_GRC_TIMEOUT) {
4236                         val = CHIP_IS_E1(bp) ? 0 :
4237                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4238                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4239                 }
4240                 if (attn & BNX2X_GRC_RSV) {
4241                         val = CHIP_IS_E1(bp) ? 0 :
4242                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4243                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4244                 }
4245                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4246         }
4247 }
4248
4249 /*
4250  * Bits map:
4251  * 0-7   - Engine0 load counter.
4252  * 8-15  - Engine1 load counter.
4253  * 16    - Engine0 RESET_IN_PROGRESS bit.
4254  * 17    - Engine1 RESET_IN_PROGRESS bit.
4255  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4256  *         on the engine
4257  * 19    - Engine1 ONE_IS_LOADED.
4258  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4259  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4260  *         just the one belonging to its engine).
4261  *
4262  */
4263 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4264
4265 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4266 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4267 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4268 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4269 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4270 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4271 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4272
4273 /*
4274  * Set the GLOBAL_RESET bit.
4275  *
4276  * Should be run under rtnl lock
4277  */
4278 void bnx2x_set_reset_global(struct bnx2x *bp)
4279 {
4280         u32 val;
4281         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4282         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4283         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4284         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4285 }
4286
4287 /*
4288  * Clear the GLOBAL_RESET bit.
4289  *
4290  * Should be run under rtnl lock
4291  */
4292 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4293 {
4294         u32 val;
4295         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4296         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4297         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4298         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4299 }
4300
4301 /*
4302  * Checks the GLOBAL_RESET bit.
4303  *
4304  * should be run under rtnl lock
4305  */
4306 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4307 {
4308         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4309
4310         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4311         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4312 }
4313
4314 /*
4315  * Clear RESET_IN_PROGRESS bit for the current engine.
4316  *
4317  * Should be run under rtnl lock
4318  */
4319 static void bnx2x_set_reset_done(struct bnx2x *bp)
4320 {
4321         u32 val;
4322         u32 bit = BP_PATH(bp) ?
4323                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4324         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4325         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4326
4327         /* Clear the bit */
4328         val &= ~bit;
4329         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4330
4331         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4332 }
4333
4334 /*
4335  * Set RESET_IN_PROGRESS for the current engine.
4336  *
4337  * should be run under rtnl lock
4338  */
4339 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4340 {
4341         u32 val;
4342         u32 bit = BP_PATH(bp) ?
4343                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4344         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4345         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4346
4347         /* Set the bit */
4348         val |= bit;
4349         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4350         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4351 }
4352
4353 /*
4354  * Checks the RESET_IN_PROGRESS bit for the given engine.
4355  * should be run under rtnl lock
4356  */
4357 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4358 {
4359         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4360         u32 bit = engine ?
4361                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4362
4363         /* return false if bit is set */
4364         return (val & bit) ? false : true;
4365 }
4366
4367 /*
4368  * set pf load for the current pf.
4369  *
4370  * should be run under rtnl lock
4371  */
4372 void bnx2x_set_pf_load(struct bnx2x *bp)
4373 {
4374         u32 val1, val;
4375         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4376                              BNX2X_PATH0_LOAD_CNT_MASK;
4377         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4378                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4379
4380         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4381         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4382
4383         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4384
4385         /* get the current counter value */
4386         val1 = (val & mask) >> shift;
4387
4388         /* set bit of that PF */
4389         val1 |= (1 << bp->pf_num);
4390
4391         /* clear the old value */
4392         val &= ~mask;
4393
4394         /* set the new one */
4395         val |= ((val1 << shift) & mask);
4396
4397         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4398         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4399 }
4400
4401 /**
4402  * bnx2x_clear_pf_load - clear pf load mark
4403  *
4404  * @bp:         driver handle
4405  *
4406  * Should be run under rtnl lock.
4407  * Decrements the load counter for the current engine. Returns
4408  * whether other functions are still loaded
4409  */
4410 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4411 {
4412         u32 val1, val;
4413         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4414                              BNX2X_PATH0_LOAD_CNT_MASK;
4415         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4416                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4417
4418         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4419         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4420         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4421
4422         /* get the current counter value */
4423         val1 = (val & mask) >> shift;
4424
4425         /* clear bit of that PF */
4426         val1 &= ~(1 << bp->pf_num);
4427
4428         /* clear the old value */
4429         val &= ~mask;
4430
4431         /* set the new one */
4432         val |= ((val1 << shift) & mask);
4433
4434         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4435         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4436         return val1 != 0;
4437 }
4438
4439 /*
4440  * Read the load status for the current engine.
4441  *
4442  * should be run under rtnl lock
4443  */
4444 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4445 {
4446         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4447                              BNX2X_PATH0_LOAD_CNT_MASK);
4448         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4449                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4450         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4451
4452         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4453
4454         val = (val & mask) >> shift;
4455
4456         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4457            engine, val);
4458
4459         return val != 0;
4460 }
4461
4462 static void _print_parity(struct bnx2x *bp, u32 reg)
4463 {
4464         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4465 }
4466
4467 static void _print_next_block(int idx, const char *blk)
4468 {
4469         pr_cont("%s%s", idx ? ", " : "", blk);
4470 }
4471
4472 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4473                                             int *par_num, bool print)
4474 {
4475         u32 cur_bit;
4476         bool res;
4477         int i;
4478
4479         res = false;
4480
4481         for (i = 0; sig; i++) {
4482                 cur_bit = (0x1UL << i);
4483                 if (sig & cur_bit) {
4484                         res |= true; /* Each bit is real error! */
4485
4486                         if (print) {
4487                                 switch (cur_bit) {
4488                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4489                                         _print_next_block((*par_num)++, "BRB");
4490                                         _print_parity(bp,
4491                                                       BRB1_REG_BRB1_PRTY_STS);
4492                                         break;
4493                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4494                                         _print_next_block((*par_num)++,
4495                                                           "PARSER");
4496                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4497                                         break;
4498                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4499                                         _print_next_block((*par_num)++, "TSDM");
4500                                         _print_parity(bp,
4501                                                       TSDM_REG_TSDM_PRTY_STS);
4502                                         break;
4503                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4504                                         _print_next_block((*par_num)++,
4505                                                           "SEARCHER");
4506                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4507                                         break;
4508                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4509                                         _print_next_block((*par_num)++, "TCM");
4510                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4511                                         break;
4512                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4513                                         _print_next_block((*par_num)++,
4514                                                           "TSEMI");
4515                                         _print_parity(bp,
4516                                                       TSEM_REG_TSEM_PRTY_STS_0);
4517                                         _print_parity(bp,
4518                                                       TSEM_REG_TSEM_PRTY_STS_1);
4519                                         break;
4520                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4521                                         _print_next_block((*par_num)++, "XPB");
4522                                         _print_parity(bp, GRCBASE_XPB +
4523                                                           PB_REG_PB_PRTY_STS);
4524                                         break;
4525                                 }
4526                         }
4527
4528                         /* Clear the bit */
4529                         sig &= ~cur_bit;
4530                 }
4531         }
4532
4533         return res;
4534 }
4535
4536 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4537                                             int *par_num, bool *global,
4538                                             bool print)
4539 {
4540         u32 cur_bit;
4541         bool res;
4542         int i;
4543
4544         res = false;
4545
4546         for (i = 0; sig; i++) {
4547                 cur_bit = (0x1UL << i);
4548                 if (sig & cur_bit) {
4549                         res |= true; /* Each bit is real error! */
4550                         switch (cur_bit) {
4551                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4552                                 if (print) {
4553                                         _print_next_block((*par_num)++, "PBF");
4554                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4555                                 }
4556                                 break;
4557                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4558                                 if (print) {
4559                                         _print_next_block((*par_num)++, "QM");
4560                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4561                                 }
4562                                 break;
4563                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4564                                 if (print) {
4565                                         _print_next_block((*par_num)++, "TM");
4566                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4567                                 }
4568                                 break;
4569                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4570                                 if (print) {
4571                                         _print_next_block((*par_num)++, "XSDM");
4572                                         _print_parity(bp,
4573                                                       XSDM_REG_XSDM_PRTY_STS);
4574                                 }
4575                                 break;
4576                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4577                                 if (print) {
4578                                         _print_next_block((*par_num)++, "XCM");
4579                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4580                                 }
4581                                 break;
4582                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4583                                 if (print) {
4584                                         _print_next_block((*par_num)++,
4585                                                           "XSEMI");
4586                                         _print_parity(bp,
4587                                                       XSEM_REG_XSEM_PRTY_STS_0);
4588                                         _print_parity(bp,
4589                                                       XSEM_REG_XSEM_PRTY_STS_1);
4590                                 }
4591                                 break;
4592                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4593                                 if (print) {
4594                                         _print_next_block((*par_num)++,
4595                                                           "DOORBELLQ");
4596                                         _print_parity(bp,
4597                                                       DORQ_REG_DORQ_PRTY_STS);
4598                                 }
4599                                 break;
4600                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4601                                 if (print) {
4602                                         _print_next_block((*par_num)++, "NIG");
4603                                         if (CHIP_IS_E1x(bp)) {
4604                                                 _print_parity(bp,
4605                                                         NIG_REG_NIG_PRTY_STS);
4606                                         } else {
4607                                                 _print_parity(bp,
4608                                                         NIG_REG_NIG_PRTY_STS_0);
4609                                                 _print_parity(bp,
4610                                                         NIG_REG_NIG_PRTY_STS_1);
4611                                         }
4612                                 }
4613                                 break;
4614                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4615                                 if (print)
4616                                         _print_next_block((*par_num)++,
4617                                                           "VAUX PCI CORE");
4618                                 *global = true;
4619                                 break;
4620                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4621                                 if (print) {
4622                                         _print_next_block((*par_num)++,
4623                                                           "DEBUG");
4624                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4625                                 }
4626                                 break;
4627                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4628                                 if (print) {
4629                                         _print_next_block((*par_num)++, "USDM");
4630                                         _print_parity(bp,
4631                                                       USDM_REG_USDM_PRTY_STS);
4632                                 }
4633                                 break;
4634                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4635                                 if (print) {
4636                                         _print_next_block((*par_num)++, "UCM");
4637                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4638                                 }
4639                                 break;
4640                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4641                                 if (print) {
4642                                         _print_next_block((*par_num)++,
4643                                                           "USEMI");
4644                                         _print_parity(bp,
4645                                                       USEM_REG_USEM_PRTY_STS_0);
4646                                         _print_parity(bp,
4647                                                       USEM_REG_USEM_PRTY_STS_1);
4648                                 }
4649                                 break;
4650                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4651                                 if (print) {
4652                                         _print_next_block((*par_num)++, "UPB");
4653                                         _print_parity(bp, GRCBASE_UPB +
4654                                                           PB_REG_PB_PRTY_STS);
4655                                 }
4656                                 break;
4657                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4658                                 if (print) {
4659                                         _print_next_block((*par_num)++, "CSDM");
4660                                         _print_parity(bp,
4661                                                       CSDM_REG_CSDM_PRTY_STS);
4662                                 }
4663                                 break;
4664                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4665                                 if (print) {
4666                                         _print_next_block((*par_num)++, "CCM");
4667                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4668                                 }
4669                                 break;
4670                         }
4671
4672                         /* Clear the bit */
4673                         sig &= ~cur_bit;
4674                 }
4675         }
4676
4677         return res;
4678 }
4679
4680 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4681                                             int *par_num, bool print)
4682 {
4683         u32 cur_bit;
4684         bool res;
4685         int i;
4686
4687         res = false;
4688
4689         for (i = 0; sig; i++) {
4690                 cur_bit = (0x1UL << i);
4691                 if (sig & cur_bit) {
4692                         res = true; /* Each bit is real error! */
4693                         if (print) {
4694                                 switch (cur_bit) {
4695                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4696                                         _print_next_block((*par_num)++,
4697                                                           "CSEMI");
4698                                         _print_parity(bp,
4699                                                       CSEM_REG_CSEM_PRTY_STS_0);
4700                                         _print_parity(bp,
4701                                                       CSEM_REG_CSEM_PRTY_STS_1);
4702                                         break;
4703                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4704                                         _print_next_block((*par_num)++, "PXP");
4705                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4706                                         _print_parity(bp,
4707                                                       PXP2_REG_PXP2_PRTY_STS_0);
4708                                         _print_parity(bp,
4709                                                       PXP2_REG_PXP2_PRTY_STS_1);
4710                                         break;
4711                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4712                                         _print_next_block((*par_num)++,
4713                                                           "PXPPCICLOCKCLIENT");
4714                                         break;
4715                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4716                                         _print_next_block((*par_num)++, "CFC");
4717                                         _print_parity(bp,
4718                                                       CFC_REG_CFC_PRTY_STS);
4719                                         break;
4720                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4721                                         _print_next_block((*par_num)++, "CDU");
4722                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4723                                         break;
4724                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4725                                         _print_next_block((*par_num)++, "DMAE");
4726                                         _print_parity(bp,
4727                                                       DMAE_REG_DMAE_PRTY_STS);
4728                                         break;
4729                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4730                                         _print_next_block((*par_num)++, "IGU");
4731                                         if (CHIP_IS_E1x(bp))
4732                                                 _print_parity(bp,
4733                                                         HC_REG_HC_PRTY_STS);
4734                                         else
4735                                                 _print_parity(bp,
4736                                                         IGU_REG_IGU_PRTY_STS);
4737                                         break;
4738                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4739                                         _print_next_block((*par_num)++, "MISC");
4740                                         _print_parity(bp,
4741                                                       MISC_REG_MISC_PRTY_STS);
4742                                         break;
4743                                 }
4744                         }
4745
4746                         /* Clear the bit */
4747                         sig &= ~cur_bit;
4748                 }
4749         }
4750
4751         return res;
4752 }
4753
4754 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4755                                             int *par_num, bool *global,
4756                                             bool print)
4757 {
4758         bool res = false;
4759         u32 cur_bit;
4760         int i;
4761
4762         for (i = 0; sig; i++) {
4763                 cur_bit = (0x1UL << i);
4764                 if (sig & cur_bit) {
4765                         switch (cur_bit) {
4766                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4767                                 if (print)
4768                                         _print_next_block((*par_num)++,
4769                                                           "MCP ROM");
4770                                 *global = true;
4771                                 res = true;
4772                                 break;
4773                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4774                                 if (print)
4775                                         _print_next_block((*par_num)++,
4776                                                           "MCP UMP RX");
4777                                 *global = true;
4778                                 res = true;
4779                                 break;
4780                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4781                                 if (print)
4782                                         _print_next_block((*par_num)++,
4783                                                           "MCP UMP TX");
4784                                 *global = true;
4785                                 res = true;
4786                                 break;
4787                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4788                                 if (print)
4789                                         _print_next_block((*par_num)++,
4790                                                           "MCP SCPAD");
4791                                 /* clear latched SCPAD PATIRY from MCP */
4792                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4793                                        1UL << 10);
4794                                 break;
4795                         }
4796
4797                         /* Clear the bit */
4798                         sig &= ~cur_bit;
4799                 }
4800         }
4801
4802         return res;
4803 }
4804
4805 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4806                                             int *par_num, bool print)
4807 {
4808         u32 cur_bit;
4809         bool res;
4810         int i;
4811
4812         res = false;
4813
4814         for (i = 0; sig; i++) {
4815                 cur_bit = (0x1UL << i);
4816                 if (sig & cur_bit) {
4817                         res = true; /* Each bit is real error! */
4818                         if (print) {
4819                                 switch (cur_bit) {
4820                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4821                                         _print_next_block((*par_num)++,
4822                                                           "PGLUE_B");
4823                                         _print_parity(bp,
4824                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4825                                         break;
4826                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4827                                         _print_next_block((*par_num)++, "ATC");
4828                                         _print_parity(bp,
4829                                                       ATC_REG_ATC_PRTY_STS);
4830                                         break;
4831                                 }
4832                         }
4833                         /* Clear the bit */
4834                         sig &= ~cur_bit;
4835                 }
4836         }
4837
4838         return res;
4839 }
4840
4841 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4842                               u32 *sig)
4843 {
4844         bool res = false;
4845
4846         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4847             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4848             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4849             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4850             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4851                 int par_num = 0;
4852                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4853                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4854                           sig[0] & HW_PRTY_ASSERT_SET_0,
4855                           sig[1] & HW_PRTY_ASSERT_SET_1,
4856                           sig[2] & HW_PRTY_ASSERT_SET_2,
4857                           sig[3] & HW_PRTY_ASSERT_SET_3,
4858                           sig[4] & HW_PRTY_ASSERT_SET_4);
4859                 if (print)
4860                         netdev_err(bp->dev,
4861                                    "Parity errors detected in blocks: ");
4862                 res |= bnx2x_check_blocks_with_parity0(bp,
4863                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4864                 res |= bnx2x_check_blocks_with_parity1(bp,
4865                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4866                 res |= bnx2x_check_blocks_with_parity2(bp,
4867                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4868                 res |= bnx2x_check_blocks_with_parity3(bp,
4869                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4870                 res |= bnx2x_check_blocks_with_parity4(bp,
4871                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4872
4873                 if (print)
4874                         pr_cont("\n");
4875         }
4876
4877         return res;
4878 }
4879
4880 /**
4881  * bnx2x_chk_parity_attn - checks for parity attentions.
4882  *
4883  * @bp:         driver handle
4884  * @global:     true if there was a global attention
4885  * @print:      show parity attention in syslog
4886  */
4887 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4888 {
4889         struct attn_route attn = { {0} };
4890         int port = BP_PORT(bp);
4891
4892         attn.sig[0] = REG_RD(bp,
4893                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4894                              port*4);
4895         attn.sig[1] = REG_RD(bp,
4896                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4897                              port*4);
4898         attn.sig[2] = REG_RD(bp,
4899                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4900                              port*4);
4901         attn.sig[3] = REG_RD(bp,
4902                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4903                              port*4);
4904         /* Since MCP attentions can't be disabled inside the block, we need to
4905          * read AEU registers to see whether they're currently disabled
4906          */
4907         attn.sig[3] &= ((REG_RD(bp,
4908                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4909                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4910                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4911                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4912
4913         if (!CHIP_IS_E1x(bp))
4914                 attn.sig[4] = REG_RD(bp,
4915                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4916                                      port*4);
4917
4918         return bnx2x_parity_attn(bp, global, print, attn.sig);
4919 }
4920
4921 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4922 {
4923         u32 val;
4924         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4925
4926                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4927                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4928                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4929                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4930                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4931                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4932                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4933                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4934                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4935                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4936                 if (val &
4937                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4938                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4939                 if (val &
4940                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4941                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4942                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4943                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4944                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4945                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4946                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4947                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4948         }
4949         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4950                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4951                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4952                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4953                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4954                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4955                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4956                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4957                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4958                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4959                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4960                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4961                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4962                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4963                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4964         }
4965
4966         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4967                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4968                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4969                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4970                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4971         }
4972 }
4973
4974 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4975 {
4976         struct attn_route attn, *group_mask;
4977         int port = BP_PORT(bp);
4978         int index;
4979         u32 reg_addr;
4980         u32 val;
4981         u32 aeu_mask;
4982         bool global = false;
4983
4984         /* need to take HW lock because MCP or other port might also
4985            try to handle this event */
4986         bnx2x_acquire_alr(bp);
4987
4988         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4989 #ifndef BNX2X_STOP_ON_ERROR
4990                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4991                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4992                 /* Disable HW interrupts */
4993                 bnx2x_int_disable(bp);
4994                 /* In case of parity errors don't handle attentions so that
4995                  * other function would "see" parity errors.
4996                  */
4997 #else
4998                 bnx2x_panic();
4999 #endif
5000                 bnx2x_release_alr(bp);
5001                 return;
5002         }
5003
5004         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5005         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5006         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5007         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5008         if (!CHIP_IS_E1x(bp))
5009                 attn.sig[4] =
5010                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5011         else
5012                 attn.sig[4] = 0;
5013
5014         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5015            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5016
5017         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5018                 if (deasserted & (1 << index)) {
5019                         group_mask = &bp->attn_group[index];
5020
5021                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5022                            index,
5023                            group_mask->sig[0], group_mask->sig[1],
5024                            group_mask->sig[2], group_mask->sig[3],
5025                            group_mask->sig[4]);
5026
5027                         bnx2x_attn_int_deasserted4(bp,
5028                                         attn.sig[4] & group_mask->sig[4]);
5029                         bnx2x_attn_int_deasserted3(bp,
5030                                         attn.sig[3] & group_mask->sig[3]);
5031                         bnx2x_attn_int_deasserted1(bp,
5032                                         attn.sig[1] & group_mask->sig[1]);
5033                         bnx2x_attn_int_deasserted2(bp,
5034                                         attn.sig[2] & group_mask->sig[2]);
5035                         bnx2x_attn_int_deasserted0(bp,
5036                                         attn.sig[0] & group_mask->sig[0]);
5037                 }
5038         }
5039
5040         bnx2x_release_alr(bp);
5041
5042         if (bp->common.int_block == INT_BLOCK_HC)
5043                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5044                             COMMAND_REG_ATTN_BITS_CLR);
5045         else
5046                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5047
5048         val = ~deasserted;
5049         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5050            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5051         REG_WR(bp, reg_addr, val);
5052
5053         if (~bp->attn_state & deasserted)
5054                 BNX2X_ERR("IGU ERROR\n");
5055
5056         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5057                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5058
5059         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5060         aeu_mask = REG_RD(bp, reg_addr);
5061
5062         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5063            aeu_mask, deasserted);
5064         aeu_mask |= (deasserted & 0x3ff);
5065         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5066
5067         REG_WR(bp, reg_addr, aeu_mask);
5068         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5069
5070         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5071         bp->attn_state &= ~deasserted;
5072         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5073 }
5074
5075 static void bnx2x_attn_int(struct bnx2x *bp)
5076 {
5077         /* read local copy of bits */
5078         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5079                                                                 attn_bits);
5080         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5081                                                                 attn_bits_ack);
5082         u32 attn_state = bp->attn_state;
5083
5084         /* look for changed bits */
5085         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5086         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5087
5088         DP(NETIF_MSG_HW,
5089            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5090            attn_bits, attn_ack, asserted, deasserted);
5091
5092         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5093                 BNX2X_ERR("BAD attention state\n");
5094
5095         /* handle bits that were raised */
5096         if (asserted)
5097                 bnx2x_attn_int_asserted(bp, asserted);
5098
5099         if (deasserted)
5100                 bnx2x_attn_int_deasserted(bp, deasserted);
5101 }
5102
5103 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5104                       u16 index, u8 op, u8 update)
5105 {
5106         u32 igu_addr = bp->igu_base_addr;
5107         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5108         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5109                              igu_addr);
5110 }
5111
5112 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5113 {
5114         /* No memory barriers */
5115         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5116         mmiowb(); /* keep prod updates ordered */
5117 }
5118
5119 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5120                                       union event_ring_elem *elem)
5121 {
5122         u8 err = elem->message.error;
5123
5124         if (!bp->cnic_eth_dev.starting_cid  ||
5125             (cid < bp->cnic_eth_dev.starting_cid &&
5126             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5127                 return 1;
5128
5129         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5130
5131         if (unlikely(err)) {
5132
5133                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5134                           cid);
5135                 bnx2x_panic_dump(bp, false);
5136         }
5137         bnx2x_cnic_cfc_comp(bp, cid, err);
5138         return 0;
5139 }
5140
5141 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5142 {
5143         struct bnx2x_mcast_ramrod_params rparam;
5144         int rc;
5145
5146         memset(&rparam, 0, sizeof(rparam));
5147
5148         rparam.mcast_obj = &bp->mcast_obj;
5149
5150         netif_addr_lock_bh(bp->dev);
5151
5152         /* Clear pending state for the last command */
5153         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5154
5155         /* If there are pending mcast commands - send them */
5156         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5157                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5158                 if (rc < 0)
5159                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5160                                   rc);
5161         }
5162
5163         netif_addr_unlock_bh(bp->dev);
5164 }
5165
5166 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5167                                             union event_ring_elem *elem)
5168 {
5169         unsigned long ramrod_flags = 0;
5170         int rc = 0;
5171         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5172         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5173
5174         /* Always push next commands out, don't wait here */
5175         __set_bit(RAMROD_CONT, &ramrod_flags);
5176
5177         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5178                             >> BNX2X_SWCID_SHIFT) {
5179         case BNX2X_FILTER_MAC_PENDING:
5180                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5181                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5182                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5183                 else
5184                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5185
5186                 break;
5187         case BNX2X_FILTER_MCAST_PENDING:
5188                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5189                 /* This is only relevant for 57710 where multicast MACs are
5190                  * configured as unicast MACs using the same ramrod.
5191                  */
5192                 bnx2x_handle_mcast_eqe(bp);
5193                 return;
5194         default:
5195                 BNX2X_ERR("Unsupported classification command: %d\n",
5196                           elem->message.data.eth_event.echo);
5197                 return;
5198         }
5199
5200         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5201
5202         if (rc < 0)
5203                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5204         else if (rc > 0)
5205                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5206 }
5207
5208 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5209
5210 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5211 {
5212         netif_addr_lock_bh(bp->dev);
5213
5214         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5215
5216         /* Send rx_mode command again if was requested */
5217         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5218                 bnx2x_set_storm_rx_mode(bp);
5219         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5220                                     &bp->sp_state))
5221                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5222         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5223                                     &bp->sp_state))
5224                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5225
5226         netif_addr_unlock_bh(bp->dev);
5227 }
5228
5229 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5230                                               union event_ring_elem *elem)
5231 {
5232         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5233                 DP(BNX2X_MSG_SP,
5234                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5235                    elem->message.data.vif_list_event.func_bit_map);
5236                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5237                         elem->message.data.vif_list_event.func_bit_map);
5238         } else if (elem->message.data.vif_list_event.echo ==
5239                    VIF_LIST_RULE_SET) {
5240                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5241                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5242         }
5243 }
5244
5245 /* called with rtnl_lock */
5246 static void bnx2x_after_function_update(struct bnx2x *bp)
5247 {
5248         int q, rc;
5249         struct bnx2x_fastpath *fp;
5250         struct bnx2x_queue_state_params queue_params = {NULL};
5251         struct bnx2x_queue_update_params *q_update_params =
5252                 &queue_params.params.update;
5253
5254         /* Send Q update command with afex vlan removal values for all Qs */
5255         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5256
5257         /* set silent vlan removal values according to vlan mode */
5258         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5259                   &q_update_params->update_flags);
5260         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5261                   &q_update_params->update_flags);
5262         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5263
5264         /* in access mode mark mask and value are 0 to strip all vlans */
5265         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5266                 q_update_params->silent_removal_value = 0;
5267                 q_update_params->silent_removal_mask = 0;
5268         } else {
5269                 q_update_params->silent_removal_value =
5270                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5271                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5272         }
5273
5274         for_each_eth_queue(bp, q) {
5275                 /* Set the appropriate Queue object */
5276                 fp = &bp->fp[q];
5277                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5278
5279                 /* send the ramrod */
5280                 rc = bnx2x_queue_state_change(bp, &queue_params);
5281                 if (rc < 0)
5282                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5283                                   q);
5284         }
5285
5286         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5287                 fp = &bp->fp[FCOE_IDX(bp)];
5288                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5289
5290                 /* clear pending completion bit */
5291                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5292
5293                 /* mark latest Q bit */
5294                 smp_mb__before_atomic();
5295                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5296                 smp_mb__after_atomic();
5297
5298                 /* send Q update ramrod for FCoE Q */
5299                 rc = bnx2x_queue_state_change(bp, &queue_params);
5300                 if (rc < 0)
5301                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5302                                   q);
5303         } else {
5304                 /* If no FCoE ring - ACK MCP now */
5305                 bnx2x_link_report(bp);
5306                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5307         }
5308 }
5309
5310 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5311         struct bnx2x *bp, u32 cid)
5312 {
5313         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5314
5315         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5316                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5317         else
5318                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5319 }
5320
5321 static void bnx2x_eq_int(struct bnx2x *bp)
5322 {
5323         u16 hw_cons, sw_cons, sw_prod;
5324         union event_ring_elem *elem;
5325         u8 echo;
5326         u32 cid;
5327         u8 opcode;
5328         int rc, spqe_cnt = 0;
5329         struct bnx2x_queue_sp_obj *q_obj;
5330         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5331         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5332
5333         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5334
5335         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5336          * when we get the next-page we need to adjust so the loop
5337          * condition below will be met. The next element is the size of a
5338          * regular element and hence incrementing by 1
5339          */
5340         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5341                 hw_cons++;
5342
5343         /* This function may never run in parallel with itself for a
5344          * specific bp, thus there is no need in "paired" read memory
5345          * barrier here.
5346          */
5347         sw_cons = bp->eq_cons;
5348         sw_prod = bp->eq_prod;
5349
5350         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5351                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5352
5353         for (; sw_cons != hw_cons;
5354               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5355
5356                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5357
5358                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5359                 if (!rc) {
5360                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5361                            rc);
5362                         goto next_spqe;
5363                 }
5364
5365                 /* elem CID originates from FW; actually LE */
5366                 cid = SW_CID((__force __le32)
5367                              elem->message.data.cfc_del_event.cid);
5368                 opcode = elem->message.opcode;
5369
5370                 /* handle eq element */
5371                 switch (opcode) {
5372                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5373                         bnx2x_vf_mbx_schedule(bp,
5374                                               &elem->message.data.vf_pf_event);
5375                         continue;
5376
5377                 case EVENT_RING_OPCODE_STAT_QUERY:
5378                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5379                                "got statistics comp event %d\n",
5380                                bp->stats_comp++);
5381                         /* nothing to do with stats comp */
5382                         goto next_spqe;
5383
5384                 case EVENT_RING_OPCODE_CFC_DEL:
5385                         /* handle according to cid range */
5386                         /*
5387                          * we may want to verify here that the bp state is
5388                          * HALTING
5389                          */
5390                         DP(BNX2X_MSG_SP,
5391                            "got delete ramrod for MULTI[%d]\n", cid);
5392
5393                         if (CNIC_LOADED(bp) &&
5394                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5395                                 goto next_spqe;
5396
5397                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5398
5399                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5400                                 break;
5401
5402                         goto next_spqe;
5403
5404                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5405                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5406                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5407                         if (f_obj->complete_cmd(bp, f_obj,
5408                                                 BNX2X_F_CMD_TX_STOP))
5409                                 break;
5410                         goto next_spqe;
5411
5412                 case EVENT_RING_OPCODE_START_TRAFFIC:
5413                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5414                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5415                         if (f_obj->complete_cmd(bp, f_obj,
5416                                                 BNX2X_F_CMD_TX_START))
5417                                 break;
5418                         goto next_spqe;
5419
5420                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5421                         echo = elem->message.data.function_update_event.echo;
5422                         if (echo == SWITCH_UPDATE) {
5423                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5424                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5425                                 if (f_obj->complete_cmd(
5426                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5427                                         break;
5428
5429                         } else {
5430                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5431
5432                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5433                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5434                                 f_obj->complete_cmd(bp, f_obj,
5435                                                     BNX2X_F_CMD_AFEX_UPDATE);
5436
5437                                 /* We will perform the Queues update from
5438                                  * sp_rtnl task as all Queue SP operations
5439                                  * should run under rtnl_lock.
5440                                  */
5441                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5442                         }
5443
5444                         goto next_spqe;
5445
5446                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5447                         f_obj->complete_cmd(bp, f_obj,
5448                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5449                         bnx2x_after_afex_vif_lists(bp, elem);
5450                         goto next_spqe;
5451                 case EVENT_RING_OPCODE_FUNCTION_START:
5452                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5453                            "got FUNC_START ramrod\n");
5454                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5455                                 break;
5456
5457                         goto next_spqe;
5458
5459                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5460                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5461                            "got FUNC_STOP ramrod\n");
5462                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5463                                 break;
5464
5465                         goto next_spqe;
5466
5467                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5468                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5469                            "got set_timesync ramrod completion\n");
5470                         if (f_obj->complete_cmd(bp, f_obj,
5471                                                 BNX2X_F_CMD_SET_TIMESYNC))
5472                                 break;
5473                         goto next_spqe;
5474                 }
5475
5476                 switch (opcode | bp->state) {
5477                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5478                       BNX2X_STATE_OPEN):
5479                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5480                       BNX2X_STATE_OPENING_WAIT4_PORT):
5481                         cid = elem->message.data.eth_event.echo &
5482                                 BNX2X_SWCID_MASK;
5483                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5484                            cid);
5485                         rss_raw->clear_pending(rss_raw);
5486                         break;
5487
5488                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5489                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5490                 case (EVENT_RING_OPCODE_SET_MAC |
5491                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5492                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5493                       BNX2X_STATE_OPEN):
5494                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5495                       BNX2X_STATE_DIAG):
5496                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5497                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5498                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5499                         bnx2x_handle_classification_eqe(bp, elem);
5500                         break;
5501
5502                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5503                       BNX2X_STATE_OPEN):
5504                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5505                       BNX2X_STATE_DIAG):
5506                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5507                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5508                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5509                         bnx2x_handle_mcast_eqe(bp);
5510                         break;
5511
5512                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5513                       BNX2X_STATE_OPEN):
5514                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5515                       BNX2X_STATE_DIAG):
5516                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5517                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5518                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5519                         bnx2x_handle_rx_mode_eqe(bp);
5520                         break;
5521                 default:
5522                         /* unknown event log error and continue */
5523                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5524                                   elem->message.opcode, bp->state);
5525                 }
5526 next_spqe:
5527                 spqe_cnt++;
5528         } /* for */
5529
5530         smp_mb__before_atomic();
5531         atomic_add(spqe_cnt, &bp->eq_spq_left);
5532
5533         bp->eq_cons = sw_cons;
5534         bp->eq_prod = sw_prod;
5535         /* Make sure that above mem writes were issued towards the memory */
5536         smp_wmb();
5537
5538         /* update producer */
5539         bnx2x_update_eq_prod(bp, bp->eq_prod);
5540 }
5541
5542 static void bnx2x_sp_task(struct work_struct *work)
5543 {
5544         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5545
5546         DP(BNX2X_MSG_SP, "sp task invoked\n");
5547
5548         /* make sure the atomic interrupt_occurred has been written */
5549         smp_rmb();
5550         if (atomic_read(&bp->interrupt_occurred)) {
5551
5552                 /* what work needs to be performed? */
5553                 u16 status = bnx2x_update_dsb_idx(bp);
5554
5555                 DP(BNX2X_MSG_SP, "status %x\n", status);
5556                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5557                 atomic_set(&bp->interrupt_occurred, 0);
5558
5559                 /* HW attentions */
5560                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5561                         bnx2x_attn_int(bp);
5562                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5563                 }
5564
5565                 /* SP events: STAT_QUERY and others */
5566                 if (status & BNX2X_DEF_SB_IDX) {
5567                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5568
5569                 if (FCOE_INIT(bp) &&
5570                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5571                                 /* Prevent local bottom-halves from running as
5572                                  * we are going to change the local NAPI list.
5573                                  */
5574                                 local_bh_disable();
5575                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5576                                 local_bh_enable();
5577                         }
5578
5579                         /* Handle EQ completions */
5580                         bnx2x_eq_int(bp);
5581                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5582                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5583
5584                         status &= ~BNX2X_DEF_SB_IDX;
5585                 }
5586
5587                 /* if status is non zero then perhaps something went wrong */
5588                 if (unlikely(status))
5589                         DP(BNX2X_MSG_SP,
5590                            "got an unknown interrupt! (status 0x%x)\n", status);
5591
5592                 /* ack status block only if something was actually handled */
5593                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5594                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5595         }
5596
5597         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5598         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5599                                &bp->sp_state)) {
5600                 bnx2x_link_report(bp);
5601                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5602         }
5603 }
5604
5605 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5606 {
5607         struct net_device *dev = dev_instance;
5608         struct bnx2x *bp = netdev_priv(dev);
5609
5610         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5611                      IGU_INT_DISABLE, 0);
5612
5613 #ifdef BNX2X_STOP_ON_ERROR
5614         if (unlikely(bp->panic))
5615                 return IRQ_HANDLED;
5616 #endif
5617
5618         if (CNIC_LOADED(bp)) {
5619                 struct cnic_ops *c_ops;
5620
5621                 rcu_read_lock();
5622                 c_ops = rcu_dereference(bp->cnic_ops);
5623                 if (c_ops)
5624                         c_ops->cnic_handler(bp->cnic_data, NULL);
5625                 rcu_read_unlock();
5626         }
5627
5628         /* schedule sp task to perform default status block work, ack
5629          * attentions and enable interrupts.
5630          */
5631         bnx2x_schedule_sp_task(bp);
5632
5633         return IRQ_HANDLED;
5634 }
5635
5636 /* end of slow path */
5637
5638 void bnx2x_drv_pulse(struct bnx2x *bp)
5639 {
5640         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5641                  bp->fw_drv_pulse_wr_seq);
5642 }
5643
5644 static void bnx2x_timer(unsigned long data)
5645 {
5646         struct bnx2x *bp = (struct bnx2x *) data;
5647
5648         if (!netif_running(bp->dev))
5649                 return;
5650
5651         if (IS_PF(bp) &&
5652             !BP_NOMCP(bp)) {
5653                 int mb_idx = BP_FW_MB_IDX(bp);
5654                 u16 drv_pulse;
5655                 u16 mcp_pulse;
5656
5657                 ++bp->fw_drv_pulse_wr_seq;
5658                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5659                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5660                 bnx2x_drv_pulse(bp);
5661
5662                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5663                              MCP_PULSE_SEQ_MASK);
5664                 /* The delta between driver pulse and mcp response
5665                  * should not get too big. If the MFW is more than 5 pulses
5666                  * behind, we should worry about it enough to generate an error
5667                  * log.
5668                  */
5669                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5670                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5671                                   drv_pulse, mcp_pulse);
5672         }
5673
5674         if (bp->state == BNX2X_STATE_OPEN)
5675                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5676
5677         /* sample pf vf bulletin board for new posts from pf */
5678         if (IS_VF(bp))
5679                 bnx2x_timer_sriov(bp);
5680
5681         mod_timer(&bp->timer, jiffies + bp->current_interval);
5682 }
5683
5684 /* end of Statistics */
5685
5686 /* nic init */
5687
5688 /*
5689  * nic init service functions
5690  */
5691
5692 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5693 {
5694         u32 i;
5695         if (!(len%4) && !(addr%4))
5696                 for (i = 0; i < len; i += 4)
5697                         REG_WR(bp, addr + i, fill);
5698         else
5699                 for (i = 0; i < len; i++)
5700                         REG_WR8(bp, addr + i, fill);
5701 }
5702
5703 /* helper: writes FP SP data to FW - data_size in dwords */
5704 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5705                                 int fw_sb_id,
5706                                 u32 *sb_data_p,
5707                                 u32 data_size)
5708 {
5709         int index;
5710         for (index = 0; index < data_size; index++)
5711                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5712                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5713                         sizeof(u32)*index,
5714                         *(sb_data_p + index));
5715 }
5716
5717 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5718 {
5719         u32 *sb_data_p;
5720         u32 data_size = 0;
5721         struct hc_status_block_data_e2 sb_data_e2;
5722         struct hc_status_block_data_e1x sb_data_e1x;
5723
5724         /* disable the function first */
5725         if (!CHIP_IS_E1x(bp)) {
5726                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5727                 sb_data_e2.common.state = SB_DISABLED;
5728                 sb_data_e2.common.p_func.vf_valid = false;
5729                 sb_data_p = (u32 *)&sb_data_e2;
5730                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5731         } else {
5732                 memset(&sb_data_e1x, 0,
5733                        sizeof(struct hc_status_block_data_e1x));
5734                 sb_data_e1x.common.state = SB_DISABLED;
5735                 sb_data_e1x.common.p_func.vf_valid = false;
5736                 sb_data_p = (u32 *)&sb_data_e1x;
5737                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5738         }
5739         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5740
5741         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5742                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5743                         CSTORM_STATUS_BLOCK_SIZE);
5744         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5745                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5746                         CSTORM_SYNC_BLOCK_SIZE);
5747 }
5748
5749 /* helper:  writes SP SB data to FW */
5750 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5751                 struct hc_sp_status_block_data *sp_sb_data)
5752 {
5753         int func = BP_FUNC(bp);
5754         int i;
5755         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5756                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5757                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5758                         i*sizeof(u32),
5759                         *((u32 *)sp_sb_data + i));
5760 }
5761
5762 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5763 {
5764         int func = BP_FUNC(bp);
5765         struct hc_sp_status_block_data sp_sb_data;
5766         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5767
5768         sp_sb_data.state = SB_DISABLED;
5769         sp_sb_data.p_func.vf_valid = false;
5770
5771         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5772
5773         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5774                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5775                         CSTORM_SP_STATUS_BLOCK_SIZE);
5776         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5777                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5778                         CSTORM_SP_SYNC_BLOCK_SIZE);
5779 }
5780
5781 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5782                                            int igu_sb_id, int igu_seg_id)
5783 {
5784         hc_sm->igu_sb_id = igu_sb_id;
5785         hc_sm->igu_seg_id = igu_seg_id;
5786         hc_sm->timer_value = 0xFF;
5787         hc_sm->time_to_expire = 0xFFFFFFFF;
5788 }
5789
5790 /* allocates state machine ids. */
5791 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5792 {
5793         /* zero out state machine indices */
5794         /* rx indices */
5795         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5796
5797         /* tx indices */
5798         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5799         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5800         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5801         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5802
5803         /* map indices */
5804         /* rx indices */
5805         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5806                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5807
5808         /* tx indices */
5809         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5810                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5811         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5812                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5813         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5814                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5815         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5816                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5817 }
5818
5819 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5820                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5821 {
5822         int igu_seg_id;
5823
5824         struct hc_status_block_data_e2 sb_data_e2;
5825         struct hc_status_block_data_e1x sb_data_e1x;
5826         struct hc_status_block_sm  *hc_sm_p;
5827         int data_size;
5828         u32 *sb_data_p;
5829
5830         if (CHIP_INT_MODE_IS_BC(bp))
5831                 igu_seg_id = HC_SEG_ACCESS_NORM;
5832         else
5833                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5834
5835         bnx2x_zero_fp_sb(bp, fw_sb_id);
5836
5837         if (!CHIP_IS_E1x(bp)) {
5838                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5839                 sb_data_e2.common.state = SB_ENABLED;
5840                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5841                 sb_data_e2.common.p_func.vf_id = vfid;
5842                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5843                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5844                 sb_data_e2.common.same_igu_sb_1b = true;
5845                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5846                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5847                 hc_sm_p = sb_data_e2.common.state_machine;
5848                 sb_data_p = (u32 *)&sb_data_e2;
5849                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5850                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5851         } else {
5852                 memset(&sb_data_e1x, 0,
5853                        sizeof(struct hc_status_block_data_e1x));
5854                 sb_data_e1x.common.state = SB_ENABLED;
5855                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5856                 sb_data_e1x.common.p_func.vf_id = 0xff;
5857                 sb_data_e1x.common.p_func.vf_valid = false;
5858                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5859                 sb_data_e1x.common.same_igu_sb_1b = true;
5860                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5861                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5862                 hc_sm_p = sb_data_e1x.common.state_machine;
5863                 sb_data_p = (u32 *)&sb_data_e1x;
5864                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5865                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5866         }
5867
5868         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5869                                        igu_sb_id, igu_seg_id);
5870         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5871                                        igu_sb_id, igu_seg_id);
5872
5873         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5874
5875         /* write indices to HW - PCI guarantees endianity of regpairs */
5876         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5877 }
5878
5879 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5880                                      u16 tx_usec, u16 rx_usec)
5881 {
5882         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5883                                     false, rx_usec);
5884         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5885                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5886                                        tx_usec);
5887         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5888                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5889                                        tx_usec);
5890         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5891                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5892                                        tx_usec);
5893 }
5894
5895 static void bnx2x_init_def_sb(struct bnx2x *bp)
5896 {
5897         struct host_sp_status_block *def_sb = bp->def_status_blk;
5898         dma_addr_t mapping = bp->def_status_blk_mapping;
5899         int igu_sp_sb_index;
5900         int igu_seg_id;
5901         int port = BP_PORT(bp);
5902         int func = BP_FUNC(bp);
5903         int reg_offset, reg_offset_en5;
5904         u64 section;
5905         int index;
5906         struct hc_sp_status_block_data sp_sb_data;
5907         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5908
5909         if (CHIP_INT_MODE_IS_BC(bp)) {
5910                 igu_sp_sb_index = DEF_SB_IGU_ID;
5911                 igu_seg_id = HC_SEG_ACCESS_DEF;
5912         } else {
5913                 igu_sp_sb_index = bp->igu_dsb_id;
5914                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5915         }
5916
5917         /* ATTN */
5918         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5919                                             atten_status_block);
5920         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5921
5922         bp->attn_state = 0;
5923
5924         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5925                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5926         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5927                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5928         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5929                 int sindex;
5930                 /* take care of sig[0]..sig[4] */
5931                 for (sindex = 0; sindex < 4; sindex++)
5932                         bp->attn_group[index].sig[sindex] =
5933                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5934
5935                 if (!CHIP_IS_E1x(bp))
5936                         /*
5937                          * enable5 is separate from the rest of the registers,
5938                          * and therefore the address skip is 4
5939                          * and not 16 between the different groups
5940                          */
5941                         bp->attn_group[index].sig[4] = REG_RD(bp,
5942                                         reg_offset_en5 + 0x4*index);
5943                 else
5944                         bp->attn_group[index].sig[4] = 0;
5945         }
5946
5947         if (bp->common.int_block == INT_BLOCK_HC) {
5948                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5949                                      HC_REG_ATTN_MSG0_ADDR_L);
5950
5951                 REG_WR(bp, reg_offset, U64_LO(section));
5952                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5953         } else if (!CHIP_IS_E1x(bp)) {
5954                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5955                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5956         }
5957
5958         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5959                                             sp_sb);
5960
5961         bnx2x_zero_sp_sb(bp);
5962
5963         /* PCI guarantees endianity of regpairs */
5964         sp_sb_data.state                = SB_ENABLED;
5965         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5966         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5967         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5968         sp_sb_data.igu_seg_id           = igu_seg_id;
5969         sp_sb_data.p_func.pf_id         = func;
5970         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5971         sp_sb_data.p_func.vf_id         = 0xff;
5972
5973         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5974
5975         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5976 }
5977
5978 void bnx2x_update_coalesce(struct bnx2x *bp)
5979 {
5980         int i;
5981
5982         for_each_eth_queue(bp, i)
5983                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5984                                          bp->tx_ticks, bp->rx_ticks);
5985 }
5986
5987 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5988 {
5989         spin_lock_init(&bp->spq_lock);
5990         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5991
5992         bp->spq_prod_idx = 0;
5993         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5994         bp->spq_prod_bd = bp->spq;
5995         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5996 }
5997
5998 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5999 {
6000         int i;
6001         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6002                 union event_ring_elem *elem =
6003                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6004
6005                 elem->next_page.addr.hi =
6006                         cpu_to_le32(U64_HI(bp->eq_mapping +
6007                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6008                 elem->next_page.addr.lo =
6009                         cpu_to_le32(U64_LO(bp->eq_mapping +
6010                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6011         }
6012         bp->eq_cons = 0;
6013         bp->eq_prod = NUM_EQ_DESC;
6014         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6015         /* we want a warning message before it gets wrought... */
6016         atomic_set(&bp->eq_spq_left,
6017                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6018 }
6019
6020 /* called with netif_addr_lock_bh() */
6021 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6022                                unsigned long rx_mode_flags,
6023                                unsigned long rx_accept_flags,
6024                                unsigned long tx_accept_flags,
6025                                unsigned long ramrod_flags)
6026 {
6027         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6028         int rc;
6029
6030         memset(&ramrod_param, 0, sizeof(ramrod_param));
6031
6032         /* Prepare ramrod parameters */
6033         ramrod_param.cid = 0;
6034         ramrod_param.cl_id = cl_id;
6035         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6036         ramrod_param.func_id = BP_FUNC(bp);
6037
6038         ramrod_param.pstate = &bp->sp_state;
6039         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6040
6041         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6042         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6043
6044         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6045
6046         ramrod_param.ramrod_flags = ramrod_flags;
6047         ramrod_param.rx_mode_flags = rx_mode_flags;
6048
6049         ramrod_param.rx_accept_flags = rx_accept_flags;
6050         ramrod_param.tx_accept_flags = tx_accept_flags;
6051
6052         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6053         if (rc < 0) {
6054                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6055                 return rc;
6056         }
6057
6058         return 0;
6059 }
6060
6061 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6062                                    unsigned long *rx_accept_flags,
6063                                    unsigned long *tx_accept_flags)
6064 {
6065         /* Clear the flags first */
6066         *rx_accept_flags = 0;
6067         *tx_accept_flags = 0;
6068
6069         switch (rx_mode) {
6070         case BNX2X_RX_MODE_NONE:
6071                 /*
6072                  * 'drop all' supersedes any accept flags that may have been
6073                  * passed to the function.
6074                  */
6075                 break;
6076         case BNX2X_RX_MODE_NORMAL:
6077                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6078                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6079                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6080
6081                 /* internal switching mode */
6082                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6083                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6084                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6085
6086                 break;
6087         case BNX2X_RX_MODE_ALLMULTI:
6088                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6089                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6090                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6091
6092                 /* internal switching mode */
6093                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6094                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6095                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6096
6097                 break;
6098         case BNX2X_RX_MODE_PROMISC:
6099                 /* According to definition of SI mode, iface in promisc mode
6100                  * should receive matched and unmatched (in resolution of port)
6101                  * unicast packets.
6102                  */
6103                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6104                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6105                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6106                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6107
6108                 /* internal switching mode */
6109                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6110                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6111
6112                 if (IS_MF_SI(bp))
6113                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6114                 else
6115                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6116
6117                 break;
6118         default:
6119                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6120                 return -EINVAL;
6121         }
6122
6123         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6124         if (rx_mode != BNX2X_RX_MODE_NONE) {
6125                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6126                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6127         }
6128
6129         return 0;
6130 }
6131
6132 /* called with netif_addr_lock_bh() */
6133 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6134 {
6135         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6136         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6137         int rc;
6138
6139         if (!NO_FCOE(bp))
6140                 /* Configure rx_mode of FCoE Queue */
6141                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6142
6143         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6144                                      &tx_accept_flags);
6145         if (rc)
6146                 return rc;
6147
6148         __set_bit(RAMROD_RX, &ramrod_flags);
6149         __set_bit(RAMROD_TX, &ramrod_flags);
6150
6151         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6152                                    rx_accept_flags, tx_accept_flags,
6153                                    ramrod_flags);
6154 }
6155
6156 static void bnx2x_init_internal_common(struct bnx2x *bp)
6157 {
6158         int i;
6159
6160         /* Zero this manually as its initialization is
6161            currently missing in the initTool */
6162         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6163                 REG_WR(bp, BAR_USTRORM_INTMEM +
6164                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6165         if (!CHIP_IS_E1x(bp)) {
6166                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6167                         CHIP_INT_MODE_IS_BC(bp) ?
6168                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6169         }
6170 }
6171
6172 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6173 {
6174         switch (load_code) {
6175         case FW_MSG_CODE_DRV_LOAD_COMMON:
6176         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6177                 bnx2x_init_internal_common(bp);
6178                 /* no break */
6179
6180         case FW_MSG_CODE_DRV_LOAD_PORT:
6181                 /* nothing to do */
6182                 /* no break */
6183
6184         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6185                 /* internal memory per function is
6186                    initialized inside bnx2x_pf_init */
6187                 break;
6188
6189         default:
6190                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6191                 break;
6192         }
6193 }
6194
6195 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6196 {
6197         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6198 }
6199
6200 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6201 {
6202         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6203 }
6204
6205 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6206 {
6207         if (CHIP_IS_E1x(fp->bp))
6208                 return BP_L_ID(fp->bp) + fp->index;
6209         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6210                 return bnx2x_fp_igu_sb_id(fp);
6211 }
6212
6213 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6214 {
6215         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6216         u8 cos;
6217         unsigned long q_type = 0;
6218         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6219         fp->rx_queue = fp_idx;
6220         fp->cid = fp_idx;
6221         fp->cl_id = bnx2x_fp_cl_id(fp);
6222         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6223         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6224         /* qZone id equals to FW (per path) client id */
6225         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6226
6227         /* init shortcut */
6228         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6229
6230         /* Setup SB indices */
6231         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6232
6233         /* Configure Queue State object */
6234         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6235         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6236
6237         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6238
6239         /* init tx data */
6240         for_each_cos_in_tx_queue(fp, cos) {
6241                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6242                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6243                                   FP_COS_TO_TXQ(fp, cos, bp),
6244                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6245                 cids[cos] = fp->txdata_ptr[cos]->cid;
6246         }
6247
6248         /* nothing more for vf to do here */
6249         if (IS_VF(bp))
6250                 return;
6251
6252         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6253                       fp->fw_sb_id, fp->igu_sb_id);
6254         bnx2x_update_fpsb_idx(fp);
6255         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6256                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6257                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6258
6259         /**
6260          * Configure classification DBs: Always enable Tx switching
6261          */
6262         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6263
6264         DP(NETIF_MSG_IFUP,
6265            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6266            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6267            fp->igu_sb_id);
6268 }
6269
6270 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6271 {
6272         int i;
6273
6274         for (i = 1; i <= NUM_TX_RINGS; i++) {
6275                 struct eth_tx_next_bd *tx_next_bd =
6276                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6277
6278                 tx_next_bd->addr_hi =
6279                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6280                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6281                 tx_next_bd->addr_lo =
6282                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6283                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6284         }
6285
6286         *txdata->tx_cons_sb = cpu_to_le16(0);
6287
6288         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6289         txdata->tx_db.data.zero_fill1 = 0;
6290         txdata->tx_db.data.prod = 0;
6291
6292         txdata->tx_pkt_prod = 0;
6293         txdata->tx_pkt_cons = 0;
6294         txdata->tx_bd_prod = 0;
6295         txdata->tx_bd_cons = 0;
6296         txdata->tx_pkt = 0;
6297 }
6298
6299 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6300 {
6301         int i;
6302
6303         for_each_tx_queue_cnic(bp, i)
6304                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6305 }
6306
6307 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6308 {
6309         int i;
6310         u8 cos;
6311
6312         for_each_eth_queue(bp, i)
6313                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6314                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6315 }
6316
6317 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6318 {
6319         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6320         unsigned long q_type = 0;
6321
6322         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6323         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6324                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6325         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6326         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6327         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6328         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6329         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6330                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6331                           fp);
6332
6333         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6334
6335         /* qZone id equals to FW (per path) client id */
6336         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6337         /* init shortcut */
6338         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6339                 bnx2x_rx_ustorm_prods_offset(fp);
6340
6341         /* Configure Queue State object */
6342         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6343         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6344
6345         /* No multi-CoS for FCoE L2 client */
6346         BUG_ON(fp->max_cos != 1);
6347
6348         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6349                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6350                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6351
6352         DP(NETIF_MSG_IFUP,
6353            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6354            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6355            fp->igu_sb_id);
6356 }
6357
6358 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6359 {
6360         if (!NO_FCOE(bp))
6361                 bnx2x_init_fcoe_fp(bp);
6362
6363         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6364                       BNX2X_VF_ID_INVALID, false,
6365                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6366
6367         /* ensure status block indices were read */
6368         rmb();
6369         bnx2x_init_rx_rings_cnic(bp);
6370         bnx2x_init_tx_rings_cnic(bp);
6371
6372         /* flush all */
6373         mb();
6374         mmiowb();
6375 }
6376
6377 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6378 {
6379         int i;
6380
6381         /* Setup NIC internals and enable interrupts */
6382         for_each_eth_queue(bp, i)
6383                 bnx2x_init_eth_fp(bp, i);
6384
6385         /* ensure status block indices were read */
6386         rmb();
6387         bnx2x_init_rx_rings(bp);
6388         bnx2x_init_tx_rings(bp);
6389
6390         if (IS_PF(bp)) {
6391                 /* Initialize MOD_ABS interrupts */
6392                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6393                                        bp->common.shmem_base,
6394                                        bp->common.shmem2_base, BP_PORT(bp));
6395
6396                 /* initialize the default status block and sp ring */
6397                 bnx2x_init_def_sb(bp);
6398                 bnx2x_update_dsb_idx(bp);
6399                 bnx2x_init_sp_ring(bp);
6400         } else {
6401                 bnx2x_memset_stats(bp);
6402         }
6403 }
6404
6405 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6406 {
6407         bnx2x_init_eq_ring(bp);
6408         bnx2x_init_internal(bp, load_code);
6409         bnx2x_pf_init(bp);
6410         bnx2x_stats_init(bp);
6411
6412         /* flush all before enabling interrupts */
6413         mb();
6414         mmiowb();
6415
6416         bnx2x_int_enable(bp);
6417
6418         /* Check for SPIO5 */
6419         bnx2x_attn_int_deasserted0(bp,
6420                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6421                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6422 }
6423
6424 /* gzip service functions */
6425 static int bnx2x_gunzip_init(struct bnx2x *bp)
6426 {
6427         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6428                                             &bp->gunzip_mapping, GFP_KERNEL);
6429         if (bp->gunzip_buf  == NULL)
6430                 goto gunzip_nomem1;
6431
6432         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6433         if (bp->strm  == NULL)
6434                 goto gunzip_nomem2;
6435
6436         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6437         if (bp->strm->workspace == NULL)
6438                 goto gunzip_nomem3;
6439
6440         return 0;
6441
6442 gunzip_nomem3:
6443         kfree(bp->strm);
6444         bp->strm = NULL;
6445
6446 gunzip_nomem2:
6447         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6448                           bp->gunzip_mapping);
6449         bp->gunzip_buf = NULL;
6450
6451 gunzip_nomem1:
6452         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6453         return -ENOMEM;
6454 }
6455
6456 static void bnx2x_gunzip_end(struct bnx2x *bp)
6457 {
6458         if (bp->strm) {
6459                 vfree(bp->strm->workspace);
6460                 kfree(bp->strm);
6461                 bp->strm = NULL;
6462         }
6463
6464         if (bp->gunzip_buf) {
6465                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6466                                   bp->gunzip_mapping);
6467                 bp->gunzip_buf = NULL;
6468         }
6469 }
6470
6471 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6472 {
6473         int n, rc;
6474
6475         /* check gzip header */
6476         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6477                 BNX2X_ERR("Bad gzip header\n");
6478                 return -EINVAL;
6479         }
6480
6481         n = 10;
6482
6483 #define FNAME                           0x8
6484
6485         if (zbuf[3] & FNAME)
6486                 while ((zbuf[n++] != 0) && (n < len));
6487
6488         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6489         bp->strm->avail_in = len - n;
6490         bp->strm->next_out = bp->gunzip_buf;
6491         bp->strm->avail_out = FW_BUF_SIZE;
6492
6493         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6494         if (rc != Z_OK)
6495                 return rc;
6496
6497         rc = zlib_inflate(bp->strm, Z_FINISH);
6498         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6499                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6500                            bp->strm->msg);
6501
6502         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6503         if (bp->gunzip_outlen & 0x3)
6504                 netdev_err(bp->dev,
6505                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6506                                 bp->gunzip_outlen);
6507         bp->gunzip_outlen >>= 2;
6508
6509         zlib_inflateEnd(bp->strm);
6510
6511         if (rc == Z_STREAM_END)
6512                 return 0;
6513
6514         return rc;
6515 }
6516
6517 /* nic load/unload */
6518
6519 /*
6520  * General service functions
6521  */
6522
6523 /* send a NIG loopback debug packet */
6524 static void bnx2x_lb_pckt(struct bnx2x *bp)
6525 {
6526         u32 wb_write[3];
6527
6528         /* Ethernet source and destination addresses */
6529         wb_write[0] = 0x55555555;
6530         wb_write[1] = 0x55555555;
6531         wb_write[2] = 0x20;             /* SOP */
6532         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6533
6534         /* NON-IP protocol */
6535         wb_write[0] = 0x09000000;
6536         wb_write[1] = 0x55555555;
6537         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6538         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6539 }
6540
6541 /* some of the internal memories
6542  * are not directly readable from the driver
6543  * to test them we send debug packets
6544  */
6545 static int bnx2x_int_mem_test(struct bnx2x *bp)
6546 {
6547         int factor;
6548         int count, i;
6549         u32 val = 0;
6550
6551         if (CHIP_REV_IS_FPGA(bp))
6552                 factor = 120;
6553         else if (CHIP_REV_IS_EMUL(bp))
6554                 factor = 200;
6555         else
6556                 factor = 1;
6557
6558         /* Disable inputs of parser neighbor blocks */
6559         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6560         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6561         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6562         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6563
6564         /*  Write 0 to parser credits for CFC search request */
6565         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6566
6567         /* send Ethernet packet */
6568         bnx2x_lb_pckt(bp);
6569
6570         /* TODO do i reset NIG statistic? */
6571         /* Wait until NIG register shows 1 packet of size 0x10 */
6572         count = 1000 * factor;
6573         while (count) {
6574
6575                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6576                 val = *bnx2x_sp(bp, wb_data[0]);
6577                 if (val == 0x10)
6578                         break;
6579
6580                 usleep_range(10000, 20000);
6581                 count--;
6582         }
6583         if (val != 0x10) {
6584                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6585                 return -1;
6586         }
6587
6588         /* Wait until PRS register shows 1 packet */
6589         count = 1000 * factor;
6590         while (count) {
6591                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6592                 if (val == 1)
6593                         break;
6594
6595                 usleep_range(10000, 20000);
6596                 count--;
6597         }
6598         if (val != 0x1) {
6599                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6600                 return -2;
6601         }
6602
6603         /* Reset and init BRB, PRS */
6604         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6605         msleep(50);
6606         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6607         msleep(50);
6608         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6609         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6610
6611         DP(NETIF_MSG_HW, "part2\n");
6612
6613         /* Disable inputs of parser neighbor blocks */
6614         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6615         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6616         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6617         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6618
6619         /* Write 0 to parser credits for CFC search request */
6620         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6621
6622         /* send 10 Ethernet packets */
6623         for (i = 0; i < 10; i++)
6624                 bnx2x_lb_pckt(bp);
6625
6626         /* Wait until NIG register shows 10 + 1
6627            packets of size 11*0x10 = 0xb0 */
6628         count = 1000 * factor;
6629         while (count) {
6630
6631                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6632                 val = *bnx2x_sp(bp, wb_data[0]);
6633                 if (val == 0xb0)
6634                         break;
6635
6636                 usleep_range(10000, 20000);
6637                 count--;
6638         }
6639         if (val != 0xb0) {
6640                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6641                 return -3;
6642         }
6643
6644         /* Wait until PRS register shows 2 packets */
6645         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6646         if (val != 2)
6647                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6648
6649         /* Write 1 to parser credits for CFC search request */
6650         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6651
6652         /* Wait until PRS register shows 3 packets */
6653         msleep(10 * factor);
6654         /* Wait until NIG register shows 1 packet of size 0x10 */
6655         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6656         if (val != 3)
6657                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6658
6659         /* clear NIG EOP FIFO */
6660         for (i = 0; i < 11; i++)
6661                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6662         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6663         if (val != 1) {
6664                 BNX2X_ERR("clear of NIG failed\n");
6665                 return -4;
6666         }
6667
6668         /* Reset and init BRB, PRS, NIG */
6669         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6670         msleep(50);
6671         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6672         msleep(50);
6673         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6674         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6675         if (!CNIC_SUPPORT(bp))
6676                 /* set NIC mode */
6677                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6678
6679         /* Enable inputs of parser neighbor blocks */
6680         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6681         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6682         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6683         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6684
6685         DP(NETIF_MSG_HW, "done\n");
6686
6687         return 0; /* OK */
6688 }
6689
6690 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6691 {
6692         u32 val;
6693
6694         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6695         if (!CHIP_IS_E1x(bp))
6696                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6697         else
6698                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6699         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6700         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6701         /*
6702          * mask read length error interrupts in brb for parser
6703          * (parsing unit and 'checksum and crc' unit)
6704          * these errors are legal (PU reads fixed length and CAC can cause
6705          * read length error on truncated packets)
6706          */
6707         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6708         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6709         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6710         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6711         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6712         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6713 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6714 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6715         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6716         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6717         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6718 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6719 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6720         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6721         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6722         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6723         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6724 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6725 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6726
6727         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6728                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6729                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6730         if (!CHIP_IS_E1x(bp))
6731                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6732                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6733         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6734
6735         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6736         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6737         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6738 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6739
6740         if (!CHIP_IS_E1x(bp))
6741                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6742                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6743
6744         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6745         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6746 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6747         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6748 }
6749
6750 static void bnx2x_reset_common(struct bnx2x *bp)
6751 {
6752         u32 val = 0x1400;
6753
6754         /* reset_common */
6755         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6756                0xd3ffff7f);
6757
6758         if (CHIP_IS_E3(bp)) {
6759                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6760                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6761         }
6762
6763         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6764 }
6765
6766 static void bnx2x_setup_dmae(struct bnx2x *bp)
6767 {
6768         bp->dmae_ready = 0;
6769         spin_lock_init(&bp->dmae_lock);
6770 }
6771
6772 static void bnx2x_init_pxp(struct bnx2x *bp)
6773 {
6774         u16 devctl;
6775         int r_order, w_order;
6776
6777         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6778         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6779         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6780         if (bp->mrrs == -1)
6781                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6782         else {
6783                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6784                 r_order = bp->mrrs;
6785         }
6786
6787         bnx2x_init_pxp_arb(bp, r_order, w_order);
6788 }
6789
6790 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6791 {
6792         int is_required;
6793         u32 val;
6794         int port;
6795
6796         if (BP_NOMCP(bp))
6797                 return;
6798
6799         is_required = 0;
6800         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6801               SHARED_HW_CFG_FAN_FAILURE_MASK;
6802
6803         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6804                 is_required = 1;
6805
6806         /*
6807          * The fan failure mechanism is usually related to the PHY type since
6808          * the power consumption of the board is affected by the PHY. Currently,
6809          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6810          */
6811         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6812                 for (port = PORT_0; port < PORT_MAX; port++) {
6813                         is_required |=
6814                                 bnx2x_fan_failure_det_req(
6815                                         bp,
6816                                         bp->common.shmem_base,
6817                                         bp->common.shmem2_base,
6818                                         port);
6819                 }
6820
6821         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6822
6823         if (is_required == 0)
6824                 return;
6825
6826         /* Fan failure is indicated by SPIO 5 */
6827         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6828
6829         /* set to active low mode */
6830         val = REG_RD(bp, MISC_REG_SPIO_INT);
6831         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6832         REG_WR(bp, MISC_REG_SPIO_INT, val);
6833
6834         /* enable interrupt to signal the IGU */
6835         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6836         val |= MISC_SPIO_SPIO5;
6837         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6838 }
6839
6840 void bnx2x_pf_disable(struct bnx2x *bp)
6841 {
6842         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6843         val &= ~IGU_PF_CONF_FUNC_EN;
6844
6845         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6846         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6847         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6848 }
6849
6850 static void bnx2x__common_init_phy(struct bnx2x *bp)
6851 {
6852         u32 shmem_base[2], shmem2_base[2];
6853         /* Avoid common init in case MFW supports LFA */
6854         if (SHMEM2_RD(bp, size) >
6855             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6856                 return;
6857         shmem_base[0] =  bp->common.shmem_base;
6858         shmem2_base[0] = bp->common.shmem2_base;
6859         if (!CHIP_IS_E1x(bp)) {
6860                 shmem_base[1] =
6861                         SHMEM2_RD(bp, other_shmem_base_addr);
6862                 shmem2_base[1] =
6863                         SHMEM2_RD(bp, other_shmem2_base_addr);
6864         }
6865         bnx2x_acquire_phy_lock(bp);
6866         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6867                               bp->common.chip_id);
6868         bnx2x_release_phy_lock(bp);
6869 }
6870
6871 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6872 {
6873         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6874         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6875         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6876         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6877         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6878
6879         /* make sure this value is 0 */
6880         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6881
6882         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6883         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6884         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6885         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6886 }
6887
6888 static void bnx2x_set_endianity(struct bnx2x *bp)
6889 {
6890 #ifdef __BIG_ENDIAN
6891         bnx2x_config_endianity(bp, 1);
6892 #else
6893         bnx2x_config_endianity(bp, 0);
6894 #endif
6895 }
6896
6897 static void bnx2x_reset_endianity(struct bnx2x *bp)
6898 {
6899         bnx2x_config_endianity(bp, 0);
6900 }
6901
6902 /**
6903  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6904  *
6905  * @bp:         driver handle
6906  */
6907 static int bnx2x_init_hw_common(struct bnx2x *bp)
6908 {
6909         u32 val;
6910
6911         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6912
6913         /*
6914          * take the RESET lock to protect undi_unload flow from accessing
6915          * registers while we're resetting the chip
6916          */
6917         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6918
6919         bnx2x_reset_common(bp);
6920         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6921
6922         val = 0xfffc;
6923         if (CHIP_IS_E3(bp)) {
6924                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6925                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6926         }
6927         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6928
6929         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6930
6931         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6932
6933         if (!CHIP_IS_E1x(bp)) {
6934                 u8 abs_func_id;
6935
6936                 /**
6937                  * 4-port mode or 2-port mode we need to turn of master-enable
6938                  * for everyone, after that, turn it back on for self.
6939                  * so, we disregard multi-function or not, and always disable
6940                  * for all functions on the given path, this means 0,2,4,6 for
6941                  * path 0 and 1,3,5,7 for path 1
6942                  */
6943                 for (abs_func_id = BP_PATH(bp);
6944                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6945                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6946                                 REG_WR(bp,
6947                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6948                                     1);
6949                                 continue;
6950                         }
6951
6952                         bnx2x_pretend_func(bp, abs_func_id);
6953                         /* clear pf enable */
6954                         bnx2x_pf_disable(bp);
6955                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6956                 }
6957         }
6958
6959         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6960         if (CHIP_IS_E1(bp)) {
6961                 /* enable HW interrupt from PXP on USDM overflow
6962                    bit 16 on INT_MASK_0 */
6963                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6964         }
6965
6966         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6967         bnx2x_init_pxp(bp);
6968         bnx2x_set_endianity(bp);
6969         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6970
6971         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6972                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6973
6974         /* let the HW do it's magic ... */
6975         msleep(100);
6976         /* finish PXP init */
6977         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6978         if (val != 1) {
6979                 BNX2X_ERR("PXP2 CFG failed\n");
6980                 return -EBUSY;
6981         }
6982         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6983         if (val != 1) {
6984                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6985                 return -EBUSY;
6986         }
6987
6988         /* Timers bug workaround E2 only. We need to set the entire ILT to
6989          * have entries with value "0" and valid bit on.
6990          * This needs to be done by the first PF that is loaded in a path
6991          * (i.e. common phase)
6992          */
6993         if (!CHIP_IS_E1x(bp)) {
6994 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6995  * (i.e. vnic3) to start even if it is marked as "scan-off".
6996  * This occurs when a different function (func2,3) is being marked
6997  * as "scan-off". Real-life scenario for example: if a driver is being
6998  * load-unloaded while func6,7 are down. This will cause the timer to access
6999  * the ilt, translate to a logical address and send a request to read/write.
7000  * Since the ilt for the function that is down is not valid, this will cause
7001  * a translation error which is unrecoverable.
7002  * The Workaround is intended to make sure that when this happens nothing fatal
7003  * will occur. The workaround:
7004  *      1.  First PF driver which loads on a path will:
7005  *              a.  After taking the chip out of reset, by using pretend,
7006  *                  it will write "0" to the following registers of
7007  *                  the other vnics.
7008  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7009  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7010  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7011  *                  And for itself it will write '1' to
7012  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7013  *                  dmae-operations (writing to pram for example.)
7014  *                  note: can be done for only function 6,7 but cleaner this
7015  *                        way.
7016  *              b.  Write zero+valid to the entire ILT.
7017  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7018  *                  VNIC3 (of that port). The range allocated will be the
7019  *                  entire ILT. This is needed to prevent  ILT range error.
7020  *      2.  Any PF driver load flow:
7021  *              a.  ILT update with the physical addresses of the allocated
7022  *                  logical pages.
7023  *              b.  Wait 20msec. - note that this timeout is needed to make
7024  *                  sure there are no requests in one of the PXP internal
7025  *                  queues with "old" ILT addresses.
7026  *              c.  PF enable in the PGLC.
7027  *              d.  Clear the was_error of the PF in the PGLC. (could have
7028  *                  occurred while driver was down)
7029  *              e.  PF enable in the CFC (WEAK + STRONG)
7030  *              f.  Timers scan enable
7031  *      3.  PF driver unload flow:
7032  *              a.  Clear the Timers scan_en.
7033  *              b.  Polling for scan_on=0 for that PF.
7034  *              c.  Clear the PF enable bit in the PXP.
7035  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7036  *              e.  Write zero+valid to all ILT entries (The valid bit must
7037  *                  stay set)
7038  *              f.  If this is VNIC 3 of a port then also init
7039  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7040  *                  to the last entry in the ILT.
7041  *
7042  *      Notes:
7043  *      Currently the PF error in the PGLC is non recoverable.
7044  *      In the future the there will be a recovery routine for this error.
7045  *      Currently attention is masked.
7046  *      Having an MCP lock on the load/unload process does not guarantee that
7047  *      there is no Timer disable during Func6/7 enable. This is because the
7048  *      Timers scan is currently being cleared by the MCP on FLR.
7049  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7050  *      there is error before clearing it. But the flow above is simpler and
7051  *      more general.
7052  *      All ILT entries are written by zero+valid and not just PF6/7
7053  *      ILT entries since in the future the ILT entries allocation for
7054  *      PF-s might be dynamic.
7055  */
7056                 struct ilt_client_info ilt_cli;
7057                 struct bnx2x_ilt ilt;
7058                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7059                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7060
7061                 /* initialize dummy TM client */
7062                 ilt_cli.start = 0;
7063                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7064                 ilt_cli.client_num = ILT_CLIENT_TM;
7065
7066                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7067                  * Step 2: set the timers first/last ilt entry to point
7068                  * to the entire range to prevent ILT range error for 3rd/4th
7069                  * vnic (this code assumes existence of the vnic)
7070                  *
7071                  * both steps performed by call to bnx2x_ilt_client_init_op()
7072                  * with dummy TM client
7073                  *
7074                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7075                  * and his brother are split registers
7076                  */
7077                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7078                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7079                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7080
7081                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7082                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7083                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7084         }
7085
7086         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7087         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7088
7089         if (!CHIP_IS_E1x(bp)) {
7090                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7091                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7092                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7093
7094                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7095
7096                 /* let the HW do it's magic ... */
7097                 do {
7098                         msleep(200);
7099                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7100                 } while (factor-- && (val != 1));
7101
7102                 if (val != 1) {
7103                         BNX2X_ERR("ATC_INIT failed\n");
7104                         return -EBUSY;
7105                 }
7106         }
7107
7108         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7109
7110         bnx2x_iov_init_dmae(bp);
7111
7112         /* clean the DMAE memory */
7113         bp->dmae_ready = 1;
7114         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7115
7116         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7117
7118         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7119
7120         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7121
7122         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7123
7124         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7125         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7126         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7127         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7128
7129         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7130
7131         /* QM queues pointers table */
7132         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7133
7134         /* soft reset pulse */
7135         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7136         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7137
7138         if (CNIC_SUPPORT(bp))
7139                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7140
7141         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7142
7143         if (!CHIP_REV_IS_SLOW(bp))
7144                 /* enable hw interrupt from doorbell Q */
7145                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7146
7147         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7148
7149         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7150         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7151
7152         if (!CHIP_IS_E1(bp))
7153                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7154
7155         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7156                 if (IS_MF_AFEX(bp)) {
7157                         /* configure that VNTag and VLAN headers must be
7158                          * received in afex mode
7159                          */
7160                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7161                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7162                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7163                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7164                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7165                 } else {
7166                         /* Bit-map indicating which L2 hdrs may appear
7167                          * after the basic Ethernet header
7168                          */
7169                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7170                                bp->path_has_ovlan ? 7 : 6);
7171                 }
7172         }
7173
7174         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7175         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7176         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7177         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7178
7179         if (!CHIP_IS_E1x(bp)) {
7180                 /* reset VFC memories */
7181                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7182                            VFC_MEMORIES_RST_REG_CAM_RST |
7183                            VFC_MEMORIES_RST_REG_RAM_RST);
7184                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7185                            VFC_MEMORIES_RST_REG_CAM_RST |
7186                            VFC_MEMORIES_RST_REG_RAM_RST);
7187
7188                 msleep(20);
7189         }
7190
7191         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7192         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7193         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7194         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7195
7196         /* sync semi rtc */
7197         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7198                0x80000000);
7199         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7200                0x80000000);
7201
7202         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7203         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7204         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7205
7206         if (!CHIP_IS_E1x(bp)) {
7207                 if (IS_MF_AFEX(bp)) {
7208                         /* configure that VNTag and VLAN headers must be
7209                          * sent in afex mode
7210                          */
7211                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7212                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7213                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7214                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7215                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7216                 } else {
7217                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7218                                bp->path_has_ovlan ? 7 : 6);
7219                 }
7220         }
7221
7222         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7223
7224         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7225
7226         if (CNIC_SUPPORT(bp)) {
7227                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7228                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7229                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7230                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7231                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7232                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7233                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7234                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7235                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7236                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7237         }
7238         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7239
7240         if (sizeof(union cdu_context) != 1024)
7241                 /* we currently assume that a context is 1024 bytes */
7242                 dev_alert(&bp->pdev->dev,
7243                           "please adjust the size of cdu_context(%ld)\n",
7244                           (long)sizeof(union cdu_context));
7245
7246         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7247         val = (4 << 24) + (0 << 12) + 1024;
7248         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7249
7250         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7251         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7252         /* enable context validation interrupt from CFC */
7253         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7254
7255         /* set the thresholds to prevent CFC/CDU race */
7256         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7257
7258         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7259
7260         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7261                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7262
7263         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7264         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7265
7266         /* Reset PCIE errors for debug */
7267         REG_WR(bp, 0x2814, 0xffffffff);
7268         REG_WR(bp, 0x3820, 0xffffffff);
7269
7270         if (!CHIP_IS_E1x(bp)) {
7271                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7272                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7273                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7274                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7275                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7276                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7277                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7278                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7279                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7280                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7281                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7282         }
7283
7284         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7285         if (!CHIP_IS_E1(bp)) {
7286                 /* in E3 this done in per-port section */
7287                 if (!CHIP_IS_E3(bp))
7288                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7289         }
7290         if (CHIP_IS_E1H(bp))
7291                 /* not applicable for E2 (and above ...) */
7292                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7293
7294         if (CHIP_REV_IS_SLOW(bp))
7295                 msleep(200);
7296
7297         /* finish CFC init */
7298         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7299         if (val != 1) {
7300                 BNX2X_ERR("CFC LL_INIT failed\n");
7301                 return -EBUSY;
7302         }
7303         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7304         if (val != 1) {
7305                 BNX2X_ERR("CFC AC_INIT failed\n");
7306                 return -EBUSY;
7307         }
7308         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7309         if (val != 1) {
7310                 BNX2X_ERR("CFC CAM_INIT failed\n");
7311                 return -EBUSY;
7312         }
7313         REG_WR(bp, CFC_REG_DEBUG0, 0);
7314
7315         if (CHIP_IS_E1(bp)) {
7316                 /* read NIG statistic
7317                    to see if this is our first up since powerup */
7318                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7319                 val = *bnx2x_sp(bp, wb_data[0]);
7320
7321                 /* do internal memory self test */
7322                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7323                         BNX2X_ERR("internal mem self test failed\n");
7324                         return -EBUSY;
7325                 }
7326         }
7327
7328         bnx2x_setup_fan_failure_detection(bp);
7329
7330         /* clear PXP2 attentions */
7331         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7332
7333         bnx2x_enable_blocks_attention(bp);
7334         bnx2x_enable_blocks_parity(bp);
7335
7336         if (!BP_NOMCP(bp)) {
7337                 if (CHIP_IS_E1x(bp))
7338                         bnx2x__common_init_phy(bp);
7339         } else
7340                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7341
7342         return 0;
7343 }
7344
7345 /**
7346  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7347  *
7348  * @bp:         driver handle
7349  */
7350 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7351 {
7352         int rc = bnx2x_init_hw_common(bp);
7353
7354         if (rc)
7355                 return rc;
7356
7357         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7358         if (!BP_NOMCP(bp))
7359                 bnx2x__common_init_phy(bp);
7360
7361         return 0;
7362 }
7363
7364 static int bnx2x_init_hw_port(struct bnx2x *bp)
7365 {
7366         int port = BP_PORT(bp);
7367         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7368         u32 low, high;
7369         u32 val, reg;
7370
7371         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7372
7373         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7374
7375         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7376         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7377         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7378
7379         /* Timers bug workaround: disables the pf_master bit in pglue at
7380          * common phase, we need to enable it here before any dmae access are
7381          * attempted. Therefore we manually added the enable-master to the
7382          * port phase (it also happens in the function phase)
7383          */
7384         if (!CHIP_IS_E1x(bp))
7385                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7386
7387         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7388         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7389         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7390         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7391
7392         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7393         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7394         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7395         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7396
7397         /* QM cid (connection) count */
7398         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7399
7400         if (CNIC_SUPPORT(bp)) {
7401                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7402                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7403                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7404         }
7405
7406         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7407
7408         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7409
7410         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7411
7412                 if (IS_MF(bp))
7413                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7414                 else if (bp->dev->mtu > 4096) {
7415                         if (bp->flags & ONE_PORT_FLAG)
7416                                 low = 160;
7417                         else {
7418                                 val = bp->dev->mtu;
7419                                 /* (24*1024 + val*4)/256 */
7420                                 low = 96 + (val/64) +
7421                                                 ((val % 64) ? 1 : 0);
7422                         }
7423                 } else
7424                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7425                 high = low + 56;        /* 14*1024/256 */
7426                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7427                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7428         }
7429
7430         if (CHIP_MODE_IS_4_PORT(bp))
7431                 REG_WR(bp, (BP_PORT(bp) ?
7432                             BRB1_REG_MAC_GUARANTIED_1 :
7433                             BRB1_REG_MAC_GUARANTIED_0), 40);
7434
7435         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7436         if (CHIP_IS_E3B0(bp)) {
7437                 if (IS_MF_AFEX(bp)) {
7438                         /* configure headers for AFEX mode */
7439                         REG_WR(bp, BP_PORT(bp) ?
7440                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7441                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7442                         REG_WR(bp, BP_PORT(bp) ?
7443                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7444                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7445                         REG_WR(bp, BP_PORT(bp) ?
7446                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7447                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7448                 } else {
7449                         /* Ovlan exists only if we are in multi-function +
7450                          * switch-dependent mode, in switch-independent there
7451                          * is no ovlan headers
7452                          */
7453                         REG_WR(bp, BP_PORT(bp) ?
7454                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7455                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7456                                (bp->path_has_ovlan ? 7 : 6));
7457                 }
7458         }
7459
7460         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7461         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7462         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7463         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7464
7465         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7466         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7467         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7468         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7469
7470         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7471         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7472
7473         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7474
7475         if (CHIP_IS_E1x(bp)) {
7476                 /* configure PBF to work without PAUSE mtu 9000 */
7477                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7478
7479                 /* update threshold */
7480                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7481                 /* update init credit */
7482                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7483
7484                 /* probe changes */
7485                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7486                 udelay(50);
7487                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7488         }
7489
7490         if (CNIC_SUPPORT(bp))
7491                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7492
7493         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7494         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7495
7496         if (CHIP_IS_E1(bp)) {
7497                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7498                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7499         }
7500         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7501
7502         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7503
7504         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7505         /* init aeu_mask_attn_func_0/1:
7506          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7507          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7508          *             bits 4-7 are used for "per vn group attention" */
7509         val = IS_MF(bp) ? 0xF7 : 0x7;
7510         /* Enable DCBX attention for all but E1 */
7511         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7512         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7513
7514         /* SCPAD_PARITY should NOT trigger close the gates */
7515         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7516         REG_WR(bp, reg,
7517                REG_RD(bp, reg) &
7518                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7519
7520         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7521         REG_WR(bp, reg,
7522                REG_RD(bp, reg) &
7523                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7524
7525         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7526
7527         if (!CHIP_IS_E1x(bp)) {
7528                 /* Bit-map indicating which L2 hdrs may appear after the
7529                  * basic Ethernet header
7530                  */
7531                 if (IS_MF_AFEX(bp))
7532                         REG_WR(bp, BP_PORT(bp) ?
7533                                NIG_REG_P1_HDRS_AFTER_BASIC :
7534                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7535                 else
7536                         REG_WR(bp, BP_PORT(bp) ?
7537                                NIG_REG_P1_HDRS_AFTER_BASIC :
7538                                NIG_REG_P0_HDRS_AFTER_BASIC,
7539                                IS_MF_SD(bp) ? 7 : 6);
7540
7541                 if (CHIP_IS_E3(bp))
7542                         REG_WR(bp, BP_PORT(bp) ?
7543                                    NIG_REG_LLH1_MF_MODE :
7544                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7545         }
7546         if (!CHIP_IS_E3(bp))
7547                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7548
7549         if (!CHIP_IS_E1(bp)) {
7550                 /* 0x2 disable mf_ov, 0x1 enable */
7551                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7552                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7553
7554                 if (!CHIP_IS_E1x(bp)) {
7555                         val = 0;
7556                         switch (bp->mf_mode) {
7557                         case MULTI_FUNCTION_SD:
7558                                 val = 1;
7559                                 break;
7560                         case MULTI_FUNCTION_SI:
7561                         case MULTI_FUNCTION_AFEX:
7562                                 val = 2;
7563                                 break;
7564                         }
7565
7566                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7567                                                   NIG_REG_LLH0_CLS_TYPE), val);
7568                 }
7569                 {
7570                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7571                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7572                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7573                 }
7574         }
7575
7576         /* If SPIO5 is set to generate interrupts, enable it for this port */
7577         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7578         if (val & MISC_SPIO_SPIO5) {
7579                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7580                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7581                 val = REG_RD(bp, reg_addr);
7582                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7583                 REG_WR(bp, reg_addr, val);
7584         }
7585
7586         return 0;
7587 }
7588
7589 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7590 {
7591         int reg;
7592         u32 wb_write[2];
7593
7594         if (CHIP_IS_E1(bp))
7595                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7596         else
7597                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7598
7599         wb_write[0] = ONCHIP_ADDR1(addr);
7600         wb_write[1] = ONCHIP_ADDR2(addr);
7601         REG_WR_DMAE(bp, reg, wb_write, 2);
7602 }
7603
7604 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7605 {
7606         u32 data, ctl, cnt = 100;
7607         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7608         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7609         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7610         u32 sb_bit =  1 << (idu_sb_id%32);
7611         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7612         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7613
7614         /* Not supported in BC mode */
7615         if (CHIP_INT_MODE_IS_BC(bp))
7616                 return;
7617
7618         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7619                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7620                 IGU_REGULAR_CLEANUP_SET                         |
7621                 IGU_REGULAR_BCLEANUP;
7622
7623         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7624               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7625               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7626
7627         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7628                          data, igu_addr_data);
7629         REG_WR(bp, igu_addr_data, data);
7630         mmiowb();
7631         barrier();
7632         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7633                           ctl, igu_addr_ctl);
7634         REG_WR(bp, igu_addr_ctl, ctl);
7635         mmiowb();
7636         barrier();
7637
7638         /* wait for clean up to finish */
7639         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7640                 msleep(20);
7641
7642         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7643                 DP(NETIF_MSG_HW,
7644                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7645                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7646         }
7647 }
7648
7649 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7650 {
7651         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7652 }
7653
7654 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7655 {
7656         u32 i, base = FUNC_ILT_BASE(func);
7657         for (i = base; i < base + ILT_PER_FUNC; i++)
7658                 bnx2x_ilt_wr(bp, i, 0);
7659 }
7660
7661 static void bnx2x_init_searcher(struct bnx2x *bp)
7662 {
7663         int port = BP_PORT(bp);
7664         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7665         /* T1 hash bits value determines the T1 number of entries */
7666         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7667 }
7668
7669 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7670 {
7671         int rc;
7672         struct bnx2x_func_state_params func_params = {NULL};
7673         struct bnx2x_func_switch_update_params *switch_update_params =
7674                 &func_params.params.switch_update;
7675
7676         /* Prepare parameters for function state transitions */
7677         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7678         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7679
7680         func_params.f_obj = &bp->func_obj;
7681         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7682
7683         /* Function parameters */
7684         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7685                   &switch_update_params->changes);
7686         if (suspend)
7687                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7688                           &switch_update_params->changes);
7689
7690         rc = bnx2x_func_state_change(bp, &func_params);
7691
7692         return rc;
7693 }
7694
7695 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7696 {
7697         int rc, i, port = BP_PORT(bp);
7698         int vlan_en = 0, mac_en[NUM_MACS];
7699
7700         /* Close input from network */
7701         if (bp->mf_mode == SINGLE_FUNCTION) {
7702                 bnx2x_set_rx_filter(&bp->link_params, 0);
7703         } else {
7704                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7705                                    NIG_REG_LLH0_FUNC_EN);
7706                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7707                           NIG_REG_LLH0_FUNC_EN, 0);
7708                 for (i = 0; i < NUM_MACS; i++) {
7709                         mac_en[i] = REG_RD(bp, port ?
7710                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7711                                               4 * i) :
7712                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7713                                               4 * i));
7714                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7715                                               4 * i) :
7716                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7717                 }
7718         }
7719
7720         /* Close BMC to host */
7721         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7722                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7723
7724         /* Suspend Tx switching to the PF. Completion of this ramrod
7725          * further guarantees that all the packets of that PF / child
7726          * VFs in BRB were processed by the Parser, so it is safe to
7727          * change the NIC_MODE register.
7728          */
7729         rc = bnx2x_func_switch_update(bp, 1);
7730         if (rc) {
7731                 BNX2X_ERR("Can't suspend tx-switching!\n");
7732                 return rc;
7733         }
7734
7735         /* Change NIC_MODE register */
7736         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7737
7738         /* Open input from network */
7739         if (bp->mf_mode == SINGLE_FUNCTION) {
7740                 bnx2x_set_rx_filter(&bp->link_params, 1);
7741         } else {
7742                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7743                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7744                 for (i = 0; i < NUM_MACS; i++) {
7745                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7746                                               4 * i) :
7747                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7748                                   mac_en[i]);
7749                 }
7750         }
7751
7752         /* Enable BMC to host */
7753         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7754                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7755
7756         /* Resume Tx switching to the PF */
7757         rc = bnx2x_func_switch_update(bp, 0);
7758         if (rc) {
7759                 BNX2X_ERR("Can't resume tx-switching!\n");
7760                 return rc;
7761         }
7762
7763         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7764         return 0;
7765 }
7766
7767 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7768 {
7769         int rc;
7770
7771         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7772
7773         if (CONFIGURE_NIC_MODE(bp)) {
7774                 /* Configure searcher as part of function hw init */
7775                 bnx2x_init_searcher(bp);
7776
7777                 /* Reset NIC mode */
7778                 rc = bnx2x_reset_nic_mode(bp);
7779                 if (rc)
7780                         BNX2X_ERR("Can't change NIC mode!\n");
7781                 return rc;
7782         }
7783
7784         return 0;
7785 }
7786
7787 static int bnx2x_init_hw_func(struct bnx2x *bp)
7788 {
7789         int port = BP_PORT(bp);
7790         int func = BP_FUNC(bp);
7791         int init_phase = PHASE_PF0 + func;
7792         struct bnx2x_ilt *ilt = BP_ILT(bp);
7793         u16 cdu_ilt_start;
7794         u32 addr, val;
7795         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7796         int i, main_mem_width, rc;
7797
7798         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7799
7800         /* FLR cleanup - hmmm */
7801         if (!CHIP_IS_E1x(bp)) {
7802                 rc = bnx2x_pf_flr_clnup(bp);
7803                 if (rc) {
7804                         bnx2x_fw_dump(bp);
7805                         return rc;
7806                 }
7807         }
7808
7809         /* set MSI reconfigure capability */
7810         if (bp->common.int_block == INT_BLOCK_HC) {
7811                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7812                 val = REG_RD(bp, addr);
7813                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7814                 REG_WR(bp, addr, val);
7815         }
7816
7817         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7818         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7819
7820         ilt = BP_ILT(bp);
7821         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7822
7823         if (IS_SRIOV(bp))
7824                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7825         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7826
7827         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7828          * those of the VFs, so start line should be reset
7829          */
7830         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7831         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7832                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7833                 ilt->lines[cdu_ilt_start + i].page_mapping =
7834                         bp->context[i].cxt_mapping;
7835                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7836         }
7837
7838         bnx2x_ilt_init_op(bp, INITOP_SET);
7839
7840         if (!CONFIGURE_NIC_MODE(bp)) {
7841                 bnx2x_init_searcher(bp);
7842                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7843                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7844         } else {
7845                 /* Set NIC mode */
7846                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7847                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7848         }
7849
7850         if (!CHIP_IS_E1x(bp)) {
7851                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7852
7853                 /* Turn on a single ISR mode in IGU if driver is going to use
7854                  * INT#x or MSI
7855                  */
7856                 if (!(bp->flags & USING_MSIX_FLAG))
7857                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7858                 /*
7859                  * Timers workaround bug: function init part.
7860                  * Need to wait 20msec after initializing ILT,
7861                  * needed to make sure there are no requests in
7862                  * one of the PXP internal queues with "old" ILT addresses
7863                  */
7864                 msleep(20);
7865                 /*
7866                  * Master enable - Due to WB DMAE writes performed before this
7867                  * register is re-initialized as part of the regular function
7868                  * init
7869                  */
7870                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7871                 /* Enable the function in IGU */
7872                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7873         }
7874
7875         bp->dmae_ready = 1;
7876
7877         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7878
7879         if (!CHIP_IS_E1x(bp))
7880                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7881
7882         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7883         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7884         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7885         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7886         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7887         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7888         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7889         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7890         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7891         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7892         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7893         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7894         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7895
7896         if (!CHIP_IS_E1x(bp))
7897                 REG_WR(bp, QM_REG_PF_EN, 1);
7898
7899         if (!CHIP_IS_E1x(bp)) {
7900                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7901                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7902                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7903                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7904         }
7905         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7906
7907         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7908         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7909         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7910
7911         bnx2x_iov_init_dq(bp);
7912
7913         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7914         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7915         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7916         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7917         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7918         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7919         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7920         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7921         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7922         if (!CHIP_IS_E1x(bp))
7923                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7924
7925         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7926
7927         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7928
7929         if (!CHIP_IS_E1x(bp))
7930                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7931
7932         if (IS_MF(bp)) {
7933                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7934                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7935         }
7936
7937         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7938
7939         /* HC init per function */
7940         if (bp->common.int_block == INT_BLOCK_HC) {
7941                 if (CHIP_IS_E1H(bp)) {
7942                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7943
7944                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7945                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7946                 }
7947                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7948
7949         } else {
7950                 int num_segs, sb_idx, prod_offset;
7951
7952                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7953
7954                 if (!CHIP_IS_E1x(bp)) {
7955                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7956                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7957                 }
7958
7959                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7960
7961                 if (!CHIP_IS_E1x(bp)) {
7962                         int dsb_idx = 0;
7963                         /**
7964                          * Producer memory:
7965                          * E2 mode: address 0-135 match to the mapping memory;
7966                          * 136 - PF0 default prod; 137 - PF1 default prod;
7967                          * 138 - PF2 default prod; 139 - PF3 default prod;
7968                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7969                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7970                          * 144-147 reserved.
7971                          *
7972                          * E1.5 mode - In backward compatible mode;
7973                          * for non default SB; each even line in the memory
7974                          * holds the U producer and each odd line hold
7975                          * the C producer. The first 128 producers are for
7976                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7977                          * producers are for the DSB for each PF.
7978                          * Each PF has five segments: (the order inside each
7979                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7980                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7981                          * 144-147 attn prods;
7982                          */
7983                         /* non-default-status-blocks */
7984                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7985                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7986                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7987                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7988                                         num_segs;
7989
7990                                 for (i = 0; i < num_segs; i++) {
7991                                         addr = IGU_REG_PROD_CONS_MEMORY +
7992                                                         (prod_offset + i) * 4;
7993                                         REG_WR(bp, addr, 0);
7994                                 }
7995                                 /* send consumer update with value 0 */
7996                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7997                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7998                                 bnx2x_igu_clear_sb(bp,
7999                                                    bp->igu_base_sb + sb_idx);
8000                         }
8001
8002                         /* default-status-blocks */
8003                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8004                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8005
8006                         if (CHIP_MODE_IS_4_PORT(bp))
8007                                 dsb_idx = BP_FUNC(bp);
8008                         else
8009                                 dsb_idx = BP_VN(bp);
8010
8011                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8012                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8013                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8014
8015                         /*
8016                          * igu prods come in chunks of E1HVN_MAX (4) -
8017                          * does not matters what is the current chip mode
8018                          */
8019                         for (i = 0; i < (num_segs * E1HVN_MAX);
8020                              i += E1HVN_MAX) {
8021                                 addr = IGU_REG_PROD_CONS_MEMORY +
8022                                                         (prod_offset + i)*4;
8023                                 REG_WR(bp, addr, 0);
8024                         }
8025                         /* send consumer update with 0 */
8026                         if (CHIP_INT_MODE_IS_BC(bp)) {
8027                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8028                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8029                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8030                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8031                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8032                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8033                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8034                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8035                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8036                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8037                         } else {
8038                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8039                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8040                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8041                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8042                         }
8043                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8044
8045                         /* !!! These should become driver const once
8046                            rf-tool supports split-68 const */
8047                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8048                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8049                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8050                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8051                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8052                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8053                 }
8054         }
8055
8056         /* Reset PCIE errors for debug */
8057         REG_WR(bp, 0x2114, 0xffffffff);
8058         REG_WR(bp, 0x2120, 0xffffffff);
8059
8060         if (CHIP_IS_E1x(bp)) {
8061                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8062                 main_mem_base = HC_REG_MAIN_MEMORY +
8063                                 BP_PORT(bp) * (main_mem_size * 4);
8064                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8065                 main_mem_width = 8;
8066
8067                 val = REG_RD(bp, main_mem_prty_clr);
8068                 if (val)
8069                         DP(NETIF_MSG_HW,
8070                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8071                            val);
8072
8073                 /* Clear "false" parity errors in MSI-X table */
8074                 for (i = main_mem_base;
8075                      i < main_mem_base + main_mem_size * 4;
8076                      i += main_mem_width) {
8077                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8078                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8079                                          i, main_mem_width / 4);
8080                 }
8081                 /* Clear HC parity attention */
8082                 REG_RD(bp, main_mem_prty_clr);
8083         }
8084
8085 #ifdef BNX2X_STOP_ON_ERROR
8086         /* Enable STORMs SP logging */
8087         REG_WR8(bp, BAR_USTRORM_INTMEM +
8088                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8089         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8090                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8091         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8092                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8093         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8094                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8095 #endif
8096
8097         bnx2x_phy_probe(&bp->link_params);
8098
8099         return 0;
8100 }
8101
8102 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8103 {
8104         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8105
8106         if (!CHIP_IS_E1x(bp))
8107                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8108                                sizeof(struct host_hc_status_block_e2));
8109         else
8110                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8111                                sizeof(struct host_hc_status_block_e1x));
8112
8113         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8114 }
8115
8116 void bnx2x_free_mem(struct bnx2x *bp)
8117 {
8118         int i;
8119
8120         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8121                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8122
8123         if (IS_VF(bp))
8124                 return;
8125
8126         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8127                        sizeof(struct host_sp_status_block));
8128
8129         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8130                        sizeof(struct bnx2x_slowpath));
8131
8132         for (i = 0; i < L2_ILT_LINES(bp); i++)
8133                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8134                                bp->context[i].size);
8135         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8136
8137         BNX2X_FREE(bp->ilt->lines);
8138
8139         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8140
8141         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8142                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8143
8144         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8145
8146         bnx2x_iov_free_mem(bp);
8147 }
8148
8149 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8150 {
8151         if (!CHIP_IS_E1x(bp)) {
8152                 /* size = the status block + ramrod buffers */
8153                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8154                                                     sizeof(struct host_hc_status_block_e2));
8155                 if (!bp->cnic_sb.e2_sb)
8156                         goto alloc_mem_err;
8157         } else {
8158                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8159                                                      sizeof(struct host_hc_status_block_e1x));
8160                 if (!bp->cnic_sb.e1x_sb)
8161                         goto alloc_mem_err;
8162         }
8163
8164         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8165                 /* allocate searcher T2 table, as it wasn't allocated before */
8166                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8167                 if (!bp->t2)
8168                         goto alloc_mem_err;
8169         }
8170
8171         /* write address to which L5 should insert its values */
8172         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8173                 &bp->slowpath->drv_info_to_mcp;
8174
8175         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8176                 goto alloc_mem_err;
8177
8178         return 0;
8179
8180 alloc_mem_err:
8181         bnx2x_free_mem_cnic(bp);
8182         BNX2X_ERR("Can't allocate memory\n");
8183         return -ENOMEM;
8184 }
8185
8186 int bnx2x_alloc_mem(struct bnx2x *bp)
8187 {
8188         int i, allocated, context_size;
8189
8190         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8191                 /* allocate searcher T2 table */
8192                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8193                 if (!bp->t2)
8194                         goto alloc_mem_err;
8195         }
8196
8197         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8198                                              sizeof(struct host_sp_status_block));
8199         if (!bp->def_status_blk)
8200                 goto alloc_mem_err;
8201
8202         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8203                                        sizeof(struct bnx2x_slowpath));
8204         if (!bp->slowpath)
8205                 goto alloc_mem_err;
8206
8207         /* Allocate memory for CDU context:
8208          * This memory is allocated separately and not in the generic ILT
8209          * functions because CDU differs in few aspects:
8210          * 1. There are multiple entities allocating memory for context -
8211          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8212          * its own ILT lines.
8213          * 2. Since CDU page-size is not a single 4KB page (which is the case
8214          * for the other ILT clients), to be efficient we want to support
8215          * allocation of sub-page-size in the last entry.
8216          * 3. Context pointers are used by the driver to pass to FW / update
8217          * the context (for the other ILT clients the pointers are used just to
8218          * free the memory during unload).
8219          */
8220         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8221
8222         for (i = 0, allocated = 0; allocated < context_size; i++) {
8223                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8224                                           (context_size - allocated));
8225                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8226                                                       bp->context[i].size);
8227                 if (!bp->context[i].vcxt)
8228                         goto alloc_mem_err;
8229                 allocated += bp->context[i].size;
8230         }
8231         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8232                                  GFP_KERNEL);
8233         if (!bp->ilt->lines)
8234                 goto alloc_mem_err;
8235
8236         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8237                 goto alloc_mem_err;
8238
8239         if (bnx2x_iov_alloc_mem(bp))
8240                 goto alloc_mem_err;
8241
8242         /* Slow path ring */
8243         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8244         if (!bp->spq)
8245                 goto alloc_mem_err;
8246
8247         /* EQ */
8248         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8249                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8250         if (!bp->eq_ring)
8251                 goto alloc_mem_err;
8252
8253         return 0;
8254
8255 alloc_mem_err:
8256         bnx2x_free_mem(bp);
8257         BNX2X_ERR("Can't allocate memory\n");
8258         return -ENOMEM;
8259 }
8260
8261 /*
8262  * Init service functions
8263  */
8264
8265 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8266                       struct bnx2x_vlan_mac_obj *obj, bool set,
8267                       int mac_type, unsigned long *ramrod_flags)
8268 {
8269         int rc;
8270         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8271
8272         memset(&ramrod_param, 0, sizeof(ramrod_param));
8273
8274         /* Fill general parameters */
8275         ramrod_param.vlan_mac_obj = obj;
8276         ramrod_param.ramrod_flags = *ramrod_flags;
8277
8278         /* Fill a user request section if needed */
8279         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8280                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8281
8282                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8283
8284                 /* Set the command: ADD or DEL */
8285                 if (set)
8286                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8287                 else
8288                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8289         }
8290
8291         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8292
8293         if (rc == -EEXIST) {
8294                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8295                 /* do not treat adding same MAC as error */
8296                 rc = 0;
8297         } else if (rc < 0)
8298                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8299
8300         return rc;
8301 }
8302
8303 int bnx2x_del_all_macs(struct bnx2x *bp,
8304                        struct bnx2x_vlan_mac_obj *mac_obj,
8305                        int mac_type, bool wait_for_comp)
8306 {
8307         int rc;
8308         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8309
8310         /* Wait for completion of requested */
8311         if (wait_for_comp)
8312                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8313
8314         /* Set the mac type of addresses we want to clear */
8315         __set_bit(mac_type, &vlan_mac_flags);
8316
8317         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8318         if (rc < 0)
8319                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8320
8321         return rc;
8322 }
8323
8324 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8325 {
8326         if (is_zero_ether_addr(bp->dev->dev_addr) &&
8327             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8328                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8329                    "Ignoring Zero MAC for STORAGE SD mode\n");
8330                 return 0;
8331         }
8332
8333         if (IS_PF(bp)) {
8334                 unsigned long ramrod_flags = 0;
8335
8336                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8337                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8338                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8339                                          &bp->sp_objs->mac_obj, set,
8340                                          BNX2X_ETH_MAC, &ramrod_flags);
8341         } else { /* vf */
8342                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8343                                              bp->fp->index, true);
8344         }
8345 }
8346
8347 int bnx2x_setup_leading(struct bnx2x *bp)
8348 {
8349         if (IS_PF(bp))
8350                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8351         else /* VF */
8352                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8353 }
8354
8355 /**
8356  * bnx2x_set_int_mode - configure interrupt mode
8357  *
8358  * @bp:         driver handle
8359  *
8360  * In case of MSI-X it will also try to enable MSI-X.
8361  */
8362 int bnx2x_set_int_mode(struct bnx2x *bp)
8363 {
8364         int rc = 0;
8365
8366         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8367                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8368                 return -EINVAL;
8369         }
8370
8371         switch (int_mode) {
8372         case BNX2X_INT_MODE_MSIX:
8373                 /* attempt to enable msix */
8374                 rc = bnx2x_enable_msix(bp);
8375
8376                 /* msix attained */
8377                 if (!rc)
8378                         return 0;
8379
8380                 /* vfs use only msix */
8381                 if (rc && IS_VF(bp))
8382                         return rc;
8383
8384                 /* failed to enable multiple MSI-X */
8385                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8386                                bp->num_queues,
8387                                1 + bp->num_cnic_queues);
8388
8389                 /* falling through... */
8390         case BNX2X_INT_MODE_MSI:
8391                 bnx2x_enable_msi(bp);
8392
8393                 /* falling through... */
8394         case BNX2X_INT_MODE_INTX:
8395                 bp->num_ethernet_queues = 1;
8396                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8397                 BNX2X_DEV_INFO("set number of queues to 1\n");
8398                 break;
8399         default:
8400                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8401                 return -EINVAL;
8402         }
8403         return 0;
8404 }
8405
8406 /* must be called prior to any HW initializations */
8407 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8408 {
8409         if (IS_SRIOV(bp))
8410                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8411         return L2_ILT_LINES(bp);
8412 }
8413
8414 void bnx2x_ilt_set_info(struct bnx2x *bp)
8415 {
8416         struct ilt_client_info *ilt_client;
8417         struct bnx2x_ilt *ilt = BP_ILT(bp);
8418         u16 line = 0;
8419
8420         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8421         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8422
8423         /* CDU */
8424         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8425         ilt_client->client_num = ILT_CLIENT_CDU;
8426         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8427         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8428         ilt_client->start = line;
8429         line += bnx2x_cid_ilt_lines(bp);
8430
8431         if (CNIC_SUPPORT(bp))
8432                 line += CNIC_ILT_LINES;
8433         ilt_client->end = line - 1;
8434
8435         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8436            ilt_client->start,
8437            ilt_client->end,
8438            ilt_client->page_size,
8439            ilt_client->flags,
8440            ilog2(ilt_client->page_size >> 12));
8441
8442         /* QM */
8443         if (QM_INIT(bp->qm_cid_count)) {
8444                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8445                 ilt_client->client_num = ILT_CLIENT_QM;
8446                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8447                 ilt_client->flags = 0;
8448                 ilt_client->start = line;
8449
8450                 /* 4 bytes for each cid */
8451                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8452                                                          QM_ILT_PAGE_SZ);
8453
8454                 ilt_client->end = line - 1;
8455
8456                 DP(NETIF_MSG_IFUP,
8457                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8458                    ilt_client->start,
8459                    ilt_client->end,
8460                    ilt_client->page_size,
8461                    ilt_client->flags,
8462                    ilog2(ilt_client->page_size >> 12));
8463         }
8464
8465         if (CNIC_SUPPORT(bp)) {
8466                 /* SRC */
8467                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8468                 ilt_client->client_num = ILT_CLIENT_SRC;
8469                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8470                 ilt_client->flags = 0;
8471                 ilt_client->start = line;
8472                 line += SRC_ILT_LINES;
8473                 ilt_client->end = line - 1;
8474
8475                 DP(NETIF_MSG_IFUP,
8476                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8477                    ilt_client->start,
8478                    ilt_client->end,
8479                    ilt_client->page_size,
8480                    ilt_client->flags,
8481                    ilog2(ilt_client->page_size >> 12));
8482
8483                 /* TM */
8484                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8485                 ilt_client->client_num = ILT_CLIENT_TM;
8486                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8487                 ilt_client->flags = 0;
8488                 ilt_client->start = line;
8489                 line += TM_ILT_LINES;
8490                 ilt_client->end = line - 1;
8491
8492                 DP(NETIF_MSG_IFUP,
8493                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8494                    ilt_client->start,
8495                    ilt_client->end,
8496                    ilt_client->page_size,
8497                    ilt_client->flags,
8498                    ilog2(ilt_client->page_size >> 12));
8499         }
8500
8501         BUG_ON(line > ILT_MAX_LINES);
8502 }
8503
8504 /**
8505  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8506  *
8507  * @bp:                 driver handle
8508  * @fp:                 pointer to fastpath
8509  * @init_params:        pointer to parameters structure
8510  *
8511  * parameters configured:
8512  *      - HC configuration
8513  *      - Queue's CDU context
8514  */
8515 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8516         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8517 {
8518         u8 cos;
8519         int cxt_index, cxt_offset;
8520
8521         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8522         if (!IS_FCOE_FP(fp)) {
8523                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8524                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8525
8526                 /* If HC is supported, enable host coalescing in the transition
8527                  * to INIT state.
8528                  */
8529                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8530                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8531
8532                 /* HC rate */
8533                 init_params->rx.hc_rate = bp->rx_ticks ?
8534                         (1000000 / bp->rx_ticks) : 0;
8535                 init_params->tx.hc_rate = bp->tx_ticks ?
8536                         (1000000 / bp->tx_ticks) : 0;
8537
8538                 /* FW SB ID */
8539                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8540                         fp->fw_sb_id;
8541
8542                 /*
8543                  * CQ index among the SB indices: FCoE clients uses the default
8544                  * SB, therefore it's different.
8545                  */
8546                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8547                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8548         }
8549
8550         /* set maximum number of COSs supported by this queue */
8551         init_params->max_cos = fp->max_cos;
8552
8553         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8554             fp->index, init_params->max_cos);
8555
8556         /* set the context pointers queue object */
8557         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8558                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8559                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8560                                 ILT_PAGE_CIDS);
8561                 init_params->cxts[cos] =
8562                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8563         }
8564 }
8565
8566 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8567                         struct bnx2x_queue_state_params *q_params,
8568                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8569                         int tx_index, bool leading)
8570 {
8571         memset(tx_only_params, 0, sizeof(*tx_only_params));
8572
8573         /* Set the command */
8574         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8575
8576         /* Set tx-only QUEUE flags: don't zero statistics */
8577         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8578
8579         /* choose the index of the cid to send the slow path on */
8580         tx_only_params->cid_index = tx_index;
8581
8582         /* Set general TX_ONLY_SETUP parameters */
8583         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8584
8585         /* Set Tx TX_ONLY_SETUP parameters */
8586         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8587
8588         DP(NETIF_MSG_IFUP,
8589            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8590            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8591            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8592            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8593
8594         /* send the ramrod */
8595         return bnx2x_queue_state_change(bp, q_params);
8596 }
8597
8598 /**
8599  * bnx2x_setup_queue - setup queue
8600  *
8601  * @bp:         driver handle
8602  * @fp:         pointer to fastpath
8603  * @leading:    is leading
8604  *
8605  * This function performs 2 steps in a Queue state machine
8606  *      actually: 1) RESET->INIT 2) INIT->SETUP
8607  */
8608
8609 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8610                        bool leading)
8611 {
8612         struct bnx2x_queue_state_params q_params = {NULL};
8613         struct bnx2x_queue_setup_params *setup_params =
8614                                                 &q_params.params.setup;
8615         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8616                                                 &q_params.params.tx_only;
8617         int rc;
8618         u8 tx_index;
8619
8620         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8621
8622         /* reset IGU state skip FCoE L2 queue */
8623         if (!IS_FCOE_FP(fp))
8624                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8625                              IGU_INT_ENABLE, 0);
8626
8627         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8628         /* We want to wait for completion in this context */
8629         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8630
8631         /* Prepare the INIT parameters */
8632         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8633
8634         /* Set the command */
8635         q_params.cmd = BNX2X_Q_CMD_INIT;
8636
8637         /* Change the state to INIT */
8638         rc = bnx2x_queue_state_change(bp, &q_params);
8639         if (rc) {
8640                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8641                 return rc;
8642         }
8643
8644         DP(NETIF_MSG_IFUP, "init complete\n");
8645
8646         /* Now move the Queue to the SETUP state... */
8647         memset(setup_params, 0, sizeof(*setup_params));
8648
8649         /* Set QUEUE flags */
8650         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8651
8652         /* Set general SETUP parameters */
8653         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8654                                 FIRST_TX_COS_INDEX);
8655
8656         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8657                             &setup_params->rxq_params);
8658
8659         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8660                            FIRST_TX_COS_INDEX);
8661
8662         /* Set the command */
8663         q_params.cmd = BNX2X_Q_CMD_SETUP;
8664
8665         if (IS_FCOE_FP(fp))
8666                 bp->fcoe_init = true;
8667
8668         /* Change the state to SETUP */
8669         rc = bnx2x_queue_state_change(bp, &q_params);
8670         if (rc) {
8671                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8672                 return rc;
8673         }
8674
8675         /* loop through the relevant tx-only indices */
8676         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8677               tx_index < fp->max_cos;
8678               tx_index++) {
8679
8680                 /* prepare and send tx-only ramrod*/
8681                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8682                                           tx_only_params, tx_index, leading);
8683                 if (rc) {
8684                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8685                                   fp->index, tx_index);
8686                         return rc;
8687                 }
8688         }
8689
8690         return rc;
8691 }
8692
8693 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8694 {
8695         struct bnx2x_fastpath *fp = &bp->fp[index];
8696         struct bnx2x_fp_txdata *txdata;
8697         struct bnx2x_queue_state_params q_params = {NULL};
8698         int rc, tx_index;
8699
8700         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8701
8702         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8703         /* We want to wait for completion in this context */
8704         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8705
8706         /* close tx-only connections */
8707         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8708              tx_index < fp->max_cos;
8709              tx_index++){
8710
8711                 /* ascertain this is a normal queue*/
8712                 txdata = fp->txdata_ptr[tx_index];
8713
8714                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8715                                                         txdata->txq_index);
8716
8717                 /* send halt terminate on tx-only connection */
8718                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8719                 memset(&q_params.params.terminate, 0,
8720                        sizeof(q_params.params.terminate));
8721                 q_params.params.terminate.cid_index = tx_index;
8722
8723                 rc = bnx2x_queue_state_change(bp, &q_params);
8724                 if (rc)
8725                         return rc;
8726
8727                 /* send halt terminate on tx-only connection */
8728                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8729                 memset(&q_params.params.cfc_del, 0,
8730                        sizeof(q_params.params.cfc_del));
8731                 q_params.params.cfc_del.cid_index = tx_index;
8732                 rc = bnx2x_queue_state_change(bp, &q_params);
8733                 if (rc)
8734                         return rc;
8735         }
8736         /* Stop the primary connection: */
8737         /* ...halt the connection */
8738         q_params.cmd = BNX2X_Q_CMD_HALT;
8739         rc = bnx2x_queue_state_change(bp, &q_params);
8740         if (rc)
8741                 return rc;
8742
8743         /* ...terminate the connection */
8744         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8745         memset(&q_params.params.terminate, 0,
8746                sizeof(q_params.params.terminate));
8747         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8748         rc = bnx2x_queue_state_change(bp, &q_params);
8749         if (rc)
8750                 return rc;
8751         /* ...delete cfc entry */
8752         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8753         memset(&q_params.params.cfc_del, 0,
8754                sizeof(q_params.params.cfc_del));
8755         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8756         return bnx2x_queue_state_change(bp, &q_params);
8757 }
8758
8759 static void bnx2x_reset_func(struct bnx2x *bp)
8760 {
8761         int port = BP_PORT(bp);
8762         int func = BP_FUNC(bp);
8763         int i;
8764
8765         /* Disable the function in the FW */
8766         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8767         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8768         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8769         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8770
8771         /* FP SBs */
8772         for_each_eth_queue(bp, i) {
8773                 struct bnx2x_fastpath *fp = &bp->fp[i];
8774                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8775                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8776                            SB_DISABLED);
8777         }
8778
8779         if (CNIC_LOADED(bp))
8780                 /* CNIC SB */
8781                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8782                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8783                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8784
8785         /* SP SB */
8786         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8787                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8788                 SB_DISABLED);
8789
8790         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8791                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8792                        0);
8793
8794         /* Configure IGU */
8795         if (bp->common.int_block == INT_BLOCK_HC) {
8796                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8797                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8798         } else {
8799                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8800                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8801         }
8802
8803         if (CNIC_LOADED(bp)) {
8804                 /* Disable Timer scan */
8805                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8806                 /*
8807                  * Wait for at least 10ms and up to 2 second for the timers
8808                  * scan to complete
8809                  */
8810                 for (i = 0; i < 200; i++) {
8811                         usleep_range(10000, 20000);
8812                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8813                                 break;
8814                 }
8815         }
8816         /* Clear ILT */
8817         bnx2x_clear_func_ilt(bp, func);
8818
8819         /* Timers workaround bug for E2: if this is vnic-3,
8820          * we need to set the entire ilt range for this timers.
8821          */
8822         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8823                 struct ilt_client_info ilt_cli;
8824                 /* use dummy TM client */
8825                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8826                 ilt_cli.start = 0;
8827                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8828                 ilt_cli.client_num = ILT_CLIENT_TM;
8829
8830                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8831         }
8832
8833         /* this assumes that reset_port() called before reset_func()*/
8834         if (!CHIP_IS_E1x(bp))
8835                 bnx2x_pf_disable(bp);
8836
8837         bp->dmae_ready = 0;
8838 }
8839
8840 static void bnx2x_reset_port(struct bnx2x *bp)
8841 {
8842         int port = BP_PORT(bp);
8843         u32 val;
8844
8845         /* Reset physical Link */
8846         bnx2x__link_reset(bp);
8847
8848         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8849
8850         /* Do not rcv packets to BRB */
8851         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8852         /* Do not direct rcv packets that are not for MCP to the BRB */
8853         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8854                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8855
8856         /* Configure AEU */
8857         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8858
8859         msleep(100);
8860         /* Check for BRB port occupancy */
8861         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8862         if (val)
8863                 DP(NETIF_MSG_IFDOWN,
8864                    "BRB1 is not empty  %d blocks are occupied\n", val);
8865
8866         /* TODO: Close Doorbell port? */
8867 }
8868
8869 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8870 {
8871         struct bnx2x_func_state_params func_params = {NULL};
8872
8873         /* Prepare parameters for function state transitions */
8874         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8875
8876         func_params.f_obj = &bp->func_obj;
8877         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8878
8879         func_params.params.hw_init.load_phase = load_code;
8880
8881         return bnx2x_func_state_change(bp, &func_params);
8882 }
8883
8884 static int bnx2x_func_stop(struct bnx2x *bp)
8885 {
8886         struct bnx2x_func_state_params func_params = {NULL};
8887         int rc;
8888
8889         /* Prepare parameters for function state transitions */
8890         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8891         func_params.f_obj = &bp->func_obj;
8892         func_params.cmd = BNX2X_F_CMD_STOP;
8893
8894         /*
8895          * Try to stop the function the 'good way'. If fails (in case
8896          * of a parity error during bnx2x_chip_cleanup()) and we are
8897          * not in a debug mode, perform a state transaction in order to
8898          * enable further HW_RESET transaction.
8899          */
8900         rc = bnx2x_func_state_change(bp, &func_params);
8901         if (rc) {
8902 #ifdef BNX2X_STOP_ON_ERROR
8903                 return rc;
8904 #else
8905                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8906                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8907                 return bnx2x_func_state_change(bp, &func_params);
8908 #endif
8909         }
8910
8911         return 0;
8912 }
8913
8914 /**
8915  * bnx2x_send_unload_req - request unload mode from the MCP.
8916  *
8917  * @bp:                 driver handle
8918  * @unload_mode:        requested function's unload mode
8919  *
8920  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8921  */
8922 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8923 {
8924         u32 reset_code = 0;
8925         int port = BP_PORT(bp);
8926
8927         /* Select the UNLOAD request mode */
8928         if (unload_mode == UNLOAD_NORMAL)
8929                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8930
8931         else if (bp->flags & NO_WOL_FLAG)
8932                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8933
8934         else if (bp->wol) {
8935                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8936                 u8 *mac_addr = bp->dev->dev_addr;
8937                 struct pci_dev *pdev = bp->pdev;
8938                 u32 val;
8939                 u16 pmc;
8940
8941                 /* The mac address is written to entries 1-4 to
8942                  * preserve entry 0 which is used by the PMF
8943                  */
8944                 u8 entry = (BP_VN(bp) + 1)*8;
8945
8946                 val = (mac_addr[0] << 8) | mac_addr[1];
8947                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8948
8949                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8950                       (mac_addr[4] << 8) | mac_addr[5];
8951                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8952
8953                 /* Enable the PME and clear the status */
8954                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
8955                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8956                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
8957
8958                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8959
8960         } else
8961                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8962
8963         /* Send the request to the MCP */
8964         if (!BP_NOMCP(bp))
8965                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8966         else {
8967                 int path = BP_PATH(bp);
8968
8969                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8970                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8971                    bnx2x_load_count[path][2]);
8972                 bnx2x_load_count[path][0]--;
8973                 bnx2x_load_count[path][1 + port]--;
8974                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8975                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8976                    bnx2x_load_count[path][2]);
8977                 if (bnx2x_load_count[path][0] == 0)
8978                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8979                 else if (bnx2x_load_count[path][1 + port] == 0)
8980                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8981                 else
8982                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8983         }
8984
8985         return reset_code;
8986 }
8987
8988 /**
8989  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8990  *
8991  * @bp:         driver handle
8992  * @keep_link:          true iff link should be kept up
8993  */
8994 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8995 {
8996         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8997
8998         /* Report UNLOAD_DONE to MCP */
8999         if (!BP_NOMCP(bp))
9000                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9001 }
9002
9003 static int bnx2x_func_wait_started(struct bnx2x *bp)
9004 {
9005         int tout = 50;
9006         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9007
9008         if (!bp->port.pmf)
9009                 return 0;
9010
9011         /*
9012          * (assumption: No Attention from MCP at this stage)
9013          * PMF probably in the middle of TX disable/enable transaction
9014          * 1. Sync IRS for default SB
9015          * 2. Sync SP queue - this guarantees us that attention handling started
9016          * 3. Wait, that TX disable/enable transaction completes
9017          *
9018          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9019          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9020          * received completion for the transaction the state is TX_STOPPED.
9021          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9022          * transaction.
9023          */
9024
9025         /* make sure default SB ISR is done */
9026         if (msix)
9027                 synchronize_irq(bp->msix_table[0].vector);
9028         else
9029                 synchronize_irq(bp->pdev->irq);
9030
9031         flush_workqueue(bnx2x_wq);
9032         flush_workqueue(bnx2x_iov_wq);
9033
9034         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9035                                 BNX2X_F_STATE_STARTED && tout--)
9036                 msleep(20);
9037
9038         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9039                                                 BNX2X_F_STATE_STARTED) {
9040 #ifdef BNX2X_STOP_ON_ERROR
9041                 BNX2X_ERR("Wrong function state\n");
9042                 return -EBUSY;
9043 #else
9044                 /*
9045                  * Failed to complete the transaction in a "good way"
9046                  * Force both transactions with CLR bit
9047                  */
9048                 struct bnx2x_func_state_params func_params = {NULL};
9049
9050                 DP(NETIF_MSG_IFDOWN,
9051                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9052
9053                 func_params.f_obj = &bp->func_obj;
9054                 __set_bit(RAMROD_DRV_CLR_ONLY,
9055                                         &func_params.ramrod_flags);
9056
9057                 /* STARTED-->TX_ST0PPED */
9058                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9059                 bnx2x_func_state_change(bp, &func_params);
9060
9061                 /* TX_ST0PPED-->STARTED */
9062                 func_params.cmd = BNX2X_F_CMD_TX_START;
9063                 return bnx2x_func_state_change(bp, &func_params);
9064 #endif
9065         }
9066
9067         return 0;
9068 }
9069
9070 static void bnx2x_disable_ptp(struct bnx2x *bp)
9071 {
9072         int port = BP_PORT(bp);
9073
9074         /* Disable sending PTP packets to host */
9075         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9076                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9077
9078         /* Reset PTP event detection rules */
9079         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9080                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9081         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9082                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9083         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9084                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9085         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9086                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9087
9088         /* Disable the PTP feature */
9089         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9090                NIG_REG_P0_PTP_EN, 0x0);
9091 }
9092
9093 /* Called during unload, to stop PTP-related stuff */
9094 void bnx2x_stop_ptp(struct bnx2x *bp)
9095 {
9096         /* Cancel PTP work queue. Should be done after the Tx queues are
9097          * drained to prevent additional scheduling.
9098          */
9099         cancel_work_sync(&bp->ptp_task);
9100
9101         if (bp->ptp_tx_skb) {
9102                 dev_kfree_skb_any(bp->ptp_tx_skb);
9103                 bp->ptp_tx_skb = NULL;
9104         }
9105
9106         /* Disable PTP in HW */
9107         bnx2x_disable_ptp(bp);
9108
9109         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9110 }
9111
9112 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9113 {
9114         int port = BP_PORT(bp);
9115         int i, rc = 0;
9116         u8 cos;
9117         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9118         u32 reset_code;
9119
9120         /* Wait until tx fastpath tasks complete */
9121         for_each_tx_queue(bp, i) {
9122                 struct bnx2x_fastpath *fp = &bp->fp[i];
9123
9124                 for_each_cos_in_tx_queue(fp, cos)
9125                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9126 #ifdef BNX2X_STOP_ON_ERROR
9127                 if (rc)
9128                         return;
9129 #endif
9130         }
9131
9132         /* Give HW time to discard old tx messages */
9133         usleep_range(1000, 2000);
9134
9135         /* Clean all ETH MACs */
9136         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9137                                 false);
9138         if (rc < 0)
9139                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9140
9141         /* Clean up UC list  */
9142         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9143                                 true);
9144         if (rc < 0)
9145                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9146                           rc);
9147
9148         /* Disable LLH */
9149         if (!CHIP_IS_E1(bp))
9150                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9151
9152         /* Set "drop all" (stop Rx).
9153          * We need to take a netif_addr_lock() here in order to prevent
9154          * a race between the completion code and this code.
9155          */
9156         netif_addr_lock_bh(bp->dev);
9157         /* Schedule the rx_mode command */
9158         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9159                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9160         else
9161                 bnx2x_set_storm_rx_mode(bp);
9162
9163         /* Cleanup multicast configuration */
9164         rparam.mcast_obj = &bp->mcast_obj;
9165         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9166         if (rc < 0)
9167                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9168
9169         netif_addr_unlock_bh(bp->dev);
9170
9171         bnx2x_iov_chip_cleanup(bp);
9172
9173         /*
9174          * Send the UNLOAD_REQUEST to the MCP. This will return if
9175          * this function should perform FUNC, PORT or COMMON HW
9176          * reset.
9177          */
9178         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9179
9180         /*
9181          * (assumption: No Attention from MCP at this stage)
9182          * PMF probably in the middle of TX disable/enable transaction
9183          */
9184         rc = bnx2x_func_wait_started(bp);
9185         if (rc) {
9186                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9187 #ifdef BNX2X_STOP_ON_ERROR
9188                 return;
9189 #endif
9190         }
9191
9192         /* Close multi and leading connections
9193          * Completions for ramrods are collected in a synchronous way
9194          */
9195         for_each_eth_queue(bp, i)
9196                 if (bnx2x_stop_queue(bp, i))
9197 #ifdef BNX2X_STOP_ON_ERROR
9198                         return;
9199 #else
9200                         goto unload_error;
9201 #endif
9202
9203         if (CNIC_LOADED(bp)) {
9204                 for_each_cnic_queue(bp, i)
9205                         if (bnx2x_stop_queue(bp, i))
9206 #ifdef BNX2X_STOP_ON_ERROR
9207                                 return;
9208 #else
9209                                 goto unload_error;
9210 #endif
9211         }
9212
9213         /* If SP settings didn't get completed so far - something
9214          * very wrong has happen.
9215          */
9216         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9217                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9218
9219 #ifndef BNX2X_STOP_ON_ERROR
9220 unload_error:
9221 #endif
9222         rc = bnx2x_func_stop(bp);
9223         if (rc) {
9224                 BNX2X_ERR("Function stop failed!\n");
9225 #ifdef BNX2X_STOP_ON_ERROR
9226                 return;
9227 #endif
9228         }
9229
9230         /* stop_ptp should be after the Tx queues are drained to prevent
9231          * scheduling to the cancelled PTP work queue. It should also be after
9232          * function stop ramrod is sent, since as part of this ramrod FW access
9233          * PTP registers.
9234          */
9235         bnx2x_stop_ptp(bp);
9236
9237         /* Disable HW interrupts, NAPI */
9238         bnx2x_netif_stop(bp, 1);
9239         /* Delete all NAPI objects */
9240         bnx2x_del_all_napi(bp);
9241         if (CNIC_LOADED(bp))
9242                 bnx2x_del_all_napi_cnic(bp);
9243
9244         /* Release IRQs */
9245         bnx2x_free_irq(bp);
9246
9247         /* Reset the chip */
9248         rc = bnx2x_reset_hw(bp, reset_code);
9249         if (rc)
9250                 BNX2X_ERR("HW_RESET failed\n");
9251
9252         /* Report UNLOAD_DONE to MCP */
9253         bnx2x_send_unload_done(bp, keep_link);
9254 }
9255
9256 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9257 {
9258         u32 val;
9259
9260         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9261
9262         if (CHIP_IS_E1(bp)) {
9263                 int port = BP_PORT(bp);
9264                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9265                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9266
9267                 val = REG_RD(bp, addr);
9268                 val &= ~(0x300);
9269                 REG_WR(bp, addr, val);
9270         } else {
9271                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9272                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9273                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9274                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9275         }
9276 }
9277
9278 /* Close gates #2, #3 and #4: */
9279 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9280 {
9281         u32 val;
9282
9283         /* Gates #2 and #4a are closed/opened for "not E1" only */
9284         if (!CHIP_IS_E1(bp)) {
9285                 /* #4 */
9286                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9287                 /* #2 */
9288                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9289         }
9290
9291         /* #3 */
9292         if (CHIP_IS_E1x(bp)) {
9293                 /* Prevent interrupts from HC on both ports */
9294                 val = REG_RD(bp, HC_REG_CONFIG_1);
9295                 REG_WR(bp, HC_REG_CONFIG_1,
9296                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9297                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9298
9299                 val = REG_RD(bp, HC_REG_CONFIG_0);
9300                 REG_WR(bp, HC_REG_CONFIG_0,
9301                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9302                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9303         } else {
9304                 /* Prevent incoming interrupts in IGU */
9305                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9306
9307                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9308                        (!close) ?
9309                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9310                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9311         }
9312
9313         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9314                 close ? "closing" : "opening");
9315         mmiowb();
9316 }
9317
9318 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9319
9320 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9321 {
9322         /* Do some magic... */
9323         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9324         *magic_val = val & SHARED_MF_CLP_MAGIC;
9325         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9326 }
9327
9328 /**
9329  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9330  *
9331  * @bp:         driver handle
9332  * @magic_val:  old value of the `magic' bit.
9333  */
9334 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9335 {
9336         /* Restore the `magic' bit value... */
9337         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9338         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9339                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9340 }
9341
9342 /**
9343  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9344  *
9345  * @bp:         driver handle
9346  * @magic_val:  old value of 'magic' bit.
9347  *
9348  * Takes care of CLP configurations.
9349  */
9350 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9351 {
9352         u32 shmem;
9353         u32 validity_offset;
9354
9355         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9356
9357         /* Set `magic' bit in order to save MF config */
9358         if (!CHIP_IS_E1(bp))
9359                 bnx2x_clp_reset_prep(bp, magic_val);
9360
9361         /* Get shmem offset */
9362         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9363         validity_offset =
9364                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9365
9366         /* Clear validity map flags */
9367         if (shmem > 0)
9368                 REG_WR(bp, shmem + validity_offset, 0);
9369 }
9370
9371 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9372 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9373
9374 /**
9375  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9376  *
9377  * @bp: driver handle
9378  */
9379 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9380 {
9381         /* special handling for emulation and FPGA,
9382            wait 10 times longer */
9383         if (CHIP_REV_IS_SLOW(bp))
9384                 msleep(MCP_ONE_TIMEOUT*10);
9385         else
9386                 msleep(MCP_ONE_TIMEOUT);
9387 }
9388
9389 /*
9390  * initializes bp->common.shmem_base and waits for validity signature to appear
9391  */
9392 static int bnx2x_init_shmem(struct bnx2x *bp)
9393 {
9394         int cnt = 0;
9395         u32 val = 0;
9396
9397         do {
9398                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9399                 if (bp->common.shmem_base) {
9400                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9401                         if (val & SHR_MEM_VALIDITY_MB)
9402                                 return 0;
9403                 }
9404
9405                 bnx2x_mcp_wait_one(bp);
9406
9407         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9408
9409         BNX2X_ERR("BAD MCP validity signature\n");
9410
9411         return -ENODEV;
9412 }
9413
9414 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9415 {
9416         int rc = bnx2x_init_shmem(bp);
9417
9418         /* Restore the `magic' bit value */
9419         if (!CHIP_IS_E1(bp))
9420                 bnx2x_clp_reset_done(bp, magic_val);
9421
9422         return rc;
9423 }
9424
9425 static void bnx2x_pxp_prep(struct bnx2x *bp)
9426 {
9427         if (!CHIP_IS_E1(bp)) {
9428                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9429                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9430                 mmiowb();
9431         }
9432 }
9433
9434 /*
9435  * Reset the whole chip except for:
9436  *      - PCIE core
9437  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9438  *              one reset bit)
9439  *      - IGU
9440  *      - MISC (including AEU)
9441  *      - GRC
9442  *      - RBCN, RBCP
9443  */
9444 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9445 {
9446         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9447         u32 global_bits2, stay_reset2;
9448
9449         /*
9450          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9451          * (per chip) blocks.
9452          */
9453         global_bits2 =
9454                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9455                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9456
9457         /* Don't reset the following blocks.
9458          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9459          *            reset, as in 4 port device they might still be owned
9460          *            by the MCP (there is only one leader per path).
9461          */
9462         not_reset_mask1 =
9463                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9464                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9465                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9466
9467         not_reset_mask2 =
9468                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9469                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9470                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9471                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9472                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9473                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9474                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9475                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9476                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9477                 MISC_REGISTERS_RESET_REG_2_PGLC |
9478                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9479                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9480                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9481                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9482                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9483                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9484
9485         /*
9486          * Keep the following blocks in reset:
9487          *  - all xxMACs are handled by the bnx2x_link code.
9488          */
9489         stay_reset2 =
9490                 MISC_REGISTERS_RESET_REG_2_XMAC |
9491                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9492
9493         /* Full reset masks according to the chip */
9494         reset_mask1 = 0xffffffff;
9495
9496         if (CHIP_IS_E1(bp))
9497                 reset_mask2 = 0xffff;
9498         else if (CHIP_IS_E1H(bp))
9499                 reset_mask2 = 0x1ffff;
9500         else if (CHIP_IS_E2(bp))
9501                 reset_mask2 = 0xfffff;
9502         else /* CHIP_IS_E3 */
9503                 reset_mask2 = 0x3ffffff;
9504
9505         /* Don't reset global blocks unless we need to */
9506         if (!global)
9507                 reset_mask2 &= ~global_bits2;
9508
9509         /*
9510          * In case of attention in the QM, we need to reset PXP
9511          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9512          * because otherwise QM reset would release 'close the gates' shortly
9513          * before resetting the PXP, then the PSWRQ would send a write
9514          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9515          * read the payload data from PSWWR, but PSWWR would not
9516          * respond. The write queue in PGLUE would stuck, dmae commands
9517          * would not return. Therefore it's important to reset the second
9518          * reset register (containing the
9519          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9520          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9521          * bit).
9522          */
9523         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9524                reset_mask2 & (~not_reset_mask2));
9525
9526         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9527                reset_mask1 & (~not_reset_mask1));
9528
9529         barrier();
9530         mmiowb();
9531
9532         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9533                reset_mask2 & (~stay_reset2));
9534
9535         barrier();
9536         mmiowb();
9537
9538         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9539         mmiowb();
9540 }
9541
9542 /**
9543  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9544  * It should get cleared in no more than 1s.
9545  *
9546  * @bp: driver handle
9547  *
9548  * It should get cleared in no more than 1s. Returns 0 if
9549  * pending writes bit gets cleared.
9550  */
9551 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9552 {
9553         u32 cnt = 1000;
9554         u32 pend_bits = 0;
9555
9556         do {
9557                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9558
9559                 if (pend_bits == 0)
9560                         break;
9561
9562                 usleep_range(1000, 2000);
9563         } while (cnt-- > 0);
9564
9565         if (cnt <= 0) {
9566                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9567                           pend_bits);
9568                 return -EBUSY;
9569         }
9570
9571         return 0;
9572 }
9573
9574 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9575 {
9576         int cnt = 1000;
9577         u32 val = 0;
9578         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9579         u32 tags_63_32 = 0;
9580
9581         /* Empty the Tetris buffer, wait for 1s */
9582         do {
9583                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9584                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9585                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9586                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9587                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9588                 if (CHIP_IS_E3(bp))
9589                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9590
9591                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9592                     ((port_is_idle_0 & 0x1) == 0x1) &&
9593                     ((port_is_idle_1 & 0x1) == 0x1) &&
9594                     (pgl_exp_rom2 == 0xffffffff) &&
9595                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9596                         break;
9597                 usleep_range(1000, 2000);
9598         } while (cnt-- > 0);
9599
9600         if (cnt <= 0) {
9601                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9602                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9603                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9604                           pgl_exp_rom2);
9605                 return -EAGAIN;
9606         }
9607
9608         barrier();
9609
9610         /* Close gates #2, #3 and #4 */
9611         bnx2x_set_234_gates(bp, true);
9612
9613         /* Poll for IGU VQs for 57712 and newer chips */
9614         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9615                 return -EAGAIN;
9616
9617         /* TBD: Indicate that "process kill" is in progress to MCP */
9618
9619         /* Clear "unprepared" bit */
9620         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9621         barrier();
9622
9623         /* Make sure all is written to the chip before the reset */
9624         mmiowb();
9625
9626         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9627          * PSWHST, GRC and PSWRD Tetris buffer.
9628          */
9629         usleep_range(1000, 2000);
9630
9631         /* Prepare to chip reset: */
9632         /* MCP */
9633         if (global)
9634                 bnx2x_reset_mcp_prep(bp, &val);
9635
9636         /* PXP */
9637         bnx2x_pxp_prep(bp);
9638         barrier();
9639
9640         /* reset the chip */
9641         bnx2x_process_kill_chip_reset(bp, global);
9642         barrier();
9643
9644         /* clear errors in PGB */
9645         if (!CHIP_IS_E1x(bp))
9646                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9647
9648         /* Recover after reset: */
9649         /* MCP */
9650         if (global && bnx2x_reset_mcp_comp(bp, val))
9651                 return -EAGAIN;
9652
9653         /* TBD: Add resetting the NO_MCP mode DB here */
9654
9655         /* Open the gates #2, #3 and #4 */
9656         bnx2x_set_234_gates(bp, false);
9657
9658         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9659          * reset state, re-enable attentions. */
9660
9661         return 0;
9662 }
9663
9664 static int bnx2x_leader_reset(struct bnx2x *bp)
9665 {
9666         int rc = 0;
9667         bool global = bnx2x_reset_is_global(bp);
9668         u32 load_code;
9669
9670         /* if not going to reset MCP - load "fake" driver to reset HW while
9671          * driver is owner of the HW
9672          */
9673         if (!global && !BP_NOMCP(bp)) {
9674                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9675                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9676                 if (!load_code) {
9677                         BNX2X_ERR("MCP response failure, aborting\n");
9678                         rc = -EAGAIN;
9679                         goto exit_leader_reset;
9680                 }
9681                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9682                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9683                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9684                         rc = -EAGAIN;
9685                         goto exit_leader_reset2;
9686                 }
9687                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9688                 if (!load_code) {
9689                         BNX2X_ERR("MCP response failure, aborting\n");
9690                         rc = -EAGAIN;
9691                         goto exit_leader_reset2;
9692                 }
9693         }
9694
9695         /* Try to recover after the failure */
9696         if (bnx2x_process_kill(bp, global)) {
9697                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9698                           BP_PATH(bp));
9699                 rc = -EAGAIN;
9700                 goto exit_leader_reset2;
9701         }
9702
9703         /*
9704          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9705          * state.
9706          */
9707         bnx2x_set_reset_done(bp);
9708         if (global)
9709                 bnx2x_clear_reset_global(bp);
9710
9711 exit_leader_reset2:
9712         /* unload "fake driver" if it was loaded */
9713         if (!global && !BP_NOMCP(bp)) {
9714                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9715                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9716         }
9717 exit_leader_reset:
9718         bp->is_leader = 0;
9719         bnx2x_release_leader_lock(bp);
9720         smp_mb();
9721         return rc;
9722 }
9723
9724 static void bnx2x_recovery_failed(struct bnx2x *bp)
9725 {
9726         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9727
9728         /* Disconnect this device */
9729         netif_device_detach(bp->dev);
9730
9731         /*
9732          * Block ifup for all function on this engine until "process kill"
9733          * or power cycle.
9734          */
9735         bnx2x_set_reset_in_progress(bp);
9736
9737         /* Shut down the power */
9738         bnx2x_set_power_state(bp, PCI_D3hot);
9739
9740         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9741
9742         smp_mb();
9743 }
9744
9745 /*
9746  * Assumption: runs under rtnl lock. This together with the fact
9747  * that it's called only from bnx2x_sp_rtnl() ensure that it
9748  * will never be called when netif_running(bp->dev) is false.
9749  */
9750 static void bnx2x_parity_recover(struct bnx2x *bp)
9751 {
9752         bool global = false;
9753         u32 error_recovered, error_unrecovered;
9754         bool is_parity;
9755
9756         DP(NETIF_MSG_HW, "Handling parity\n");
9757         while (1) {
9758                 switch (bp->recovery_state) {
9759                 case BNX2X_RECOVERY_INIT:
9760                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9761                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9762                         WARN_ON(!is_parity);
9763
9764                         /* Try to get a LEADER_LOCK HW lock */
9765                         if (bnx2x_trylock_leader_lock(bp)) {
9766                                 bnx2x_set_reset_in_progress(bp);
9767                                 /*
9768                                  * Check if there is a global attention and if
9769                                  * there was a global attention, set the global
9770                                  * reset bit.
9771                                  */
9772
9773                                 if (global)
9774                                         bnx2x_set_reset_global(bp);
9775
9776                                 bp->is_leader = 1;
9777                         }
9778
9779                         /* Stop the driver */
9780                         /* If interface has been removed - break */
9781                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9782                                 return;
9783
9784                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9785
9786                         /* Ensure "is_leader", MCP command sequence and
9787                          * "recovery_state" update values are seen on other
9788                          * CPUs.
9789                          */
9790                         smp_mb();
9791                         break;
9792
9793                 case BNX2X_RECOVERY_WAIT:
9794                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9795                         if (bp->is_leader) {
9796                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9797                                 bool other_load_status =
9798                                         bnx2x_get_load_status(bp, other_engine);
9799                                 bool load_status =
9800                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9801                                 global = bnx2x_reset_is_global(bp);
9802
9803                                 /*
9804                                  * In case of a parity in a global block, let
9805                                  * the first leader that performs a
9806                                  * leader_reset() reset the global blocks in
9807                                  * order to clear global attentions. Otherwise
9808                                  * the gates will remain closed for that
9809                                  * engine.
9810                                  */
9811                                 if (load_status ||
9812                                     (global && other_load_status)) {
9813                                         /* Wait until all other functions get
9814                                          * down.
9815                                          */
9816                                         schedule_delayed_work(&bp->sp_rtnl_task,
9817                                                                 HZ/10);
9818                                         return;
9819                                 } else {
9820                                         /* If all other functions got down -
9821                                          * try to bring the chip back to
9822                                          * normal. In any case it's an exit
9823                                          * point for a leader.
9824                                          */
9825                                         if (bnx2x_leader_reset(bp)) {
9826                                                 bnx2x_recovery_failed(bp);
9827                                                 return;
9828                                         }
9829
9830                                         /* If we are here, means that the
9831                                          * leader has succeeded and doesn't
9832                                          * want to be a leader any more. Try
9833                                          * to continue as a none-leader.
9834                                          */
9835                                         break;
9836                                 }
9837                         } else { /* non-leader */
9838                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9839                                         /* Try to get a LEADER_LOCK HW lock as
9840                                          * long as a former leader may have
9841                                          * been unloaded by the user or
9842                                          * released a leadership by another
9843                                          * reason.
9844                                          */
9845                                         if (bnx2x_trylock_leader_lock(bp)) {
9846                                                 /* I'm a leader now! Restart a
9847                                                  * switch case.
9848                                                  */
9849                                                 bp->is_leader = 1;
9850                                                 break;
9851                                         }
9852
9853                                         schedule_delayed_work(&bp->sp_rtnl_task,
9854                                                                 HZ/10);
9855                                         return;
9856
9857                                 } else {
9858                                         /*
9859                                          * If there was a global attention, wait
9860                                          * for it to be cleared.
9861                                          */
9862                                         if (bnx2x_reset_is_global(bp)) {
9863                                                 schedule_delayed_work(
9864                                                         &bp->sp_rtnl_task,
9865                                                         HZ/10);
9866                                                 return;
9867                                         }
9868
9869                                         error_recovered =
9870                                           bp->eth_stats.recoverable_error;
9871                                         error_unrecovered =
9872                                           bp->eth_stats.unrecoverable_error;
9873                                         bp->recovery_state =
9874                                                 BNX2X_RECOVERY_NIC_LOADING;
9875                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9876                                                 error_unrecovered++;
9877                                                 netdev_err(bp->dev,
9878                                                            "Recovery failed. Power cycle needed\n");
9879                                                 /* Disconnect this device */
9880                                                 netif_device_detach(bp->dev);
9881                                                 /* Shut down the power */
9882                                                 bnx2x_set_power_state(
9883                                                         bp, PCI_D3hot);
9884                                                 smp_mb();
9885                                         } else {
9886                                                 bp->recovery_state =
9887                                                         BNX2X_RECOVERY_DONE;
9888                                                 error_recovered++;
9889                                                 smp_mb();
9890                                         }
9891                                         bp->eth_stats.recoverable_error =
9892                                                 error_recovered;
9893                                         bp->eth_stats.unrecoverable_error =
9894                                                 error_unrecovered;
9895
9896                                         return;
9897                                 }
9898                         }
9899                 default:
9900                         return;
9901                 }
9902         }
9903 }
9904
9905 static int bnx2x_close(struct net_device *dev);
9906
9907 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9908  * scheduled on a general queue in order to prevent a dead lock.
9909  */
9910 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9911 {
9912         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9913
9914         rtnl_lock();
9915
9916         if (!netif_running(bp->dev)) {
9917                 rtnl_unlock();
9918                 return;
9919         }
9920
9921         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9922 #ifdef BNX2X_STOP_ON_ERROR
9923                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9924                           "you will need to reboot when done\n");
9925                 goto sp_rtnl_not_reset;
9926 #endif
9927                 /*
9928                  * Clear all pending SP commands as we are going to reset the
9929                  * function anyway.
9930                  */
9931                 bp->sp_rtnl_state = 0;
9932                 smp_mb();
9933
9934                 bnx2x_parity_recover(bp);
9935
9936                 rtnl_unlock();
9937                 return;
9938         }
9939
9940         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9941 #ifdef BNX2X_STOP_ON_ERROR
9942                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9943                           "you will need to reboot when done\n");
9944                 goto sp_rtnl_not_reset;
9945 #endif
9946
9947                 /*
9948                  * Clear all pending SP commands as we are going to reset the
9949                  * function anyway.
9950                  */
9951                 bp->sp_rtnl_state = 0;
9952                 smp_mb();
9953
9954                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9955                 bnx2x_nic_load(bp, LOAD_NORMAL);
9956
9957                 rtnl_unlock();
9958                 return;
9959         }
9960 #ifdef BNX2X_STOP_ON_ERROR
9961 sp_rtnl_not_reset:
9962 #endif
9963         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9964                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9965         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9966                 bnx2x_after_function_update(bp);
9967         /*
9968          * in case of fan failure we need to reset id if the "stop on error"
9969          * debug flag is set, since we trying to prevent permanent overheating
9970          * damage
9971          */
9972         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9973                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9974                 netif_device_detach(bp->dev);
9975                 bnx2x_close(bp->dev);
9976                 rtnl_unlock();
9977                 return;
9978         }
9979
9980         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9981                 DP(BNX2X_MSG_SP,
9982                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9983                 bnx2x_vfpf_set_mcast(bp->dev);
9984         }
9985         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9986                                &bp->sp_rtnl_state)){
9987                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9988                         bnx2x_tx_disable(bp);
9989                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9990                 }
9991         }
9992
9993         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9994                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9995                 bnx2x_set_rx_mode_inner(bp);
9996         }
9997
9998         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9999                                &bp->sp_rtnl_state))
10000                 bnx2x_pf_set_vfs_vlan(bp);
10001
10002         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10003                 bnx2x_dcbx_stop_hw_tx(bp);
10004                 bnx2x_dcbx_resume_hw_tx(bp);
10005         }
10006
10007         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10008                                &bp->sp_rtnl_state))
10009                 bnx2x_update_mng_version(bp);
10010
10011         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10012          * can be called from other contexts as well)
10013          */
10014         rtnl_unlock();
10015
10016         /* enable SR-IOV if applicable */
10017         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10018                                                &bp->sp_rtnl_state)) {
10019                 bnx2x_disable_sriov(bp);
10020                 bnx2x_enable_sriov(bp);
10021         }
10022 }
10023
10024 static void bnx2x_period_task(struct work_struct *work)
10025 {
10026         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10027
10028         if (!netif_running(bp->dev))
10029                 goto period_task_exit;
10030
10031         if (CHIP_REV_IS_SLOW(bp)) {
10032                 BNX2X_ERR("period task called on emulation, ignoring\n");
10033                 goto period_task_exit;
10034         }
10035
10036         bnx2x_acquire_phy_lock(bp);
10037         /*
10038          * The barrier is needed to ensure the ordering between the writing to
10039          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10040          * the reading here.
10041          */
10042         smp_mb();
10043         if (bp->port.pmf) {
10044                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10045
10046                 /* Re-queue task in 1 sec */
10047                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10048         }
10049
10050         bnx2x_release_phy_lock(bp);
10051 period_task_exit:
10052         return;
10053 }
10054
10055 /*
10056  * Init service functions
10057  */
10058
10059 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10060 {
10061         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10062         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10063         return base + (BP_ABS_FUNC(bp)) * stride;
10064 }
10065
10066 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10067                                         struct bnx2x_mac_vals *vals)
10068 {
10069         u32 val, base_addr, offset, mask, reset_reg;
10070         bool mac_stopped = false;
10071         u8 port = BP_PORT(bp);
10072
10073         /* reset addresses as they also mark which values were changed */
10074         vals->bmac_addr = 0;
10075         vals->umac_addr = 0;
10076         vals->xmac_addr = 0;
10077         vals->emac_addr = 0;
10078
10079         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10080
10081         if (!CHIP_IS_E3(bp)) {
10082                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10083                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10084                 if ((mask & reset_reg) && val) {
10085                         u32 wb_data[2];
10086                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10087                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10088                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10089                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10090                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10091
10092                         /*
10093                          * use rd/wr since we cannot use dmae. This is safe
10094                          * since MCP won't access the bus due to the request
10095                          * to unload, and no function on the path can be
10096                          * loaded at this time.
10097                          */
10098                         wb_data[0] = REG_RD(bp, base_addr + offset);
10099                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10100                         vals->bmac_addr = base_addr + offset;
10101                         vals->bmac_val[0] = wb_data[0];
10102                         vals->bmac_val[1] = wb_data[1];
10103                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10104                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10105                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10106                 }
10107                 BNX2X_DEV_INFO("Disable emac Rx\n");
10108                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10109                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10110                 REG_WR(bp, vals->emac_addr, 0);
10111                 mac_stopped = true;
10112         } else {
10113                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10114                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10115                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10116                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10117                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10118                                val & ~(1 << 1));
10119                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10120                                val | (1 << 1));
10121                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10122                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10123                         REG_WR(bp, vals->xmac_addr, 0);
10124                         mac_stopped = true;
10125                 }
10126                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10127                 if (mask & reset_reg) {
10128                         BNX2X_DEV_INFO("Disable umac Rx\n");
10129                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10130                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10131                         vals->umac_val = REG_RD(bp, vals->umac_addr);
10132                         REG_WR(bp, vals->umac_addr, 0);
10133                         mac_stopped = true;
10134                 }
10135         }
10136
10137         if (mac_stopped)
10138                 msleep(20);
10139 }
10140
10141 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10142 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10143                                         0x1848 + ((f) << 4))
10144 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10145 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10146 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10147
10148 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10149 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10150 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10151
10152 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10153 {
10154         /* UNDI marks its presence in DORQ -
10155          * it initializes CID offset for normal bell to 0x7
10156          */
10157         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10158             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10159                 return false;
10160
10161         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10162                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10163                 return true;
10164         }
10165
10166         return false;
10167 }
10168
10169 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10170 {
10171         u16 rcq, bd;
10172         u32 addr, tmp_reg;
10173
10174         if (BP_FUNC(bp) < 2)
10175                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10176         else
10177                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10178
10179         tmp_reg = REG_RD(bp, addr);
10180         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10181         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10182
10183         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10184         REG_WR(bp, addr, tmp_reg);
10185
10186         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10187                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10188 }
10189
10190 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10191 {
10192         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10193                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10194         if (!rc) {
10195                 BNX2X_ERR("MCP response failure, aborting\n");
10196                 return -EBUSY;
10197         }
10198
10199         return 0;
10200 }
10201
10202 static struct bnx2x_prev_path_list *
10203                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10204 {
10205         struct bnx2x_prev_path_list *tmp_list;
10206
10207         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10208                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10209                     bp->pdev->bus->number == tmp_list->bus &&
10210                     BP_PATH(bp) == tmp_list->path)
10211                         return tmp_list;
10212
10213         return NULL;
10214 }
10215
10216 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10217 {
10218         struct bnx2x_prev_path_list *tmp_list;
10219         int rc;
10220
10221         rc = down_interruptible(&bnx2x_prev_sem);
10222         if (rc) {
10223                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10224                 return rc;
10225         }
10226
10227         tmp_list = bnx2x_prev_path_get_entry(bp);
10228         if (tmp_list) {
10229                 tmp_list->aer = 1;
10230                 rc = 0;
10231         } else {
10232                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10233                           BP_PATH(bp));
10234         }
10235
10236         up(&bnx2x_prev_sem);
10237
10238         return rc;
10239 }
10240
10241 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10242 {
10243         struct bnx2x_prev_path_list *tmp_list;
10244         bool rc = false;
10245
10246         if (down_trylock(&bnx2x_prev_sem))
10247                 return false;
10248
10249         tmp_list = bnx2x_prev_path_get_entry(bp);
10250         if (tmp_list) {
10251                 if (tmp_list->aer) {
10252                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10253                            BP_PATH(bp));
10254                 } else {
10255                         rc = true;
10256                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10257                                        BP_PATH(bp));
10258                 }
10259         }
10260
10261         up(&bnx2x_prev_sem);
10262
10263         return rc;
10264 }
10265
10266 bool bnx2x_port_after_undi(struct bnx2x *bp)
10267 {
10268         struct bnx2x_prev_path_list *entry;
10269         bool val;
10270
10271         down(&bnx2x_prev_sem);
10272
10273         entry = bnx2x_prev_path_get_entry(bp);
10274         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10275
10276         up(&bnx2x_prev_sem);
10277
10278         return val;
10279 }
10280
10281 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10282 {
10283         struct bnx2x_prev_path_list *tmp_list;
10284         int rc;
10285
10286         rc = down_interruptible(&bnx2x_prev_sem);
10287         if (rc) {
10288                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10289                 return rc;
10290         }
10291
10292         /* Check whether the entry for this path already exists */
10293         tmp_list = bnx2x_prev_path_get_entry(bp);
10294         if (tmp_list) {
10295                 if (!tmp_list->aer) {
10296                         BNX2X_ERR("Re-Marking the path.\n");
10297                 } else {
10298                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10299                            BP_PATH(bp));
10300                         tmp_list->aer = 0;
10301                 }
10302                 up(&bnx2x_prev_sem);
10303                 return 0;
10304         }
10305         up(&bnx2x_prev_sem);
10306
10307         /* Create an entry for this path and add it */
10308         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10309         if (!tmp_list) {
10310                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10311                 return -ENOMEM;
10312         }
10313
10314         tmp_list->bus = bp->pdev->bus->number;
10315         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10316         tmp_list->path = BP_PATH(bp);
10317         tmp_list->aer = 0;
10318         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10319
10320         rc = down_interruptible(&bnx2x_prev_sem);
10321         if (rc) {
10322                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10323                 kfree(tmp_list);
10324         } else {
10325                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10326                    BP_PATH(bp));
10327                 list_add(&tmp_list->list, &bnx2x_prev_list);
10328                 up(&bnx2x_prev_sem);
10329         }
10330
10331         return rc;
10332 }
10333
10334 static int bnx2x_do_flr(struct bnx2x *bp)
10335 {
10336         struct pci_dev *dev = bp->pdev;
10337
10338         if (CHIP_IS_E1x(bp)) {
10339                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10340                 return -EINVAL;
10341         }
10342
10343         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10344         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10345                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10346                           bp->common.bc_ver);
10347                 return -EINVAL;
10348         }
10349
10350         if (!pci_wait_for_pending_transaction(dev))
10351                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10352
10353         BNX2X_DEV_INFO("Initiating FLR\n");
10354         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10355
10356         return 0;
10357 }
10358
10359 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10360 {
10361         int rc;
10362
10363         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10364
10365         /* Test if previous unload process was already finished for this path */
10366         if (bnx2x_prev_is_path_marked(bp))
10367                 return bnx2x_prev_mcp_done(bp);
10368
10369         BNX2X_DEV_INFO("Path is unmarked\n");
10370
10371         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10372         if (bnx2x_prev_is_after_undi(bp))
10373                 goto out;
10374
10375         /* If function has FLR capabilities, and existing FW version matches
10376          * the one required, then FLR will be sufficient to clean any residue
10377          * left by previous driver
10378          */
10379         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10380
10381         if (!rc) {
10382                 /* fw version is good */
10383                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10384                 rc = bnx2x_do_flr(bp);
10385         }
10386
10387         if (!rc) {
10388                 /* FLR was performed */
10389                 BNX2X_DEV_INFO("FLR successful\n");
10390                 return 0;
10391         }
10392
10393         BNX2X_DEV_INFO("Could not FLR\n");
10394
10395 out:
10396         /* Close the MCP request, return failure*/
10397         rc = bnx2x_prev_mcp_done(bp);
10398         if (!rc)
10399                 rc = BNX2X_PREV_WAIT_NEEDED;
10400
10401         return rc;
10402 }
10403
10404 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10405 {
10406         u32 reset_reg, tmp_reg = 0, rc;
10407         bool prev_undi = false;
10408         struct bnx2x_mac_vals mac_vals;
10409
10410         /* It is possible a previous function received 'common' answer,
10411          * but hasn't loaded yet, therefore creating a scenario of
10412          * multiple functions receiving 'common' on the same path.
10413          */
10414         BNX2X_DEV_INFO("Common unload Flow\n");
10415
10416         memset(&mac_vals, 0, sizeof(mac_vals));
10417
10418         if (bnx2x_prev_is_path_marked(bp))
10419                 return bnx2x_prev_mcp_done(bp);
10420
10421         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10422
10423         /* Reset should be performed after BRB is emptied */
10424         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10425                 u32 timer_count = 1000;
10426
10427                 /* Close the MAC Rx to prevent BRB from filling up */
10428                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10429
10430                 /* close LLH filters towards the BRB */
10431                 bnx2x_set_rx_filter(&bp->link_params, 0);
10432
10433                 /* Check if the UNDI driver was previously loaded */
10434                 if (bnx2x_prev_is_after_undi(bp)) {
10435                         prev_undi = true;
10436                         /* clear the UNDI indication */
10437                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10438                         /* clear possible idle check errors */
10439                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10440                 }
10441                 if (!CHIP_IS_E1x(bp))
10442                         /* block FW from writing to host */
10443                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10444
10445                 /* wait until BRB is empty */
10446                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10447                 while (timer_count) {
10448                         u32 prev_brb = tmp_reg;
10449
10450                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10451                         if (!tmp_reg)
10452                                 break;
10453
10454                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10455
10456                         /* reset timer as long as BRB actually gets emptied */
10457                         if (prev_brb > tmp_reg)
10458                                 timer_count = 1000;
10459                         else
10460                                 timer_count--;
10461
10462                         /* If UNDI resides in memory, manually increment it */
10463                         if (prev_undi)
10464                                 bnx2x_prev_unload_undi_inc(bp, 1);
10465
10466                         udelay(10);
10467                 }
10468
10469                 if (!timer_count)
10470                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10471         }
10472
10473         /* No packets are in the pipeline, path is ready for reset */
10474         bnx2x_reset_common(bp);
10475
10476         if (mac_vals.xmac_addr)
10477                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10478         if (mac_vals.umac_addr)
10479                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10480         if (mac_vals.emac_addr)
10481                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10482         if (mac_vals.bmac_addr) {
10483                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10484                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10485         }
10486
10487         rc = bnx2x_prev_mark_path(bp, prev_undi);
10488         if (rc) {
10489                 bnx2x_prev_mcp_done(bp);
10490                 return rc;
10491         }
10492
10493         return bnx2x_prev_mcp_done(bp);
10494 }
10495
10496 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10497  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10498  * the addresses of the transaction, resulting in was-error bit set in the pci
10499  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10500  * to clear the interrupt which detected this from the pglueb and the was done
10501  * bit
10502  */
10503 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10504 {
10505         if (!CHIP_IS_E1x(bp)) {
10506                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10507                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10508                         DP(BNX2X_MSG_SP,
10509                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10510                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10511                                1 << BP_FUNC(bp));
10512                 }
10513         }
10514 }
10515
10516 static int bnx2x_prev_unload(struct bnx2x *bp)
10517 {
10518         int time_counter = 10;
10519         u32 rc, fw, hw_lock_reg, hw_lock_val;
10520         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10521
10522         /* clear hw from errors which may have resulted from an interrupted
10523          * dmae transaction.
10524          */
10525         bnx2x_prev_interrupted_dmae(bp);
10526
10527         /* Release previously held locks */
10528         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10529                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10530                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10531
10532         hw_lock_val = REG_RD(bp, hw_lock_reg);
10533         if (hw_lock_val) {
10534                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10535                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10536                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10537                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10538                 }
10539
10540                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10541                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10542         } else
10543                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10544
10545         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10546                 BNX2X_DEV_INFO("Release previously held alr\n");
10547                 bnx2x_release_alr(bp);
10548         }
10549
10550         do {
10551                 int aer = 0;
10552                 /* Lock MCP using an unload request */
10553                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10554                 if (!fw) {
10555                         BNX2X_ERR("MCP response failure, aborting\n");
10556                         rc = -EBUSY;
10557                         break;
10558                 }
10559
10560                 rc = down_interruptible(&bnx2x_prev_sem);
10561                 if (rc) {
10562                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10563                                   rc);
10564                 } else {
10565                         /* If Path is marked by EEH, ignore unload status */
10566                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10567                                  bnx2x_prev_path_get_entry(bp)->aer);
10568                         up(&bnx2x_prev_sem);
10569                 }
10570
10571                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10572                         rc = bnx2x_prev_unload_common(bp);
10573                         break;
10574                 }
10575
10576                 /* non-common reply from MCP might require looping */
10577                 rc = bnx2x_prev_unload_uncommon(bp);
10578                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10579                         break;
10580
10581                 msleep(20);
10582         } while (--time_counter);
10583
10584         if (!time_counter || rc) {
10585                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10586                 rc = -EPROBE_DEFER;
10587         }
10588
10589         /* Mark function if its port was used to boot from SAN */
10590         if (bnx2x_port_after_undi(bp))
10591                 bp->link_params.feature_config_flags |=
10592                         FEATURE_CONFIG_BOOT_FROM_SAN;
10593
10594         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10595
10596         return rc;
10597 }
10598
10599 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10600 {
10601         u32 val, val2, val3, val4, id, boot_mode;
10602         u16 pmc;
10603
10604         /* Get the chip revision id and number. */
10605         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10606         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10607         id = ((val & 0xffff) << 16);
10608         val = REG_RD(bp, MISC_REG_CHIP_REV);
10609         id |= ((val & 0xf) << 12);
10610
10611         /* Metal is read from PCI regs, but we can't access >=0x400 from
10612          * the configuration space (so we need to reg_rd)
10613          */
10614         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10615         id |= (((val >> 24) & 0xf) << 4);
10616         val = REG_RD(bp, MISC_REG_BOND_ID);
10617         id |= (val & 0xf);
10618         bp->common.chip_id = id;
10619
10620         /* force 57811 according to MISC register */
10621         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10622                 if (CHIP_IS_57810(bp))
10623                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10624                                 (bp->common.chip_id & 0x0000FFFF);
10625                 else if (CHIP_IS_57810_MF(bp))
10626                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10627                                 (bp->common.chip_id & 0x0000FFFF);
10628                 bp->common.chip_id |= 0x1;
10629         }
10630
10631         /* Set doorbell size */
10632         bp->db_size = (1 << BNX2X_DB_SHIFT);
10633
10634         if (!CHIP_IS_E1x(bp)) {
10635                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10636                 if ((val & 1) == 0)
10637                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10638                 else
10639                         val = (val >> 1) & 1;
10640                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10641                                                        "2_PORT_MODE");
10642                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10643                                                  CHIP_2_PORT_MODE;
10644
10645                 if (CHIP_MODE_IS_4_PORT(bp))
10646                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10647                 else
10648                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10649         } else {
10650                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10651                 bp->pfid = bp->pf_num;                  /* 0..7 */
10652         }
10653
10654         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10655
10656         bp->link_params.chip_id = bp->common.chip_id;
10657         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10658
10659         val = (REG_RD(bp, 0x2874) & 0x55);
10660         if ((bp->common.chip_id & 0x1) ||
10661             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10662                 bp->flags |= ONE_PORT_FLAG;
10663                 BNX2X_DEV_INFO("single port device\n");
10664         }
10665
10666         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10667         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10668                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10669         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10670                        bp->common.flash_size, bp->common.flash_size);
10671
10672         bnx2x_init_shmem(bp);
10673
10674         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10675                                         MISC_REG_GENERIC_CR_1 :
10676                                         MISC_REG_GENERIC_CR_0));
10677
10678         bp->link_params.shmem_base = bp->common.shmem_base;
10679         bp->link_params.shmem2_base = bp->common.shmem2_base;
10680         if (SHMEM2_RD(bp, size) >
10681             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10682                 bp->link_params.lfa_base =
10683                 REG_RD(bp, bp->common.shmem2_base +
10684                        (u32)offsetof(struct shmem2_region,
10685                                      lfa_host_addr[BP_PORT(bp)]));
10686         else
10687                 bp->link_params.lfa_base = 0;
10688         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10689                        bp->common.shmem_base, bp->common.shmem2_base);
10690
10691         if (!bp->common.shmem_base) {
10692                 BNX2X_DEV_INFO("MCP not active\n");
10693                 bp->flags |= NO_MCP_FLAG;
10694                 return;
10695         }
10696
10697         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10698         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10699
10700         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10701                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10702                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10703
10704         bp->link_params.feature_config_flags = 0;
10705         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10706         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10707                 bp->link_params.feature_config_flags |=
10708                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10709         else
10710                 bp->link_params.feature_config_flags &=
10711                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10712
10713         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10714         bp->common.bc_ver = val;
10715         BNX2X_DEV_INFO("bc_ver %X\n", val);
10716         if (val < BNX2X_BC_VER) {
10717                 /* for now only warn
10718                  * later we might need to enforce this */
10719                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10720                           BNX2X_BC_VER, val);
10721         }
10722         bp->link_params.feature_config_flags |=
10723                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10724                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10725
10726         bp->link_params.feature_config_flags |=
10727                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10728                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10729         bp->link_params.feature_config_flags |=
10730                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10731                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10732         bp->link_params.feature_config_flags |=
10733                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10734                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10735
10736         bp->link_params.feature_config_flags |=
10737                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10738                 FEATURE_CONFIG_MT_SUPPORT : 0;
10739
10740         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10741                         BC_SUPPORTS_PFC_STATS : 0;
10742
10743         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10744                         BC_SUPPORTS_FCOE_FEATURES : 0;
10745
10746         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10747                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10748
10749         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10750                         BC_SUPPORTS_RMMOD_CMD : 0;
10751
10752         boot_mode = SHMEM_RD(bp,
10753                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10754                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10755         switch (boot_mode) {
10756         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10757                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10758                 break;
10759         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10760                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10761                 break;
10762         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10763                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10764                 break;
10765         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10766                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10767                 break;
10768         }
10769
10770         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10771         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10772
10773         BNX2X_DEV_INFO("%sWoL capable\n",
10774                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10775
10776         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10777         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10778         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10779         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10780
10781         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10782                  val, val2, val3, val4);
10783 }
10784
10785 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10786 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10787
10788 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10789 {
10790         int pfid = BP_FUNC(bp);
10791         int igu_sb_id;
10792         u32 val;
10793         u8 fid, igu_sb_cnt = 0;
10794
10795         bp->igu_base_sb = 0xff;
10796         if (CHIP_INT_MODE_IS_BC(bp)) {
10797                 int vn = BP_VN(bp);
10798                 igu_sb_cnt = bp->igu_sb_cnt;
10799                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10800                         FP_SB_MAX_E1x;
10801
10802                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10803                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10804
10805                 return 0;
10806         }
10807
10808         /* IGU in normal mode - read CAM */
10809         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10810              igu_sb_id++) {
10811                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10812                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10813                         continue;
10814                 fid = IGU_FID(val);
10815                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10816                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10817                                 continue;
10818                         if (IGU_VEC(val) == 0)
10819                                 /* default status block */
10820                                 bp->igu_dsb_id = igu_sb_id;
10821                         else {
10822                                 if (bp->igu_base_sb == 0xff)
10823                                         bp->igu_base_sb = igu_sb_id;
10824                                 igu_sb_cnt++;
10825                         }
10826                 }
10827         }
10828
10829 #ifdef CONFIG_PCI_MSI
10830         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10831          * optional that number of CAM entries will not be equal to the value
10832          * advertised in PCI.
10833          * Driver should use the minimal value of both as the actual status
10834          * block count
10835          */
10836         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10837 #endif
10838
10839         if (igu_sb_cnt == 0) {
10840                 BNX2X_ERR("CAM configuration error\n");
10841                 return -EINVAL;
10842         }
10843
10844         return 0;
10845 }
10846
10847 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10848 {
10849         int cfg_size = 0, idx, port = BP_PORT(bp);
10850
10851         /* Aggregation of supported attributes of all external phys */
10852         bp->port.supported[0] = 0;
10853         bp->port.supported[1] = 0;
10854         switch (bp->link_params.num_phys) {
10855         case 1:
10856                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10857                 cfg_size = 1;
10858                 break;
10859         case 2:
10860                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10861                 cfg_size = 1;
10862                 break;
10863         case 3:
10864                 if (bp->link_params.multi_phy_config &
10865                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10866                         bp->port.supported[1] =
10867                                 bp->link_params.phy[EXT_PHY1].supported;
10868                         bp->port.supported[0] =
10869                                 bp->link_params.phy[EXT_PHY2].supported;
10870                 } else {
10871                         bp->port.supported[0] =
10872                                 bp->link_params.phy[EXT_PHY1].supported;
10873                         bp->port.supported[1] =
10874                                 bp->link_params.phy[EXT_PHY2].supported;
10875                 }
10876                 cfg_size = 2;
10877                 break;
10878         }
10879
10880         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10881                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10882                            SHMEM_RD(bp,
10883                            dev_info.port_hw_config[port].external_phy_config),
10884                            SHMEM_RD(bp,
10885                            dev_info.port_hw_config[port].external_phy_config2));
10886                         return;
10887         }
10888
10889         if (CHIP_IS_E3(bp))
10890                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10891         else {
10892                 switch (switch_cfg) {
10893                 case SWITCH_CFG_1G:
10894                         bp->port.phy_addr = REG_RD(
10895                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10896                         break;
10897                 case SWITCH_CFG_10G:
10898                         bp->port.phy_addr = REG_RD(
10899                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10900                         break;
10901                 default:
10902                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10903                                   bp->port.link_config[0]);
10904                         return;
10905                 }
10906         }
10907         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10908         /* mask what we support according to speed_cap_mask per configuration */
10909         for (idx = 0; idx < cfg_size; idx++) {
10910                 if (!(bp->link_params.speed_cap_mask[idx] &
10911                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10912                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10913
10914                 if (!(bp->link_params.speed_cap_mask[idx] &
10915                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10916                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10917
10918                 if (!(bp->link_params.speed_cap_mask[idx] &
10919                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10920                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10921
10922                 if (!(bp->link_params.speed_cap_mask[idx] &
10923                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10924                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10925
10926                 if (!(bp->link_params.speed_cap_mask[idx] &
10927                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10928                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10929                                                      SUPPORTED_1000baseT_Full);
10930
10931                 if (!(bp->link_params.speed_cap_mask[idx] &
10932                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10933                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10934
10935                 if (!(bp->link_params.speed_cap_mask[idx] &
10936                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10937                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10938
10939                 if (!(bp->link_params.speed_cap_mask[idx] &
10940                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10941                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10942         }
10943
10944         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10945                        bp->port.supported[1]);
10946 }
10947
10948 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10949 {
10950         u32 link_config, idx, cfg_size = 0;
10951         bp->port.advertising[0] = 0;
10952         bp->port.advertising[1] = 0;
10953         switch (bp->link_params.num_phys) {
10954         case 1:
10955         case 2:
10956                 cfg_size = 1;
10957                 break;
10958         case 3:
10959                 cfg_size = 2;
10960                 break;
10961         }
10962         for (idx = 0; idx < cfg_size; idx++) {
10963                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10964                 link_config = bp->port.link_config[idx];
10965                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10966                 case PORT_FEATURE_LINK_SPEED_AUTO:
10967                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10968                                 bp->link_params.req_line_speed[idx] =
10969                                         SPEED_AUTO_NEG;
10970                                 bp->port.advertising[idx] |=
10971                                         bp->port.supported[idx];
10972                                 if (bp->link_params.phy[EXT_PHY1].type ==
10973                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10974                                         bp->port.advertising[idx] |=
10975                                         (SUPPORTED_100baseT_Half |
10976                                          SUPPORTED_100baseT_Full);
10977                         } else {
10978                                 /* force 10G, no AN */
10979                                 bp->link_params.req_line_speed[idx] =
10980                                         SPEED_10000;
10981                                 bp->port.advertising[idx] |=
10982                                         (ADVERTISED_10000baseT_Full |
10983                                          ADVERTISED_FIBRE);
10984                                 continue;
10985                         }
10986                         break;
10987
10988                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10989                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10990                                 bp->link_params.req_line_speed[idx] =
10991                                         SPEED_10;
10992                                 bp->port.advertising[idx] |=
10993                                         (ADVERTISED_10baseT_Full |
10994                                          ADVERTISED_TP);
10995                         } else {
10996                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10997                                             link_config,
10998                                     bp->link_params.speed_cap_mask[idx]);
10999                                 return;
11000                         }
11001                         break;
11002
11003                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11004                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11005                                 bp->link_params.req_line_speed[idx] =
11006                                         SPEED_10;
11007                                 bp->link_params.req_duplex[idx] =
11008                                         DUPLEX_HALF;
11009                                 bp->port.advertising[idx] |=
11010                                         (ADVERTISED_10baseT_Half |
11011                                          ADVERTISED_TP);
11012                         } else {
11013                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11014                                             link_config,
11015                                           bp->link_params.speed_cap_mask[idx]);
11016                                 return;
11017                         }
11018                         break;
11019
11020                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11021                         if (bp->port.supported[idx] &
11022                             SUPPORTED_100baseT_Full) {
11023                                 bp->link_params.req_line_speed[idx] =
11024                                         SPEED_100;
11025                                 bp->port.advertising[idx] |=
11026                                         (ADVERTISED_100baseT_Full |
11027                                          ADVERTISED_TP);
11028                         } else {
11029                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11030                                             link_config,
11031                                           bp->link_params.speed_cap_mask[idx]);
11032                                 return;
11033                         }
11034                         break;
11035
11036                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11037                         if (bp->port.supported[idx] &
11038                             SUPPORTED_100baseT_Half) {
11039                                 bp->link_params.req_line_speed[idx] =
11040                                                                 SPEED_100;
11041                                 bp->link_params.req_duplex[idx] =
11042                                                                 DUPLEX_HALF;
11043                                 bp->port.advertising[idx] |=
11044                                         (ADVERTISED_100baseT_Half |
11045                                          ADVERTISED_TP);
11046                         } else {
11047                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11048                                     link_config,
11049                                     bp->link_params.speed_cap_mask[idx]);
11050                                 return;
11051                         }
11052                         break;
11053
11054                 case PORT_FEATURE_LINK_SPEED_1G:
11055                         if (bp->port.supported[idx] &
11056                             SUPPORTED_1000baseT_Full) {
11057                                 bp->link_params.req_line_speed[idx] =
11058                                         SPEED_1000;
11059                                 bp->port.advertising[idx] |=
11060                                         (ADVERTISED_1000baseT_Full |
11061                                          ADVERTISED_TP);
11062                         } else {
11063                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11064                                     link_config,
11065                                     bp->link_params.speed_cap_mask[idx]);
11066                                 return;
11067                         }
11068                         break;
11069
11070                 case PORT_FEATURE_LINK_SPEED_2_5G:
11071                         if (bp->port.supported[idx] &
11072                             SUPPORTED_2500baseX_Full) {
11073                                 bp->link_params.req_line_speed[idx] =
11074                                         SPEED_2500;
11075                                 bp->port.advertising[idx] |=
11076                                         (ADVERTISED_2500baseX_Full |
11077                                                 ADVERTISED_TP);
11078                         } else {
11079                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11080                                     link_config,
11081                                     bp->link_params.speed_cap_mask[idx]);
11082                                 return;
11083                         }
11084                         break;
11085
11086                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11087                         if (bp->port.supported[idx] &
11088                             SUPPORTED_10000baseT_Full) {
11089                                 bp->link_params.req_line_speed[idx] =
11090                                         SPEED_10000;
11091                                 bp->port.advertising[idx] |=
11092                                         (ADVERTISED_10000baseT_Full |
11093                                                 ADVERTISED_FIBRE);
11094                         } else {
11095                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11096                                     link_config,
11097                                     bp->link_params.speed_cap_mask[idx]);
11098                                 return;
11099                         }
11100                         break;
11101                 case PORT_FEATURE_LINK_SPEED_20G:
11102                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11103
11104                         break;
11105                 default:
11106                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11107                                   link_config);
11108                                 bp->link_params.req_line_speed[idx] =
11109                                                         SPEED_AUTO_NEG;
11110                                 bp->port.advertising[idx] =
11111                                                 bp->port.supported[idx];
11112                         break;
11113                 }
11114
11115                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11116                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11117                 if (bp->link_params.req_flow_ctrl[idx] ==
11118                     BNX2X_FLOW_CTRL_AUTO) {
11119                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11120                                 bp->link_params.req_flow_ctrl[idx] =
11121                                                         BNX2X_FLOW_CTRL_NONE;
11122                         else
11123                                 bnx2x_set_requested_fc(bp);
11124                 }
11125
11126                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11127                                bp->link_params.req_line_speed[idx],
11128                                bp->link_params.req_duplex[idx],
11129                                bp->link_params.req_flow_ctrl[idx],
11130                                bp->port.advertising[idx]);
11131         }
11132 }
11133
11134 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11135 {
11136         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11137         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11138         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11139         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11140 }
11141
11142 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11143 {
11144         int port = BP_PORT(bp);
11145         u32 config;
11146         u32 ext_phy_type, ext_phy_config, eee_mode;
11147
11148         bp->link_params.bp = bp;
11149         bp->link_params.port = port;
11150
11151         bp->link_params.lane_config =
11152                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11153
11154         bp->link_params.speed_cap_mask[0] =
11155                 SHMEM_RD(bp,
11156                          dev_info.port_hw_config[port].speed_capability_mask) &
11157                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11158         bp->link_params.speed_cap_mask[1] =
11159                 SHMEM_RD(bp,
11160                          dev_info.port_hw_config[port].speed_capability_mask2) &
11161                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11162         bp->port.link_config[0] =
11163                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11164
11165         bp->port.link_config[1] =
11166                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11167
11168         bp->link_params.multi_phy_config =
11169                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11170         /* If the device is capable of WoL, set the default state according
11171          * to the HW
11172          */
11173         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11174         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11175                    (config & PORT_FEATURE_WOL_ENABLED));
11176
11177         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11178             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11179                 bp->flags |= NO_ISCSI_FLAG;
11180         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11181             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11182                 bp->flags |= NO_FCOE_FLAG;
11183
11184         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11185                        bp->link_params.lane_config,
11186                        bp->link_params.speed_cap_mask[0],
11187                        bp->port.link_config[0]);
11188
11189         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11190                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11191         bnx2x_phy_probe(&bp->link_params);
11192         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11193
11194         bnx2x_link_settings_requested(bp);
11195
11196         /*
11197          * If connected directly, work with the internal PHY, otherwise, work
11198          * with the external PHY
11199          */
11200         ext_phy_config =
11201                 SHMEM_RD(bp,
11202                          dev_info.port_hw_config[port].external_phy_config);
11203         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11204         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11205                 bp->mdio.prtad = bp->port.phy_addr;
11206
11207         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11208                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11209                 bp->mdio.prtad =
11210                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11211
11212         /* Configure link feature according to nvram value */
11213         eee_mode = (((SHMEM_RD(bp, dev_info.
11214                       port_feature_config[port].eee_power_mode)) &
11215                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11216                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11217         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11218                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11219                                            EEE_MODE_ENABLE_LPI |
11220                                            EEE_MODE_OUTPUT_TIME;
11221         } else {
11222                 bp->link_params.eee_mode = 0;
11223         }
11224 }
11225
11226 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11227 {
11228         u32 no_flags = NO_ISCSI_FLAG;
11229         int port = BP_PORT(bp);
11230         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11231                                 drv_lic_key[port].max_iscsi_conn);
11232
11233         if (!CNIC_SUPPORT(bp)) {
11234                 bp->flags |= no_flags;
11235                 return;
11236         }
11237
11238         /* Get the number of maximum allowed iSCSI connections */
11239         bp->cnic_eth_dev.max_iscsi_conn =
11240                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11241                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11242
11243         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11244                        bp->cnic_eth_dev.max_iscsi_conn);
11245
11246         /*
11247          * If maximum allowed number of connections is zero -
11248          * disable the feature.
11249          */
11250         if (!bp->cnic_eth_dev.max_iscsi_conn)
11251                 bp->flags |= no_flags;
11252 }
11253
11254 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11255 {
11256         /* Port info */
11257         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11258                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11259         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11260                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11261
11262         /* Node info */
11263         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11264                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11265         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11266                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11267 }
11268
11269 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11270 {
11271         u8 count = 0;
11272
11273         if (IS_MF(bp)) {
11274                 u8 fid;
11275
11276                 /* iterate over absolute function ids for this path: */
11277                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11278                         if (IS_MF_SD(bp)) {
11279                                 u32 cfg = MF_CFG_RD(bp,
11280                                                     func_mf_config[fid].config);
11281
11282                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11283                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11284                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11285                                         count++;
11286                         } else {
11287                                 u32 cfg = MF_CFG_RD(bp,
11288                                                     func_ext_config[fid].
11289                                                                       func_cfg);
11290
11291                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11292                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11293                                         count++;
11294                         }
11295                 }
11296         } else { /* SF */
11297                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11298
11299                 for (port = 0; port < port_cnt; port++) {
11300                         u32 lic = SHMEM_RD(bp,
11301                                            drv_lic_key[port].max_fcoe_conn) ^
11302                                   FW_ENCODE_32BIT_PATTERN;
11303                         if (lic)
11304                                 count++;
11305                 }
11306         }
11307
11308         return count;
11309 }
11310
11311 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11312 {
11313         int port = BP_PORT(bp);
11314         int func = BP_ABS_FUNC(bp);
11315         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11316                                 drv_lic_key[port].max_fcoe_conn);
11317         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11318
11319         if (!CNIC_SUPPORT(bp)) {
11320                 bp->flags |= NO_FCOE_FLAG;
11321                 return;
11322         }
11323
11324         /* Get the number of maximum allowed FCoE connections */
11325         bp->cnic_eth_dev.max_fcoe_conn =
11326                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11327                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11328
11329         /* Calculate the number of maximum allowed FCoE tasks */
11330         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11331
11332         /* check if FCoE resources must be shared between different functions */
11333         if (num_fcoe_func)
11334                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11335
11336         /* Read the WWN: */
11337         if (!IS_MF(bp)) {
11338                 /* Port info */
11339                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11340                         SHMEM_RD(bp,
11341                                  dev_info.port_hw_config[port].
11342                                  fcoe_wwn_port_name_upper);
11343                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11344                         SHMEM_RD(bp,
11345                                  dev_info.port_hw_config[port].
11346                                  fcoe_wwn_port_name_lower);
11347
11348                 /* Node info */
11349                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11350                         SHMEM_RD(bp,
11351                                  dev_info.port_hw_config[port].
11352                                  fcoe_wwn_node_name_upper);
11353                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11354                         SHMEM_RD(bp,
11355                                  dev_info.port_hw_config[port].
11356                                  fcoe_wwn_node_name_lower);
11357         } else if (!IS_MF_SD(bp)) {
11358                 /*
11359                  * Read the WWN info only if the FCoE feature is enabled for
11360                  * this function.
11361                  */
11362                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11363                         bnx2x_get_ext_wwn_info(bp, func);
11364
11365         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11366                 bnx2x_get_ext_wwn_info(bp, func);
11367         }
11368
11369         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11370
11371         /*
11372          * If maximum allowed number of connections is zero -
11373          * disable the feature.
11374          */
11375         if (!bp->cnic_eth_dev.max_fcoe_conn)
11376                 bp->flags |= NO_FCOE_FLAG;
11377 }
11378
11379 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11380 {
11381         /*
11382          * iSCSI may be dynamically disabled but reading
11383          * info here we will decrease memory usage by driver
11384          * if the feature is disabled for good
11385          */
11386         bnx2x_get_iscsi_info(bp);
11387         bnx2x_get_fcoe_info(bp);
11388 }
11389
11390 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11391 {
11392         u32 val, val2;
11393         int func = BP_ABS_FUNC(bp);
11394         int port = BP_PORT(bp);
11395         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11396         u8 *fip_mac = bp->fip_mac;
11397
11398         if (IS_MF(bp)) {
11399                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11400                  * FCoE MAC then the appropriate feature should be disabled.
11401                  * In non SD mode features configuration comes from struct
11402                  * func_ext_config.
11403                  */
11404                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11405                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11406                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11407                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11408                                                  iscsi_mac_addr_upper);
11409                                 val = MF_CFG_RD(bp, func_ext_config[func].
11410                                                 iscsi_mac_addr_lower);
11411                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11412                                 BNX2X_DEV_INFO
11413                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11414                         } else {
11415                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11416                         }
11417
11418                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11419                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11420                                                  fcoe_mac_addr_upper);
11421                                 val = MF_CFG_RD(bp, func_ext_config[func].
11422                                                 fcoe_mac_addr_lower);
11423                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11424                                 BNX2X_DEV_INFO
11425                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11426                         } else {
11427                                 bp->flags |= NO_FCOE_FLAG;
11428                         }
11429
11430                         bp->mf_ext_config = cfg;
11431
11432                 } else { /* SD MODE */
11433                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11434                                 /* use primary mac as iscsi mac */
11435                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11436
11437                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11438                                 BNX2X_DEV_INFO
11439                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11440                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11441                                 /* use primary mac as fip mac */
11442                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11443                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11444                                 BNX2X_DEV_INFO
11445                                         ("Read FIP MAC: %pM\n", fip_mac);
11446                         }
11447                 }
11448
11449                 /* If this is a storage-only interface, use SAN mac as
11450                  * primary MAC. Notice that for SD this is already the case,
11451                  * as the SAN mac was copied from the primary MAC.
11452                  */
11453                 if (IS_MF_FCOE_AFEX(bp))
11454                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11455         } else {
11456                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11457                                 iscsi_mac_upper);
11458                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11459                                iscsi_mac_lower);
11460                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11461
11462                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11463                                 fcoe_fip_mac_upper);
11464                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11465                                fcoe_fip_mac_lower);
11466                 bnx2x_set_mac_buf(fip_mac, val, val2);
11467         }
11468
11469         /* Disable iSCSI OOO if MAC configuration is invalid. */
11470         if (!is_valid_ether_addr(iscsi_mac)) {
11471                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11472                 memset(iscsi_mac, 0, ETH_ALEN);
11473         }
11474
11475         /* Disable FCoE if MAC configuration is invalid. */
11476         if (!is_valid_ether_addr(fip_mac)) {
11477                 bp->flags |= NO_FCOE_FLAG;
11478                 memset(bp->fip_mac, 0, ETH_ALEN);
11479         }
11480 }
11481
11482 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11483 {
11484         u32 val, val2;
11485         int func = BP_ABS_FUNC(bp);
11486         int port = BP_PORT(bp);
11487
11488         /* Zero primary MAC configuration */
11489         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11490
11491         if (BP_NOMCP(bp)) {
11492                 BNX2X_ERROR("warning: random MAC workaround active\n");
11493                 eth_hw_addr_random(bp->dev);
11494         } else if (IS_MF(bp)) {
11495                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11496                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11497                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11498                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11499                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11500
11501                 if (CNIC_SUPPORT(bp))
11502                         bnx2x_get_cnic_mac_hwinfo(bp);
11503         } else {
11504                 /* in SF read MACs from port configuration */
11505                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11506                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11507                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11508
11509                 if (CNIC_SUPPORT(bp))
11510                         bnx2x_get_cnic_mac_hwinfo(bp);
11511         }
11512
11513         if (!BP_NOMCP(bp)) {
11514                 /* Read physical port identifier from shmem */
11515                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11516                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11517                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11518                 bp->flags |= HAS_PHYS_PORT_ID;
11519         }
11520
11521         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11522
11523         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11524                 dev_err(&bp->pdev->dev,
11525                         "bad Ethernet MAC address configuration: %pM\n"
11526                         "change it manually before bringing up the appropriate network interface\n",
11527                         bp->dev->dev_addr);
11528 }
11529
11530 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11531 {
11532         int tmp;
11533         u32 cfg;
11534
11535         if (IS_VF(bp))
11536                 return 0;
11537
11538         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11539                 /* Take function: tmp = func */
11540                 tmp = BP_ABS_FUNC(bp);
11541                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11542                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11543         } else {
11544                 /* Take port: tmp = port */
11545                 tmp = BP_PORT(bp);
11546                 cfg = SHMEM_RD(bp,
11547                                dev_info.port_hw_config[tmp].generic_features);
11548                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11549         }
11550         return cfg;
11551 }
11552
11553 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11554 {
11555         int /*abs*/func = BP_ABS_FUNC(bp);
11556         int vn;
11557         u32 val = 0;
11558         int rc = 0;
11559
11560         bnx2x_get_common_hwinfo(bp);
11561
11562         /*
11563          * initialize IGU parameters
11564          */
11565         if (CHIP_IS_E1x(bp)) {
11566                 bp->common.int_block = INT_BLOCK_HC;
11567
11568                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11569                 bp->igu_base_sb = 0;
11570         } else {
11571                 bp->common.int_block = INT_BLOCK_IGU;
11572
11573                 /* do not allow device reset during IGU info processing */
11574                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11575
11576                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11577
11578                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11579                         int tout = 5000;
11580
11581                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11582
11583                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11584                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11585                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11586
11587                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11588                                 tout--;
11589                                 usleep_range(1000, 2000);
11590                         }
11591
11592                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11593                                 dev_err(&bp->pdev->dev,
11594                                         "FORCING Normal Mode failed!!!\n");
11595                                 bnx2x_release_hw_lock(bp,
11596                                                       HW_LOCK_RESOURCE_RESET);
11597                                 return -EPERM;
11598                         }
11599                 }
11600
11601                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11602                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11603                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11604                 } else
11605                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11606
11607                 rc = bnx2x_get_igu_cam_info(bp);
11608                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11609                 if (rc)
11610                         return rc;
11611         }
11612
11613         /*
11614          * set base FW non-default (fast path) status block id, this value is
11615          * used to initialize the fw_sb_id saved on the fp/queue structure to
11616          * determine the id used by the FW.
11617          */
11618         if (CHIP_IS_E1x(bp))
11619                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11620         else /*
11621               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11622               * the same queue are indicated on the same IGU SB). So we prefer
11623               * FW and IGU SBs to be the same value.
11624               */
11625                 bp->base_fw_ndsb = bp->igu_base_sb;
11626
11627         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11628                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11629                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11630
11631         /*
11632          * Initialize MF configuration
11633          */
11634
11635         bp->mf_ov = 0;
11636         bp->mf_mode = 0;
11637         vn = BP_VN(bp);
11638
11639         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11640                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11641                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11642                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11643
11644                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11645                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11646                 else
11647                         bp->common.mf_cfg_base = bp->common.shmem_base +
11648                                 offsetof(struct shmem_region, func_mb) +
11649                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11650                 /*
11651                  * get mf configuration:
11652                  * 1. Existence of MF configuration
11653                  * 2. MAC address must be legal (check only upper bytes)
11654                  *    for  Switch-Independent mode;
11655                  *    OVLAN must be legal for Switch-Dependent mode
11656                  * 3. SF_MODE configures specific MF mode
11657                  */
11658                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11659                         /* get mf configuration */
11660                         val = SHMEM_RD(bp,
11661                                        dev_info.shared_feature_config.config);
11662                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11663
11664                         switch (val) {
11665                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11666                                 val = MF_CFG_RD(bp, func_mf_config[func].
11667                                                 mac_upper);
11668                                 /* check for legal mac (upper bytes)*/
11669                                 if (val != 0xffff) {
11670                                         bp->mf_mode = MULTI_FUNCTION_SI;
11671                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11672                                                    func_mf_config[func].config);
11673                                 } else
11674                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11675                                 break;
11676                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11677                                 if ((!CHIP_IS_E1x(bp)) &&
11678                                     (MF_CFG_RD(bp, func_mf_config[func].
11679                                                mac_upper) != 0xffff) &&
11680                                     (SHMEM2_HAS(bp,
11681                                                 afex_driver_support))) {
11682                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11683                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11684                                                 func_mf_config[func].config);
11685                                 } else {
11686                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11687                                 }
11688                                 break;
11689                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11690                                 /* get OV configuration */
11691                                 val = MF_CFG_RD(bp,
11692                                         func_mf_config[FUNC_0].e1hov_tag);
11693                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11694
11695                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11696                                         bp->mf_mode = MULTI_FUNCTION_SD;
11697                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11698                                                 func_mf_config[func].config);
11699                                 } else
11700                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11701                                 break;
11702                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11703                                 bp->mf_config[vn] = 0;
11704                                 break;
11705                         default:
11706                                 /* Unknown configuration: reset mf_config */
11707                                 bp->mf_config[vn] = 0;
11708                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11709                         }
11710                 }
11711
11712                 BNX2X_DEV_INFO("%s function mode\n",
11713                                IS_MF(bp) ? "multi" : "single");
11714
11715                 switch (bp->mf_mode) {
11716                 case MULTI_FUNCTION_SD:
11717                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11718                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11719                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11720                                 bp->mf_ov = val;
11721                                 bp->path_has_ovlan = true;
11722
11723                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11724                                                func, bp->mf_ov, bp->mf_ov);
11725                         } else {
11726                                 dev_err(&bp->pdev->dev,
11727                                         "No valid MF OV for func %d, aborting\n",
11728                                         func);
11729                                 return -EPERM;
11730                         }
11731                         break;
11732                 case MULTI_FUNCTION_AFEX:
11733                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11734                         break;
11735                 case MULTI_FUNCTION_SI:
11736                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11737                                        func);
11738                         break;
11739                 default:
11740                         if (vn) {
11741                                 dev_err(&bp->pdev->dev,
11742                                         "VN %d is in a single function mode, aborting\n",
11743                                         vn);
11744                                 return -EPERM;
11745                         }
11746                         break;
11747                 }
11748
11749                 /* check if other port on the path needs ovlan:
11750                  * Since MF configuration is shared between ports
11751                  * Possible mixed modes are only
11752                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11753                  */
11754                 if (CHIP_MODE_IS_4_PORT(bp) &&
11755                     !bp->path_has_ovlan &&
11756                     !IS_MF(bp) &&
11757                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11758                         u8 other_port = !BP_PORT(bp);
11759                         u8 other_func = BP_PATH(bp) + 2*other_port;
11760                         val = MF_CFG_RD(bp,
11761                                         func_mf_config[other_func].e1hov_tag);
11762                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11763                                 bp->path_has_ovlan = true;
11764                 }
11765         }
11766
11767         /* adjust igu_sb_cnt to MF for E1H */
11768         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11769                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11770
11771         /* port info */
11772         bnx2x_get_port_hwinfo(bp);
11773
11774         /* Get MAC addresses */
11775         bnx2x_get_mac_hwinfo(bp);
11776
11777         bnx2x_get_cnic_info(bp);
11778
11779         return rc;
11780 }
11781
11782 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11783 {
11784         int cnt, i, block_end, rodi;
11785         char vpd_start[BNX2X_VPD_LEN+1];
11786         char str_id_reg[VENDOR_ID_LEN+1];
11787         char str_id_cap[VENDOR_ID_LEN+1];
11788         char *vpd_data;
11789         char *vpd_extended_data = NULL;
11790         u8 len;
11791
11792         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11793         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11794
11795         if (cnt < BNX2X_VPD_LEN)
11796                 goto out_not_found;
11797
11798         /* VPD RO tag should be first tag after identifier string, hence
11799          * we should be able to find it in first BNX2X_VPD_LEN chars
11800          */
11801         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11802                              PCI_VPD_LRDT_RO_DATA);
11803         if (i < 0)
11804                 goto out_not_found;
11805
11806         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11807                     pci_vpd_lrdt_size(&vpd_start[i]);
11808
11809         i += PCI_VPD_LRDT_TAG_SIZE;
11810
11811         if (block_end > BNX2X_VPD_LEN) {
11812                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11813                 if (vpd_extended_data  == NULL)
11814                         goto out_not_found;
11815
11816                 /* read rest of vpd image into vpd_extended_data */
11817                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11818                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11819                                    block_end - BNX2X_VPD_LEN,
11820                                    vpd_extended_data + BNX2X_VPD_LEN);
11821                 if (cnt < (block_end - BNX2X_VPD_LEN))
11822                         goto out_not_found;
11823                 vpd_data = vpd_extended_data;
11824         } else
11825                 vpd_data = vpd_start;
11826
11827         /* now vpd_data holds full vpd content in both cases */
11828
11829         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11830                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11831         if (rodi < 0)
11832                 goto out_not_found;
11833
11834         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11835
11836         if (len != VENDOR_ID_LEN)
11837                 goto out_not_found;
11838
11839         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11840
11841         /* vendor specific info */
11842         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11843         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11844         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11845             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11846
11847                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11848                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11849                 if (rodi >= 0) {
11850                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11851
11852                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11853
11854                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11855                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11856                                 bp->fw_ver[len] = ' ';
11857                         }
11858                 }
11859                 kfree(vpd_extended_data);
11860                 return;
11861         }
11862 out_not_found:
11863         kfree(vpd_extended_data);
11864         return;
11865 }
11866
11867 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11868 {
11869         u32 flags = 0;
11870
11871         if (CHIP_REV_IS_FPGA(bp))
11872                 SET_FLAGS(flags, MODE_FPGA);
11873         else if (CHIP_REV_IS_EMUL(bp))
11874                 SET_FLAGS(flags, MODE_EMUL);
11875         else
11876                 SET_FLAGS(flags, MODE_ASIC);
11877
11878         if (CHIP_MODE_IS_4_PORT(bp))
11879                 SET_FLAGS(flags, MODE_PORT4);
11880         else
11881                 SET_FLAGS(flags, MODE_PORT2);
11882
11883         if (CHIP_IS_E2(bp))
11884                 SET_FLAGS(flags, MODE_E2);
11885         else if (CHIP_IS_E3(bp)) {
11886                 SET_FLAGS(flags, MODE_E3);
11887                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11888                         SET_FLAGS(flags, MODE_E3_A0);
11889                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11890                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11891         }
11892
11893         if (IS_MF(bp)) {
11894                 SET_FLAGS(flags, MODE_MF);
11895                 switch (bp->mf_mode) {
11896                 case MULTI_FUNCTION_SD:
11897                         SET_FLAGS(flags, MODE_MF_SD);
11898                         break;
11899                 case MULTI_FUNCTION_SI:
11900                         SET_FLAGS(flags, MODE_MF_SI);
11901                         break;
11902                 case MULTI_FUNCTION_AFEX:
11903                         SET_FLAGS(flags, MODE_MF_AFEX);
11904                         break;
11905                 }
11906         } else
11907                 SET_FLAGS(flags, MODE_SF);
11908
11909 #if defined(__LITTLE_ENDIAN)
11910         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11911 #else /*(__BIG_ENDIAN)*/
11912         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11913 #endif
11914         INIT_MODE_FLAGS(bp) = flags;
11915 }
11916
11917 static int bnx2x_init_bp(struct bnx2x *bp)
11918 {
11919         int func;
11920         int rc;
11921
11922         mutex_init(&bp->port.phy_mutex);
11923         mutex_init(&bp->fw_mb_mutex);
11924         mutex_init(&bp->drv_info_mutex);
11925         bp->drv_info_mng_owner = false;
11926         spin_lock_init(&bp->stats_lock);
11927         sema_init(&bp->stats_sema, 1);
11928
11929         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11930         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11931         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11932         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
11933         if (IS_PF(bp)) {
11934                 rc = bnx2x_get_hwinfo(bp);
11935                 if (rc)
11936                         return rc;
11937         } else {
11938                 eth_zero_addr(bp->dev->dev_addr);
11939         }
11940
11941         bnx2x_set_modes_bitmap(bp);
11942
11943         rc = bnx2x_alloc_mem_bp(bp);
11944         if (rc)
11945                 return rc;
11946
11947         bnx2x_read_fwinfo(bp);
11948
11949         func = BP_FUNC(bp);
11950
11951         /* need to reset chip if undi was active */
11952         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11953                 /* init fw_seq */
11954                 bp->fw_seq =
11955                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11956                                                         DRV_MSG_SEQ_NUMBER_MASK;
11957                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11958
11959                 rc = bnx2x_prev_unload(bp);
11960                 if (rc) {
11961                         bnx2x_free_mem_bp(bp);
11962                         return rc;
11963                 }
11964         }
11965
11966         if (CHIP_REV_IS_FPGA(bp))
11967                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11968
11969         if (BP_NOMCP(bp) && (func == 0))
11970                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11971
11972         bp->disable_tpa = disable_tpa;
11973         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11974         /* Reduce memory usage in kdump environment by disabling TPA */
11975         bp->disable_tpa |= is_kdump_kernel();
11976
11977         /* Set TPA flags */
11978         if (bp->disable_tpa) {
11979                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11980                 bp->dev->features &= ~NETIF_F_LRO;
11981         } else {
11982                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11983                 bp->dev->features |= NETIF_F_LRO;
11984         }
11985
11986         if (CHIP_IS_E1(bp))
11987                 bp->dropless_fc = 0;
11988         else
11989                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11990
11991         bp->mrrs = mrrs;
11992
11993         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11994         if (IS_VF(bp))
11995                 bp->rx_ring_size = MAX_RX_AVAIL;
11996
11997         /* make sure that the numbers are in the right granularity */
11998         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11999         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12000
12001         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12002
12003         init_timer(&bp->timer);
12004         bp->timer.expires = jiffies + bp->current_interval;
12005         bp->timer.data = (unsigned long) bp;
12006         bp->timer.function = bnx2x_timer;
12007
12008         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12009             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12010             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12011             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12012                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12013                 bnx2x_dcbx_init_params(bp);
12014         } else {
12015                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12016         }
12017
12018         if (CHIP_IS_E1x(bp))
12019                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12020         else
12021                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12022
12023         /* multiple tx priority */
12024         if (IS_VF(bp))
12025                 bp->max_cos = 1;
12026         else if (CHIP_IS_E1x(bp))
12027                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12028         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12029                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12030         else if (CHIP_IS_E3B0(bp))
12031                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12032         else
12033                 BNX2X_ERR("unknown chip %x revision %x\n",
12034                           CHIP_NUM(bp), CHIP_REV(bp));
12035         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12036
12037         /* We need at least one default status block for slow-path events,
12038          * second status block for the L2 queue, and a third status block for
12039          * CNIC if supported.
12040          */
12041         if (IS_VF(bp))
12042                 bp->min_msix_vec_cnt = 1;
12043         else if (CNIC_SUPPORT(bp))
12044                 bp->min_msix_vec_cnt = 3;
12045         else /* PF w/o cnic */
12046                 bp->min_msix_vec_cnt = 2;
12047         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12048
12049         bp->dump_preset_idx = 1;
12050
12051         if (CHIP_IS_E3B0(bp))
12052                 bp->flags |= PTP_SUPPORTED;
12053
12054         return rc;
12055 }
12056
12057 /****************************************************************************
12058 * General service functions
12059 ****************************************************************************/
12060
12061 /*
12062  * net_device service functions
12063  */
12064
12065 /* called with rtnl_lock */
12066 static int bnx2x_open(struct net_device *dev)
12067 {
12068         struct bnx2x *bp = netdev_priv(dev);
12069         int rc;
12070
12071         bp->stats_init = true;
12072
12073         netif_carrier_off(dev);
12074
12075         bnx2x_set_power_state(bp, PCI_D0);
12076
12077         /* If parity had happen during the unload, then attentions
12078          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12079          * want the first function loaded on the current engine to
12080          * complete the recovery.
12081          * Parity recovery is only relevant for PF driver.
12082          */
12083         if (IS_PF(bp)) {
12084                 int other_engine = BP_PATH(bp) ? 0 : 1;
12085                 bool other_load_status, load_status;
12086                 bool global = false;
12087
12088                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12089                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12090                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12091                     bnx2x_chk_parity_attn(bp, &global, true)) {
12092                         do {
12093                                 /* If there are attentions and they are in a
12094                                  * global blocks, set the GLOBAL_RESET bit
12095                                  * regardless whether it will be this function
12096                                  * that will complete the recovery or not.
12097                                  */
12098                                 if (global)
12099                                         bnx2x_set_reset_global(bp);
12100
12101                                 /* Only the first function on the current
12102                                  * engine should try to recover in open. In case
12103                                  * of attentions in global blocks only the first
12104                                  * in the chip should try to recover.
12105                                  */
12106                                 if ((!load_status &&
12107                                      (!global || !other_load_status)) &&
12108                                       bnx2x_trylock_leader_lock(bp) &&
12109                                       !bnx2x_leader_reset(bp)) {
12110                                         netdev_info(bp->dev,
12111                                                     "Recovered in open\n");
12112                                         break;
12113                                 }
12114
12115                                 /* recovery has failed... */
12116                                 bnx2x_set_power_state(bp, PCI_D3hot);
12117                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12118
12119                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12120                                           "If you still see this message after a few retries then power cycle is required.\n");
12121
12122                                 return -EAGAIN;
12123                         } while (0);
12124                 }
12125         }
12126
12127         bp->recovery_state = BNX2X_RECOVERY_DONE;
12128         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12129         if (rc)
12130                 return rc;
12131         return 0;
12132 }
12133
12134 /* called with rtnl_lock */
12135 static int bnx2x_close(struct net_device *dev)
12136 {
12137         struct bnx2x *bp = netdev_priv(dev);
12138
12139         /* Unload the driver, release IRQs */
12140         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12141
12142         return 0;
12143 }
12144
12145 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12146                                       struct bnx2x_mcast_ramrod_params *p)
12147 {
12148         int mc_count = netdev_mc_count(bp->dev);
12149         struct bnx2x_mcast_list_elem *mc_mac =
12150                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12151         struct netdev_hw_addr *ha;
12152
12153         if (!mc_mac)
12154                 return -ENOMEM;
12155
12156         INIT_LIST_HEAD(&p->mcast_list);
12157
12158         netdev_for_each_mc_addr(ha, bp->dev) {
12159                 mc_mac->mac = bnx2x_mc_addr(ha);
12160                 list_add_tail(&mc_mac->link, &p->mcast_list);
12161                 mc_mac++;
12162         }
12163
12164         p->mcast_list_len = mc_count;
12165
12166         return 0;
12167 }
12168
12169 static void bnx2x_free_mcast_macs_list(
12170         struct bnx2x_mcast_ramrod_params *p)
12171 {
12172         struct bnx2x_mcast_list_elem *mc_mac =
12173                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12174                                  link);
12175
12176         WARN_ON(!mc_mac);
12177         kfree(mc_mac);
12178 }
12179
12180 /**
12181  * bnx2x_set_uc_list - configure a new unicast MACs list.
12182  *
12183  * @bp: driver handle
12184  *
12185  * We will use zero (0) as a MAC type for these MACs.
12186  */
12187 static int bnx2x_set_uc_list(struct bnx2x *bp)
12188 {
12189         int rc;
12190         struct net_device *dev = bp->dev;
12191         struct netdev_hw_addr *ha;
12192         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12193         unsigned long ramrod_flags = 0;
12194
12195         /* First schedule a cleanup up of old configuration */
12196         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12197         if (rc < 0) {
12198                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12199                 return rc;
12200         }
12201
12202         netdev_for_each_uc_addr(ha, dev) {
12203                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12204                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12205                 if (rc == -EEXIST) {
12206                         DP(BNX2X_MSG_SP,
12207                            "Failed to schedule ADD operations: %d\n", rc);
12208                         /* do not treat adding same MAC as error */
12209                         rc = 0;
12210
12211                 } else if (rc < 0) {
12212
12213                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12214                                   rc);
12215                         return rc;
12216                 }
12217         }
12218
12219         /* Execute the pending commands */
12220         __set_bit(RAMROD_CONT, &ramrod_flags);
12221         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12222                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12223 }
12224
12225 static int bnx2x_set_mc_list(struct bnx2x *bp)
12226 {
12227         struct net_device *dev = bp->dev;
12228         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12229         int rc = 0;
12230
12231         rparam.mcast_obj = &bp->mcast_obj;
12232
12233         /* first, clear all configured multicast MACs */
12234         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12235         if (rc < 0) {
12236                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12237                 return rc;
12238         }
12239
12240         /* then, configure a new MACs list */
12241         if (netdev_mc_count(dev)) {
12242                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12243                 if (rc) {
12244                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12245                                   rc);
12246                         return rc;
12247                 }
12248
12249                 /* Now add the new MACs */
12250                 rc = bnx2x_config_mcast(bp, &rparam,
12251                                         BNX2X_MCAST_CMD_ADD);
12252                 if (rc < 0)
12253                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12254                                   rc);
12255
12256                 bnx2x_free_mcast_macs_list(&rparam);
12257         }
12258
12259         return rc;
12260 }
12261
12262 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12263 static void bnx2x_set_rx_mode(struct net_device *dev)
12264 {
12265         struct bnx2x *bp = netdev_priv(dev);
12266
12267         if (bp->state != BNX2X_STATE_OPEN) {
12268                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12269                 return;
12270         } else {
12271                 /* Schedule an SP task to handle rest of change */
12272                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12273                                        NETIF_MSG_IFUP);
12274         }
12275 }
12276
12277 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12278 {
12279         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12280
12281         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12282
12283         netif_addr_lock_bh(bp->dev);
12284
12285         if (bp->dev->flags & IFF_PROMISC) {
12286                 rx_mode = BNX2X_RX_MODE_PROMISC;
12287         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12288                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12289                     CHIP_IS_E1(bp))) {
12290                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12291         } else {
12292                 if (IS_PF(bp)) {
12293                         /* some multicasts */
12294                         if (bnx2x_set_mc_list(bp) < 0)
12295                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12296
12297                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12298                         netif_addr_unlock_bh(bp->dev);
12299                         if (bnx2x_set_uc_list(bp) < 0)
12300                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12301                         netif_addr_lock_bh(bp->dev);
12302                 } else {
12303                         /* configuring mcast to a vf involves sleeping (when we
12304                          * wait for the pf's response).
12305                          */
12306                         bnx2x_schedule_sp_rtnl(bp,
12307                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12308                 }
12309         }
12310
12311         bp->rx_mode = rx_mode;
12312         /* handle ISCSI SD mode */
12313         if (IS_MF_ISCSI_SD(bp))
12314                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12315
12316         /* Schedule the rx_mode command */
12317         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12318                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12319                 netif_addr_unlock_bh(bp->dev);
12320                 return;
12321         }
12322
12323         if (IS_PF(bp)) {
12324                 bnx2x_set_storm_rx_mode(bp);
12325                 netif_addr_unlock_bh(bp->dev);
12326         } else {
12327                 /* VF will need to request the PF to make this change, and so
12328                  * the VF needs to release the bottom-half lock prior to the
12329                  * request (as it will likely require sleep on the VF side)
12330                  */
12331                 netif_addr_unlock_bh(bp->dev);
12332                 bnx2x_vfpf_storm_rx_mode(bp);
12333         }
12334 }
12335
12336 /* called with rtnl_lock */
12337 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12338                            int devad, u16 addr)
12339 {
12340         struct bnx2x *bp = netdev_priv(netdev);
12341         u16 value;
12342         int rc;
12343
12344         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12345            prtad, devad, addr);
12346
12347         /* The HW expects different devad if CL22 is used */
12348         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12349
12350         bnx2x_acquire_phy_lock(bp);
12351         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12352         bnx2x_release_phy_lock(bp);
12353         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12354
12355         if (!rc)
12356                 rc = value;
12357         return rc;
12358 }
12359
12360 /* called with rtnl_lock */
12361 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12362                             u16 addr, u16 value)
12363 {
12364         struct bnx2x *bp = netdev_priv(netdev);
12365         int rc;
12366
12367         DP(NETIF_MSG_LINK,
12368            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12369            prtad, devad, addr, value);
12370
12371         /* The HW expects different devad if CL22 is used */
12372         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12373
12374         bnx2x_acquire_phy_lock(bp);
12375         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12376         bnx2x_release_phy_lock(bp);
12377         return rc;
12378 }
12379
12380 /* called with rtnl_lock */
12381 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12382 {
12383         struct bnx2x *bp = netdev_priv(dev);
12384         struct mii_ioctl_data *mdio = if_mii(ifr);
12385
12386         if (!netif_running(dev))
12387                 return -EAGAIN;
12388
12389         switch (cmd) {
12390         case SIOCSHWTSTAMP:
12391                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12392         default:
12393                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12394                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12395                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12396         }
12397 }
12398
12399 #ifdef CONFIG_NET_POLL_CONTROLLER
12400 static void poll_bnx2x(struct net_device *dev)
12401 {
12402         struct bnx2x *bp = netdev_priv(dev);
12403         int i;
12404
12405         for_each_eth_queue(bp, i) {
12406                 struct bnx2x_fastpath *fp = &bp->fp[i];
12407                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12408         }
12409 }
12410 #endif
12411
12412 static int bnx2x_validate_addr(struct net_device *dev)
12413 {
12414         struct bnx2x *bp = netdev_priv(dev);
12415
12416         /* query the bulletin board for mac address configured by the PF */
12417         if (IS_VF(bp))
12418                 bnx2x_sample_bulletin(bp);
12419
12420         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12421                 BNX2X_ERR("Non-valid Ethernet address\n");
12422                 return -EADDRNOTAVAIL;
12423         }
12424         return 0;
12425 }
12426
12427 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12428                                   struct netdev_phys_port_id *ppid)
12429 {
12430         struct bnx2x *bp = netdev_priv(netdev);
12431
12432         if (!(bp->flags & HAS_PHYS_PORT_ID))
12433                 return -EOPNOTSUPP;
12434
12435         ppid->id_len = sizeof(bp->phys_port_id);
12436         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12437
12438         return 0;
12439 }
12440
12441 static const struct net_device_ops bnx2x_netdev_ops = {
12442         .ndo_open               = bnx2x_open,
12443         .ndo_stop               = bnx2x_close,
12444         .ndo_start_xmit         = bnx2x_start_xmit,
12445         .ndo_select_queue       = bnx2x_select_queue,
12446         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12447         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12448         .ndo_validate_addr      = bnx2x_validate_addr,
12449         .ndo_do_ioctl           = bnx2x_ioctl,
12450         .ndo_change_mtu         = bnx2x_change_mtu,
12451         .ndo_fix_features       = bnx2x_fix_features,
12452         .ndo_set_features       = bnx2x_set_features,
12453         .ndo_tx_timeout         = bnx2x_tx_timeout,
12454 #ifdef CONFIG_NET_POLL_CONTROLLER
12455         .ndo_poll_controller    = poll_bnx2x,
12456 #endif
12457         .ndo_setup_tc           = bnx2x_setup_tc,
12458 #ifdef CONFIG_BNX2X_SRIOV
12459         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12460         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12461         .ndo_get_vf_config      = bnx2x_get_vf_config,
12462 #endif
12463 #ifdef NETDEV_FCOE_WWNN
12464         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12465 #endif
12466
12467 #ifdef CONFIG_NET_RX_BUSY_POLL
12468         .ndo_busy_poll          = bnx2x_low_latency_recv,
12469 #endif
12470         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12471         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12472 };
12473
12474 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12475 {
12476         struct device *dev = &bp->pdev->dev;
12477
12478         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12479             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12480                 dev_err(dev, "System does not support DMA, aborting\n");
12481                 return -EIO;
12482         }
12483
12484         return 0;
12485 }
12486
12487 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12488 {
12489         if (bp->flags & AER_ENABLED) {
12490                 pci_disable_pcie_error_reporting(bp->pdev);
12491                 bp->flags &= ~AER_ENABLED;
12492         }
12493 }
12494
12495 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12496                           struct net_device *dev, unsigned long board_type)
12497 {
12498         int rc;
12499         u32 pci_cfg_dword;
12500         bool chip_is_e1x = (board_type == BCM57710 ||
12501                             board_type == BCM57711 ||
12502                             board_type == BCM57711E);
12503
12504         SET_NETDEV_DEV(dev, &pdev->dev);
12505
12506         bp->dev = dev;
12507         bp->pdev = pdev;
12508
12509         rc = pci_enable_device(pdev);
12510         if (rc) {
12511                 dev_err(&bp->pdev->dev,
12512                         "Cannot enable PCI device, aborting\n");
12513                 goto err_out;
12514         }
12515
12516         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12517                 dev_err(&bp->pdev->dev,
12518                         "Cannot find PCI device base address, aborting\n");
12519                 rc = -ENODEV;
12520                 goto err_out_disable;
12521         }
12522
12523         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12524                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12525                 rc = -ENODEV;
12526                 goto err_out_disable;
12527         }
12528
12529         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12530         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12531             PCICFG_REVESION_ID_ERROR_VAL) {
12532                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12533                 rc = -ENODEV;
12534                 goto err_out_disable;
12535         }
12536
12537         if (atomic_read(&pdev->enable_cnt) == 1) {
12538                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12539                 if (rc) {
12540                         dev_err(&bp->pdev->dev,
12541                                 "Cannot obtain PCI resources, aborting\n");
12542                         goto err_out_disable;
12543                 }
12544
12545                 pci_set_master(pdev);
12546                 pci_save_state(pdev);
12547         }
12548
12549         if (IS_PF(bp)) {
12550                 if (!pdev->pm_cap) {
12551                         dev_err(&bp->pdev->dev,
12552                                 "Cannot find power management capability, aborting\n");
12553                         rc = -EIO;
12554                         goto err_out_release;
12555                 }
12556         }
12557
12558         if (!pci_is_pcie(pdev)) {
12559                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12560                 rc = -EIO;
12561                 goto err_out_release;
12562         }
12563
12564         rc = bnx2x_set_coherency_mask(bp);
12565         if (rc)
12566                 goto err_out_release;
12567
12568         dev->mem_start = pci_resource_start(pdev, 0);
12569         dev->base_addr = dev->mem_start;
12570         dev->mem_end = pci_resource_end(pdev, 0);
12571
12572         dev->irq = pdev->irq;
12573
12574         bp->regview = pci_ioremap_bar(pdev, 0);
12575         if (!bp->regview) {
12576                 dev_err(&bp->pdev->dev,
12577                         "Cannot map register space, aborting\n");
12578                 rc = -ENOMEM;
12579                 goto err_out_release;
12580         }
12581
12582         /* In E1/E1H use pci device function given by kernel.
12583          * In E2/E3 read physical function from ME register since these chips
12584          * support Physical Device Assignment where kernel BDF maybe arbitrary
12585          * (depending on hypervisor).
12586          */
12587         if (chip_is_e1x) {
12588                 bp->pf_num = PCI_FUNC(pdev->devfn);
12589         } else {
12590                 /* chip is E2/3*/
12591                 pci_read_config_dword(bp->pdev,
12592                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12593                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12594                                   ME_REG_ABS_PF_NUM_SHIFT);
12595         }
12596         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12597
12598         /* clean indirect addresses */
12599         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12600                                PCICFG_VENDOR_ID_OFFSET);
12601
12602         /* AER (Advanced Error reporting) configuration */
12603         rc = pci_enable_pcie_error_reporting(pdev);
12604         if (!rc)
12605                 bp->flags |= AER_ENABLED;
12606         else
12607                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12608
12609         /*
12610          * Clean the following indirect addresses for all functions since it
12611          * is not used by the driver.
12612          */
12613         if (IS_PF(bp)) {
12614                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12615                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12616                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12617                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12618
12619                 if (chip_is_e1x) {
12620                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12621                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12622                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12623                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12624                 }
12625
12626                 /* Enable internal target-read (in case we are probed after PF
12627                  * FLR). Must be done prior to any BAR read access. Only for
12628                  * 57712 and up
12629                  */
12630                 if (!chip_is_e1x)
12631                         REG_WR(bp,
12632                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12633         }
12634
12635         dev->watchdog_timeo = TX_TIMEOUT;
12636
12637         dev->netdev_ops = &bnx2x_netdev_ops;
12638         bnx2x_set_ethtool_ops(bp, dev);
12639
12640         dev->priv_flags |= IFF_UNICAST_FLT;
12641
12642         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12643                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12644                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12645                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12646         if (!CHIP_IS_E1x(bp)) {
12647                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12648                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12649                 dev->hw_enc_features =
12650                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12651                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12652                         NETIF_F_GSO_IPIP |
12653                         NETIF_F_GSO_SIT |
12654                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12655         }
12656
12657         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12658                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12659
12660         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12661         dev->features |= NETIF_F_HIGHDMA;
12662
12663         /* Add Loopback capability to the device */
12664         dev->hw_features |= NETIF_F_LOOPBACK;
12665
12666 #ifdef BCM_DCBNL
12667         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12668 #endif
12669
12670         /* get_port_hwinfo() will set prtad and mmds properly */
12671         bp->mdio.prtad = MDIO_PRTAD_NONE;
12672         bp->mdio.mmds = 0;
12673         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12674         bp->mdio.dev = dev;
12675         bp->mdio.mdio_read = bnx2x_mdio_read;
12676         bp->mdio.mdio_write = bnx2x_mdio_write;
12677
12678         return 0;
12679
12680 err_out_release:
12681         if (atomic_read(&pdev->enable_cnt) == 1)
12682                 pci_release_regions(pdev);
12683
12684 err_out_disable:
12685         pci_disable_device(pdev);
12686
12687 err_out:
12688         return rc;
12689 }
12690
12691 static int bnx2x_check_firmware(struct bnx2x *bp)
12692 {
12693         const struct firmware *firmware = bp->firmware;
12694         struct bnx2x_fw_file_hdr *fw_hdr;
12695         struct bnx2x_fw_file_section *sections;
12696         u32 offset, len, num_ops;
12697         __be16 *ops_offsets;
12698         int i;
12699         const u8 *fw_ver;
12700
12701         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12702                 BNX2X_ERR("Wrong FW size\n");
12703                 return -EINVAL;
12704         }
12705
12706         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12707         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12708
12709         /* Make sure none of the offsets and sizes make us read beyond
12710          * the end of the firmware data */
12711         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12712                 offset = be32_to_cpu(sections[i].offset);
12713                 len = be32_to_cpu(sections[i].len);
12714                 if (offset + len > firmware->size) {
12715                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12716                         return -EINVAL;
12717                 }
12718         }
12719
12720         /* Likewise for the init_ops offsets */
12721         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12722         ops_offsets = (__force __be16 *)(firmware->data + offset);
12723         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12724
12725         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12726                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12727                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12728                         return -EINVAL;
12729                 }
12730         }
12731
12732         /* Check FW version */
12733         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12734         fw_ver = firmware->data + offset;
12735         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12736             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12737             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12738             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12739                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12740                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12741                        BCM_5710_FW_MAJOR_VERSION,
12742                        BCM_5710_FW_MINOR_VERSION,
12743                        BCM_5710_FW_REVISION_VERSION,
12744                        BCM_5710_FW_ENGINEERING_VERSION);
12745                 return -EINVAL;
12746         }
12747
12748         return 0;
12749 }
12750
12751 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12752 {
12753         const __be32 *source = (const __be32 *)_source;
12754         u32 *target = (u32 *)_target;
12755         u32 i;
12756
12757         for (i = 0; i < n/4; i++)
12758                 target[i] = be32_to_cpu(source[i]);
12759 }
12760
12761 /*
12762    Ops array is stored in the following format:
12763    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12764  */
12765 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12766 {
12767         const __be32 *source = (const __be32 *)_source;
12768         struct raw_op *target = (struct raw_op *)_target;
12769         u32 i, j, tmp;
12770
12771         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12772                 tmp = be32_to_cpu(source[j]);
12773                 target[i].op = (tmp >> 24) & 0xff;
12774                 target[i].offset = tmp & 0xffffff;
12775                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12776         }
12777 }
12778
12779 /* IRO array is stored in the following format:
12780  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12781  */
12782 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12783 {
12784         const __be32 *source = (const __be32 *)_source;
12785         struct iro *target = (struct iro *)_target;
12786         u32 i, j, tmp;
12787
12788         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12789                 target[i].base = be32_to_cpu(source[j]);
12790                 j++;
12791                 tmp = be32_to_cpu(source[j]);
12792                 target[i].m1 = (tmp >> 16) & 0xffff;
12793                 target[i].m2 = tmp & 0xffff;
12794                 j++;
12795                 tmp = be32_to_cpu(source[j]);
12796                 target[i].m3 = (tmp >> 16) & 0xffff;
12797                 target[i].size = tmp & 0xffff;
12798                 j++;
12799         }
12800 }
12801
12802 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12803 {
12804         const __be16 *source = (const __be16 *)_source;
12805         u16 *target = (u16 *)_target;
12806         u32 i;
12807
12808         for (i = 0; i < n/2; i++)
12809                 target[i] = be16_to_cpu(source[i]);
12810 }
12811
12812 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12813 do {                                                                    \
12814         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12815         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12816         if (!bp->arr)                                                   \
12817                 goto lbl;                                               \
12818         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12819              (u8 *)bp->arr, len);                                       \
12820 } while (0)
12821
12822 static int bnx2x_init_firmware(struct bnx2x *bp)
12823 {
12824         const char *fw_file_name;
12825         struct bnx2x_fw_file_hdr *fw_hdr;
12826         int rc;
12827
12828         if (bp->firmware)
12829                 return 0;
12830
12831         if (CHIP_IS_E1(bp))
12832                 fw_file_name = FW_FILE_NAME_E1;
12833         else if (CHIP_IS_E1H(bp))
12834                 fw_file_name = FW_FILE_NAME_E1H;
12835         else if (!CHIP_IS_E1x(bp))
12836                 fw_file_name = FW_FILE_NAME_E2;
12837         else {
12838                 BNX2X_ERR("Unsupported chip revision\n");
12839                 return -EINVAL;
12840         }
12841         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12842
12843         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12844         if (rc) {
12845                 BNX2X_ERR("Can't load firmware file %s\n",
12846                           fw_file_name);
12847                 goto request_firmware_exit;
12848         }
12849
12850         rc = bnx2x_check_firmware(bp);
12851         if (rc) {
12852                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12853                 goto request_firmware_exit;
12854         }
12855
12856         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12857
12858         /* Initialize the pointers to the init arrays */
12859         /* Blob */
12860         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12861
12862         /* Opcodes */
12863         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12864
12865         /* Offsets */
12866         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12867                             be16_to_cpu_n);
12868
12869         /* STORMs firmware */
12870         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12871                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12872         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12873                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12874         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12875                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12876         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12877                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12878         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12879                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12880         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12881                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12882         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12883                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12884         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12885                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12886         /* IRO */
12887         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12888
12889         return 0;
12890
12891 iro_alloc_err:
12892         kfree(bp->init_ops_offsets);
12893 init_offsets_alloc_err:
12894         kfree(bp->init_ops);
12895 init_ops_alloc_err:
12896         kfree(bp->init_data);
12897 request_firmware_exit:
12898         release_firmware(bp->firmware);
12899         bp->firmware = NULL;
12900
12901         return rc;
12902 }
12903
12904 static void bnx2x_release_firmware(struct bnx2x *bp)
12905 {
12906         kfree(bp->init_ops_offsets);
12907         kfree(bp->init_ops);
12908         kfree(bp->init_data);
12909         release_firmware(bp->firmware);
12910         bp->firmware = NULL;
12911 }
12912
12913 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12914         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12915         .init_hw_cmn      = bnx2x_init_hw_common,
12916         .init_hw_port     = bnx2x_init_hw_port,
12917         .init_hw_func     = bnx2x_init_hw_func,
12918
12919         .reset_hw_cmn     = bnx2x_reset_common,
12920         .reset_hw_port    = bnx2x_reset_port,
12921         .reset_hw_func    = bnx2x_reset_func,
12922
12923         .gunzip_init      = bnx2x_gunzip_init,
12924         .gunzip_end       = bnx2x_gunzip_end,
12925
12926         .init_fw          = bnx2x_init_firmware,
12927         .release_fw       = bnx2x_release_firmware,
12928 };
12929
12930 void bnx2x__init_func_obj(struct bnx2x *bp)
12931 {
12932         /* Prepare DMAE related driver resources */
12933         bnx2x_setup_dmae(bp);
12934
12935         bnx2x_init_func_obj(bp, &bp->func_obj,
12936                             bnx2x_sp(bp, func_rdata),
12937                             bnx2x_sp_mapping(bp, func_rdata),
12938                             bnx2x_sp(bp, func_afex_rdata),
12939                             bnx2x_sp_mapping(bp, func_afex_rdata),
12940                             &bnx2x_func_sp_drv);
12941 }
12942
12943 /* must be called after sriov-enable */
12944 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12945 {
12946         int cid_count = BNX2X_L2_MAX_CID(bp);
12947
12948         if (IS_SRIOV(bp))
12949                 cid_count += BNX2X_VF_CIDS;
12950
12951         if (CNIC_SUPPORT(bp))
12952                 cid_count += CNIC_CID_MAX;
12953
12954         return roundup(cid_count, QM_CID_ROUND);
12955 }
12956
12957 /**
12958  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12959  *
12960  * @dev:        pci device
12961  *
12962  */
12963 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
12964 {
12965         int index;
12966         u16 control = 0;
12967
12968         /*
12969          * If MSI-X is not supported - return number of SBs needed to support
12970          * one fast path queue: one FP queue + SB for CNIC
12971          */
12972         if (!pdev->msix_cap) {
12973                 dev_info(&pdev->dev, "no msix capability found\n");
12974                 return 1 + cnic_cnt;
12975         }
12976         dev_info(&pdev->dev, "msix capability found\n");
12977
12978         /*
12979          * The value in the PCI configuration space is the index of the last
12980          * entry, namely one less than the actual size of the table, which is
12981          * exactly what we want to return from this function: number of all SBs
12982          * without the default SB.
12983          * For VFs there is no default SB, then we return (index+1).
12984          */
12985         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
12986
12987         index = control & PCI_MSIX_FLAGS_QSIZE;
12988
12989         return index;
12990 }
12991
12992 static int set_max_cos_est(int chip_id)
12993 {
12994         switch (chip_id) {
12995         case BCM57710:
12996         case BCM57711:
12997         case BCM57711E:
12998                 return BNX2X_MULTI_TX_COS_E1X;
12999         case BCM57712:
13000         case BCM57712_MF:
13001                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13002         case BCM57800:
13003         case BCM57800_MF:
13004         case BCM57810:
13005         case BCM57810_MF:
13006         case BCM57840_4_10:
13007         case BCM57840_2_20:
13008         case BCM57840_O:
13009         case BCM57840_MFO:
13010         case BCM57840_MF:
13011         case BCM57811:
13012         case BCM57811_MF:
13013                 return BNX2X_MULTI_TX_COS_E3B0;
13014         case BCM57712_VF:
13015         case BCM57800_VF:
13016         case BCM57810_VF:
13017         case BCM57840_VF:
13018         case BCM57811_VF:
13019                 return 1;
13020         default:
13021                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13022                 return -ENODEV;
13023         }
13024 }
13025
13026 static int set_is_vf(int chip_id)
13027 {
13028         switch (chip_id) {
13029         case BCM57712_VF:
13030         case BCM57800_VF:
13031         case BCM57810_VF:
13032         case BCM57840_VF:
13033         case BCM57811_VF:
13034                 return true;
13035         default:
13036                 return false;
13037         }
13038 }
13039
13040 /* nig_tsgen registers relative address */
13041 #define tsgen_ctrl 0x0
13042 #define tsgen_freecount 0x10
13043 #define tsgen_synctime_t0 0x20
13044 #define tsgen_offset_t0 0x28
13045 #define tsgen_drift_t0 0x30
13046 #define tsgen_synctime_t1 0x58
13047 #define tsgen_offset_t1 0x60
13048 #define tsgen_drift_t1 0x68
13049
13050 /* FW workaround for setting drift */
13051 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13052                                           int best_val, int best_period)
13053 {
13054         struct bnx2x_func_state_params func_params = {NULL};
13055         struct bnx2x_func_set_timesync_params *set_timesync_params =
13056                 &func_params.params.set_timesync;
13057
13058         /* Prepare parameters for function state transitions */
13059         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13060         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13061
13062         func_params.f_obj = &bp->func_obj;
13063         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13064
13065         /* Function parameters */
13066         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13067         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13068         set_timesync_params->add_sub_drift_adjust_value =
13069                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13070         set_timesync_params->drift_adjust_value = best_val;
13071         set_timesync_params->drift_adjust_period = best_period;
13072
13073         return bnx2x_func_state_change(bp, &func_params);
13074 }
13075
13076 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13077 {
13078         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13079         int rc;
13080         int drift_dir = 1;
13081         int val, period, period1, period2, dif, dif1, dif2;
13082         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13083
13084         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13085
13086         if (!netif_running(bp->dev)) {
13087                 DP(BNX2X_MSG_PTP,
13088                    "PTP adjfreq called while the interface is down\n");
13089                 return -EFAULT;
13090         }
13091
13092         if (ppb < 0) {
13093                 ppb = -ppb;
13094                 drift_dir = 0;
13095         }
13096
13097         if (ppb == 0) {
13098                 best_val = 1;
13099                 best_period = 0x1FFFFFF;
13100         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13101                 best_val = 31;
13102                 best_period = 1;
13103         } else {
13104                 /* Changed not to allow val = 8, 16, 24 as these values
13105                  * are not supported in workaround.
13106                  */
13107                 for (val = 0; val <= 31; val++) {
13108                         if ((val & 0x7) == 0)
13109                                 continue;
13110                         period1 = val * 1000000 / ppb;
13111                         period2 = period1 + 1;
13112                         if (period1 != 0)
13113                                 dif1 = ppb - (val * 1000000 / period1);
13114                         else
13115                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13116                         if (dif1 < 0)
13117                                 dif1 = -dif1;
13118                         dif2 = ppb - (val * 1000000 / period2);
13119                         if (dif2 < 0)
13120                                 dif2 = -dif2;
13121                         dif = (dif1 < dif2) ? dif1 : dif2;
13122                         period = (dif1 < dif2) ? period1 : period2;
13123                         if (dif < best_dif) {
13124                                 best_dif = dif;
13125                                 best_val = val;
13126                                 best_period = period;
13127                         }
13128                 }
13129         }
13130
13131         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13132                                             best_period);
13133         if (rc) {
13134                 BNX2X_ERR("Failed to set drift\n");
13135                 return -EFAULT;
13136         }
13137
13138         DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
13139            best_period);
13140
13141         return 0;
13142 }
13143
13144 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13145 {
13146         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13147         u64 now;
13148
13149         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13150
13151         now = timecounter_read(&bp->timecounter);
13152         now += delta;
13153         /* Re-init the timecounter */
13154         timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
13155
13156         return 0;
13157 }
13158
13159 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13160 {
13161         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13162         u64 ns;
13163         u32 remainder;
13164
13165         ns = timecounter_read(&bp->timecounter);
13166
13167         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13168
13169         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13170         ts->tv_nsec = remainder;
13171
13172         return 0;
13173 }
13174
13175 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13176                              const struct timespec *ts)
13177 {
13178         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13179         u64 ns;
13180
13181         ns = ts->tv_sec * 1000000000ULL;
13182         ns += ts->tv_nsec;
13183
13184         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13185
13186         /* Re-init the timecounter */
13187         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13188
13189         return 0;
13190 }
13191
13192 /* Enable (or disable) ancillary features of the phc subsystem */
13193 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13194                             struct ptp_clock_request *rq, int on)
13195 {
13196         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13197
13198         BNX2X_ERR("PHC ancillary features are not supported\n");
13199         return -ENOTSUPP;
13200 }
13201
13202 void bnx2x_register_phc(struct bnx2x *bp)
13203 {
13204         /* Fill the ptp_clock_info struct and register PTP clock*/
13205         bp->ptp_clock_info.owner = THIS_MODULE;
13206         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13207         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13208         bp->ptp_clock_info.n_alarm = 0;
13209         bp->ptp_clock_info.n_ext_ts = 0;
13210         bp->ptp_clock_info.n_per_out = 0;
13211         bp->ptp_clock_info.pps = 0;
13212         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13213         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13214         bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13215         bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13216         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13217
13218         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13219         if (IS_ERR(bp->ptp_clock)) {
13220                 bp->ptp_clock = NULL;
13221                 BNX2X_ERR("PTP clock registeration failed\n");
13222         }
13223 }
13224
13225 static int bnx2x_init_one(struct pci_dev *pdev,
13226                                     const struct pci_device_id *ent)
13227 {
13228         struct net_device *dev = NULL;
13229         struct bnx2x *bp;
13230         enum pcie_link_width pcie_width;
13231         enum pci_bus_speed pcie_speed;
13232         int rc, max_non_def_sbs;
13233         int rx_count, tx_count, rss_count, doorbell_size;
13234         int max_cos_est;
13235         bool is_vf;
13236         int cnic_cnt;
13237
13238         /* An estimated maximum supported CoS number according to the chip
13239          * version.
13240          * We will try to roughly estimate the maximum number of CoSes this chip
13241          * may support in order to minimize the memory allocated for Tx
13242          * netdev_queue's. This number will be accurately calculated during the
13243          * initialization of bp->max_cos based on the chip versions AND chip
13244          * revision in the bnx2x_init_bp().
13245          */
13246         max_cos_est = set_max_cos_est(ent->driver_data);
13247         if (max_cos_est < 0)
13248                 return max_cos_est;
13249         is_vf = set_is_vf(ent->driver_data);
13250         cnic_cnt = is_vf ? 0 : 1;
13251
13252         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13253
13254         /* add another SB for VF as it has no default SB */
13255         max_non_def_sbs += is_vf ? 1 : 0;
13256
13257         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13258         rss_count = max_non_def_sbs - cnic_cnt;
13259
13260         if (rss_count < 1)
13261                 return -EINVAL;
13262
13263         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13264         rx_count = rss_count + cnic_cnt;
13265
13266         /* Maximum number of netdev Tx queues:
13267          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13268          */
13269         tx_count = rss_count * max_cos_est + cnic_cnt;
13270
13271         /* dev zeroed in init_etherdev */
13272         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13273         if (!dev)
13274                 return -ENOMEM;
13275
13276         bp = netdev_priv(dev);
13277
13278         bp->flags = 0;
13279         if (is_vf)
13280                 bp->flags |= IS_VF_FLAG;
13281
13282         bp->igu_sb_cnt = max_non_def_sbs;
13283         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13284         bp->msg_enable = debug;
13285         bp->cnic_support = cnic_cnt;
13286         bp->cnic_probe = bnx2x_cnic_probe;
13287
13288         pci_set_drvdata(pdev, dev);
13289
13290         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13291         if (rc < 0) {
13292                 free_netdev(dev);
13293                 return rc;
13294         }
13295
13296         BNX2X_DEV_INFO("This is a %s function\n",
13297                        IS_PF(bp) ? "physical" : "virtual");
13298         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13299         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13300         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13301                        tx_count, rx_count);
13302
13303         rc = bnx2x_init_bp(bp);
13304         if (rc)
13305                 goto init_one_exit;
13306
13307         /* Map doorbells here as we need the real value of bp->max_cos which
13308          * is initialized in bnx2x_init_bp() to determine the number of
13309          * l2 connections.
13310          */
13311         if (IS_VF(bp)) {
13312                 bp->doorbells = bnx2x_vf_doorbells(bp);
13313                 rc = bnx2x_vf_pci_alloc(bp);
13314                 if (rc)
13315                         goto init_one_exit;
13316         } else {
13317                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13318                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13319                         dev_err(&bp->pdev->dev,
13320                                 "Cannot map doorbells, bar size too small, aborting\n");
13321                         rc = -ENOMEM;
13322                         goto init_one_exit;
13323                 }
13324                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13325                                                 doorbell_size);
13326         }
13327         if (!bp->doorbells) {
13328                 dev_err(&bp->pdev->dev,
13329                         "Cannot map doorbell space, aborting\n");
13330                 rc = -ENOMEM;
13331                 goto init_one_exit;
13332         }
13333
13334         if (IS_VF(bp)) {
13335                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13336                 if (rc)
13337                         goto init_one_exit;
13338         }
13339
13340         /* Enable SRIOV if capability found in configuration space */
13341         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13342         if (rc)
13343                 goto init_one_exit;
13344
13345         /* calc qm_cid_count */
13346         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13347         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13348
13349         /* disable FCOE L2 queue for E1x*/
13350         if (CHIP_IS_E1x(bp))
13351                 bp->flags |= NO_FCOE_FLAG;
13352
13353         /* Set bp->num_queues for MSI-X mode*/
13354         bnx2x_set_num_queues(bp);
13355
13356         /* Configure interrupt mode: try to enable MSI-X/MSI if
13357          * needed.
13358          */
13359         rc = bnx2x_set_int_mode(bp);
13360         if (rc) {
13361                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13362                 goto init_one_exit;
13363         }
13364         BNX2X_DEV_INFO("set interrupts successfully\n");
13365
13366         /* register the net device */
13367         rc = register_netdev(dev);
13368         if (rc) {
13369                 dev_err(&pdev->dev, "Cannot register net device\n");
13370                 goto init_one_exit;
13371         }
13372         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13373
13374         if (!NO_FCOE(bp)) {
13375                 /* Add storage MAC address */
13376                 rtnl_lock();
13377                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13378                 rtnl_unlock();
13379         }
13380         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13381             pcie_speed == PCI_SPEED_UNKNOWN ||
13382             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13383                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13384         else
13385                 BNX2X_DEV_INFO(
13386                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13387                        board_info[ent->driver_data].name,
13388                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13389                        pcie_width,
13390                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13391                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13392                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13393                        "Unknown",
13394                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13395
13396         bnx2x_register_phc(bp);
13397
13398         return 0;
13399
13400 init_one_exit:
13401         bnx2x_disable_pcie_error_reporting(bp);
13402
13403         if (bp->regview)
13404                 iounmap(bp->regview);
13405
13406         if (IS_PF(bp) && bp->doorbells)
13407                 iounmap(bp->doorbells);
13408
13409         free_netdev(dev);
13410
13411         if (atomic_read(&pdev->enable_cnt) == 1)
13412                 pci_release_regions(pdev);
13413
13414         pci_disable_device(pdev);
13415
13416         return rc;
13417 }
13418
13419 static void __bnx2x_remove(struct pci_dev *pdev,
13420                            struct net_device *dev,
13421                            struct bnx2x *bp,
13422                            bool remove_netdev)
13423 {
13424         if (bp->ptp_clock) {
13425                 ptp_clock_unregister(bp->ptp_clock);
13426                 bp->ptp_clock = NULL;
13427         }
13428
13429         /* Delete storage MAC address */
13430         if (!NO_FCOE(bp)) {
13431                 rtnl_lock();
13432                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13433                 rtnl_unlock();
13434         }
13435
13436 #ifdef BCM_DCBNL
13437         /* Delete app tlvs from dcbnl */
13438         bnx2x_dcbnl_update_applist(bp, true);
13439 #endif
13440
13441         if (IS_PF(bp) &&
13442             !BP_NOMCP(bp) &&
13443             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13444                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13445
13446         /* Close the interface - either directly or implicitly */
13447         if (remove_netdev) {
13448                 unregister_netdev(dev);
13449         } else {
13450                 rtnl_lock();
13451                 dev_close(dev);
13452                 rtnl_unlock();
13453         }
13454
13455         bnx2x_iov_remove_one(bp);
13456
13457         /* Power on: we can't let PCI layer write to us while we are in D3 */
13458         if (IS_PF(bp)) {
13459                 bnx2x_set_power_state(bp, PCI_D0);
13460
13461                 /* Set endianity registers to reset values in case next driver
13462                  * boots in different endianty environment.
13463                  */
13464                 bnx2x_reset_endianity(bp);
13465         }
13466
13467         /* Disable MSI/MSI-X */
13468         bnx2x_disable_msi(bp);
13469
13470         /* Power off */
13471         if (IS_PF(bp))
13472                 bnx2x_set_power_state(bp, PCI_D3hot);
13473
13474         /* Make sure RESET task is not scheduled before continuing */
13475         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13476
13477         /* send message via vfpf channel to release the resources of this vf */
13478         if (IS_VF(bp))
13479                 bnx2x_vfpf_release(bp);
13480
13481         /* Assumes no further PCIe PM changes will occur */
13482         if (system_state == SYSTEM_POWER_OFF) {
13483                 pci_wake_from_d3(pdev, bp->wol);
13484                 pci_set_power_state(pdev, PCI_D3hot);
13485         }
13486
13487         bnx2x_disable_pcie_error_reporting(bp);
13488         if (remove_netdev) {
13489                 if (bp->regview)
13490                         iounmap(bp->regview);
13491
13492                 /* For vfs, doorbells are part of the regview and were unmapped
13493                  * along with it. FW is only loaded by PF.
13494                  */
13495                 if (IS_PF(bp)) {
13496                         if (bp->doorbells)
13497                                 iounmap(bp->doorbells);
13498
13499                         bnx2x_release_firmware(bp);
13500                 } else {
13501                         bnx2x_vf_pci_dealloc(bp);
13502                 }
13503                 bnx2x_free_mem_bp(bp);
13504
13505                 free_netdev(dev);
13506
13507                 if (atomic_read(&pdev->enable_cnt) == 1)
13508                         pci_release_regions(pdev);
13509
13510                 pci_disable_device(pdev);
13511         }
13512 }
13513
13514 static void bnx2x_remove_one(struct pci_dev *pdev)
13515 {
13516         struct net_device *dev = pci_get_drvdata(pdev);
13517         struct bnx2x *bp;
13518
13519         if (!dev) {
13520                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13521                 return;
13522         }
13523         bp = netdev_priv(dev);
13524
13525         __bnx2x_remove(pdev, dev, bp, true);
13526 }
13527
13528 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13529 {
13530         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13531
13532         bp->rx_mode = BNX2X_RX_MODE_NONE;
13533
13534         if (CNIC_LOADED(bp))
13535                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13536
13537         /* Stop Tx */
13538         bnx2x_tx_disable(bp);
13539         /* Delete all NAPI objects */
13540         bnx2x_del_all_napi(bp);
13541         if (CNIC_LOADED(bp))
13542                 bnx2x_del_all_napi_cnic(bp);
13543         netdev_reset_tc(bp->dev);
13544
13545         del_timer_sync(&bp->timer);
13546         cancel_delayed_work_sync(&bp->sp_task);
13547         cancel_delayed_work_sync(&bp->period_task);
13548
13549         spin_lock_bh(&bp->stats_lock);
13550         bp->stats_state = STATS_STATE_DISABLED;
13551         spin_unlock_bh(&bp->stats_lock);
13552
13553         bnx2x_save_statistics(bp);
13554
13555         netif_carrier_off(bp->dev);
13556
13557         return 0;
13558 }
13559
13560 /**
13561  * bnx2x_io_error_detected - called when PCI error is detected
13562  * @pdev: Pointer to PCI device
13563  * @state: The current pci connection state
13564  *
13565  * This function is called after a PCI bus error affecting
13566  * this device has been detected.
13567  */
13568 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13569                                                 pci_channel_state_t state)
13570 {
13571         struct net_device *dev = pci_get_drvdata(pdev);
13572         struct bnx2x *bp = netdev_priv(dev);
13573
13574         rtnl_lock();
13575
13576         BNX2X_ERR("IO error detected\n");
13577
13578         netif_device_detach(dev);
13579
13580         if (state == pci_channel_io_perm_failure) {
13581                 rtnl_unlock();
13582                 return PCI_ERS_RESULT_DISCONNECT;
13583         }
13584
13585         if (netif_running(dev))
13586                 bnx2x_eeh_nic_unload(bp);
13587
13588         bnx2x_prev_path_mark_eeh(bp);
13589
13590         pci_disable_device(pdev);
13591
13592         rtnl_unlock();
13593
13594         /* Request a slot reset */
13595         return PCI_ERS_RESULT_NEED_RESET;
13596 }
13597
13598 /**
13599  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13600  * @pdev: Pointer to PCI device
13601  *
13602  * Restart the card from scratch, as if from a cold-boot.
13603  */
13604 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13605 {
13606         struct net_device *dev = pci_get_drvdata(pdev);
13607         struct bnx2x *bp = netdev_priv(dev);
13608         int i;
13609
13610         rtnl_lock();
13611         BNX2X_ERR("IO slot reset initializing...\n");
13612         if (pci_enable_device(pdev)) {
13613                 dev_err(&pdev->dev,
13614                         "Cannot re-enable PCI device after reset\n");
13615                 rtnl_unlock();
13616                 return PCI_ERS_RESULT_DISCONNECT;
13617         }
13618
13619         pci_set_master(pdev);
13620         pci_restore_state(pdev);
13621         pci_save_state(pdev);
13622
13623         if (netif_running(dev))
13624                 bnx2x_set_power_state(bp, PCI_D0);
13625
13626         if (netif_running(dev)) {
13627                 BNX2X_ERR("IO slot reset --> driver unload\n");
13628
13629                 /* MCP should have been reset; Need to wait for validity */
13630                 bnx2x_init_shmem(bp);
13631
13632                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13633                         u32 v;
13634
13635                         v = SHMEM2_RD(bp,
13636                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13637                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13638                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13639                 }
13640                 bnx2x_drain_tx_queues(bp);
13641                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13642                 bnx2x_netif_stop(bp, 1);
13643                 bnx2x_free_irq(bp);
13644
13645                 /* Report UNLOAD_DONE to MCP */
13646                 bnx2x_send_unload_done(bp, true);
13647
13648                 bp->sp_state = 0;
13649                 bp->port.pmf = 0;
13650
13651                 bnx2x_prev_unload(bp);
13652
13653                 /* We should have reseted the engine, so It's fair to
13654                  * assume the FW will no longer write to the bnx2x driver.
13655                  */
13656                 bnx2x_squeeze_objects(bp);
13657                 bnx2x_free_skbs(bp);
13658                 for_each_rx_queue(bp, i)
13659                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13660                 bnx2x_free_fp_mem(bp);
13661                 bnx2x_free_mem(bp);
13662
13663                 bp->state = BNX2X_STATE_CLOSED;
13664         }
13665
13666         rtnl_unlock();
13667
13668         /* If AER, perform cleanup of the PCIe registers */
13669         if (bp->flags & AER_ENABLED) {
13670                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13671                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13672                 else
13673                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13674         }
13675
13676         return PCI_ERS_RESULT_RECOVERED;
13677 }
13678
13679 /**
13680  * bnx2x_io_resume - called when traffic can start flowing again
13681  * @pdev: Pointer to PCI device
13682  *
13683  * This callback is called when the error recovery driver tells us that
13684  * its OK to resume normal operation.
13685  */
13686 static void bnx2x_io_resume(struct pci_dev *pdev)
13687 {
13688         struct net_device *dev = pci_get_drvdata(pdev);
13689         struct bnx2x *bp = netdev_priv(dev);
13690
13691         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13692                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13693                 return;
13694         }
13695
13696         rtnl_lock();
13697
13698         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13699                                                         DRV_MSG_SEQ_NUMBER_MASK;
13700
13701         if (netif_running(dev))
13702                 bnx2x_nic_load(bp, LOAD_NORMAL);
13703
13704         netif_device_attach(dev);
13705
13706         rtnl_unlock();
13707 }
13708
13709 static const struct pci_error_handlers bnx2x_err_handler = {
13710         .error_detected = bnx2x_io_error_detected,
13711         .slot_reset     = bnx2x_io_slot_reset,
13712         .resume         = bnx2x_io_resume,
13713 };
13714
13715 static void bnx2x_shutdown(struct pci_dev *pdev)
13716 {
13717         struct net_device *dev = pci_get_drvdata(pdev);
13718         struct bnx2x *bp;
13719
13720         if (!dev)
13721                 return;
13722
13723         bp = netdev_priv(dev);
13724         if (!bp)
13725                 return;
13726
13727         rtnl_lock();
13728         netif_device_detach(dev);
13729         rtnl_unlock();
13730
13731         /* Don't remove the netdevice, as there are scenarios which will cause
13732          * the kernel to hang, e.g., when trying to remove bnx2i while the
13733          * rootfs is mounted from SAN.
13734          */
13735         __bnx2x_remove(pdev, dev, bp, false);
13736 }
13737
13738 static struct pci_driver bnx2x_pci_driver = {
13739         .name        = DRV_MODULE_NAME,
13740         .id_table    = bnx2x_pci_tbl,
13741         .probe       = bnx2x_init_one,
13742         .remove      = bnx2x_remove_one,
13743         .suspend     = bnx2x_suspend,
13744         .resume      = bnx2x_resume,
13745         .err_handler = &bnx2x_err_handler,
13746 #ifdef CONFIG_BNX2X_SRIOV
13747         .sriov_configure = bnx2x_sriov_configure,
13748 #endif
13749         .shutdown    = bnx2x_shutdown,
13750 };
13751
13752 static int __init bnx2x_init(void)
13753 {
13754         int ret;
13755
13756         pr_info("%s", version);
13757
13758         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13759         if (bnx2x_wq == NULL) {
13760                 pr_err("Cannot create workqueue\n");
13761                 return -ENOMEM;
13762         }
13763         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13764         if (!bnx2x_iov_wq) {
13765                 pr_err("Cannot create iov workqueue\n");
13766                 destroy_workqueue(bnx2x_wq);
13767                 return -ENOMEM;
13768         }
13769
13770         ret = pci_register_driver(&bnx2x_pci_driver);
13771         if (ret) {
13772                 pr_err("Cannot register driver\n");
13773                 destroy_workqueue(bnx2x_wq);
13774                 destroy_workqueue(bnx2x_iov_wq);
13775         }
13776         return ret;
13777 }
13778
13779 static void __exit bnx2x_cleanup(void)
13780 {
13781         struct list_head *pos, *q;
13782
13783         pci_unregister_driver(&bnx2x_pci_driver);
13784
13785         destroy_workqueue(bnx2x_wq);
13786         destroy_workqueue(bnx2x_iov_wq);
13787
13788         /* Free globally allocated resources */
13789         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13790                 struct bnx2x_prev_path_list *tmp =
13791                         list_entry(pos, struct bnx2x_prev_path_list, list);
13792                 list_del(pos);
13793                 kfree(tmp);
13794         }
13795 }
13796
13797 void bnx2x_notify_link_changed(struct bnx2x *bp)
13798 {
13799         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13800 }
13801
13802 module_init(bnx2x_init);
13803 module_exit(bnx2x_cleanup);
13804
13805 /**
13806  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13807  *
13808  * @bp:         driver handle
13809  * @set:        set or clear the CAM entry
13810  *
13811  * This function will wait until the ramrod completion returns.
13812  * Return 0 if success, -ENODEV if ramrod doesn't return.
13813  */
13814 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13815 {
13816         unsigned long ramrod_flags = 0;
13817
13818         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13819         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13820                                  &bp->iscsi_l2_mac_obj, true,
13821                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13822 }
13823
13824 /* count denotes the number of new completions we have seen */
13825 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13826 {
13827         struct eth_spe *spe;
13828         int cxt_index, cxt_offset;
13829
13830 #ifdef BNX2X_STOP_ON_ERROR
13831         if (unlikely(bp->panic))
13832                 return;
13833 #endif
13834
13835         spin_lock_bh(&bp->spq_lock);
13836         BUG_ON(bp->cnic_spq_pending < count);
13837         bp->cnic_spq_pending -= count;
13838
13839         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13840                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13841                                 & SPE_HDR_CONN_TYPE) >>
13842                                 SPE_HDR_CONN_TYPE_SHIFT;
13843                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13844                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13845
13846                 /* Set validation for iSCSI L2 client before sending SETUP
13847                  *  ramrod
13848                  */
13849                 if (type == ETH_CONNECTION_TYPE) {
13850                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13851                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13852                                         ILT_PAGE_CIDS;
13853                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13854                                         (cxt_index * ILT_PAGE_CIDS);
13855                                 bnx2x_set_ctx_validation(bp,
13856                                         &bp->context[cxt_index].
13857                                                          vcxt[cxt_offset].eth,
13858                                         BNX2X_ISCSI_ETH_CID(bp));
13859                         }
13860                 }
13861
13862                 /*
13863                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13864                  * and in the air. We also check that number of outstanding
13865                  * COMMON ramrods is not more than the EQ and SPQ can
13866                  * accommodate.
13867                  */
13868                 if (type == ETH_CONNECTION_TYPE) {
13869                         if (!atomic_read(&bp->cq_spq_left))
13870                                 break;
13871                         else
13872                                 atomic_dec(&bp->cq_spq_left);
13873                 } else if (type == NONE_CONNECTION_TYPE) {
13874                         if (!atomic_read(&bp->eq_spq_left))
13875                                 break;
13876                         else
13877                                 atomic_dec(&bp->eq_spq_left);
13878                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13879                            (type == FCOE_CONNECTION_TYPE)) {
13880                         if (bp->cnic_spq_pending >=
13881                             bp->cnic_eth_dev.max_kwqe_pending)
13882                                 break;
13883                         else
13884                                 bp->cnic_spq_pending++;
13885                 } else {
13886                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13887                         bnx2x_panic();
13888                         break;
13889                 }
13890
13891                 spe = bnx2x_sp_get_next(bp);
13892                 *spe = *bp->cnic_kwq_cons;
13893
13894                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13895                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13896
13897                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13898                         bp->cnic_kwq_cons = bp->cnic_kwq;
13899                 else
13900                         bp->cnic_kwq_cons++;
13901         }
13902         bnx2x_sp_prod_update(bp);
13903         spin_unlock_bh(&bp->spq_lock);
13904 }
13905
13906 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13907                                struct kwqe_16 *kwqes[], u32 count)
13908 {
13909         struct bnx2x *bp = netdev_priv(dev);
13910         int i;
13911
13912 #ifdef BNX2X_STOP_ON_ERROR
13913         if (unlikely(bp->panic)) {
13914                 BNX2X_ERR("Can't post to SP queue while panic\n");
13915                 return -EIO;
13916         }
13917 #endif
13918
13919         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13920             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13921                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13922                 return -EAGAIN;
13923         }
13924
13925         spin_lock_bh(&bp->spq_lock);
13926
13927         for (i = 0; i < count; i++) {
13928                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13929
13930                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13931                         break;
13932
13933                 *bp->cnic_kwq_prod = *spe;
13934
13935                 bp->cnic_kwq_pending++;
13936
13937                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13938                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13939                    spe->data.update_data_addr.hi,
13940                    spe->data.update_data_addr.lo,
13941                    bp->cnic_kwq_pending);
13942
13943                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13944                         bp->cnic_kwq_prod = bp->cnic_kwq;
13945                 else
13946                         bp->cnic_kwq_prod++;
13947         }
13948
13949         spin_unlock_bh(&bp->spq_lock);
13950
13951         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13952                 bnx2x_cnic_sp_post(bp, 0);
13953
13954         return i;
13955 }
13956
13957 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13958 {
13959         struct cnic_ops *c_ops;
13960         int rc = 0;
13961
13962         mutex_lock(&bp->cnic_mutex);
13963         c_ops = rcu_dereference_protected(bp->cnic_ops,
13964                                           lockdep_is_held(&bp->cnic_mutex));
13965         if (c_ops)
13966                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13967         mutex_unlock(&bp->cnic_mutex);
13968
13969         return rc;
13970 }
13971
13972 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13973 {
13974         struct cnic_ops *c_ops;
13975         int rc = 0;
13976
13977         rcu_read_lock();
13978         c_ops = rcu_dereference(bp->cnic_ops);
13979         if (c_ops)
13980                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13981         rcu_read_unlock();
13982
13983         return rc;
13984 }
13985
13986 /*
13987  * for commands that have no data
13988  */
13989 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13990 {
13991         struct cnic_ctl_info ctl = {0};
13992
13993         ctl.cmd = cmd;
13994
13995         return bnx2x_cnic_ctl_send(bp, &ctl);
13996 }
13997
13998 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13999 {
14000         struct cnic_ctl_info ctl = {0};
14001
14002         /* first we tell CNIC and only then we count this as a completion */
14003         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14004         ctl.data.comp.cid = cid;
14005         ctl.data.comp.error = err;
14006
14007         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14008         bnx2x_cnic_sp_post(bp, 0);
14009 }
14010
14011 /* Called with netif_addr_lock_bh() taken.
14012  * Sets an rx_mode config for an iSCSI ETH client.
14013  * Doesn't block.
14014  * Completion should be checked outside.
14015  */
14016 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14017 {
14018         unsigned long accept_flags = 0, ramrod_flags = 0;
14019         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14020         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14021
14022         if (start) {
14023                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14024                  * because it's the only way for UIO Queue to accept
14025                  * multicasts (in non-promiscuous mode only one Queue per
14026                  * function will receive multicast packets (leading in our
14027                  * case).
14028                  */
14029                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14030                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14031                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14032                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14033
14034                 /* Clear STOP_PENDING bit if START is requested */
14035                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14036
14037                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14038         } else
14039                 /* Clear START_PENDING bit if STOP is requested */
14040                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14041
14042         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14043                 set_bit(sched_state, &bp->sp_state);
14044         else {
14045                 __set_bit(RAMROD_RX, &ramrod_flags);
14046                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14047                                     ramrod_flags);
14048         }
14049 }
14050
14051 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14052 {
14053         struct bnx2x *bp = netdev_priv(dev);
14054         int rc = 0;
14055
14056         switch (ctl->cmd) {
14057         case DRV_CTL_CTXTBL_WR_CMD: {
14058                 u32 index = ctl->data.io.offset;
14059                 dma_addr_t addr = ctl->data.io.dma_addr;
14060
14061                 bnx2x_ilt_wr(bp, index, addr);
14062                 break;
14063         }
14064
14065         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14066                 int count = ctl->data.credit.credit_count;
14067
14068                 bnx2x_cnic_sp_post(bp, count);
14069                 break;
14070         }
14071
14072         /* rtnl_lock is held.  */
14073         case DRV_CTL_START_L2_CMD: {
14074                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14075                 unsigned long sp_bits = 0;
14076
14077                 /* Configure the iSCSI classification object */
14078                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14079                                    cp->iscsi_l2_client_id,
14080                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14081                                    bnx2x_sp(bp, mac_rdata),
14082                                    bnx2x_sp_mapping(bp, mac_rdata),
14083                                    BNX2X_FILTER_MAC_PENDING,
14084                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14085                                    &bp->macs_pool);
14086
14087                 /* Set iSCSI MAC address */
14088                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14089                 if (rc)
14090                         break;
14091
14092                 mmiowb();
14093                 barrier();
14094
14095                 /* Start accepting on iSCSI L2 ring */
14096
14097                 netif_addr_lock_bh(dev);
14098                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14099                 netif_addr_unlock_bh(dev);
14100
14101                 /* bits to wait on */
14102                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14103                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14104
14105                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14106                         BNX2X_ERR("rx_mode completion timed out!\n");
14107
14108                 break;
14109         }
14110
14111         /* rtnl_lock is held.  */
14112         case DRV_CTL_STOP_L2_CMD: {
14113                 unsigned long sp_bits = 0;
14114
14115                 /* Stop accepting on iSCSI L2 ring */
14116                 netif_addr_lock_bh(dev);
14117                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14118                 netif_addr_unlock_bh(dev);
14119
14120                 /* bits to wait on */
14121                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14122                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14123
14124                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14125                         BNX2X_ERR("rx_mode completion timed out!\n");
14126
14127                 mmiowb();
14128                 barrier();
14129
14130                 /* Unset iSCSI L2 MAC */
14131                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14132                                         BNX2X_ISCSI_ETH_MAC, true);
14133                 break;
14134         }
14135         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14136                 int count = ctl->data.credit.credit_count;
14137
14138                 smp_mb__before_atomic();
14139                 atomic_add(count, &bp->cq_spq_left);
14140                 smp_mb__after_atomic();
14141                 break;
14142         }
14143         case DRV_CTL_ULP_REGISTER_CMD: {
14144                 int ulp_type = ctl->data.register_data.ulp_type;
14145
14146                 if (CHIP_IS_E3(bp)) {
14147                         int idx = BP_FW_MB_IDX(bp);
14148                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14149                         int path = BP_PATH(bp);
14150                         int port = BP_PORT(bp);
14151                         int i;
14152                         u32 scratch_offset;
14153                         u32 *host_addr;
14154
14155                         /* first write capability to shmem2 */
14156                         if (ulp_type == CNIC_ULP_ISCSI)
14157                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14158                         else if (ulp_type == CNIC_ULP_FCOE)
14159                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14160                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14161
14162                         if ((ulp_type != CNIC_ULP_FCOE) ||
14163                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14164                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14165                                 break;
14166
14167                         /* if reached here - should write fcoe capabilities */
14168                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14169                         if (!scratch_offset)
14170                                 break;
14171                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14172                                                    fcoe_features[path][port]);
14173                         host_addr = (u32 *) &(ctl->data.register_data.
14174                                               fcoe_features);
14175                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14176                              i += 4)
14177                                 REG_WR(bp, scratch_offset + i,
14178                                        *(host_addr + i/4));
14179                 }
14180                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14181                 break;
14182         }
14183
14184         case DRV_CTL_ULP_UNREGISTER_CMD: {
14185                 int ulp_type = ctl->data.ulp_type;
14186
14187                 if (CHIP_IS_E3(bp)) {
14188                         int idx = BP_FW_MB_IDX(bp);
14189                         u32 cap;
14190
14191                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14192                         if (ulp_type == CNIC_ULP_ISCSI)
14193                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14194                         else if (ulp_type == CNIC_ULP_FCOE)
14195                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14196                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14197                 }
14198                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14199                 break;
14200         }
14201
14202         default:
14203                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14204                 rc = -EINVAL;
14205         }
14206
14207         return rc;
14208 }
14209
14210 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14211 {
14212         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14213
14214         if (bp->flags & USING_MSIX_FLAG) {
14215                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14216                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14217                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14218         } else {
14219                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14220                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14221         }
14222         if (!CHIP_IS_E1x(bp))
14223                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14224         else
14225                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14226
14227         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14228         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14229         cp->irq_arr[1].status_blk = bp->def_status_blk;
14230         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14231         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14232
14233         cp->num_irq = 2;
14234 }
14235
14236 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14237 {
14238         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14239
14240         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14241                              bnx2x_cid_ilt_lines(bp);
14242         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14243         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14244         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14245
14246         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14247            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14248            cp->iscsi_l2_cid);
14249
14250         if (NO_ISCSI_OOO(bp))
14251                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14252 }
14253
14254 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14255                                void *data)
14256 {
14257         struct bnx2x *bp = netdev_priv(dev);
14258         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14259         int rc;
14260
14261         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14262
14263         if (ops == NULL) {
14264                 BNX2X_ERR("NULL ops received\n");
14265                 return -EINVAL;
14266         }
14267
14268         if (!CNIC_SUPPORT(bp)) {
14269                 BNX2X_ERR("Can't register CNIC when not supported\n");
14270                 return -EOPNOTSUPP;
14271         }
14272
14273         if (!CNIC_LOADED(bp)) {
14274                 rc = bnx2x_load_cnic(bp);
14275                 if (rc) {
14276                         BNX2X_ERR("CNIC-related load failed\n");
14277                         return rc;
14278                 }
14279         }
14280
14281         bp->cnic_enabled = true;
14282
14283         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14284         if (!bp->cnic_kwq)
14285                 return -ENOMEM;
14286
14287         bp->cnic_kwq_cons = bp->cnic_kwq;
14288         bp->cnic_kwq_prod = bp->cnic_kwq;
14289         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14290
14291         bp->cnic_spq_pending = 0;
14292         bp->cnic_kwq_pending = 0;
14293
14294         bp->cnic_data = data;
14295
14296         cp->num_irq = 0;
14297         cp->drv_state |= CNIC_DRV_STATE_REGD;
14298         cp->iro_arr = bp->iro_arr;
14299
14300         bnx2x_setup_cnic_irq_info(bp);
14301
14302         rcu_assign_pointer(bp->cnic_ops, ops);
14303
14304         /* Schedule driver to read CNIC driver versions */
14305         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14306
14307         return 0;
14308 }
14309
14310 static int bnx2x_unregister_cnic(struct net_device *dev)
14311 {
14312         struct bnx2x *bp = netdev_priv(dev);
14313         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14314
14315         mutex_lock(&bp->cnic_mutex);
14316         cp->drv_state = 0;
14317         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14318         mutex_unlock(&bp->cnic_mutex);
14319         synchronize_rcu();
14320         bp->cnic_enabled = false;
14321         kfree(bp->cnic_kwq);
14322         bp->cnic_kwq = NULL;
14323
14324         return 0;
14325 }
14326
14327 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14328 {
14329         struct bnx2x *bp = netdev_priv(dev);
14330         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14331
14332         /* If both iSCSI and FCoE are disabled - return NULL in
14333          * order to indicate CNIC that it should not try to work
14334          * with this device.
14335          */
14336         if (NO_ISCSI(bp) && NO_FCOE(bp))
14337                 return NULL;
14338
14339         cp->drv_owner = THIS_MODULE;
14340         cp->chip_id = CHIP_ID(bp);
14341         cp->pdev = bp->pdev;
14342         cp->io_base = bp->regview;
14343         cp->io_base2 = bp->doorbells;
14344         cp->max_kwqe_pending = 8;
14345         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14346         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14347                              bnx2x_cid_ilt_lines(bp);
14348         cp->ctx_tbl_len = CNIC_ILT_LINES;
14349         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14350         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14351         cp->drv_ctl = bnx2x_drv_ctl;
14352         cp->drv_register_cnic = bnx2x_register_cnic;
14353         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14354         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14355         cp->iscsi_l2_client_id =
14356                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14357         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14358
14359         if (NO_ISCSI_OOO(bp))
14360                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14361
14362         if (NO_ISCSI(bp))
14363                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14364
14365         if (NO_FCOE(bp))
14366                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14367
14368         BNX2X_DEV_INFO(
14369                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14370            cp->ctx_blk_size,
14371            cp->ctx_tbl_offset,
14372            cp->ctx_tbl_len,
14373            cp->starting_cid);
14374         return cp;
14375 }
14376
14377 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14378 {
14379         struct bnx2x *bp = fp->bp;
14380         u32 offset = BAR_USTRORM_INTMEM;
14381
14382         if (IS_VF(bp))
14383                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14384         else if (!CHIP_IS_E1x(bp))
14385                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14386         else
14387                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14388
14389         return offset;
14390 }
14391
14392 /* called only on E1H or E2.
14393  * When pretending to be PF, the pretend value is the function number 0...7
14394  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14395  * combination
14396  */
14397 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14398 {
14399         u32 pretend_reg;
14400
14401         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14402                 return -1;
14403
14404         /* get my own pretend register */
14405         pretend_reg = bnx2x_get_pretend_reg(bp);
14406         REG_WR(bp, pretend_reg, pretend_func_val);
14407         REG_RD(bp, pretend_reg);
14408         return 0;
14409 }
14410
14411 static void bnx2x_ptp_task(struct work_struct *work)
14412 {
14413         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14414         int port = BP_PORT(bp);
14415         u32 val_seq;
14416         u64 timestamp, ns;
14417         struct skb_shared_hwtstamps shhwtstamps;
14418
14419         /* Read Tx timestamp registers */
14420         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14421                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14422         if (val_seq & 0x10000) {
14423                 /* There is a valid timestamp value */
14424                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14425                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14426                 timestamp <<= 32;
14427                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14428                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14429                 /* Reset timestamp register to allow new timestamp */
14430                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14431                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14432                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14433
14434                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14435                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14436                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14437                 dev_kfree_skb_any(bp->ptp_tx_skb);
14438                 bp->ptp_tx_skb = NULL;
14439
14440                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14441                    timestamp, ns);
14442         } else {
14443                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14444                 /* Reschedule to keep checking for a valid timestamp value */
14445                 schedule_work(&bp->ptp_task);
14446         }
14447 }
14448
14449 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14450 {
14451         int port = BP_PORT(bp);
14452         u64 timestamp, ns;
14453
14454         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14455                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14456         timestamp <<= 32;
14457         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14458                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14459
14460         /* Reset timestamp register to allow new timestamp */
14461         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14462                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14463
14464         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14465
14466         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14467
14468         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14469            timestamp, ns);
14470 }
14471
14472 /* Read the PHC */
14473 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14474 {
14475         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14476         int port = BP_PORT(bp);
14477         u32 wb_data[2];
14478         u64 phc_cycles;
14479
14480         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14481                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14482         phc_cycles = wb_data[1];
14483         phc_cycles = (phc_cycles << 32) + wb_data[0];
14484
14485         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14486
14487         return phc_cycles;
14488 }
14489
14490 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14491 {
14492         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14493         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14494         bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14495         bp->cyclecounter.shift = 1;
14496         bp->cyclecounter.mult = 1;
14497 }
14498
14499 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14500 {
14501         struct bnx2x_func_state_params func_params = {NULL};
14502         struct bnx2x_func_set_timesync_params *set_timesync_params =
14503                 &func_params.params.set_timesync;
14504
14505         /* Prepare parameters for function state transitions */
14506         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14507         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14508
14509         func_params.f_obj = &bp->func_obj;
14510         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14511
14512         /* Function parameters */
14513         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14514         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14515
14516         return bnx2x_func_state_change(bp, &func_params);
14517 }
14518
14519 int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14520 {
14521         struct bnx2x_queue_state_params q_params;
14522         int rc, i;
14523
14524         /* send queue update ramrod to enable PTP packets */
14525         memset(&q_params, 0, sizeof(q_params));
14526         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14527         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14528         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14529                   &q_params.params.update.update_flags);
14530         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14531                   &q_params.params.update.update_flags);
14532
14533         /* send the ramrod on all the queues of the PF */
14534         for_each_eth_queue(bp, i) {
14535                 struct bnx2x_fastpath *fp = &bp->fp[i];
14536
14537                 /* Set the appropriate Queue object */
14538                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14539
14540                 /* Update the Queue state */
14541                 rc = bnx2x_queue_state_change(bp, &q_params);
14542                 if (rc) {
14543                         BNX2X_ERR("Failed to enable PTP packets\n");
14544                         return rc;
14545                 }
14546         }
14547
14548         return 0;
14549 }
14550
14551 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14552 {
14553         int port = BP_PORT(bp);
14554         int rc;
14555
14556         if (!bp->hwtstamp_ioctl_called)
14557                 return 0;
14558
14559         switch (bp->tx_type) {
14560         case HWTSTAMP_TX_ON:
14561                 bp->flags |= TX_TIMESTAMPING_EN;
14562                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14563                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14564                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14565                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14566                 break;
14567         case HWTSTAMP_TX_ONESTEP_SYNC:
14568                 BNX2X_ERR("One-step timestamping is not supported\n");
14569                 return -ERANGE;
14570         }
14571
14572         switch (bp->rx_filter) {
14573         case HWTSTAMP_FILTER_NONE:
14574                 break;
14575         case HWTSTAMP_FILTER_ALL:
14576         case HWTSTAMP_FILTER_SOME:
14577                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14578                 break;
14579         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14580         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14581         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14582                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14583                 /* Initialize PTP detection for UDP/IPv4 events */
14584                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14585                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14586                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14587                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14588                 break;
14589         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14590         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14591         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14592                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14593                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14594                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14595                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14596                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14597                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14598                 break;
14599         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14600         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14601         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14602                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14603                 /* Initialize PTP detection L2 events */
14604                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14605                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14606                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14607                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14608
14609                 break;
14610         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14611         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14612         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14613                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14614                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14615                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14616                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14617                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14618                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14619                 break;
14620         }
14621
14622         /* Indicate to FW that this PF expects recorded PTP packets */
14623         rc = bnx2x_enable_ptp_packets(bp);
14624         if (rc)
14625                 return rc;
14626
14627         /* Enable sending PTP packets to host */
14628         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14629                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14630
14631         return 0;
14632 }
14633
14634 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14635 {
14636         struct hwtstamp_config config;
14637         int rc;
14638
14639         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14640
14641         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14642                 return -EFAULT;
14643
14644         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14645            config.tx_type, config.rx_filter);
14646
14647         if (config.flags) {
14648                 BNX2X_ERR("config.flags is reserved for future use\n");
14649                 return -EINVAL;
14650         }
14651
14652         bp->hwtstamp_ioctl_called = 1;
14653         bp->tx_type = config.tx_type;
14654         bp->rx_filter = config.rx_filter;
14655
14656         rc = bnx2x_configure_ptp_filters(bp);
14657         if (rc)
14658                 return rc;
14659
14660         config.rx_filter = bp->rx_filter;
14661
14662         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14663                 -EFAULT : 0;
14664 }
14665
14666 /* Configrues HW for PTP */
14667 static int bnx2x_configure_ptp(struct bnx2x *bp)
14668 {
14669         int rc, port = BP_PORT(bp);
14670         u32 wb_data[2];
14671
14672         /* Reset PTP event detection rules - will be configured in the IOCTL */
14673         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14674                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14675         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14676                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14677         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14678                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14679         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14680                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14681
14682         /* Disable PTP packets to host - will be configured in the IOCTL*/
14683         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14684                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14685
14686         /* Enable the PTP feature */
14687         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14688                NIG_REG_P0_PTP_EN, 0x3F);
14689
14690         /* Enable the free-running counter */
14691         wb_data[0] = 0;
14692         wb_data[1] = 0;
14693         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14694
14695         /* Reset drift register (offset register is not reset) */
14696         rc = bnx2x_send_reset_timesync_ramrod(bp);
14697         if (rc) {
14698                 BNX2X_ERR("Failed to reset PHC drift register\n");
14699                 return -EFAULT;
14700         }
14701
14702         /* Reset possibly old timestamps */
14703         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14704                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14705         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14706                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14707
14708         return 0;
14709 }
14710
14711 /* Called during load, to initialize PTP-related stuff */
14712 void bnx2x_init_ptp(struct bnx2x *bp)
14713 {
14714         int rc;
14715
14716         /* Configure PTP in HW */
14717         rc = bnx2x_configure_ptp(bp);
14718         if (rc) {
14719                 BNX2X_ERR("Stopping PTP initialization\n");
14720                 return;
14721         }
14722
14723         /* Init work queue for Tx timestamping */
14724         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14725
14726         /* Init cyclecounter and timecounter. This is done only in the first
14727          * load. If done in every load, PTP application will fail when doing
14728          * unload / load (e.g. MTU change) while it is running.
14729          */
14730         if (!bp->timecounter_init_done) {
14731                 bnx2x_init_cyclecounter(bp);
14732                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14733                                  ktime_to_ns(ktime_get_real()));
14734                 bp->timecounter_init_done = 1;
14735         }
14736
14737         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14738 }