drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2012 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_dcb.h"
  63 #include "bnx2x_sp.h"
  64
  65 #include <linux/firmware.h>
  66 #include "bnx2x_fw_file_hdr.h"
  67 /* FW files */
  68 #define FW_FILE_VERSION                                 \
  69         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  70         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  72         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  73 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  74 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  76
  77 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
  78
  79 /* Time in jiffies before concluding the transmitter is hung */
  80 #define TX_TIMEOUT              (5*HZ)
  81
  82 static char version[] =
  83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  85
  86 MODULE_AUTHOR("Eliezer Tamir");
  87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  88                    "BCM57710/57711/57711E/"
  89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  90                    "57840/57840_MF Driver");
  91 MODULE_LICENSE("GPL");
  92 MODULE_VERSION(DRV_MODULE_VERSION);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  96
  97
  98 int num_queues;
  99 module_param(num_queues, int, 0);
 100 MODULE_PARM_DESC(num_queues,
 101                  " Set number of queues (default is as a number of CPUs)");
 102
 103 static int disable_tpa;
 104 module_param(disable_tpa, int, 0);
 105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 106
 107 #define INT_MODE_INTx                   1
 108 #define INT_MODE_MSI                    2
 109 int int_mode;
 110 module_param(int_mode, int, 0);
 111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 112                                 "(1 INT#x; 2 MSI)");
 113
 114 static int dropless_fc;
 115 module_param(dropless_fc, int, 0);
 116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 117
 118 static int mrrs = -1;
 119 module_param(mrrs, int, 0);
 120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 121
 122 static int debug;
 123 module_param(debug, int, 0);
 124 MODULE_PARM_DESC(debug, " Default debug msglevel");
 125
 126
 127
 128 struct workqueue_struct *bnx2x_wq;
 129
 130 enum bnx2x_board_type {
 131         BCM57710 = 0,
 132         BCM57711,
 133         BCM57711E,
 134         BCM57712,
 135         BCM57712_MF,
 136         BCM57800,
 137         BCM57800_MF,
 138         BCM57810,
 139         BCM57810_MF,
 140         BCM57840_O,
 141         BCM57840_4_10,
 142         BCM57840_2_20,
 143         BCM57840_MFO,
 144         BCM57840_MF,
 145         BCM57811,
 146         BCM57811_MF
 147 };
 148
 149 /* indexed by board_type, above */
 150 static struct {
 151         char *name;
 152 } board_info[] = {
 153         { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 154         { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 155         { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 156         { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 157         { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 158         { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 159         { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 160         { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 161         { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 162         { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 163         { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 164         { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 165         { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
 166         { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
 167         { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
 168         { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
 169 };
 170
 171 #ifndef PCI_DEVICE_ID_NX2_57710
 172 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 173 #endif
 174 #ifndef PCI_DEVICE_ID_NX2_57711
 175 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 176 #endif
 177 #ifndef PCI_DEVICE_ID_NX2_57711E
 178 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 179 #endif
 180 #ifndef PCI_DEVICE_ID_NX2_57712
 181 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 182 #endif
 183 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 184 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 185 #endif
 186 #ifndef PCI_DEVICE_ID_NX2_57800
 187 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 188 #endif
 189 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 190 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57810
 193 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 196 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57840_O
 199 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 202 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 205 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 208 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 211 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57811
 214 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 217 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 218 #endif
 219 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 220         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 221         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 222         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 223         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 224         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 225         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 226         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 227         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 228         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 229         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 230         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 231         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 232         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 233         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 234         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 235         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 236         { 0 }
 237 };
 238
 239 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 240
 241 /* Global resources for unloading a previously loaded device */
 242 #define BNX2X_PREV_WAIT_NEEDED 1
 243 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 244 static LIST_HEAD(bnx2x_prev_list);
 245 /****************************************************************************
 246 * General service functions
 247 ****************************************************************************/
 248
 249 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 250                                        u32 addr, dma_addr_t mapping)
 251 {
 252         REG_WR(bp,  addr, U64_LO(mapping));
 253         REG_WR(bp,  addr + 4, U64_HI(mapping));
 254 }
 255
 256 static void storm_memset_spq_addr(struct bnx2x *bp,
 257                                   dma_addr_t mapping, u16 abs_fid)
 258 {
 259         u32 addr = XSEM_REG_FAST_MEMORY +
 260                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 261
 262         __storm_memset_dma_mapping(bp, addr, mapping);
 263 }
 264
 265 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 266                                   u16 pf_id)
 267 {
 268         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 269                 pf_id);
 270         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 271                 pf_id);
 272         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 273                 pf_id);
 274         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 275                 pf_id);
 276 }
 277
 278 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 279                                  u8 enable)
 280 {
 281         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 282                 enable);
 283         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 284                 enable);
 285         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 286                 enable);
 287         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 288                 enable);
 289 }
 290
 291 static void storm_memset_eq_data(struct bnx2x *bp,
 292                                  struct event_ring_data *eq_data,
 293                                 u16 pfid)
 294 {
 295         size_t size = sizeof(struct event_ring_data);
 296
 297         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 298
 299         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 300 }
 301
 302 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 303                                  u16 pfid)
 304 {
 305         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 306         REG_WR16(bp, addr, eq_prod);
 307 }
 308
 309 /* used only at init
 310  * locking is done by mcp
 311  */
 312 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 313 {
 314         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 315         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 316         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 317                                PCICFG_VENDOR_ID_OFFSET);
 318 }
 319
 320 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 321 {
 322         u32 val;
 323
 324         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 325         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 326         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 327                                PCICFG_VENDOR_ID_OFFSET);
 328
 329         return val;
 330 }
 331
 332 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 333 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 334 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 335 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 336 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 337
 338
 339 /* copy command into DMAE command memory and set DMAE command go */
 340 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 341 {
 342         u32 cmd_offset;
 343         int i;
 344
 345         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 346         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 347                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 348         }
 349         REG_WR(bp, dmae_reg_go_c[idx], 1);
 350 }
 351
 352 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 353 {
 354         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 355                            DMAE_CMD_C_ENABLE);
 356 }
 357
 358 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 359 {
 360         return opcode & ~DMAE_CMD_SRC_RESET;
 361 }
 362
 363 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 364                              bool with_comp, u8 comp_type)
 365 {
 366         u32 opcode = 0;
 367
 368         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 369                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 370
 371         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 372
 373         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 374         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 375                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 376         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 377
 378 #ifdef __BIG_ENDIAN
 379         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 380 #else
 381         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 382 #endif
 383         if (with_comp)
 384                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 385         return opcode;
 386 }
 387
 388 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 389                                       struct dmae_command *dmae,
 390                                       u8 src_type, u8 dst_type)
 391 {
 392         memset(dmae, 0, sizeof(struct dmae_command));
 393
 394         /* set the opcode */
 395         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 396                                          true, DMAE_COMP_PCI);
 397
 398         /* fill in the completion parameters */
 399         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 400         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 401         dmae->comp_val = DMAE_COMP_VAL;
 402 }
 403
 404 /* issue a dmae command over the init-channel and wailt for completion */
 405 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
 406                                       struct dmae_command *dmae)
 407 {
 408         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 409         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 410         int rc = 0;
 411
 412         /*
 413          * Lock the dmae channel. Disable BHs to prevent a dead-lock
 414          * as long as this code is called both from syscall context and
 415          * from ndo_set_rx_mode() flow that may be called from BH.
 416          */
 417         spin_lock_bh(&bp->dmae_lock);
 418
 419         /* reset completion */
 420         *wb_comp = 0;
 421
 422         /* post the command on the channel used for initializations */
 423         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 424
 425         /* wait for completion */
 426         udelay(5);
 427         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 428
 429                 if (!cnt ||
 430                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 431                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 432                         BNX2X_ERR("DMAE timeout!\n");
 433                         rc = DMAE_TIMEOUT;
 434                         goto unlock;
 435                 }
 436                 cnt--;
 437                 udelay(50);
 438         }
 439         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 440                 BNX2X_ERR("DMAE PCI error!\n");
 441                 rc = DMAE_PCI_ERROR;
 442         }
 443
 444 unlock:
 445         spin_unlock_bh(&bp->dmae_lock);
 446         return rc;
 447 }
 448
 449 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 450                       u32 len32)
 451 {
 452         struct dmae_command dmae;
 453
 454         if (!bp->dmae_ready) {
 455                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 456
 457                 if (CHIP_IS_E1(bp))
 458                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 459                 else
 460                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 461                 return;
 462         }
 463
 464         /* set opcode and fixed command fields */
 465         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 466
 467         /* fill in addresses and len */
 468         dmae.src_addr_lo = U64_LO(dma_addr);
 469         dmae.src_addr_hi = U64_HI(dma_addr);
 470         dmae.dst_addr_lo = dst_addr >> 2;
 471         dmae.dst_addr_hi = 0;
 472         dmae.len = len32;
 473
 474         /* issue the command and wait for completion */
 475         bnx2x_issue_dmae_with_comp(bp, &dmae);
 476 }
 477
 478 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 479 {
 480         struct dmae_command dmae;
 481
 482         if (!bp->dmae_ready) {
 483                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 484                 int i;
 485
 486                 if (CHIP_IS_E1(bp))
 487                         for (i = 0; i < len32; i++)
 488                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 489                 else
 490                         for (i = 0; i < len32; i++)
 491                                 data[i] = REG_RD(bp, src_addr + i*4);
 492
 493                 return;
 494         }
 495
 496         /* set opcode and fixed command fields */
 497         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 498
 499         /* fill in addresses and len */
 500         dmae.src_addr_lo = src_addr >> 2;
 501         dmae.src_addr_hi = 0;
 502         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 503         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 504         dmae.len = len32;
 505
 506         /* issue the command and wait for completion */
 507         bnx2x_issue_dmae_with_comp(bp, &dmae);
 508 }
 509
 510 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 511                                       u32 addr, u32 len)
 512 {
 513         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 514         int offset = 0;
 515
 516         while (len > dmae_wr_max) {
 517                 bnx2x_write_dmae(bp, phys_addr + offset,
 518                                  addr + offset, dmae_wr_max);
 519                 offset += dmae_wr_max * 4;
 520                 len -= dmae_wr_max;
 521         }
 522
 523         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 524 }
 525
 526 static int bnx2x_mc_assert(struct bnx2x *bp)
 527 {
 528         char last_idx;
 529         int i, rc = 0;
 530         u32 row0, row1, row2, row3;
 531
 532         /* XSTORM */
 533         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 534                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 535         if (last_idx)
 536                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 537
 538         /* print the asserts */
 539         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 540
 541                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 542                               XSTORM_ASSERT_LIST_OFFSET(i));
 543                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 544                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 545                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 546                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 547                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 548                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 549
 550                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 551                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 552                                   i, row3, row2, row1, row0);
 553                         rc++;
 554                 } else {
 555                         break;
 556                 }
 557         }
 558
 559         /* TSTORM */
 560         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 561                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 562         if (last_idx)
 563                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 564
 565         /* print the asserts */
 566         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 567
 568                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 569                               TSTORM_ASSERT_LIST_OFFSET(i));
 570                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 571                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 572                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 573                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 574                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 575                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 576
 577                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 578                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 579                                   i, row3, row2, row1, row0);
 580                         rc++;
 581                 } else {
 582                         break;
 583                 }
 584         }
 585
 586         /* CSTORM */
 587         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 588                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 589         if (last_idx)
 590                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 591
 592         /* print the asserts */
 593         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 594
 595                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 596                               CSTORM_ASSERT_LIST_OFFSET(i));
 597                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 598                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 599                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 600                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 601                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 602                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 603
 604                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 605                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 606                                   i, row3, row2, row1, row0);
 607                         rc++;
 608                 } else {
 609                         break;
 610                 }
 611         }
 612
 613         /* USTORM */
 614         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 615                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 616         if (last_idx)
 617                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 618
 619         /* print the asserts */
 620         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 621
 622                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 623                               USTORM_ASSERT_LIST_OFFSET(i));
 624                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 625                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 626                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 627                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 628                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 629                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 630
 631                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 632                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 633                                   i, row3, row2, row1, row0);
 634                         rc++;
 635                 } else {
 636                         break;
 637                 }
 638         }
 639
 640         return rc;
 641 }
 642
 643 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 644 {
 645         u32 addr, val;
 646         u32 mark, offset;
 647         __be32 data[9];
 648         int word;
 649         u32 trace_shmem_base;
 650         if (BP_NOMCP(bp)) {
 651                 BNX2X_ERR("NO MCP - can not dump\n");
 652                 return;
 653         }
 654         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 655                 (bp->common.bc_ver & 0xff0000) >> 16,
 656                 (bp->common.bc_ver & 0xff00) >> 8,
 657                 (bp->common.bc_ver & 0xff));
 658
 659         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 660         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 661                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 662
 663         if (BP_PATH(bp) == 0)
 664                 trace_shmem_base = bp->common.shmem_base;
 665         else
 666                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 667         addr = trace_shmem_base - 0x800;
 668
 669         /* validate TRCB signature */
 670         mark = REG_RD(bp, addr);
 671         if (mark != MFW_TRACE_SIGNATURE) {
 672                 BNX2X_ERR("Trace buffer signature is missing.");
 673                 return ;
 674         }
 675
 676         /* read cyclic buffer pointer */
 677         addr += 4;
 678         mark = REG_RD(bp, addr);
 679         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 680                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 681         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 682
 683         printk("%s", lvl);
 684         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 685                 for (word = 0; word < 8; word++)
 686                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 687                 data[8] = 0x0;
 688                 pr_cont("%s", (char *)data);
 689         }
 690         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 691                 for (word = 0; word < 8; word++)
 692                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 693                 data[8] = 0x0;
 694                 pr_cont("%s", (char *)data);
 695         }
 696         printk("%s" "end of fw dump\n", lvl);
 697 }
 698
 699 static void bnx2x_fw_dump(struct bnx2x *bp)
 700 {
 701         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 702 }
 703
 704 void bnx2x_panic_dump(struct bnx2x *bp)
 705 {
 706         int i;
 707         u16 j;
 708         struct hc_sp_status_block_data sp_sb_data;
 709         int func = BP_FUNC(bp);
 710 #ifdef BNX2X_STOP_ON_ERROR
 711         u16 start = 0, end = 0;
 712         u8 cos;
 713 #endif
 714
 715         bp->stats_state = STATS_STATE_DISABLED;
 716         bp->eth_stats.unrecoverable_error++;
 717         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 718
 719         BNX2X_ERR("begin crash dump -----------------\n");
 720
 721         /* Indices */
 722         /* Common */
 723         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 724                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 725                   bp->spq_prod_idx, bp->stats_counter);
 726         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 727                   bp->def_status_blk->atten_status_block.attn_bits,
 728                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 729                   bp->def_status_blk->atten_status_block.status_block_id,
 730                   bp->def_status_blk->atten_status_block.attn_bits_index);
 731         BNX2X_ERR("     def (");
 732         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 733                 pr_cont("0x%x%s",
 734                         bp->def_status_blk->sp_sb.index_values[i],
 735                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 736
 737         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 738                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 739                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 740                         i*sizeof(u32));
 741
 742         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 743                sp_sb_data.igu_sb_id,
 744                sp_sb_data.igu_seg_id,
 745                sp_sb_data.p_func.pf_id,
 746                sp_sb_data.p_func.vnic_id,
 747                sp_sb_data.p_func.vf_id,
 748                sp_sb_data.p_func.vf_valid,
 749                sp_sb_data.state);
 750
 751
 752         for_each_eth_queue(bp, i) {
 753                 struct bnx2x_fastpath *fp = &bp->fp[i];
 754                 int loop;
 755                 struct hc_status_block_data_e2 sb_data_e2;
 756                 struct hc_status_block_data_e1x sb_data_e1x;
 757                 struct hc_status_block_sm  *hc_sm_p =
 758                         CHIP_IS_E1x(bp) ?
 759                         sb_data_e1x.common.state_machine :
 760                         sb_data_e2.common.state_machine;
 761                 struct hc_index_data *hc_index_p =
 762                         CHIP_IS_E1x(bp) ?
 763                         sb_data_e1x.index_data :
 764                         sb_data_e2.index_data;
 765                 u8 data_size, cos;
 766                 u32 *sb_data_p;
 767                 struct bnx2x_fp_txdata txdata;
 768
 769                 /* Rx */
 770                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 771                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 772                           fp->rx_comp_prod,
 773                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 774                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 775                           fp->rx_sge_prod, fp->last_max_sge,
 776                           le16_to_cpu(fp->fp_hc_idx));
 777
 778                 /* Tx */
 779                 for_each_cos_in_tx_queue(fp, cos)
 780                 {
 781                         txdata = *fp->txdata_ptr[cos];
 782                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 783                                   i, txdata.tx_pkt_prod,
 784                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 785                                   txdata.tx_bd_cons,
 786                                   le16_to_cpu(*txdata.tx_cons_sb));
 787                 }
 788
 789                 loop = CHIP_IS_E1x(bp) ?
 790                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 791
 792                 /* host sb data */
 793
 794                 if (IS_FCOE_FP(fp))
 795                         continue;
 796
 797                 BNX2X_ERR("     run indexes (");
 798                 for (j = 0; j < HC_SB_MAX_SM; j++)
 799                         pr_cont("0x%x%s",
 800                                fp->sb_running_index[j],
 801                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 802
 803                 BNX2X_ERR("     indexes (");
 804                 for (j = 0; j < loop; j++)
 805                         pr_cont("0x%x%s",
 806                                fp->sb_index_values[j],
 807                                (j == loop - 1) ? ")" : " ");
 808                 /* fw sb data */
 809                 data_size = CHIP_IS_E1x(bp) ?
 810                         sizeof(struct hc_status_block_data_e1x) :
 811                         sizeof(struct hc_status_block_data_e2);
 812                 data_size /= sizeof(u32);
 813                 sb_data_p = CHIP_IS_E1x(bp) ?
 814                         (u32 *)&sb_data_e1x :
 815                         (u32 *)&sb_data_e2;
 816                 /* copy sb data in here */
 817                 for (j = 0; j < data_size; j++)
 818                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 819                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
 820                                 j * sizeof(u32));
 821
 822                 if (!CHIP_IS_E1x(bp)) {
 823                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 824                                 sb_data_e2.common.p_func.pf_id,
 825                                 sb_data_e2.common.p_func.vf_id,
 826                                 sb_data_e2.common.p_func.vf_valid,
 827                                 sb_data_e2.common.p_func.vnic_id,
 828                                 sb_data_e2.common.same_igu_sb_1b,
 829                                 sb_data_e2.common.state);
 830                 } else {
 831                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 832                                 sb_data_e1x.common.p_func.pf_id,
 833                                 sb_data_e1x.common.p_func.vf_id,
 834                                 sb_data_e1x.common.p_func.vf_valid,
 835                                 sb_data_e1x.common.p_func.vnic_id,
 836                                 sb_data_e1x.common.same_igu_sb_1b,
 837                                 sb_data_e1x.common.state);
 838                 }
 839
 840                 /* SB_SMs data */
 841                 for (j = 0; j < HC_SB_MAX_SM; j++) {
 842                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
 843                                 j, hc_sm_p[j].__flags,
 844                                 hc_sm_p[j].igu_sb_id,
 845                                 hc_sm_p[j].igu_seg_id,
 846                                 hc_sm_p[j].time_to_expire,
 847                                 hc_sm_p[j].timer_value);
 848                 }
 849
 850                 /* Indecies data */
 851                 for (j = 0; j < loop; j++) {
 852                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
 853                                hc_index_p[j].flags,
 854                                hc_index_p[j].timeout);
 855                 }
 856         }
 857
 858 #ifdef BNX2X_STOP_ON_ERROR
 859         /* Rings */
 860         /* Rx */
 861         for_each_valid_rx_queue(bp, i) {
 862                 struct bnx2x_fastpath *fp = &bp->fp[i];
 863
 864                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
 865                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
 866                 for (j = start; j != end; j = RX_BD(j + 1)) {
 867                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
 868                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
 869
 870                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
 871                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
 872                 }
 873
 874                 start = RX_SGE(fp->rx_sge_prod);
 875                 end = RX_SGE(fp->last_max_sge);
 876                 for (j = start; j != end; j = RX_SGE(j + 1)) {
 877                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
 878                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
 879
 880                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
 881                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
 882                 }
 883
 884                 start = RCQ_BD(fp->rx_comp_cons - 10);
 885                 end = RCQ_BD(fp->rx_comp_cons + 503);
 886                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
 887                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
 888
 889                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
 890                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
 891                 }
 892         }
 893
 894         /* Tx */
 895         for_each_valid_tx_queue(bp, i) {
 896                 struct bnx2x_fastpath *fp = &bp->fp[i];
 897                 for_each_cos_in_tx_queue(fp, cos) {
 898                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
 899
 900                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
 901                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
 902                         for (j = start; j != end; j = TX_BD(j + 1)) {
 903                                 struct sw_tx_bd *sw_bd =
 904                                         &txdata->tx_buf_ring[j];
 905
 906                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
 907                                           i, cos, j, sw_bd->skb,
 908                                           sw_bd->first_bd);
 909                         }
 910
 911                         start = TX_BD(txdata->tx_bd_cons - 10);
 912                         end = TX_BD(txdata->tx_bd_cons + 254);
 913                         for (j = start; j != end; j = TX_BD(j + 1)) {
 914                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
 915
 916                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
 917                                           i, cos, j, tx_bd[0], tx_bd[1],
 918                                           tx_bd[2], tx_bd[3]);
 919                         }
 920                 }
 921         }
 922 #endif
 923         bnx2x_fw_dump(bp);
 924         bnx2x_mc_assert(bp);
 925         BNX2X_ERR("end crash dump -----------------\n");
 926 }
 927
 928 /*
 929  * FLR Support for E2
 930  *
 931  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
 932  * initialization.
 933  */
 934 #define FLR_WAIT_USEC           10000   /* 10 miliseconds */
 935 #define FLR_WAIT_INTERVAL       50      /* usec */
 936 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
 937
 938 struct pbf_pN_buf_regs {
 939         int pN;
 940         u32 init_crd;
 941         u32 crd;
 942         u32 crd_freed;
 943 };
 944
 945 struct pbf_pN_cmd_regs {
 946         int pN;
 947         u32 lines_occup;
 948         u32 lines_freed;
 949 };
 950
 951 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
 952                                      struct pbf_pN_buf_regs *regs,
 953                                      u32 poll_count)
 954 {
 955         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
 956         u32 cur_cnt = poll_count;
 957
 958         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
 959         crd = crd_start = REG_RD(bp, regs->crd);
 960         init_crd = REG_RD(bp, regs->init_crd);
 961
 962         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
 963         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
 964         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
 965
 966         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
 967                (init_crd - crd_start))) {
 968                 if (cur_cnt--) {
 969                         udelay(FLR_WAIT_INTERVAL);
 970                         crd = REG_RD(bp, regs->crd);
 971                         crd_freed = REG_RD(bp, regs->crd_freed);
 972                 } else {
 973                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
 974                            regs->pN);
 975                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
 976                            regs->pN, crd);
 977                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
 978                            regs->pN, crd_freed);
 979                         break;
 980                 }
 981         }
 982         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
 983            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
 984 }
 985
 986 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
 987                                      struct pbf_pN_cmd_regs *regs,
 988                                      u32 poll_count)
 989 {
 990         u32 occup, to_free, freed, freed_start;
 991         u32 cur_cnt = poll_count;
 992
 993         occup = to_free = REG_RD(bp, regs->lines_occup);
 994         freed = freed_start = REG_RD(bp, regs->lines_freed);
 995
 996         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
 997         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
 998
 999         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1000                 if (cur_cnt--) {
1001                         udelay(FLR_WAIT_INTERVAL);
1002                         occup = REG_RD(bp, regs->lines_occup);
1003                         freed = REG_RD(bp, regs->lines_freed);
1004                 } else {
1005                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1006                            regs->pN);
1007                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1008                            regs->pN, occup);
1009                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1010                            regs->pN, freed);
1011                         break;
1012                 }
1013         }
1014         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1015            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1016 }
1017
1018 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1019                                     u32 expected, u32 poll_count)
1020 {
1021         u32 cur_cnt = poll_count;
1022         u32 val;
1023
1024         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1025                 udelay(FLR_WAIT_INTERVAL);
1026
1027         return val;
1028 }
1029
1030 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1031                                            char *msg, u32 poll_cnt)
1032 {
1033         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1034         if (val != 0) {
1035                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1036                 return 1;
1037         }
1038         return 0;
1039 }
1040
1041 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1042 {
1043         /* adjust polling timeout */
1044         if (CHIP_REV_IS_EMUL(bp))
1045                 return FLR_POLL_CNT * 2000;
1046
1047         if (CHIP_REV_IS_FPGA(bp))
1048                 return FLR_POLL_CNT * 120;
1049
1050         return FLR_POLL_CNT;
1051 }
1052
1053 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1054 {
1055         struct pbf_pN_cmd_regs cmd_regs[] = {
1056                 {0, (CHIP_IS_E3B0(bp)) ?
1057                         PBF_REG_TQ_OCCUPANCY_Q0 :
1058                         PBF_REG_P0_TQ_OCCUPANCY,
1059                     (CHIP_IS_E3B0(bp)) ?
1060                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1061                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1062                 {1, (CHIP_IS_E3B0(bp)) ?
1063                         PBF_REG_TQ_OCCUPANCY_Q1 :
1064                         PBF_REG_P1_TQ_OCCUPANCY,
1065                     (CHIP_IS_E3B0(bp)) ?
1066                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1067                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1068                 {4, (CHIP_IS_E3B0(bp)) ?
1069                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1070                         PBF_REG_P4_TQ_OCCUPANCY,
1071                     (CHIP_IS_E3B0(bp)) ?
1072                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1073                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1074         };
1075
1076         struct pbf_pN_buf_regs buf_regs[] = {
1077                 {0, (CHIP_IS_E3B0(bp)) ?
1078                         PBF_REG_INIT_CRD_Q0 :
1079                         PBF_REG_P0_INIT_CRD ,
1080                     (CHIP_IS_E3B0(bp)) ?
1081                         PBF_REG_CREDIT_Q0 :
1082                         PBF_REG_P0_CREDIT,
1083                     (CHIP_IS_E3B0(bp)) ?
1084                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1085                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1086                 {1, (CHIP_IS_E3B0(bp)) ?
1087                         PBF_REG_INIT_CRD_Q1 :
1088                         PBF_REG_P1_INIT_CRD,
1089                     (CHIP_IS_E3B0(bp)) ?
1090                         PBF_REG_CREDIT_Q1 :
1091                         PBF_REG_P1_CREDIT,
1092                     (CHIP_IS_E3B0(bp)) ?
1093                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1094                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1095                 {4, (CHIP_IS_E3B0(bp)) ?
1096                         PBF_REG_INIT_CRD_LB_Q :
1097                         PBF_REG_P4_INIT_CRD,
1098                     (CHIP_IS_E3B0(bp)) ?
1099                         PBF_REG_CREDIT_LB_Q :
1100                         PBF_REG_P4_CREDIT,
1101                     (CHIP_IS_E3B0(bp)) ?
1102                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1103                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1104         };
1105
1106         int i;
1107
1108         /* Verify the command queues are flushed P0, P1, P4 */
1109         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1110                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1111
1112
1113         /* Verify the transmission buffers are flushed P0, P1, P4 */
1114         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1115                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1116 }
1117
1118 #define OP_GEN_PARAM(param) \
1119         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1120
1121 #define OP_GEN_TYPE(type) \
1122         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1123
1124 #define OP_GEN_AGG_VECT(index) \
1125         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1126
1127
1128 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1129                                          u32 poll_cnt)
1130 {
1131         struct sdm_op_gen op_gen = {0};
1132
1133         u32 comp_addr = BAR_CSTRORM_INTMEM +
1134                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1135         int ret = 0;
1136
1137         if (REG_RD(bp, comp_addr)) {
1138                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1139                 return 1;
1140         }
1141
1142         op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1143         op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1144         op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1145         op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1146
1147         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1148         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1149
1150         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1151                 BNX2X_ERR("FW final cleanup did not succeed\n");
1152                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1153                    (REG_RD(bp, comp_addr)));
1154                 ret = 1;
1155         }
1156         /* Zero completion for nxt FLR */
1157         REG_WR(bp, comp_addr, 0);
1158
1159         return ret;
1160 }
1161
1162 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1163 {
1164         u16 status;
1165
1166         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1167         return status & PCI_EXP_DEVSTA_TRPND;
1168 }
1169
1170 /* PF FLR specific routines
1171 */
1172 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1173 {
1174
1175         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1176         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1177                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1178                         "CFC PF usage counter timed out",
1179                         poll_cnt))
1180                 return 1;
1181
1182
1183         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1184         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1185                         DORQ_REG_PF_USAGE_CNT,
1186                         "DQ PF usage counter timed out",
1187                         poll_cnt))
1188                 return 1;
1189
1190         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1191         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1192                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1193                         "QM PF usage counter timed out",
1194                         poll_cnt))
1195                 return 1;
1196
1197         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1198         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1199                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1200                         "Timers VNIC usage counter timed out",
1201                         poll_cnt))
1202                 return 1;
1203         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1204                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1205                         "Timers NUM_SCANS usage counter timed out",
1206                         poll_cnt))
1207                 return 1;
1208
1209         /* Wait DMAE PF usage counter to zero */
1210         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1211                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1212                         "DMAE dommand register timed out",
1213                         poll_cnt))
1214                 return 1;
1215
1216         return 0;
1217 }
1218
1219 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1220 {
1221         u32 val;
1222
1223         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1224         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1225
1226         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1227         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1228
1229         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1230         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1231
1232         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1233         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1234
1235         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1236         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1237
1238         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1239         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1240
1241         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1242         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1243
1244         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1245         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1246            val);
1247 }
1248
1249 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1250 {
1251         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1252
1253         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1254
1255         /* Re-enable PF target read access */
1256         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1257
1258         /* Poll HW usage counters */
1259         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1260         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1261                 return -EBUSY;
1262
1263         /* Zero the igu 'trailing edge' and 'leading edge' */
1264
1265         /* Send the FW cleanup command */
1266         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1267                 return -EBUSY;
1268
1269         /* ATC cleanup */
1270
1271         /* Verify TX hw is flushed */
1272         bnx2x_tx_hw_flushed(bp, poll_cnt);
1273
1274         /* Wait 100ms (not adjusted according to platform) */
1275         msleep(100);
1276
1277         /* Verify no pending pci transactions */
1278         if (bnx2x_is_pcie_pending(bp->pdev))
1279                 BNX2X_ERR("PCIE Transactions still pending\n");
1280
1281         /* Debug */
1282         bnx2x_hw_enable_status(bp);
1283
1284         /*
1285          * Master enable - Due to WB DMAE writes performed before this
1286          * register is re-initialized as part of the regular function init
1287          */
1288         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1289
1290         return 0;
1291 }
1292
1293 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1294 {
1295         int port = BP_PORT(bp);
1296         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1297         u32 val = REG_RD(bp, addr);
1298         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1299         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1300         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1301
1302         if (msix) {
1303                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1304                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1305                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1306                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1307                 if (single_msix)
1308                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1309         } else if (msi) {
1310                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1311                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1312                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1313                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1314         } else {
1315                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1316                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1317                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1318                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1319
1320                 if (!CHIP_IS_E1(bp)) {
1321                         DP(NETIF_MSG_IFUP,
1322                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1323
1324                         REG_WR(bp, addr, val);
1325
1326                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1327                 }
1328         }
1329
1330         if (CHIP_IS_E1(bp))
1331                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1332
1333         DP(NETIF_MSG_IFUP,
1334            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1335            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1336
1337         REG_WR(bp, addr, val);
1338         /*
1339          * Ensure that HC_CONFIG is written before leading/trailing edge config
1340          */
1341         mmiowb();
1342         barrier();
1343
1344         if (!CHIP_IS_E1(bp)) {
1345                 /* init leading/trailing edge */
1346                 if (IS_MF(bp)) {
1347                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1348                         if (bp->port.pmf)
1349                                 /* enable nig and gpio3 attention */
1350                                 val |= 0x1100;
1351                 } else
1352                         val = 0xffff;
1353
1354                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1355                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1356         }
1357
1358         /* Make sure that interrupts are indeed enabled from here on */
1359         mmiowb();
1360 }
1361
1362 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1363 {
1364         u32 val;
1365         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1366         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1367         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1368
1369         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1370
1371         if (msix) {
1372                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1373                          IGU_PF_CONF_SINGLE_ISR_EN);
1374                 val |= (IGU_PF_CONF_FUNC_EN |
1375                         IGU_PF_CONF_MSI_MSIX_EN |
1376                         IGU_PF_CONF_ATTN_BIT_EN);
1377
1378                 if (single_msix)
1379                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1380         } else if (msi) {
1381                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1382                 val |= (IGU_PF_CONF_FUNC_EN |
1383                         IGU_PF_CONF_MSI_MSIX_EN |
1384                         IGU_PF_CONF_ATTN_BIT_EN |
1385                         IGU_PF_CONF_SINGLE_ISR_EN);
1386         } else {
1387                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1388                 val |= (IGU_PF_CONF_FUNC_EN |
1389                         IGU_PF_CONF_INT_LINE_EN |
1390                         IGU_PF_CONF_ATTN_BIT_EN |
1391                         IGU_PF_CONF_SINGLE_ISR_EN);
1392         }
1393
1394         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1395            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1396
1397         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1398
1399         if (val & IGU_PF_CONF_INT_LINE_EN)
1400                 pci_intx(bp->pdev, true);
1401
1402         barrier();
1403
1404         /* init leading/trailing edge */
1405         if (IS_MF(bp)) {
1406                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1407                 if (bp->port.pmf)
1408                         /* enable nig and gpio3 attention */
1409                         val |= 0x1100;
1410         } else
1411                 val = 0xffff;
1412
1413         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1414         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1415
1416         /* Make sure that interrupts are indeed enabled from here on */
1417         mmiowb();
1418 }
1419
1420 void bnx2x_int_enable(struct bnx2x *bp)
1421 {
1422         if (bp->common.int_block == INT_BLOCK_HC)
1423                 bnx2x_hc_int_enable(bp);
1424         else
1425                 bnx2x_igu_int_enable(bp);
1426 }
1427
1428 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1429 {
1430         int port = BP_PORT(bp);
1431         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1432         u32 val = REG_RD(bp, addr);
1433
1434         /*
1435          * in E1 we must use only PCI configuration space to disable
1436          * MSI/MSIX capablility
1437          * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1438          */
1439         if (CHIP_IS_E1(bp)) {
1440                 /*  Since IGU_PF_CONF_MSI_MSIX_EN still always on
1441                  *  Use mask register to prevent from HC sending interrupts
1442                  *  after we exit the function
1443                  */
1444                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1445
1446                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1447                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
1448                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1449         } else
1450                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1451                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1452                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
1453                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1454
1455         DP(NETIF_MSG_IFDOWN,
1456            "write %x to HC %d (addr 0x%x)\n",
1457            val, port, addr);
1458
1459         /* flush all outstanding writes */
1460         mmiowb();
1461
1462         REG_WR(bp, addr, val);
1463         if (REG_RD(bp, addr) != val)
1464                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1465 }
1466
1467 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1468 {
1469         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1470
1471         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1472                  IGU_PF_CONF_INT_LINE_EN |
1473                  IGU_PF_CONF_ATTN_BIT_EN);
1474
1475         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1476
1477         /* flush all outstanding writes */
1478         mmiowb();
1479
1480         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1481         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1482                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1483 }
1484
1485 static void bnx2x_int_disable(struct bnx2x *bp)
1486 {
1487         if (bp->common.int_block == INT_BLOCK_HC)
1488                 bnx2x_hc_int_disable(bp);
1489         else
1490                 bnx2x_igu_int_disable(bp);
1491 }
1492
1493 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1494 {
1495         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1496         int i, offset;
1497
1498         if (disable_hw)
1499                 /* prevent the HW from sending interrupts */
1500                 bnx2x_int_disable(bp);
1501
1502         /* make sure all ISRs are done */
1503         if (msix) {
1504                 synchronize_irq(bp->msix_table[0].vector);
1505                 offset = 1;
1506                 if (CNIC_SUPPORT(bp))
1507                         offset++;
1508                 for_each_eth_queue(bp, i)
1509                         synchronize_irq(bp->msix_table[offset++].vector);
1510         } else
1511                 synchronize_irq(bp->pdev->irq);
1512
1513         /* make sure sp_task is not running */
1514         cancel_delayed_work(&bp->sp_task);
1515         cancel_delayed_work(&bp->period_task);
1516         flush_workqueue(bnx2x_wq);
1517 }
1518
1519 /* fast path */
1520
1521 /*
1522  * General service functions
1523  */
1524
1525 /* Return true if succeeded to acquire the lock */
1526 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1527 {
1528         u32 lock_status;
1529         u32 resource_bit = (1 << resource);
1530         int func = BP_FUNC(bp);
1531         u32 hw_lock_control_reg;
1532
1533         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1534            "Trying to take a lock on resource %d\n", resource);
1535
1536         /* Validating that the resource is within range */
1537         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1538                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1539                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1540                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1541                 return false;
1542         }
1543
1544         if (func <= 5)
1545                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1546         else
1547                 hw_lock_control_reg =
1548                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1549
1550         /* Try to acquire the lock */
1551         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1552         lock_status = REG_RD(bp, hw_lock_control_reg);
1553         if (lock_status & resource_bit)
1554                 return true;
1555
1556         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1557            "Failed to get a lock on resource %d\n", resource);
1558         return false;
1559 }
1560
1561 /**
1562  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1563  *
1564  * @bp: driver handle
1565  *
1566  * Returns the recovery leader resource id according to the engine this function
1567  * belongs to. Currently only only 2 engines is supported.
1568  */
1569 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1570 {
1571         if (BP_PATH(bp))
1572                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1573         else
1574                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1575 }
1576
1577 /**
1578  * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1579  *
1580  * @bp: driver handle
1581  *
1582  * Tries to aquire a leader lock for current engine.
1583  */
1584 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1585 {
1586         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1587 }
1588
1589 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1590
1591
1592 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1593 {
1594         struct bnx2x *bp = fp->bp;
1595         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1596         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1597         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1598         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1599
1600         DP(BNX2X_MSG_SP,
1601            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1602            fp->index, cid, command, bp->state,
1603            rr_cqe->ramrod_cqe.ramrod_type);
1604
1605         switch (command) {
1606         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1607                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1608                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1609                 break;
1610
1611         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1612                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1613                 drv_cmd = BNX2X_Q_CMD_SETUP;
1614                 break;
1615
1616         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1617                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1618                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1619                 break;
1620
1621         case (RAMROD_CMD_ID_ETH_HALT):
1622                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1623                 drv_cmd = BNX2X_Q_CMD_HALT;
1624                 break;
1625
1626         case (RAMROD_CMD_ID_ETH_TERMINATE):
1627                 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1628                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1629                 break;
1630
1631         case (RAMROD_CMD_ID_ETH_EMPTY):
1632                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1633                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1634                 break;
1635
1636         default:
1637                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1638                           command, fp->index);
1639                 return;
1640         }
1641
1642         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1643             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1644                 /* q_obj->complete_cmd() failure means that this was
1645                  * an unexpected completion.
1646                  *
1647                  * In this case we don't want to increase the bp->spq_left
1648                  * because apparently we haven't sent this command the first
1649                  * place.
1650                  */
1651 #ifdef BNX2X_STOP_ON_ERROR
1652                 bnx2x_panic();
1653 #else
1654                 return;
1655 #endif
1656
1657         smp_mb__before_atomic_inc();
1658         atomic_inc(&bp->cq_spq_left);
1659         /* push the change in bp->spq_left and towards the memory */
1660         smp_mb__after_atomic_inc();
1661
1662         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1663
1664         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1665             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1666                 /* if Q update ramrod is completed for last Q in AFEX vif set
1667                  * flow, then ACK MCP at the end
1668                  *
1669                  * mark pending ACK to MCP bit.
1670                  * prevent case that both bits are cleared.
1671                  * At the end of load/unload driver checks that
1672                  * sp_state is cleaerd, and this order prevents
1673                  * races
1674                  */
1675                 smp_mb__before_clear_bit();
1676                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1677                 wmb();
1678                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1679                 smp_mb__after_clear_bit();
1680
1681                 /* schedule workqueue to send ack to MCP */
1682                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1683         }
1684
1685         return;
1686 }
1687
1688 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1689                         u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1690 {
1691         u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1692
1693         bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1694                                  start);
1695 }
1696
1697 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1698 {
1699         struct bnx2x *bp = netdev_priv(dev_instance);
1700         u16 status = bnx2x_ack_int(bp);
1701         u16 mask;
1702         int i;
1703         u8 cos;
1704
1705         /* Return here if interrupt is shared and it's not for us */
1706         if (unlikely(status == 0)) {
1707                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1708                 return IRQ_NONE;
1709         }
1710         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1711
1712 #ifdef BNX2X_STOP_ON_ERROR
1713         if (unlikely(bp->panic))
1714                 return IRQ_HANDLED;
1715 #endif
1716
1717         for_each_eth_queue(bp, i) {
1718                 struct bnx2x_fastpath *fp = &bp->fp[i];
1719
1720                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1721                 if (status & mask) {
1722                         /* Handle Rx or Tx according to SB id */
1723                         prefetch(fp->rx_cons_sb);
1724                         for_each_cos_in_tx_queue(fp, cos)
1725                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1726                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1727                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1728                         status &= ~mask;
1729                 }
1730         }
1731
1732         if (CNIC_SUPPORT(bp)) {
1733                 mask = 0x2;
1734                 if (status & (mask | 0x1)) {
1735                         struct cnic_ops *c_ops = NULL;
1736
1737                         if (likely(bp->state == BNX2X_STATE_OPEN)) {
1738                                 rcu_read_lock();
1739                                 c_ops = rcu_dereference(bp->cnic_ops);
1740                                 if (c_ops)
1741                                         c_ops->cnic_handler(bp->cnic_data,
1742                                                             NULL);
1743                                 rcu_read_unlock();
1744                         }
1745
1746                         status &= ~mask;
1747                 }
1748         }
1749
1750         if (unlikely(status & 0x1)) {
1751                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1752
1753                 status &= ~0x1;
1754                 if (!status)
1755                         return IRQ_HANDLED;
1756         }
1757
1758         if (unlikely(status))
1759                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1760                    status);
1761
1762         return IRQ_HANDLED;
1763 }
1764
1765 /* Link */
1766
1767 /*
1768  * General service functions
1769  */
1770
1771 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1772 {
1773         u32 lock_status;
1774         u32 resource_bit = (1 << resource);
1775         int func = BP_FUNC(bp);
1776         u32 hw_lock_control_reg;
1777         int cnt;
1778
1779         /* Validating that the resource is within range */
1780         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1781                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1782                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1783                 return -EINVAL;
1784         }
1785
1786         if (func <= 5) {
1787                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1788         } else {
1789                 hw_lock_control_reg =
1790                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1791         }
1792
1793         /* Validating that the resource is not already taken */
1794         lock_status = REG_RD(bp, hw_lock_control_reg);
1795         if (lock_status & resource_bit) {
1796                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1797                    lock_status, resource_bit);
1798                 return -EEXIST;
1799         }
1800
1801         /* Try for 5 second every 5ms */
1802         for (cnt = 0; cnt < 1000; cnt++) {
1803                 /* Try to acquire the lock */
1804                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1805                 lock_status = REG_RD(bp, hw_lock_control_reg);
1806                 if (lock_status & resource_bit)
1807                         return 0;
1808
1809                 msleep(5);
1810         }
1811         BNX2X_ERR("Timeout\n");
1812         return -EAGAIN;
1813 }
1814
1815 int bnx2x_release_leader_lock(struct bnx2x *bp)
1816 {
1817         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1818 }
1819
1820 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1821 {
1822         u32 lock_status;
1823         u32 resource_bit = (1 << resource);
1824         int func = BP_FUNC(bp);
1825         u32 hw_lock_control_reg;
1826
1827         /* Validating that the resource is within range */
1828         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1829                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1830                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1831                 return -EINVAL;
1832         }
1833
1834         if (func <= 5) {
1835                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1836         } else {
1837                 hw_lock_control_reg =
1838                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1839         }
1840
1841         /* Validating that the resource is currently taken */
1842         lock_status = REG_RD(bp, hw_lock_control_reg);
1843         if (!(lock_status & resource_bit)) {
1844                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1845                    lock_status, resource_bit);
1846                 return -EFAULT;
1847         }
1848
1849         REG_WR(bp, hw_lock_control_reg, resource_bit);
1850         return 0;
1851 }
1852
1853
1854 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1855 {
1856         /* The GPIO should be swapped if swap register is set and active */
1857         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1858                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1859         int gpio_shift = gpio_num +
1860                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1861         u32 gpio_mask = (1 << gpio_shift);
1862         u32 gpio_reg;
1863         int value;
1864
1865         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1866                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1867                 return -EINVAL;
1868         }
1869
1870         /* read GPIO value */
1871         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1872
1873         /* get the requested pin value */
1874         if ((gpio_reg & gpio_mask) == gpio_mask)
1875                 value = 1;
1876         else
1877                 value = 0;
1878
1879         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
1880
1881         return value;
1882 }
1883
1884 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1885 {
1886         /* The GPIO should be swapped if swap register is set and active */
1887         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1888                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1889         int gpio_shift = gpio_num +
1890                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1891         u32 gpio_mask = (1 << gpio_shift);
1892         u32 gpio_reg;
1893
1894         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1895                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1896                 return -EINVAL;
1897         }
1898
1899         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1900         /* read GPIO and mask except the float bits */
1901         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1902
1903         switch (mode) {
1904         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1905                 DP(NETIF_MSG_LINK,
1906                    "Set GPIO %d (shift %d) -> output low\n",
1907                    gpio_num, gpio_shift);
1908                 /* clear FLOAT and set CLR */
1909                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1910                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1911                 break;
1912
1913         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1914                 DP(NETIF_MSG_LINK,
1915                    "Set GPIO %d (shift %d) -> output high\n",
1916                    gpio_num, gpio_shift);
1917                 /* clear FLOAT and set SET */
1918                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1919                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1920                 break;
1921
1922         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1923                 DP(NETIF_MSG_LINK,
1924                    "Set GPIO %d (shift %d) -> input\n",
1925                    gpio_num, gpio_shift);
1926                 /* set FLOAT */
1927                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1928                 break;
1929
1930         default:
1931                 break;
1932         }
1933
1934         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1935         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1936
1937         return 0;
1938 }
1939
1940 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1941 {
1942         u32 gpio_reg = 0;
1943         int rc = 0;
1944
1945         /* Any port swapping should be handled by caller. */
1946
1947         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1948         /* read GPIO and mask except the float bits */
1949         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1950         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1951         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1952         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1953
1954         switch (mode) {
1955         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1956                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1957                 /* set CLR */
1958                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1959                 break;
1960
1961         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1962                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1963                 /* set SET */
1964                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1965                 break;
1966
1967         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1968                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1969                 /* set FLOAT */
1970                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1971                 break;
1972
1973         default:
1974                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1975                 rc = -EINVAL;
1976                 break;
1977         }
1978
1979         if (rc == 0)
1980                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1981
1982         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1983
1984         return rc;
1985 }
1986
1987 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1988 {
1989         /* The GPIO should be swapped if swap register is set and active */
1990         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1991                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1992         int gpio_shift = gpio_num +
1993                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1994         u32 gpio_mask = (1 << gpio_shift);
1995         u32 gpio_reg;
1996
1997         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1998                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1999                 return -EINVAL;
2000         }
2001
2002         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2003         /* read GPIO int */
2004         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2005
2006         switch (mode) {
2007         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2008                 DP(NETIF_MSG_LINK,
2009                    "Clear GPIO INT %d (shift %d) -> output low\n",
2010                    gpio_num, gpio_shift);
2011                 /* clear SET and set CLR */
2012                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2013                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2014                 break;
2015
2016         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2017                 DP(NETIF_MSG_LINK,
2018                    "Set GPIO INT %d (shift %d) -> output high\n",
2019                    gpio_num, gpio_shift);
2020                 /* clear CLR and set SET */
2021                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2022                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2023                 break;
2024
2025         default:
2026                 break;
2027         }
2028
2029         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2030         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2031
2032         return 0;
2033 }
2034
2035 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2036 {
2037         u32 spio_reg;
2038
2039         /* Only 2 SPIOs are configurable */
2040         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2041                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2042                 return -EINVAL;
2043         }
2044
2045         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2046         /* read SPIO and mask except the float bits */
2047         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2048
2049         switch (mode) {
2050         case MISC_SPIO_OUTPUT_LOW:
2051                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2052                 /* clear FLOAT and set CLR */
2053                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2054                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2055                 break;
2056
2057         case MISC_SPIO_OUTPUT_HIGH:
2058                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2059                 /* clear FLOAT and set SET */
2060                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2061                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2062                 break;
2063
2064         case MISC_SPIO_INPUT_HI_Z:
2065                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2066                 /* set FLOAT */
2067                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2068                 break;
2069
2070         default:
2071                 break;
2072         }
2073
2074         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2075         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2076
2077         return 0;
2078 }
2079
2080 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2081 {
2082         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2083         switch (bp->link_vars.ieee_fc &
2084                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2085         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2086                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2087                                                    ADVERTISED_Pause);
2088                 break;
2089
2090         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2091                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2092                                                   ADVERTISED_Pause);
2093                 break;
2094
2095         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2096                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2097                 break;
2098
2099         default:
2100                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2101                                                    ADVERTISED_Pause);
2102                 break;
2103         }
2104 }
2105
2106 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2107 {
2108         /* Initialize link parameters structure variables
2109          * It is recommended to turn off RX FC for jumbo frames
2110          *  for better performance
2111          */
2112         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2113                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2114         else
2115                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2116 }
2117
2118 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2119 {
2120         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2121         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2122
2123         if (!BP_NOMCP(bp)) {
2124                 bnx2x_set_requested_fc(bp);
2125                 bnx2x_acquire_phy_lock(bp);
2126
2127                 if (load_mode == LOAD_DIAG) {
2128                         struct link_params *lp = &bp->link_params;
2129                         lp->loopback_mode = LOOPBACK_XGXS;
2130                         /* do PHY loopback at 10G speed, if possible */
2131                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2132                                 if (lp->speed_cap_mask[cfx_idx] &
2133                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2134                                         lp->req_line_speed[cfx_idx] =
2135                                         SPEED_10000;
2136                                 else
2137                                         lp->req_line_speed[cfx_idx] =
2138                                         SPEED_1000;
2139                         }
2140                 }
2141
2142                 if (load_mode == LOAD_LOOPBACK_EXT) {
2143                         struct link_params *lp = &bp->link_params;
2144                         lp->loopback_mode = LOOPBACK_EXT;
2145                 }
2146
2147                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2148
2149                 bnx2x_release_phy_lock(bp);
2150
2151                 bnx2x_calc_fc_adv(bp);
2152
2153                 if (bp->link_vars.link_up) {
2154                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2155                         bnx2x_link_report(bp);
2156                 }
2157                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2158                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2159                 return rc;
2160         }
2161         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2162         return -EINVAL;
2163 }
2164
2165 void bnx2x_link_set(struct bnx2x *bp)
2166 {
2167         if (!BP_NOMCP(bp)) {
2168                 bnx2x_acquire_phy_lock(bp);
2169                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2170                 bnx2x_release_phy_lock(bp);
2171
2172                 bnx2x_calc_fc_adv(bp);
2173         } else
2174                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2175 }
2176
2177 static void bnx2x__link_reset(struct bnx2x *bp)
2178 {
2179         if (!BP_NOMCP(bp)) {
2180                 bnx2x_acquire_phy_lock(bp);
2181                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2182                 bnx2x_release_phy_lock(bp);
2183         } else
2184                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2185 }
2186
2187 void bnx2x_force_link_reset(struct bnx2x *bp)
2188 {
2189         bnx2x_acquire_phy_lock(bp);
2190         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2191         bnx2x_release_phy_lock(bp);
2192 }
2193
2194 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2195 {
2196         u8 rc = 0;
2197
2198         if (!BP_NOMCP(bp)) {
2199                 bnx2x_acquire_phy_lock(bp);
2200                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2201                                      is_serdes);
2202                 bnx2x_release_phy_lock(bp);
2203         } else
2204                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2205
2206         return rc;
2207 }
2208
2209
2210 /* Calculates the sum of vn_min_rates.
2211    It's needed for further normalizing of the min_rates.
2212    Returns:
2213      sum of vn_min_rates.
2214        or
2215      0 - if all the min_rates are 0.
2216      In the later case fainess algorithm should be deactivated.
2217      If not all min_rates are zero then those that are zeroes will be set to 1.
2218  */
2219 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2220                                       struct cmng_init_input *input)
2221 {
2222         int all_zero = 1;
2223         int vn;
2224
2225         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2226                 u32 vn_cfg = bp->mf_config[vn];
2227                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2228                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2229
2230                 /* Skip hidden vns */
2231                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2232                         vn_min_rate = 0;
2233                 /* If min rate is zero - set it to 1 */
2234                 else if (!vn_min_rate)
2235                         vn_min_rate = DEF_MIN_RATE;
2236                 else
2237                         all_zero = 0;
2238
2239                 input->vnic_min_rate[vn] = vn_min_rate;
2240         }
2241
2242         /* if ETS or all min rates are zeros - disable fairness */
2243         if (BNX2X_IS_ETS_ENABLED(bp)) {
2244                 input->flags.cmng_enables &=
2245                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2246                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2247         } else if (all_zero) {
2248                 input->flags.cmng_enables &=
2249                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2250                 DP(NETIF_MSG_IFUP,
2251                    "All MIN values are zeroes fairness will be disabled\n");
2252         } else
2253                 input->flags.cmng_enables |=
2254                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2255 }
2256
2257 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2258                                     struct cmng_init_input *input)
2259 {
2260         u16 vn_max_rate;
2261         u32 vn_cfg = bp->mf_config[vn];
2262
2263         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2264                 vn_max_rate = 0;
2265         else {
2266                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2267
2268                 if (IS_MF_SI(bp)) {
2269                         /* maxCfg in percents of linkspeed */
2270                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2271                 } else /* SD modes */
2272                         /* maxCfg is absolute in 100Mb units */
2273                         vn_max_rate = maxCfg * 100;
2274         }
2275
2276         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2277
2278         input->vnic_max_rate[vn] = vn_max_rate;
2279 }
2280
2281
2282 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2283 {
2284         if (CHIP_REV_IS_SLOW(bp))
2285                 return CMNG_FNS_NONE;
2286         if (IS_MF(bp))
2287                 return CMNG_FNS_MINMAX;
2288
2289         return CMNG_FNS_NONE;
2290 }
2291
2292 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2293 {
2294         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2295
2296         if (BP_NOMCP(bp))
2297                 return; /* what should be the default bvalue in this case */
2298
2299         /* For 2 port configuration the absolute function number formula
2300          * is:
2301          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2302          *
2303          *      and there are 4 functions per port
2304          *
2305          * For 4 port configuration it is
2306          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2307          *
2308          *      and there are 2 functions per port
2309          */
2310         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2311                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2312
2313                 if (func >= E1H_FUNC_MAX)
2314                         break;
2315
2316                 bp->mf_config[vn] =
2317                         MF_CFG_RD(bp, func_mf_config[func].config);
2318         }
2319         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2320                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2321                 bp->flags |= MF_FUNC_DIS;
2322         } else {
2323                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2324                 bp->flags &= ~MF_FUNC_DIS;
2325         }
2326 }
2327
2328 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2329 {
2330         struct cmng_init_input input;
2331         memset(&input, 0, sizeof(struct cmng_init_input));
2332
2333         input.port_rate = bp->link_vars.line_speed;
2334
2335         if (cmng_type == CMNG_FNS_MINMAX) {
2336                 int vn;
2337
2338                 /* read mf conf from shmem */
2339                 if (read_cfg)
2340                         bnx2x_read_mf_cfg(bp);
2341
2342                 /* vn_weight_sum and enable fairness if not 0 */
2343                 bnx2x_calc_vn_min(bp, &input);
2344
2345                 /* calculate and set min-max rate for each vn */
2346                 if (bp->port.pmf)
2347                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2348                                 bnx2x_calc_vn_max(bp, vn, &input);
2349
2350                 /* always enable rate shaping and fairness */
2351                 input.flags.cmng_enables |=
2352                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2353
2354                 bnx2x_init_cmng(&input, &bp->cmng);
2355                 return;
2356         }
2357
2358         /* rate shaping and fairness are disabled */
2359         DP(NETIF_MSG_IFUP,
2360            "rate shaping and fairness are disabled\n");
2361 }
2362
2363 static void storm_memset_cmng(struct bnx2x *bp,
2364                               struct cmng_init *cmng,
2365                               u8 port)
2366 {
2367         int vn;
2368         size_t size = sizeof(struct cmng_struct_per_port);
2369
2370         u32 addr = BAR_XSTRORM_INTMEM +
2371                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2372
2373         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2374
2375         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2376                 int func = func_by_vn(bp, vn);
2377
2378                 addr = BAR_XSTRORM_INTMEM +
2379                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2380                 size = sizeof(struct rate_shaping_vars_per_vn);
2381                 __storm_memset_struct(bp, addr, size,
2382                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2383
2384                 addr = BAR_XSTRORM_INTMEM +
2385                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2386                 size = sizeof(struct fairness_vars_per_vn);
2387                 __storm_memset_struct(bp, addr, size,
2388                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2389         }
2390 }
2391
2392 /* This function is called upon link interrupt */
2393 static void bnx2x_link_attn(struct bnx2x *bp)
2394 {
2395         /* Make sure that we are synced with the current statistics */
2396         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2397
2398         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2399
2400         if (bp->link_vars.link_up) {
2401
2402                 /* dropless flow control */
2403                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2404                         int port = BP_PORT(bp);
2405                         u32 pause_enabled = 0;
2406
2407                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2408                                 pause_enabled = 1;
2409
2410                         REG_WR(bp, BAR_USTRORM_INTMEM +
2411                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2412                                pause_enabled);
2413                 }
2414
2415                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2416                         struct host_port_stats *pstats;
2417
2418                         pstats = bnx2x_sp(bp, port_stats);
2419                         /* reset old mac stats */
2420                         memset(&(pstats->mac_stx[0]), 0,
2421                                sizeof(struct mac_stx));
2422                 }
2423                 if (bp->state == BNX2X_STATE_OPEN)
2424                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2425         }
2426
2427         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2428                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2429
2430                 if (cmng_fns != CMNG_FNS_NONE) {
2431                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2432                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2433                 } else
2434                         /* rate shaping and fairness are disabled */
2435                         DP(NETIF_MSG_IFUP,
2436                            "single function mode without fairness\n");
2437         }
2438
2439         __bnx2x_link_report(bp);
2440
2441         if (IS_MF(bp))
2442                 bnx2x_link_sync_notify(bp);
2443 }
2444
2445 void bnx2x__link_status_update(struct bnx2x *bp)
2446 {
2447         if (bp->state != BNX2X_STATE_OPEN)
2448                 return;
2449
2450         /* read updated dcb configuration */
2451         bnx2x_dcbx_pmf_update(bp);
2452
2453         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2454
2455         if (bp->link_vars.link_up)
2456                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2457         else
2458                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2459
2460         /* indicate link status */
2461         bnx2x_link_report(bp);
2462 }
2463
2464 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2465                                   u16 vlan_val, u8 allowed_prio)
2466 {
2467         struct bnx2x_func_state_params func_params = {0};
2468         struct bnx2x_func_afex_update_params *f_update_params =
2469                 &func_params.params.afex_update;
2470
2471         func_params.f_obj = &bp->func_obj;
2472         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2473
2474         /* no need to wait for RAMROD completion, so don't
2475          * set RAMROD_COMP_WAIT flag
2476          */
2477
2478         f_update_params->vif_id = vifid;
2479         f_update_params->afex_default_vlan = vlan_val;
2480         f_update_params->allowed_priorities = allowed_prio;
2481
2482         /* if ramrod can not be sent, response to MCP immediately */
2483         if (bnx2x_func_state_change(bp, &func_params) < 0)
2484                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2485
2486         return 0;
2487 }
2488
2489 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2490                                           u16 vif_index, u8 func_bit_map)
2491 {
2492         struct bnx2x_func_state_params func_params = {0};
2493         struct bnx2x_func_afex_viflists_params *update_params =
2494                 &func_params.params.afex_viflists;
2495         int rc;
2496         u32 drv_msg_code;
2497
2498         /* validate only LIST_SET and LIST_GET are received from switch */
2499         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2500                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2501                           cmd_type);
2502
2503         func_params.f_obj = &bp->func_obj;
2504         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2505
2506         /* set parameters according to cmd_type */
2507         update_params->afex_vif_list_command = cmd_type;
2508         update_params->vif_list_index = cpu_to_le16(vif_index);
2509         update_params->func_bit_map =
2510                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2511         update_params->func_to_clear = 0;
2512         drv_msg_code =
2513                 (cmd_type == VIF_LIST_RULE_GET) ?
2514                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2515                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2516
2517         /* if ramrod can not be sent, respond to MCP immediately for
2518          * SET and GET requests (other are not triggered from MCP)
2519          */
2520         rc = bnx2x_func_state_change(bp, &func_params);
2521         if (rc < 0)
2522                 bnx2x_fw_command(bp, drv_msg_code, 0);
2523
2524         return 0;
2525 }
2526
2527 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2528 {
2529         struct afex_stats afex_stats;
2530         u32 func = BP_ABS_FUNC(bp);
2531         u32 mf_config;
2532         u16 vlan_val;
2533         u32 vlan_prio;
2534         u16 vif_id;
2535         u8 allowed_prio;
2536         u8 vlan_mode;
2537         u32 addr_to_write, vifid, addrs, stats_type, i;
2538
2539         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2540                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2541                 DP(BNX2X_MSG_MCP,
2542                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2543                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2544         }
2545
2546         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2547                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2548                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2549                 DP(BNX2X_MSG_MCP,
2550                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2551                    vifid, addrs);
2552                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2553                                                addrs);
2554         }
2555
2556         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2557                 addr_to_write = SHMEM2_RD(bp,
2558                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2559                 stats_type = SHMEM2_RD(bp,
2560                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2561
2562                 DP(BNX2X_MSG_MCP,
2563                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2564                    addr_to_write);
2565
2566                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2567
2568                 /* write response to scratchpad, for MCP */
2569                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2570                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2571                                *(((u32 *)(&afex_stats))+i));
2572
2573                 /* send ack message to MCP */
2574                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2575         }
2576
2577         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2578                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2579                 bp->mf_config[BP_VN(bp)] = mf_config;
2580                 DP(BNX2X_MSG_MCP,
2581                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2582                    mf_config);
2583
2584                 /* if VIF_SET is "enabled" */
2585                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2586                         /* set rate limit directly to internal RAM */
2587                         struct cmng_init_input cmng_input;
2588                         struct rate_shaping_vars_per_vn m_rs_vn;
2589                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2590                         u32 addr = BAR_XSTRORM_INTMEM +
2591                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2592
2593                         bp->mf_config[BP_VN(bp)] = mf_config;
2594
2595                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2596                         m_rs_vn.vn_counter.rate =
2597                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2598                         m_rs_vn.vn_counter.quota =
2599                                 (m_rs_vn.vn_counter.rate *
2600                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2601
2602                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2603
2604                         /* read relevant values from mf_cfg struct in shmem */
2605                         vif_id =
2606                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2607                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2608                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2609                         vlan_val =
2610                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2611                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2612                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2613                         vlan_prio = (mf_config &
2614                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2615                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2616                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2617                         vlan_mode =
2618                                 (MF_CFG_RD(bp,
2619                                            func_mf_config[func].afex_config) &
2620                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2621                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2622                         allowed_prio =
2623                                 (MF_CFG_RD(bp,
2624                                            func_mf_config[func].afex_config) &
2625                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2626                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2627
2628                         /* send ramrod to FW, return in case of failure */
2629                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2630                                                    allowed_prio))
2631                                 return;
2632
2633                         bp->afex_def_vlan_tag = vlan_val;
2634                         bp->afex_vlan_mode = vlan_mode;
2635                 } else {
2636                         /* notify link down because BP->flags is disabled */
2637                         bnx2x_link_report(bp);
2638
2639                         /* send INVALID VIF ramrod to FW */
2640                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2641
2642                         /* Reset the default afex VLAN */
2643                         bp->afex_def_vlan_tag = -1;
2644                 }
2645         }
2646 }
2647
2648 static void bnx2x_pmf_update(struct bnx2x *bp)
2649 {
2650         int port = BP_PORT(bp);
2651         u32 val;
2652
2653         bp->port.pmf = 1;
2654         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2655
2656         /*
2657          * We need the mb() to ensure the ordering between the writing to
2658          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2659          */
2660         smp_mb();
2661
2662         /* queue a periodic task */
2663         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2664
2665         bnx2x_dcbx_pmf_update(bp);
2666
2667         /* enable nig attention */
2668         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2669         if (bp->common.int_block == INT_BLOCK_HC) {
2670                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2671                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2672         } else if (!CHIP_IS_E1x(bp)) {
2673                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2674                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2675         }
2676
2677         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2678 }
2679
2680 /* end of Link */
2681
2682 /* slow path */
2683
2684 /*
2685  * General service functions
2686  */
2687
2688 /* send the MCP a request, block until there is a reply */
2689 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2690 {
2691         int mb_idx = BP_FW_MB_IDX(bp);
2692         u32 seq;
2693         u32 rc = 0;
2694         u32 cnt = 1;
2695         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2696
2697         mutex_lock(&bp->fw_mb_mutex);
2698         seq = ++bp->fw_seq;
2699         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2700         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2701
2702         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2703                         (command | seq), param);
2704
2705         do {
2706                 /* let the FW do it's magic ... */
2707                 msleep(delay);
2708
2709                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2710
2711                 /* Give the FW up to 5 second (500*10ms) */
2712         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2713
2714         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2715            cnt*delay, rc, seq);
2716
2717         /* is this a reply to our command? */
2718         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2719                 rc &= FW_MSG_CODE_MASK;
2720         else {
2721                 /* FW BUG! */
2722                 BNX2X_ERR("FW failed to respond!\n");
2723                 bnx2x_fw_dump(bp);
2724                 rc = 0;
2725         }
2726         mutex_unlock(&bp->fw_mb_mutex);
2727
2728         return rc;
2729 }
2730
2731
2732 static void storm_memset_func_cfg(struct bnx2x *bp,
2733                                  struct tstorm_eth_function_common_config *tcfg,
2734                                  u16 abs_fid)
2735 {
2736         size_t size = sizeof(struct tstorm_eth_function_common_config);
2737
2738         u32 addr = BAR_TSTRORM_INTMEM +
2739                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2740
2741         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2742 }
2743
2744 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2745 {
2746         if (CHIP_IS_E1x(bp)) {
2747                 struct tstorm_eth_function_common_config tcfg = {0};
2748
2749                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2750         }
2751
2752         /* Enable the function in the FW */
2753         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2754         storm_memset_func_en(bp, p->func_id, 1);
2755
2756         /* spq */
2757         if (p->func_flgs & FUNC_FLG_SPQ) {
2758                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2759                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2760                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2761         }
2762 }
2763
2764 /**
2765  * bnx2x_get_tx_only_flags - Return common flags
2766  *
2767  * @bp          device handle
2768  * @fp          queue handle
2769  * @zero_stats  TRUE if statistics zeroing is needed
2770  *
2771  * Return the flags that are common for the Tx-only and not normal connections.
2772  */
2773 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2774                                             struct bnx2x_fastpath *fp,
2775                                             bool zero_stats)
2776 {
2777         unsigned long flags = 0;
2778
2779         /* PF driver will always initialize the Queue to an ACTIVE state */
2780         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2781
2782         /* tx only connections collect statistics (on the same index as the
2783          *  parent connection). The statistics are zeroed when the parent
2784          *  connection is initialized.
2785          */
2786
2787         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2788         if (zero_stats)
2789                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2790
2791
2792         return flags;
2793 }
2794
2795 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2796                                        struct bnx2x_fastpath *fp,
2797                                        bool leading)
2798 {
2799         unsigned long flags = 0;
2800
2801         /* calculate other queue flags */
2802         if (IS_MF_SD(bp))
2803                 __set_bit(BNX2X_Q_FLG_OV, &flags);
2804
2805         if (IS_FCOE_FP(fp)) {
2806                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2807                 /* For FCoE - force usage of default priority (for afex) */
2808                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2809         }
2810
2811         if (!fp->disable_tpa) {
2812                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2813                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2814                 if (fp->mode == TPA_MODE_GRO)
2815                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2816         }
2817
2818         if (leading) {
2819                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2820                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2821         }
2822
2823         /* Always set HW VLAN stripping */
2824         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2825
2826         /* configure silent vlan removal */
2827         if (IS_MF_AFEX(bp))
2828                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2829
2830
2831         return flags | bnx2x_get_common_flags(bp, fp, true);
2832 }
2833
2834 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2835         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2836         u8 cos)
2837 {
2838         gen_init->stat_id = bnx2x_stats_id(fp);
2839         gen_init->spcl_id = fp->cl_id;
2840
2841         /* Always use mini-jumbo MTU for FCoE L2 ring */
2842         if (IS_FCOE_FP(fp))
2843                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2844         else
2845                 gen_init->mtu = bp->dev->mtu;
2846
2847         gen_init->cos = cos;
2848 }
2849
2850 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2851         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2852         struct bnx2x_rxq_setup_params *rxq_init)
2853 {
2854         u8 max_sge = 0;
2855         u16 sge_sz = 0;
2856         u16 tpa_agg_size = 0;
2857
2858         if (!fp->disable_tpa) {
2859                 pause->sge_th_lo = SGE_TH_LO(bp);
2860                 pause->sge_th_hi = SGE_TH_HI(bp);
2861
2862                 /* validate SGE ring has enough to cross high threshold */
2863                 WARN_ON(bp->dropless_fc &&
2864                                 pause->sge_th_hi + FW_PREFETCH_CNT >
2865                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2866
2867                 tpa_agg_size = min_t(u32,
2868                         (min_t(u32, 8, MAX_SKB_FRAGS) *
2869                         SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2870                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2871                         SGE_PAGE_SHIFT;
2872                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2873                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2874                 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2875                                     0xffff);
2876         }
2877
2878         /* pause - not for e1 */
2879         if (!CHIP_IS_E1(bp)) {
2880                 pause->bd_th_lo = BD_TH_LO(bp);
2881                 pause->bd_th_hi = BD_TH_HI(bp);
2882
2883                 pause->rcq_th_lo = RCQ_TH_LO(bp);
2884                 pause->rcq_th_hi = RCQ_TH_HI(bp);
2885                 /*
2886                  * validate that rings have enough entries to cross
2887                  * high thresholds
2888                  */
2889                 WARN_ON(bp->dropless_fc &&
2890                                 pause->bd_th_hi + FW_PREFETCH_CNT >
2891                                 bp->rx_ring_size);
2892                 WARN_ON(bp->dropless_fc &&
2893                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
2894                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2895
2896                 pause->pri_map = 1;
2897         }
2898
2899         /* rxq setup */
2900         rxq_init->dscr_map = fp->rx_desc_mapping;
2901         rxq_init->sge_map = fp->rx_sge_mapping;
2902         rxq_init->rcq_map = fp->rx_comp_mapping;
2903         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2904
2905         /* This should be a maximum number of data bytes that may be
2906          * placed on the BD (not including paddings).
2907          */
2908         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2909                 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2910
2911         rxq_init->cl_qzone_id = fp->cl_qzone_id;
2912         rxq_init->tpa_agg_sz = tpa_agg_size;
2913         rxq_init->sge_buf_sz = sge_sz;
2914         rxq_init->max_sges_pkt = max_sge;
2915         rxq_init->rss_engine_id = BP_FUNC(bp);
2916         rxq_init->mcast_engine_id = BP_FUNC(bp);
2917
2918         /* Maximum number or simultaneous TPA aggregation for this Queue.
2919          *
2920          * For PF Clients it should be the maximum avaliable number.
2921          * VF driver(s) may want to define it to a smaller value.
2922          */
2923         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2924
2925         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2926         rxq_init->fw_sb_id = fp->fw_sb_id;
2927
2928         if (IS_FCOE_FP(fp))
2929                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2930         else
2931                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2932         /* configure silent vlan removal
2933          * if multi function mode is afex, then mask default vlan
2934          */
2935         if (IS_MF_AFEX(bp)) {
2936                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2937                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2938         }
2939 }
2940
2941 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2942         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2943         u8 cos)
2944 {
2945         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2946         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2947         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2948         txq_init->fw_sb_id = fp->fw_sb_id;
2949
2950         /*
2951          * set the tss leading client id for TX classfication ==
2952          * leading RSS client id
2953          */
2954         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2955
2956         if (IS_FCOE_FP(fp)) {
2957                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2958                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2959         }
2960 }
2961
2962 static void bnx2x_pf_init(struct bnx2x *bp)
2963 {
2964         struct bnx2x_func_init_params func_init = {0};
2965         struct event_ring_data eq_data = { {0} };
2966         u16 flags;
2967
2968         if (!CHIP_IS_E1x(bp)) {
2969                 /* reset IGU PF statistics: MSIX + ATTN */
2970                 /* PF */
2971                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2972                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2973                            (CHIP_MODE_IS_4_PORT(bp) ?
2974                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2975                 /* ATTN */
2976                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2977                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2978                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2979                            (CHIP_MODE_IS_4_PORT(bp) ?
2980                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2981         }
2982
2983         /* function setup flags */
2984         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2985
2986         /* This flag is relevant for E1x only.
2987          * E2 doesn't have a TPA configuration in a function level.
2988          */
2989         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2990
2991         func_init.func_flgs = flags;
2992         func_init.pf_id = BP_FUNC(bp);
2993         func_init.func_id = BP_FUNC(bp);
2994         func_init.spq_map = bp->spq_mapping;
2995         func_init.spq_prod = bp->spq_prod_idx;
2996
2997         bnx2x_func_init(bp, &func_init);
2998
2999         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3000
3001         /*
3002          * Congestion management values depend on the link rate
3003          * There is no active link so initial link rate is set to 10 Gbps.
3004          * When the link comes up The congestion management values are
3005          * re-calculated according to the actual link rate.
3006          */
3007         bp->link_vars.line_speed = SPEED_10000;
3008         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3009
3010         /* Only the PMF sets the HW */
3011         if (bp->port.pmf)
3012                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3013
3014         /* init Event Queue */
3015         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3016         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3017         eq_data.producer = bp->eq_prod;
3018         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3019         eq_data.sb_id = DEF_SB_ID;
3020         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3021 }
3022
3023
3024 static void bnx2x_e1h_disable(struct bnx2x *bp)
3025 {
3026         int port = BP_PORT(bp);
3027
3028         bnx2x_tx_disable(bp);
3029
3030         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3031 }
3032
3033 static void bnx2x_e1h_enable(struct bnx2x *bp)
3034 {
3035         int port = BP_PORT(bp);
3036
3037         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3038
3039         /* Tx queue should be only reenabled */
3040         netif_tx_wake_all_queues(bp->dev);
3041
3042         /*
3043          * Should not call netif_carrier_on since it will be called if the link
3044          * is up when checking for link state
3045          */
3046 }
3047
3048 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3049
3050 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3051 {
3052         struct eth_stats_info *ether_stat =
3053                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3054
3055         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3056                 ETH_STAT_INFO_VERSION_LEN);
3057
3058         bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3059                                         DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3060                                         ether_stat->mac_local);
3061
3062         ether_stat->mtu_size = bp->dev->mtu;
3063
3064         if (bp->dev->features & NETIF_F_RXCSUM)
3065                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3066         if (bp->dev->features & NETIF_F_TSO)
3067                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3068         ether_stat->feature_flags |= bp->common.boot_mode;
3069
3070         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3071
3072         ether_stat->txq_size = bp->tx_ring_size;
3073         ether_stat->rxq_size = bp->rx_ring_size;
3074 }
3075
3076 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3077 {
3078         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3079         struct fcoe_stats_info *fcoe_stat =
3080                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3081
3082         if (!CNIC_LOADED(bp))
3083                 return;
3084
3085         memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3086                bp->fip_mac, ETH_ALEN);
3087
3088         fcoe_stat->qos_priority =
3089                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3090
3091         /* insert FCoE stats from ramrod response */
3092         if (!NO_FCOE(bp)) {
3093                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3094                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3095                         tstorm_queue_statistics;
3096
3097                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3098                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3099                         xstorm_queue_statistics;
3100
3101                 struct fcoe_statistics_params *fw_fcoe_stat =
3102                         &bp->fw_stats_data->fcoe;
3103
3104                 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3105                        fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3106
3107                 ADD_64(fcoe_stat->rx_bytes_hi,
3108                        fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3109                        fcoe_stat->rx_bytes_lo,
3110                        fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3111
3112                 ADD_64(fcoe_stat->rx_bytes_hi,
3113                        fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3114                        fcoe_stat->rx_bytes_lo,
3115                        fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3116
3117                 ADD_64(fcoe_stat->rx_bytes_hi,
3118                        fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3119                        fcoe_stat->rx_bytes_lo,
3120                        fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3121
3122                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3123                        fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3124
3125                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3126                        fcoe_q_tstorm_stats->rcv_ucast_pkts);
3127
3128                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3129                        fcoe_q_tstorm_stats->rcv_bcast_pkts);
3130
3131                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3132                        fcoe_q_tstorm_stats->rcv_mcast_pkts);
3133
3134                 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3135                        fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3136
3137                 ADD_64(fcoe_stat->tx_bytes_hi,
3138                        fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3139                        fcoe_stat->tx_bytes_lo,
3140                        fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3141
3142                 ADD_64(fcoe_stat->tx_bytes_hi,
3143                        fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3144                        fcoe_stat->tx_bytes_lo,
3145                        fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3146
3147                 ADD_64(fcoe_stat->tx_bytes_hi,
3148                        fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3149                        fcoe_stat->tx_bytes_lo,
3150                        fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3151
3152                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3153                        fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3154
3155                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3156                        fcoe_q_xstorm_stats->ucast_pkts_sent);
3157
3158                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3159                        fcoe_q_xstorm_stats->bcast_pkts_sent);
3160
3161                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3162                        fcoe_q_xstorm_stats->mcast_pkts_sent);
3163         }
3164
3165         /* ask L5 driver to add data to the struct */
3166         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3167 }
3168
3169 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3170 {
3171         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3172         struct iscsi_stats_info *iscsi_stat =
3173                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3174
3175         if (!CNIC_LOADED(bp))
3176                 return;
3177
3178         memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3179                bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3180
3181         iscsi_stat->qos_priority =
3182                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3183
3184         /* ask L5 driver to add data to the struct */
3185         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3186 }
3187
3188 /* called due to MCP event (on pmf):
3189  *      reread new bandwidth configuration
3190  *      configure FW
3191  *      notify others function about the change
3192  */
3193 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3194 {
3195         if (bp->link_vars.link_up) {
3196                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3197                 bnx2x_link_sync_notify(bp);
3198         }
3199         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3200 }
3201
3202 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3203 {
3204         bnx2x_config_mf_bw(bp);
3205         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3206 }
3207
3208 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3209 {
3210         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3211         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3212 }
3213
3214 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3215 {
3216         enum drv_info_opcode op_code;
3217         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3218
3219         /* if drv_info version supported by MFW doesn't match - send NACK */
3220         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3221                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3222                 return;
3223         }
3224
3225         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3226                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3227
3228         memset(&bp->slowpath->drv_info_to_mcp, 0,
3229                sizeof(union drv_info_to_mcp));
3230
3231         switch (op_code) {
3232         case ETH_STATS_OPCODE:
3233                 bnx2x_drv_info_ether_stat(bp);
3234                 break;
3235         case FCOE_STATS_OPCODE:
3236                 bnx2x_drv_info_fcoe_stat(bp);
3237                 break;
3238         case ISCSI_STATS_OPCODE:
3239                 bnx2x_drv_info_iscsi_stat(bp);
3240                 break;
3241         default:
3242                 /* if op code isn't supported - send NACK */
3243                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3244                 return;
3245         }
3246
3247         /* if we got drv_info attn from MFW then these fields are defined in
3248          * shmem2 for sure
3249          */
3250         SHMEM2_WR(bp, drv_info_host_addr_lo,
3251                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3252         SHMEM2_WR(bp, drv_info_host_addr_hi,
3253                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3254
3255         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3256 }
3257
3258 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3259 {
3260         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3261
3262         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3263
3264                 /*
3265                  * This is the only place besides the function initialization
3266                  * where the bp->flags can change so it is done without any
3267                  * locks
3268                  */
3269                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3270                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3271                         bp->flags |= MF_FUNC_DIS;
3272
3273                         bnx2x_e1h_disable(bp);
3274                 } else {
3275                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3276                         bp->flags &= ~MF_FUNC_DIS;
3277
3278                         bnx2x_e1h_enable(bp);
3279                 }
3280                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3281         }
3282         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3283                 bnx2x_config_mf_bw(bp);
3284                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3285         }
3286
3287         /* Report results to MCP */
3288         if (dcc_event)
3289                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3290         else
3291                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3292 }
3293
3294 /* must be called under the spq lock */
3295 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3296 {
3297         struct eth_spe *next_spe = bp->spq_prod_bd;
3298
3299         if (bp->spq_prod_bd == bp->spq_last_bd) {
3300                 bp->spq_prod_bd = bp->spq;
3301                 bp->spq_prod_idx = 0;
3302                 DP(BNX2X_MSG_SP, "end of spq\n");
3303         } else {
3304                 bp->spq_prod_bd++;
3305                 bp->spq_prod_idx++;
3306         }
3307         return next_spe;
3308 }
3309
3310 /* must be called under the spq lock */
3311 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3312 {
3313         int func = BP_FUNC(bp);
3314
3315         /*
3316          * Make sure that BD data is updated before writing the producer:
3317          * BD data is written to the memory, the producer is read from the
3318          * memory, thus we need a full memory barrier to ensure the ordering.
3319          */
3320         mb();
3321
3322         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3323                  bp->spq_prod_idx);
3324         mmiowb();
3325 }
3326
3327 /**
3328  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3329  *
3330  * @cmd:        command to check
3331  * @cmd_type:   command type
3332  */
3333 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3334 {
3335         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3336             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3337             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3338             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3339             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3340             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3341             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3342                 return true;
3343         else
3344                 return false;
3345
3346 }
3347
3348
3349 /**
3350  * bnx2x_sp_post - place a single command on an SP ring
3351  *
3352  * @bp:         driver handle
3353  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3354  * @cid:        SW CID the command is related to
3355  * @data_hi:    command private data address (high 32 bits)
3356  * @data_lo:    command private data address (low 32 bits)
3357  * @cmd_type:   command type (e.g. NONE, ETH)
3358  *
3359  * SP data is handled as if it's always an address pair, thus data fields are
3360  * not swapped to little endian in upper functions. Instead this function swaps
3361  * data as if it's two u32 fields.
3362  */
3363 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3364                   u32 data_hi, u32 data_lo, int cmd_type)
3365 {
3366         struct eth_spe *spe;
3367         u16 type;
3368         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3369
3370 #ifdef BNX2X_STOP_ON_ERROR
3371         if (unlikely(bp->panic)) {
3372                 BNX2X_ERR("Can't post SP when there is panic\n");
3373                 return -EIO;
3374         }
3375 #endif
3376
3377         spin_lock_bh(&bp->spq_lock);
3378
3379         if (common) {
3380                 if (!atomic_read(&bp->eq_spq_left)) {
3381                         BNX2X_ERR("BUG! EQ ring full!\n");
3382                         spin_unlock_bh(&bp->spq_lock);
3383                         bnx2x_panic();
3384                         return -EBUSY;
3385                 }
3386         } else if (!atomic_read(&bp->cq_spq_left)) {
3387                         BNX2X_ERR("BUG! SPQ ring full!\n");
3388                         spin_unlock_bh(&bp->spq_lock);
3389                         bnx2x_panic();
3390                         return -EBUSY;
3391         }
3392
3393         spe = bnx2x_sp_get_next(bp);
3394
3395         /* CID needs port number to be encoded int it */
3396         spe->hdr.conn_and_cmd_data =
3397                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3398                                     HW_CID(bp, cid));
3399
3400         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3401
3402         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3403                  SPE_HDR_FUNCTION_ID);
3404
3405         spe->hdr.type = cpu_to_le16(type);
3406
3407         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3408         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3409
3410         /*
3411          * It's ok if the actual decrement is issued towards the memory
3412          * somewhere between the spin_lock and spin_unlock. Thus no
3413          * more explict memory barrier is needed.
3414          */
3415         if (common)
3416                 atomic_dec(&bp->eq_spq_left);
3417         else
3418                 atomic_dec(&bp->cq_spq_left);
3419
3420
3421         DP(BNX2X_MSG_SP,
3422            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3423            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3424            (u32)(U64_LO(bp->spq_mapping) +
3425            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3426            HW_CID(bp, cid), data_hi, data_lo, type,
3427            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3428
3429         bnx2x_sp_prod_update(bp);
3430         spin_unlock_bh(&bp->spq_lock);
3431         return 0;
3432 }
3433
3434 /* acquire split MCP access lock register */
3435 static int bnx2x_acquire_alr(struct bnx2x *bp)
3436 {
3437         u32 j, val;
3438         int rc = 0;
3439
3440         might_sleep();
3441         for (j = 0; j < 1000; j++) {
3442                 val = (1UL << 31);
3443                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3444                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3445                 if (val & (1L << 31))
3446                         break;
3447
3448                 msleep(5);
3449         }
3450         if (!(val & (1L << 31))) {
3451                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3452                 rc = -EBUSY;
3453         }
3454
3455         return rc;
3456 }
3457
3458 /* release split MCP access lock register */
3459 static void bnx2x_release_alr(struct bnx2x *bp)
3460 {
3461         REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3462 }
3463
3464 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3465 #define BNX2X_DEF_SB_IDX        0x0002
3466
3467 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3468 {
3469         struct host_sp_status_block *def_sb = bp->def_status_blk;
3470         u16 rc = 0;
3471
3472         barrier(); /* status block is written to by the chip */
3473         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3474                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3475                 rc |= BNX2X_DEF_SB_ATT_IDX;
3476         }
3477
3478         if (bp->def_idx != def_sb->sp_sb.running_index) {
3479                 bp->def_idx = def_sb->sp_sb.running_index;
3480                 rc |= BNX2X_DEF_SB_IDX;
3481         }
3482
3483         /* Do not reorder: indecies reading should complete before handling */
3484         barrier();
3485         return rc;
3486 }
3487
3488 /*
3489  * slow path service functions
3490  */
3491
3492 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3493 {
3494         int port = BP_PORT(bp);
3495         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3496                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3497         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3498                                        NIG_REG_MASK_INTERRUPT_PORT0;
3499         u32 aeu_mask;
3500         u32 nig_mask = 0;
3501         u32 reg_addr;
3502
3503         if (bp->attn_state & asserted)
3504                 BNX2X_ERR("IGU ERROR\n");
3505
3506         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3507         aeu_mask = REG_RD(bp, aeu_addr);
3508
3509         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3510            aeu_mask, asserted);
3511         aeu_mask &= ~(asserted & 0x3ff);
3512         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3513
3514         REG_WR(bp, aeu_addr, aeu_mask);
3515         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3516
3517         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3518         bp->attn_state |= asserted;
3519         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3520
3521         if (asserted & ATTN_HARD_WIRED_MASK) {
3522                 if (asserted & ATTN_NIG_FOR_FUNC) {
3523
3524                         bnx2x_acquire_phy_lock(bp);
3525
3526                         /* save nig interrupt mask */
3527                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3528
3529                         /* If nig_mask is not set, no need to call the update
3530                          * function.
3531                          */
3532                         if (nig_mask) {
3533                                 REG_WR(bp, nig_int_mask_addr, 0);
3534
3535                                 bnx2x_link_attn(bp);
3536                         }
3537
3538                         /* handle unicore attn? */
3539                 }
3540                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3541                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3542
3543                 if (asserted & GPIO_2_FUNC)
3544                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3545
3546                 if (asserted & GPIO_3_FUNC)
3547                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3548
3549                 if (asserted & GPIO_4_FUNC)
3550                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3551
3552                 if (port == 0) {
3553                         if (asserted & ATTN_GENERAL_ATTN_1) {
3554                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3555                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3556                         }
3557                         if (asserted & ATTN_GENERAL_ATTN_2) {
3558                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3559                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3560                         }
3561                         if (asserted & ATTN_GENERAL_ATTN_3) {
3562                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3563                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3564                         }
3565                 } else {
3566                         if (asserted & ATTN_GENERAL_ATTN_4) {
3567                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3568                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3569                         }
3570                         if (asserted & ATTN_GENERAL_ATTN_5) {
3571                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3572                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3573                         }
3574                         if (asserted & ATTN_GENERAL_ATTN_6) {
3575                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3576                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3577                         }
3578                 }
3579
3580         } /* if hardwired */
3581
3582         if (bp->common.int_block == INT_BLOCK_HC)
3583                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3584                             COMMAND_REG_ATTN_BITS_SET);
3585         else
3586                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3587
3588         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3589            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3590         REG_WR(bp, reg_addr, asserted);
3591
3592         /* now set back the mask */
3593         if (asserted & ATTN_NIG_FOR_FUNC) {
3594                 /* Verify that IGU ack through BAR was written before restoring
3595                  * NIG mask. This loop should exit after 2-3 iterations max.
3596                  */
3597                 if (bp->common.int_block != INT_BLOCK_HC) {
3598                         u32 cnt = 0, igu_acked;
3599                         do {
3600                                 igu_acked = REG_RD(bp,
3601                                                    IGU_REG_ATTENTION_ACK_BITS);
3602                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3603                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3604                         if (!igu_acked)
3605                                 DP(NETIF_MSG_HW,
3606                                    "Failed to verify IGU ack on time\n");
3607                         barrier();
3608                 }
3609                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3610                 bnx2x_release_phy_lock(bp);
3611         }
3612 }
3613
3614 static void bnx2x_fan_failure(struct bnx2x *bp)
3615 {
3616         int port = BP_PORT(bp);
3617         u32 ext_phy_config;
3618         /* mark the failure */
3619         ext_phy_config =
3620                 SHMEM_RD(bp,
3621                          dev_info.port_hw_config[port].external_phy_config);
3622
3623         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3624         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3625         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3626                  ext_phy_config);
3627
3628         /* log the failure */
3629         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3630                             "Please contact OEM Support for assistance\n");
3631
3632         /*
3633          * Scheudle device reset (unload)
3634          * This is due to some boards consuming sufficient power when driver is
3635          * up to overheat if fan fails.
3636          */
3637         smp_mb__before_clear_bit();
3638         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3639         smp_mb__after_clear_bit();
3640         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3641
3642 }
3643
3644 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3645 {
3646         int port = BP_PORT(bp);
3647         int reg_offset;
3648         u32 val;
3649
3650         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3651                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3652
3653         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3654
3655                 val = REG_RD(bp, reg_offset);
3656                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3657                 REG_WR(bp, reg_offset, val);
3658
3659                 BNX2X_ERR("SPIO5 hw attention\n");
3660
3661                 /* Fan failure attention */
3662                 bnx2x_hw_reset_phy(&bp->link_params);
3663                 bnx2x_fan_failure(bp);
3664         }
3665
3666         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3667                 bnx2x_acquire_phy_lock(bp);
3668                 bnx2x_handle_module_detect_int(&bp->link_params);
3669                 bnx2x_release_phy_lock(bp);
3670         }
3671
3672         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3673
3674                 val = REG_RD(bp, reg_offset);
3675                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3676                 REG_WR(bp, reg_offset, val);
3677
3678                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3679                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3680                 bnx2x_panic();
3681         }
3682 }
3683
3684 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3685 {
3686         u32 val;
3687
3688         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3689
3690                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3691                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3692                 /* DORQ discard attention */
3693                 if (val & 0x2)
3694                         BNX2X_ERR("FATAL error from DORQ\n");
3695         }
3696
3697         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3698
3699                 int port = BP_PORT(bp);
3700                 int reg_offset;
3701
3702                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3703                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3704
3705                 val = REG_RD(bp, reg_offset);
3706                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3707                 REG_WR(bp, reg_offset, val);
3708
3709                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3710                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3711                 bnx2x_panic();
3712         }
3713 }
3714
3715 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3716 {
3717         u32 val;
3718
3719         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3720
3721                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3722                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3723                 /* CFC error attention */
3724                 if (val & 0x2)
3725                         BNX2X_ERR("FATAL error from CFC\n");
3726         }
3727
3728         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3729                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3730                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3731                 /* RQ_USDMDP_FIFO_OVERFLOW */
3732                 if (val & 0x18000)
3733                         BNX2X_ERR("FATAL error from PXP\n");
3734
3735                 if (!CHIP_IS_E1x(bp)) {
3736                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3737                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3738                 }
3739         }
3740
3741         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3742
3743                 int port = BP_PORT(bp);
3744                 int reg_offset;
3745
3746                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3747                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3748
3749                 val = REG_RD(bp, reg_offset);
3750                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3751                 REG_WR(bp, reg_offset, val);
3752
3753                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3754                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3755                 bnx2x_panic();
3756         }
3757 }
3758
3759 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3760 {
3761         u32 val;
3762
3763         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3764
3765                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3766                         int func = BP_FUNC(bp);
3767
3768                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3769                         bnx2x_read_mf_cfg(bp);
3770                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3771                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3772                         val = SHMEM_RD(bp,
3773                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3774                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3775                                 bnx2x_dcc_event(bp,
3776                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3777
3778                         if (val & DRV_STATUS_SET_MF_BW)
3779                                 bnx2x_set_mf_bw(bp);
3780
3781                         if (val & DRV_STATUS_DRV_INFO_REQ)
3782                                 bnx2x_handle_drv_info_req(bp);
3783                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3784                                 bnx2x_pmf_update(bp);
3785
3786                         if (bp->port.pmf &&
3787                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3788                                 bp->dcbx_enabled > 0)
3789                                 /* start dcbx state machine */
3790                                 bnx2x_dcbx_set_params(bp,
3791                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3792                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
3793                                 bnx2x_handle_afex_cmd(bp,
3794                                         val & DRV_STATUS_AFEX_EVENT_MASK);
3795                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3796                                 bnx2x_handle_eee_event(bp);
3797                         if (bp->link_vars.periodic_flags &
3798                             PERIODIC_FLAGS_LINK_EVENT) {
3799                                 /*  sync with link */
3800                                 bnx2x_acquire_phy_lock(bp);
3801                                 bp->link_vars.periodic_flags &=
3802                                         ~PERIODIC_FLAGS_LINK_EVENT;
3803                                 bnx2x_release_phy_lock(bp);
3804                                 if (IS_MF(bp))
3805                                         bnx2x_link_sync_notify(bp);
3806                                 bnx2x_link_report(bp);
3807                         }
3808                         /* Always call it here: bnx2x_link_report() will
3809                          * prevent the link indication duplication.
3810                          */
3811                         bnx2x__link_status_update(bp);
3812                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3813
3814                         BNX2X_ERR("MC assert!\n");
3815                         bnx2x_mc_assert(bp);
3816                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3817                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3818                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3819                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3820                         bnx2x_panic();
3821
3822                 } else if (attn & BNX2X_MCP_ASSERT) {
3823
3824                         BNX2X_ERR("MCP assert!\n");
3825                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3826                         bnx2x_fw_dump(bp);
3827
3828                 } else
3829                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3830         }
3831
3832         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3833                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3834                 if (attn & BNX2X_GRC_TIMEOUT) {
3835                         val = CHIP_IS_E1(bp) ? 0 :
3836                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3837                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
3838                 }
3839                 if (attn & BNX2X_GRC_RSV) {
3840                         val = CHIP_IS_E1(bp) ? 0 :
3841                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3842                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
3843                 }
3844                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3845         }
3846 }
3847
3848 /*
3849  * Bits map:
3850  * 0-7   - Engine0 load counter.
3851  * 8-15  - Engine1 load counter.
3852  * 16    - Engine0 RESET_IN_PROGRESS bit.
3853  * 17    - Engine1 RESET_IN_PROGRESS bit.
3854  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3855  *         on the engine
3856  * 19    - Engine1 ONE_IS_LOADED.
3857  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
3858  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
3859  *         just the one belonging to its engine).
3860  *
3861  */
3862 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
3863
3864 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
3865 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
3866 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
3867 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
3868 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
3869 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
3870 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
3871
3872 /*
3873  * Set the GLOBAL_RESET bit.
3874  *
3875  * Should be run under rtnl lock
3876  */
3877 void bnx2x_set_reset_global(struct bnx2x *bp)
3878 {
3879         u32 val;
3880         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3881         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3882         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3883         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3884 }
3885
3886 /*
3887  * Clear the GLOBAL_RESET bit.
3888  *
3889  * Should be run under rtnl lock
3890  */
3891 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3892 {
3893         u32 val;
3894         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3895         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3896         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3897         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3898 }
3899
3900 /*
3901  * Checks the GLOBAL_RESET bit.
3902  *
3903  * should be run under rtnl lock
3904  */
3905 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3906 {
3907         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3908
3909         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3910         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3911 }
3912
3913 /*
3914  * Clear RESET_IN_PROGRESS bit for the current engine.
3915  *
3916  * Should be run under rtnl lock
3917  */
3918 static void bnx2x_set_reset_done(struct bnx2x *bp)
3919 {
3920         u32 val;
3921         u32 bit = BP_PATH(bp) ?
3922                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3923         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3924         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3925
3926         /* Clear the bit */
3927         val &= ~bit;
3928         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3929
3930         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3931 }
3932
3933 /*
3934  * Set RESET_IN_PROGRESS for the current engine.
3935  *
3936  * should be run under rtnl lock
3937  */
3938 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3939 {
3940         u32 val;
3941         u32 bit = BP_PATH(bp) ?
3942                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3943         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3944         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3945
3946         /* Set the bit */
3947         val |= bit;
3948         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3949         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3950 }
3951
3952 /*
3953  * Checks the RESET_IN_PROGRESS bit for the given engine.
3954  * should be run under rtnl lock
3955  */
3956 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3957 {
3958         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3959         u32 bit = engine ?
3960                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3961
3962         /* return false if bit is set */
3963         return (val & bit) ? false : true;
3964 }
3965
3966 /*
3967  * set pf load for the current pf.
3968  *
3969  * should be run under rtnl lock
3970  */
3971 void bnx2x_set_pf_load(struct bnx2x *bp)
3972 {
3973         u32 val1, val;
3974         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3975                              BNX2X_PATH0_LOAD_CNT_MASK;
3976         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3977                              BNX2X_PATH0_LOAD_CNT_SHIFT;
3978
3979         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3980         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3981
3982         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3983
3984         /* get the current counter value */
3985         val1 = (val & mask) >> shift;
3986
3987         /* set bit of that PF */
3988         val1 |= (1 << bp->pf_num);
3989
3990         /* clear the old value */
3991         val &= ~mask;
3992
3993         /* set the new one */
3994         val |= ((val1 << shift) & mask);
3995
3996         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3997         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3998 }
3999
4000 /**
4001  * bnx2x_clear_pf_load - clear pf load mark
4002  *
4003  * @bp:         driver handle
4004  *
4005  * Should be run under rtnl lock.
4006  * Decrements the load counter for the current engine. Returns
4007  * whether other functions are still loaded
4008  */
4009 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4010 {
4011         u32 val1, val;
4012         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4013                              BNX2X_PATH0_LOAD_CNT_MASK;
4014         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4015                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4016
4017         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4018         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4019         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4020
4021         /* get the current counter value */
4022         val1 = (val & mask) >> shift;
4023
4024         /* clear bit of that PF */
4025         val1 &= ~(1 << bp->pf_num);
4026
4027         /* clear the old value */
4028         val &= ~mask;
4029
4030         /* set the new one */
4031         val |= ((val1 << shift) & mask);
4032
4033         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4034         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4035         return val1 != 0;
4036 }
4037
4038 /*
4039  * Read the load status for the current engine.
4040  *
4041  * should be run under rtnl lock
4042  */
4043 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4044 {
4045         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4046                              BNX2X_PATH0_LOAD_CNT_MASK);
4047         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4048                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4049         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4050
4051         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4052
4053         val = (val & mask) >> shift;
4054
4055         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4056            engine, val);
4057
4058         return val != 0;
4059 }
4060
4061 static void _print_next_block(int idx, const char *blk)
4062 {
4063         pr_cont("%s%s", idx ? ", " : "", blk);
4064 }
4065
4066 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4067                                            bool print)
4068 {
4069         int i = 0;
4070         u32 cur_bit = 0;
4071         for (i = 0; sig; i++) {
4072                 cur_bit = ((u32)0x1 << i);
4073                 if (sig & cur_bit) {
4074                         switch (cur_bit) {
4075                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4076                                 if (print)
4077                                         _print_next_block(par_num++, "BRB");
4078                                 break;
4079                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4080                                 if (print)
4081                                         _print_next_block(par_num++, "PARSER");
4082                                 break;
4083                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4084                                 if (print)
4085                                         _print_next_block(par_num++, "TSDM");
4086                                 break;
4087                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4088                                 if (print)
4089                                         _print_next_block(par_num++,
4090                                                           "SEARCHER");
4091                                 break;
4092                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4093                                 if (print)
4094                                         _print_next_block(par_num++, "TCM");
4095                                 break;
4096                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4097                                 if (print)
4098                                         _print_next_block(par_num++, "TSEMI");
4099                                 break;
4100                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4101                                 if (print)
4102                                         _print_next_block(par_num++, "XPB");
4103                                 break;
4104                         }
4105
4106                         /* Clear the bit */
4107                         sig &= ~cur_bit;
4108                 }
4109         }
4110
4111         return par_num;
4112 }
4113
4114 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4115                                            bool *global, bool print)
4116 {
4117         int i = 0;
4118         u32 cur_bit = 0;
4119         for (i = 0; sig; i++) {
4120                 cur_bit = ((u32)0x1 << i);
4121                 if (sig & cur_bit) {
4122                         switch (cur_bit) {
4123                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4124                                 if (print)
4125                                         _print_next_block(par_num++, "PBF");
4126                                 break;
4127                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4128                                 if (print)
4129                                         _print_next_block(par_num++, "QM");
4130                                 break;
4131                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4132                                 if (print)
4133                                         _print_next_block(par_num++, "TM");
4134                                 break;
4135                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4136                                 if (print)
4137                                         _print_next_block(par_num++, "XSDM");
4138                                 break;
4139                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4140                                 if (print)
4141                                         _print_next_block(par_num++, "XCM");
4142                                 break;
4143                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4144                                 if (print)
4145                                         _print_next_block(par_num++, "XSEMI");
4146                                 break;
4147                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4148                                 if (print)
4149                                         _print_next_block(par_num++,
4150                                                           "DOORBELLQ");
4151                                 break;
4152                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4153                                 if (print)
4154                                         _print_next_block(par_num++, "NIG");
4155                                 break;
4156                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4157                                 if (print)
4158                                         _print_next_block(par_num++,
4159                                                           "VAUX PCI CORE");
4160                                 *global = true;
4161                                 break;
4162                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4163                                 if (print)
4164                                         _print_next_block(par_num++, "DEBUG");
4165                                 break;
4166                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4167                                 if (print)
4168                                         _print_next_block(par_num++, "USDM");
4169                                 break;
4170                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4171                                 if (print)
4172                                         _print_next_block(par_num++, "UCM");
4173                                 break;
4174                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4175                                 if (print)
4176                                         _print_next_block(par_num++, "USEMI");
4177                                 break;
4178                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4179                                 if (print)
4180                                         _print_next_block(par_num++, "UPB");
4181                                 break;
4182                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4183                                 if (print)
4184                                         _print_next_block(par_num++, "CSDM");
4185                                 break;
4186                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4187                                 if (print)
4188                                         _print_next_block(par_num++, "CCM");
4189                                 break;
4190                         }
4191
4192                         /* Clear the bit */
4193                         sig &= ~cur_bit;
4194                 }
4195         }
4196
4197         return par_num;
4198 }
4199
4200 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4201                                            bool print)
4202 {
4203         int i = 0;
4204         u32 cur_bit = 0;
4205         for (i = 0; sig; i++) {
4206                 cur_bit = ((u32)0x1 << i);
4207                 if (sig & cur_bit) {
4208                         switch (cur_bit) {
4209                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4210                                 if (print)
4211                                         _print_next_block(par_num++, "CSEMI");
4212                                 break;
4213                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4214                                 if (print)
4215                                         _print_next_block(par_num++, "PXP");
4216                                 break;
4217                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4218                                 if (print)
4219                                         _print_next_block(par_num++,
4220                                         "PXPPCICLOCKCLIENT");
4221                                 break;
4222                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4223                                 if (print)
4224                                         _print_next_block(par_num++, "CFC");
4225                                 break;
4226                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4227                                 if (print)
4228                                         _print_next_block(par_num++, "CDU");
4229                                 break;
4230                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4231                                 if (print)
4232                                         _print_next_block(par_num++, "DMAE");
4233                                 break;
4234                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4235                                 if (print)
4236                                         _print_next_block(par_num++, "IGU");
4237                                 break;
4238                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4239                                 if (print)
4240                                         _print_next_block(par_num++, "MISC");
4241                                 break;
4242                         }
4243
4244                         /* Clear the bit */
4245                         sig &= ~cur_bit;
4246                 }
4247         }
4248
4249         return par_num;
4250 }
4251
4252 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4253                                            bool *global, bool print)
4254 {
4255         int i = 0;
4256         u32 cur_bit = 0;
4257         for (i = 0; sig; i++) {
4258                 cur_bit = ((u32)0x1 << i);
4259                 if (sig & cur_bit) {
4260                         switch (cur_bit) {
4261                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4262                                 if (print)
4263                                         _print_next_block(par_num++, "MCP ROM");
4264                                 *global = true;
4265                                 break;
4266                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4267                                 if (print)
4268                                         _print_next_block(par_num++,
4269                                                           "MCP UMP RX");
4270                                 *global = true;
4271                                 break;
4272                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4273                                 if (print)
4274                                         _print_next_block(par_num++,
4275                                                           "MCP UMP TX");
4276                                 *global = true;
4277                                 break;
4278                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4279                                 if (print)
4280                                         _print_next_block(par_num++,
4281                                                           "MCP SCPAD");
4282                                 *global = true;
4283                                 break;
4284                         }
4285
4286                         /* Clear the bit */
4287                         sig &= ~cur_bit;
4288                 }
4289         }
4290
4291         return par_num;
4292 }
4293
4294 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4295                                            bool print)
4296 {
4297         int i = 0;
4298         u32 cur_bit = 0;
4299         for (i = 0; sig; i++) {
4300                 cur_bit = ((u32)0x1 << i);
4301                 if (sig & cur_bit) {
4302                         switch (cur_bit) {
4303                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4304                                 if (print)
4305                                         _print_next_block(par_num++, "PGLUE_B");
4306                                 break;
4307                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4308                                 if (print)
4309                                         _print_next_block(par_num++, "ATC");
4310                                 break;
4311                         }
4312
4313                         /* Clear the bit */
4314                         sig &= ~cur_bit;
4315                 }
4316         }
4317
4318         return par_num;
4319 }
4320
4321 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4322                               u32 *sig)
4323 {
4324         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4325             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4326             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4327             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4328             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4329                 int par_num = 0;
4330                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4331                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4332                           sig[0] & HW_PRTY_ASSERT_SET_0,
4333                           sig[1] & HW_PRTY_ASSERT_SET_1,
4334                           sig[2] & HW_PRTY_ASSERT_SET_2,
4335                           sig[3] & HW_PRTY_ASSERT_SET_3,
4336                           sig[4] & HW_PRTY_ASSERT_SET_4);
4337                 if (print)
4338                         netdev_err(bp->dev,
4339                                    "Parity errors detected in blocks: ");
4340                 par_num = bnx2x_check_blocks_with_parity0(
4341                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4342                 par_num = bnx2x_check_blocks_with_parity1(
4343                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4344                 par_num = bnx2x_check_blocks_with_parity2(
4345                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4346                 par_num = bnx2x_check_blocks_with_parity3(
4347                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4348                 par_num = bnx2x_check_blocks_with_parity4(
4349                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4350
4351                 if (print)
4352                         pr_cont("\n");
4353
4354                 return true;
4355         } else
4356                 return false;
4357 }
4358
4359 /**
4360  * bnx2x_chk_parity_attn - checks for parity attentions.
4361  *
4362  * @bp:         driver handle
4363  * @global:     true if there was a global attention
4364  * @print:      show parity attention in syslog
4365  */
4366 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4367 {
4368         struct attn_route attn = { {0} };
4369         int port = BP_PORT(bp);
4370
4371         attn.sig[0] = REG_RD(bp,
4372                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4373                              port*4);
4374         attn.sig[1] = REG_RD(bp,
4375                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4376                              port*4);
4377         attn.sig[2] = REG_RD(bp,
4378                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4379                              port*4);
4380         attn.sig[3] = REG_RD(bp,
4381                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4382                              port*4);
4383
4384         if (!CHIP_IS_E1x(bp))
4385                 attn.sig[4] = REG_RD(bp,
4386                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4387                                      port*4);
4388
4389         return bnx2x_parity_attn(bp, global, print, attn.sig);
4390 }
4391
4392
4393 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4394 {
4395         u32 val;
4396         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4397
4398                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4399                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4400                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4401                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4402                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4403                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4404                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4405                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4406                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4407                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4408                 if (val &
4409                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4410                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4411                 if (val &
4412                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4413                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4414                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4415                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4416                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4417                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4418                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4419                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4420         }
4421         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4422                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4423                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4424                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4425                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4426                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4427                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4428                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4429                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4430                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4431                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4432                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4433                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4434                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4435                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4436         }
4437
4438         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4439                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4440                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4441                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4442                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4443         }
4444
4445 }
4446
4447 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4448 {
4449         struct attn_route attn, *group_mask;
4450         int port = BP_PORT(bp);
4451         int index;
4452         u32 reg_addr;
4453         u32 val;
4454         u32 aeu_mask;
4455         bool global = false;
4456
4457         /* need to take HW lock because MCP or other port might also
4458            try to handle this event */
4459         bnx2x_acquire_alr(bp);
4460
4461         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4462 #ifndef BNX2X_STOP_ON_ERROR
4463                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4464                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4465                 /* Disable HW interrupts */
4466                 bnx2x_int_disable(bp);
4467                 /* In case of parity errors don't handle attentions so that
4468                  * other function would "see" parity errors.
4469                  */
4470 #else
4471                 bnx2x_panic();
4472 #endif
4473                 bnx2x_release_alr(bp);
4474                 return;
4475         }
4476
4477         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4478         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4479         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4480         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4481         if (!CHIP_IS_E1x(bp))
4482                 attn.sig[4] =
4483                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4484         else
4485                 attn.sig[4] = 0;
4486
4487         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4488            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4489
4490         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4491                 if (deasserted & (1 << index)) {
4492                         group_mask = &bp->attn_group[index];
4493
4494                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4495                            index,
4496                            group_mask->sig[0], group_mask->sig[1],
4497                            group_mask->sig[2], group_mask->sig[3],
4498                            group_mask->sig[4]);
4499
4500                         bnx2x_attn_int_deasserted4(bp,
4501                                         attn.sig[4] & group_mask->sig[4]);
4502                         bnx2x_attn_int_deasserted3(bp,
4503                                         attn.sig[3] & group_mask->sig[3]);
4504                         bnx2x_attn_int_deasserted1(bp,
4505                                         attn.sig[1] & group_mask->sig[1]);
4506                         bnx2x_attn_int_deasserted2(bp,
4507                                         attn.sig[2] & group_mask->sig[2]);
4508                         bnx2x_attn_int_deasserted0(bp,
4509                                         attn.sig[0] & group_mask->sig[0]);
4510                 }
4511         }
4512
4513         bnx2x_release_alr(bp);
4514
4515         if (bp->common.int_block == INT_BLOCK_HC)
4516                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4517                             COMMAND_REG_ATTN_BITS_CLR);
4518         else
4519                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4520
4521         val = ~deasserted;
4522         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4523            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4524         REG_WR(bp, reg_addr, val);
4525
4526         if (~bp->attn_state & deasserted)
4527                 BNX2X_ERR("IGU ERROR\n");
4528
4529         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4530                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4531
4532         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4533         aeu_mask = REG_RD(bp, reg_addr);
4534
4535         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4536            aeu_mask, deasserted);
4537         aeu_mask |= (deasserted & 0x3ff);
4538         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4539
4540         REG_WR(bp, reg_addr, aeu_mask);
4541         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4542
4543         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4544         bp->attn_state &= ~deasserted;
4545         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4546 }
4547
4548 static void bnx2x_attn_int(struct bnx2x *bp)
4549 {
4550         /* read local copy of bits */
4551         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4552                                                                 attn_bits);
4553         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4554                                                                 attn_bits_ack);
4555         u32 attn_state = bp->attn_state;
4556
4557         /* look for changed bits */
4558         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4559         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4560
4561         DP(NETIF_MSG_HW,
4562            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4563            attn_bits, attn_ack, asserted, deasserted);
4564
4565         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4566                 BNX2X_ERR("BAD attention state\n");
4567
4568         /* handle bits that were raised */
4569         if (asserted)
4570                 bnx2x_attn_int_asserted(bp, asserted);
4571
4572         if (deasserted)
4573                 bnx2x_attn_int_deasserted(bp, deasserted);
4574 }
4575
4576 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4577                       u16 index, u8 op, u8 update)
4578 {
4579         u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4580
4581         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4582                              igu_addr);
4583 }
4584
4585 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4586 {
4587         /* No memory barriers */
4588         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4589         mmiowb(); /* keep prod updates ordered */
4590 }
4591
4592 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4593                                       union event_ring_elem *elem)
4594 {
4595         u8 err = elem->message.error;
4596
4597         if (!bp->cnic_eth_dev.starting_cid  ||
4598             (cid < bp->cnic_eth_dev.starting_cid &&
4599             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4600                 return 1;
4601
4602         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4603
4604         if (unlikely(err)) {
4605
4606                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4607                           cid);
4608                 bnx2x_panic_dump(bp);
4609         }
4610         bnx2x_cnic_cfc_comp(bp, cid, err);
4611         return 0;
4612 }
4613
4614 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4615 {
4616         struct bnx2x_mcast_ramrod_params rparam;
4617         int rc;
4618
4619         memset(&rparam, 0, sizeof(rparam));
4620
4621         rparam.mcast_obj = &bp->mcast_obj;
4622
4623         netif_addr_lock_bh(bp->dev);
4624
4625         /* Clear pending state for the last command */
4626         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4627
4628         /* If there are pending mcast commands - send them */
4629         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4630                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4631                 if (rc < 0)
4632                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4633                                   rc);
4634         }
4635
4636         netif_addr_unlock_bh(bp->dev);
4637 }
4638
4639 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4640                                             union event_ring_elem *elem)
4641 {
4642         unsigned long ramrod_flags = 0;
4643         int rc = 0;
4644         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4645         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4646
4647         /* Always push next commands out, don't wait here */
4648         __set_bit(RAMROD_CONT, &ramrod_flags);
4649
4650         switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4651         case BNX2X_FILTER_MAC_PENDING:
4652                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4653                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4654                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4655                 else
4656                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4657
4658                 break;
4659         case BNX2X_FILTER_MCAST_PENDING:
4660                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4661                 /* This is only relevant for 57710 where multicast MACs are
4662                  * configured as unicast MACs using the same ramrod.
4663                  */
4664                 bnx2x_handle_mcast_eqe(bp);
4665                 return;
4666         default:
4667                 BNX2X_ERR("Unsupported classification command: %d\n",
4668                           elem->message.data.eth_event.echo);
4669                 return;
4670         }
4671
4672         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4673
4674         if (rc < 0)
4675                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4676         else if (rc > 0)
4677                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4678
4679 }
4680
4681 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4682
4683 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4684 {
4685         netif_addr_lock_bh(bp->dev);
4686
4687         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4688
4689         /* Send rx_mode command again if was requested */
4690         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4691                 bnx2x_set_storm_rx_mode(bp);
4692         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4693                                     &bp->sp_state))
4694                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4695         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4696                                     &bp->sp_state))
4697                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4698
4699         netif_addr_unlock_bh(bp->dev);
4700 }
4701
4702 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4703                                               union event_ring_elem *elem)
4704 {
4705         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4706                 DP(BNX2X_MSG_SP,
4707                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4708                    elem->message.data.vif_list_event.func_bit_map);
4709                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4710                         elem->message.data.vif_list_event.func_bit_map);
4711         } else if (elem->message.data.vif_list_event.echo ==
4712                    VIF_LIST_RULE_SET) {
4713                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4714                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4715         }
4716 }
4717
4718 /* called with rtnl_lock */
4719 static void bnx2x_after_function_update(struct bnx2x *bp)
4720 {
4721         int q, rc;
4722         struct bnx2x_fastpath *fp;
4723         struct bnx2x_queue_state_params queue_params = {NULL};
4724         struct bnx2x_queue_update_params *q_update_params =
4725                 &queue_params.params.update;
4726
4727         /* Send Q update command with afex vlan removal values  for all Qs */
4728         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4729
4730         /* set silent vlan removal values according to vlan mode */
4731         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4732                   &q_update_params->update_flags);
4733         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4734                   &q_update_params->update_flags);
4735         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4736
4737         /* in access mode mark mask and value are 0 to strip all vlans */
4738         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4739                 q_update_params->silent_removal_value = 0;
4740                 q_update_params->silent_removal_mask = 0;
4741         } else {
4742                 q_update_params->silent_removal_value =
4743                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4744                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4745         }
4746
4747         for_each_eth_queue(bp, q) {
4748                 /* Set the appropriate Queue object */
4749                 fp = &bp->fp[q];
4750                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4751
4752                 /* send the ramrod */
4753                 rc = bnx2x_queue_state_change(bp, &queue_params);
4754                 if (rc < 0)
4755                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4756                                   q);
4757         }
4758
4759         if (!NO_FCOE(bp)) {
4760                 fp = &bp->fp[FCOE_IDX(bp)];
4761                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4762
4763                 /* clear pending completion bit */
4764                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4765
4766                 /* mark latest Q bit */
4767                 smp_mb__before_clear_bit();
4768                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4769                 smp_mb__after_clear_bit();
4770
4771                 /* send Q update ramrod for FCoE Q */
4772                 rc = bnx2x_queue_state_change(bp, &queue_params);
4773                 if (rc < 0)
4774                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4775                                   q);
4776         } else {
4777                 /* If no FCoE ring - ACK MCP now */
4778                 bnx2x_link_report(bp);
4779                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4780         }
4781 }
4782
4783 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4784         struct bnx2x *bp, u32 cid)
4785 {
4786         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4787
4788         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4789                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4790         else
4791                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4792 }
4793
4794 static void bnx2x_eq_int(struct bnx2x *bp)
4795 {
4796         u16 hw_cons, sw_cons, sw_prod;
4797         union event_ring_elem *elem;
4798         u8 echo;
4799         u32 cid;
4800         u8 opcode;
4801         int spqe_cnt = 0;
4802         struct bnx2x_queue_sp_obj *q_obj;
4803         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4804         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4805
4806         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4807
4808         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4809          * when we get the the next-page we nned to adjust so the loop
4810          * condition below will be met. The next element is the size of a
4811          * regular element and hence incrementing by 1
4812          */
4813         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4814                 hw_cons++;
4815
4816         /* This function may never run in parallel with itself for a
4817          * specific bp, thus there is no need in "paired" read memory
4818          * barrier here.
4819          */
4820         sw_cons = bp->eq_cons;
4821         sw_prod = bp->eq_prod;
4822
4823         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
4824                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4825
4826         for (; sw_cons != hw_cons;
4827               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4828
4829
4830                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4831
4832                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4833                 opcode = elem->message.opcode;
4834
4835
4836                 /* handle eq element */
4837                 switch (opcode) {
4838                 case EVENT_RING_OPCODE_STAT_QUERY:
4839                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4840                            "got statistics comp event %d\n",
4841                            bp->stats_comp++);
4842                         /* nothing to do with stats comp */
4843                         goto next_spqe;
4844
4845                 case EVENT_RING_OPCODE_CFC_DEL:
4846                         /* handle according to cid range */
4847                         /*
4848                          * we may want to verify here that the bp state is
4849                          * HALTING
4850                          */
4851                         DP(BNX2X_MSG_SP,
4852                            "got delete ramrod for MULTI[%d]\n", cid);
4853
4854                         if (CNIC_LOADED(bp) &&
4855                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4856                                 goto next_spqe;
4857
4858                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
4859
4860                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4861                                 break;
4862
4863
4864
4865                         goto next_spqe;
4866
4867                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4868                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4869                         if (f_obj->complete_cmd(bp, f_obj,
4870                                                 BNX2X_F_CMD_TX_STOP))
4871                                 break;
4872                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4873                         goto next_spqe;
4874
4875                 case EVENT_RING_OPCODE_START_TRAFFIC:
4876                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4877                         if (f_obj->complete_cmd(bp, f_obj,
4878                                                 BNX2X_F_CMD_TX_START))
4879                                 break;
4880                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4881                         goto next_spqe;
4882
4883                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4884                         echo = elem->message.data.function_update_event.echo;
4885                         if (echo == SWITCH_UPDATE) {
4886                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4887                                    "got FUNC_SWITCH_UPDATE ramrod\n");
4888                                 if (f_obj->complete_cmd(
4889                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
4890                                         break;
4891
4892                         } else {
4893                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4894                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
4895                                 f_obj->complete_cmd(bp, f_obj,
4896                                                     BNX2X_F_CMD_AFEX_UPDATE);
4897
4898                                 /* We will perform the Queues update from
4899                                  * sp_rtnl task as all Queue SP operations
4900                                  * should run under rtnl_lock.
4901                                  */
4902                                 smp_mb__before_clear_bit();
4903                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4904                                         &bp->sp_rtnl_state);
4905                                 smp_mb__after_clear_bit();
4906
4907                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4908                         }
4909
4910                         goto next_spqe;
4911
4912                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4913                         f_obj->complete_cmd(bp, f_obj,
4914                                             BNX2X_F_CMD_AFEX_VIFLISTS);
4915                         bnx2x_after_afex_vif_lists(bp, elem);
4916                         goto next_spqe;
4917                 case EVENT_RING_OPCODE_FUNCTION_START:
4918                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4919                            "got FUNC_START ramrod\n");
4920                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4921                                 break;
4922
4923                         goto next_spqe;
4924
4925                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4926                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4927                            "got FUNC_STOP ramrod\n");
4928                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4929                                 break;
4930
4931                         goto next_spqe;
4932                 }
4933
4934                 switch (opcode | bp->state) {
4935                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4936                       BNX2X_STATE_OPEN):
4937                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4938                       BNX2X_STATE_OPENING_WAIT4_PORT):
4939                         cid = elem->message.data.eth_event.echo &
4940                                 BNX2X_SWCID_MASK;
4941                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4942                            cid);
4943                         rss_raw->clear_pending(rss_raw);
4944                         break;
4945
4946                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4947                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4948                 case (EVENT_RING_OPCODE_SET_MAC |
4949                       BNX2X_STATE_CLOSING_WAIT4_HALT):
4950                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4951                       BNX2X_STATE_OPEN):
4952                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4953                       BNX2X_STATE_DIAG):
4954                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4955                       BNX2X_STATE_CLOSING_WAIT4_HALT):
4956                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4957                         bnx2x_handle_classification_eqe(bp, elem);
4958                         break;
4959
4960                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4961                       BNX2X_STATE_OPEN):
4962                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4963                       BNX2X_STATE_DIAG):
4964                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4965                       BNX2X_STATE_CLOSING_WAIT4_HALT):
4966                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4967                         bnx2x_handle_mcast_eqe(bp);
4968                         break;
4969
4970                 case (EVENT_RING_OPCODE_FILTERS_RULES |
4971                       BNX2X_STATE_OPEN):
4972                 case (EVENT_RING_OPCODE_FILTERS_RULES |
4973                       BNX2X_STATE_DIAG):
4974                 case (EVENT_RING_OPCODE_FILTERS_RULES |
4975                       BNX2X_STATE_CLOSING_WAIT4_HALT):
4976                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4977                         bnx2x_handle_rx_mode_eqe(bp);
4978                         break;
4979                 default:
4980                         /* unknown event log error and continue */
4981                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4982                                   elem->message.opcode, bp->state);
4983                 }
4984 next_spqe:
4985                 spqe_cnt++;
4986         } /* for */
4987
4988         smp_mb__before_atomic_inc();
4989         atomic_add(spqe_cnt, &bp->eq_spq_left);
4990
4991         bp->eq_cons = sw_cons;
4992         bp->eq_prod = sw_prod;
4993         /* Make sure that above mem writes were issued towards the memory */
4994         smp_wmb();
4995
4996         /* update producer */
4997         bnx2x_update_eq_prod(bp, bp->eq_prod);
4998 }
4999
5000 static void bnx2x_sp_task(struct work_struct *work)
5001 {
5002         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5003         u16 status;
5004
5005         status = bnx2x_update_dsb_idx(bp);
5006 /*      if (status == 0)                                     */
5007 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
5008
5009         DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
5010
5011         /* HW attentions */
5012         if (status & BNX2X_DEF_SB_ATT_IDX) {
5013                 bnx2x_attn_int(bp);
5014                 status &= ~BNX2X_DEF_SB_ATT_IDX;
5015         }
5016
5017         /* SP events: STAT_QUERY and others */
5018         if (status & BNX2X_DEF_SB_IDX) {
5019                 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5020
5021                 if (FCOE_INIT(bp) &&
5022                     (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5023                         /*
5024                          * Prevent local bottom-halves from running as
5025                          * we are going to change the local NAPI list.
5026                          */
5027                         local_bh_disable();
5028                         napi_schedule(&bnx2x_fcoe(bp, napi));
5029                         local_bh_enable();
5030                 }
5031
5032                 /* Handle EQ completions */
5033                 bnx2x_eq_int(bp);
5034
5035                 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5036                         le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5037
5038                 status &= ~BNX2X_DEF_SB_IDX;
5039         }
5040
5041         if (unlikely(status))
5042                 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5043                    status);
5044
5045         bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5046              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5047
5048         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5049         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5050                                &bp->sp_state)) {
5051                 bnx2x_link_report(bp);
5052                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5053         }
5054 }
5055
5056 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5057 {
5058         struct net_device *dev = dev_instance;
5059         struct bnx2x *bp = netdev_priv(dev);
5060
5061         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5062                      IGU_INT_DISABLE, 0);
5063
5064 #ifdef BNX2X_STOP_ON_ERROR
5065         if (unlikely(bp->panic))
5066                 return IRQ_HANDLED;
5067 #endif
5068
5069         if (CNIC_LOADED(bp)) {
5070                 struct cnic_ops *c_ops;
5071
5072                 rcu_read_lock();
5073                 c_ops = rcu_dereference(bp->cnic_ops);
5074                 if (c_ops)
5075                         c_ops->cnic_handler(bp->cnic_data, NULL);
5076                 rcu_read_unlock();
5077         }
5078
5079         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5080
5081         return IRQ_HANDLED;
5082 }
5083
5084 /* end of slow path */
5085
5086
5087 void bnx2x_drv_pulse(struct bnx2x *bp)
5088 {
5089         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5090                  bp->fw_drv_pulse_wr_seq);
5091 }
5092
5093
5094 static void bnx2x_timer(unsigned long data)
5095 {
5096         struct bnx2x *bp = (struct bnx2x *) data;
5097
5098         if (!netif_running(bp->dev))
5099                 return;
5100
5101         if (!BP_NOMCP(bp)) {
5102                 int mb_idx = BP_FW_MB_IDX(bp);
5103                 u32 drv_pulse;
5104                 u32 mcp_pulse;
5105
5106                 ++bp->fw_drv_pulse_wr_seq;
5107                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5108                 /* TBD - add SYSTEM_TIME */
5109                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5110                 bnx2x_drv_pulse(bp);
5111
5112                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5113                              MCP_PULSE_SEQ_MASK);
5114                 /* The delta between driver pulse and mcp response
5115                  * should be 1 (before mcp response) or 0 (after mcp response)
5116                  */
5117                 if ((drv_pulse != mcp_pulse) &&
5118                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5119                         /* someone lost a heartbeat... */
5120                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5121                                   drv_pulse, mcp_pulse);
5122                 }
5123         }
5124
5125         if (bp->state == BNX2X_STATE_OPEN)
5126                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5127
5128         mod_timer(&bp->timer, jiffies + bp->current_interval);
5129 }
5130
5131 /* end of Statistics */
5132
5133 /* nic init */
5134
5135 /*
5136  * nic init service functions
5137  */
5138
5139 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5140 {
5141         u32 i;
5142         if (!(len%4) && !(addr%4))
5143                 for (i = 0; i < len; i += 4)
5144                         REG_WR(bp, addr + i, fill);
5145         else
5146                 for (i = 0; i < len; i++)
5147                         REG_WR8(bp, addr + i, fill);
5148
5149 }
5150
5151 /* helper: writes FP SP data to FW - data_size in dwords */
5152 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5153                                 int fw_sb_id,
5154                                 u32 *sb_data_p,
5155                                 u32 data_size)
5156 {
5157         int index;
5158         for (index = 0; index < data_size; index++)
5159                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5160                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5161                         sizeof(u32)*index,
5162                         *(sb_data_p + index));
5163 }
5164
5165 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5166 {
5167         u32 *sb_data_p;
5168         u32 data_size = 0;
5169         struct hc_status_block_data_e2 sb_data_e2;
5170         struct hc_status_block_data_e1x sb_data_e1x;
5171
5172         /* disable the function first */
5173         if (!CHIP_IS_E1x(bp)) {
5174                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5175                 sb_data_e2.common.state = SB_DISABLED;
5176                 sb_data_e2.common.p_func.vf_valid = false;
5177                 sb_data_p = (u32 *)&sb_data_e2;
5178                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5179         } else {
5180                 memset(&sb_data_e1x, 0,
5181                        sizeof(struct hc_status_block_data_e1x));
5182                 sb_data_e1x.common.state = SB_DISABLED;
5183                 sb_data_e1x.common.p_func.vf_valid = false;
5184                 sb_data_p = (u32 *)&sb_data_e1x;
5185                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5186         }
5187         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5188
5189         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5190                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5191                         CSTORM_STATUS_BLOCK_SIZE);
5192         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5193                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5194                         CSTORM_SYNC_BLOCK_SIZE);
5195 }
5196
5197 /* helper:  writes SP SB data to FW */
5198 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5199                 struct hc_sp_status_block_data *sp_sb_data)
5200 {
5201         int func = BP_FUNC(bp);
5202         int i;
5203         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5204                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5205                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5206                         i*sizeof(u32),
5207                         *((u32 *)sp_sb_data + i));
5208 }
5209
5210 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5211 {
5212         int func = BP_FUNC(bp);
5213         struct hc_sp_status_block_data sp_sb_data;
5214         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5215
5216         sp_sb_data.state = SB_DISABLED;
5217         sp_sb_data.p_func.vf_valid = false;
5218
5219         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5220
5221         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5222                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5223                         CSTORM_SP_STATUS_BLOCK_SIZE);
5224         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5225                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5226                         CSTORM_SP_SYNC_BLOCK_SIZE);
5227
5228 }
5229
5230
5231 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5232                                            int igu_sb_id, int igu_seg_id)
5233 {
5234         hc_sm->igu_sb_id = igu_sb_id;
5235         hc_sm->igu_seg_id = igu_seg_id;
5236         hc_sm->timer_value = 0xFF;
5237         hc_sm->time_to_expire = 0xFFFFFFFF;
5238 }
5239
5240
5241 /* allocates state machine ids. */
5242 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5243 {
5244         /* zero out state machine indices */
5245         /* rx indices */
5246         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5247
5248         /* tx indices */
5249         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5250         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5251         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5252         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5253
5254         /* map indices */
5255         /* rx indices */
5256         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5257                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5258
5259         /* tx indices */
5260         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5261                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5262         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5263                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5264         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5265                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5266         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5267                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5268 }
5269
5270 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5271                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5272 {
5273         int igu_seg_id;
5274
5275         struct hc_status_block_data_e2 sb_data_e2;
5276         struct hc_status_block_data_e1x sb_data_e1x;
5277         struct hc_status_block_sm  *hc_sm_p;
5278         int data_size;
5279         u32 *sb_data_p;
5280
5281         if (CHIP_INT_MODE_IS_BC(bp))
5282                 igu_seg_id = HC_SEG_ACCESS_NORM;
5283         else
5284                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5285
5286         bnx2x_zero_fp_sb(bp, fw_sb_id);
5287
5288         if (!CHIP_IS_E1x(bp)) {
5289                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5290                 sb_data_e2.common.state = SB_ENABLED;
5291                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5292                 sb_data_e2.common.p_func.vf_id = vfid;
5293                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5294                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5295                 sb_data_e2.common.same_igu_sb_1b = true;
5296                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5297                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5298                 hc_sm_p = sb_data_e2.common.state_machine;
5299                 sb_data_p = (u32 *)&sb_data_e2;
5300                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5301                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5302         } else {
5303                 memset(&sb_data_e1x, 0,
5304                        sizeof(struct hc_status_block_data_e1x));
5305                 sb_data_e1x.common.state = SB_ENABLED;
5306                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5307                 sb_data_e1x.common.p_func.vf_id = 0xff;
5308                 sb_data_e1x.common.p_func.vf_valid = false;
5309                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5310                 sb_data_e1x.common.same_igu_sb_1b = true;
5311                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5312                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5313                 hc_sm_p = sb_data_e1x.common.state_machine;
5314                 sb_data_p = (u32 *)&sb_data_e1x;
5315                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5316                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5317         }
5318
5319         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5320                                        igu_sb_id, igu_seg_id);
5321         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5322                                        igu_sb_id, igu_seg_id);
5323
5324         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5325
5326         /* write indecies to HW */
5327         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5328 }
5329
5330 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5331                                      u16 tx_usec, u16 rx_usec)
5332 {
5333         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5334                                     false, rx_usec);
5335         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5336                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5337                                        tx_usec);
5338         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5339                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5340                                        tx_usec);
5341         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5342                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5343                                        tx_usec);
5344 }
5345
5346 static void bnx2x_init_def_sb(struct bnx2x *bp)
5347 {
5348         struct host_sp_status_block *def_sb = bp->def_status_blk;
5349         dma_addr_t mapping = bp->def_status_blk_mapping;
5350         int igu_sp_sb_index;
5351         int igu_seg_id;
5352         int port = BP_PORT(bp);
5353         int func = BP_FUNC(bp);
5354         int reg_offset, reg_offset_en5;
5355         u64 section;
5356         int index;
5357         struct hc_sp_status_block_data sp_sb_data;
5358         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5359
5360         if (CHIP_INT_MODE_IS_BC(bp)) {
5361                 igu_sp_sb_index = DEF_SB_IGU_ID;
5362                 igu_seg_id = HC_SEG_ACCESS_DEF;
5363         } else {
5364                 igu_sp_sb_index = bp->igu_dsb_id;
5365                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5366         }
5367
5368         /* ATTN */
5369         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5370                                             atten_status_block);
5371         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5372
5373         bp->attn_state = 0;
5374
5375         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5376                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5377         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5378                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5379         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5380                 int sindex;
5381                 /* take care of sig[0]..sig[4] */
5382                 for (sindex = 0; sindex < 4; sindex++)
5383                         bp->attn_group[index].sig[sindex] =
5384                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5385
5386                 if (!CHIP_IS_E1x(bp))
5387                         /*
5388                          * enable5 is separate from the rest of the registers,
5389                          * and therefore the address skip is 4
5390                          * and not 16 between the different groups
5391                          */
5392                         bp->attn_group[index].sig[4] = REG_RD(bp,
5393                                         reg_offset_en5 + 0x4*index);
5394                 else
5395                         bp->attn_group[index].sig[4] = 0;
5396         }
5397
5398         if (bp->common.int_block == INT_BLOCK_HC) {
5399                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5400                                      HC_REG_ATTN_MSG0_ADDR_L);
5401
5402                 REG_WR(bp, reg_offset, U64_LO(section));
5403                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5404         } else if (!CHIP_IS_E1x(bp)) {
5405                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5406                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5407         }
5408
5409         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5410                                             sp_sb);
5411
5412         bnx2x_zero_sp_sb(bp);
5413
5414         sp_sb_data.state                = SB_ENABLED;
5415         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5416         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5417         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5418         sp_sb_data.igu_seg_id           = igu_seg_id;
5419         sp_sb_data.p_func.pf_id         = func;
5420         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5421         sp_sb_data.p_func.vf_id         = 0xff;
5422
5423         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5424
5425         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5426 }
5427
5428 void bnx2x_update_coalesce(struct bnx2x *bp)
5429 {
5430         int i;
5431
5432         for_each_eth_queue(bp, i)
5433                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5434                                          bp->tx_ticks, bp->rx_ticks);
5435 }
5436
5437 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5438 {
5439         spin_lock_init(&bp->spq_lock);
5440         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5441
5442         bp->spq_prod_idx = 0;
5443         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5444         bp->spq_prod_bd = bp->spq;
5445         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5446 }
5447
5448 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5449 {
5450         int i;
5451         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5452                 union event_ring_elem *elem =
5453                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5454
5455                 elem->next_page.addr.hi =
5456                         cpu_to_le32(U64_HI(bp->eq_mapping +
5457                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5458                 elem->next_page.addr.lo =
5459                         cpu_to_le32(U64_LO(bp->eq_mapping +
5460                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5461         }
5462         bp->eq_cons = 0;
5463         bp->eq_prod = NUM_EQ_DESC;
5464         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5465         /* we want a warning message before it gets rought... */
5466         atomic_set(&bp->eq_spq_left,
5467                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5468 }
5469
5470
5471 /* called with netif_addr_lock_bh() */
5472 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5473                          unsigned long rx_mode_flags,
5474                          unsigned long rx_accept_flags,
5475                          unsigned long tx_accept_flags,
5476                          unsigned long ramrod_flags)
5477 {
5478         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5479         int rc;
5480
5481         memset(&ramrod_param, 0, sizeof(ramrod_param));
5482
5483         /* Prepare ramrod parameters */
5484         ramrod_param.cid = 0;
5485         ramrod_param.cl_id = cl_id;
5486         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5487         ramrod_param.func_id = BP_FUNC(bp);
5488
5489         ramrod_param.pstate = &bp->sp_state;
5490         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5491
5492         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5493         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5494
5495         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5496
5497         ramrod_param.ramrod_flags = ramrod_flags;
5498         ramrod_param.rx_mode_flags = rx_mode_flags;
5499
5500         ramrod_param.rx_accept_flags = rx_accept_flags;
5501         ramrod_param.tx_accept_flags = tx_accept_flags;
5502
5503         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5504         if (rc < 0) {
5505                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5506                 return;
5507         }
5508 }
5509
5510 /* called with netif_addr_lock_bh() */
5511 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5512 {
5513         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5514         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5515
5516         if (!NO_FCOE(bp))
5517
5518                 /* Configure rx_mode of FCoE Queue */
5519                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5520
5521         switch (bp->rx_mode) {
5522         case BNX2X_RX_MODE_NONE:
5523                 /*
5524                  * 'drop all' supersedes any accept flags that may have been
5525                  * passed to the function.
5526                  */
5527                 break;
5528         case BNX2X_RX_MODE_NORMAL:
5529                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5530                 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5531                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5532
5533                 /* internal switching mode */
5534                 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5535                 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5536                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5537
5538                 break;
5539         case BNX2X_RX_MODE_ALLMULTI:
5540                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5541                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5542                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5543
5544                 /* internal switching mode */
5545                 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5546                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5547                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5548
5549                 break;
5550         case BNX2X_RX_MODE_PROMISC:
5551                 /* According to deffinition of SI mode, iface in promisc mode
5552                  * should receive matched and unmatched (in resolution of port)
5553                  * unicast packets.
5554                  */
5555                 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5556                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5557                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5558                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5559
5560                 /* internal switching mode */
5561                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5562                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5563
5564                 if (IS_MF_SI(bp))
5565                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5566                 else
5567                         __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5568
5569                 break;
5570         default:
5571                 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5572                 return;
5573         }
5574
5575         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5576                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5577                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5578         }
5579
5580         __set_bit(RAMROD_RX, &ramrod_flags);
5581         __set_bit(RAMROD_TX, &ramrod_flags);
5582
5583         bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5584                             tx_accept_flags, ramrod_flags);
5585 }
5586
5587 static void bnx2x_init_internal_common(struct bnx2x *bp)
5588 {
5589         int i;
5590
5591         if (IS_MF_SI(bp))
5592                 /*
5593                  * In switch independent mode, the TSTORM needs to accept
5594                  * packets that failed classification, since approximate match
5595                  * mac addresses aren't written to NIG LLH
5596                  */
5597                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5598                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5599         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5600                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5601                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5602
5603         /* Zero this manually as its initialization is
5604            currently missing in the initTool */
5605         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5606                 REG_WR(bp, BAR_USTRORM_INTMEM +
5607                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5608         if (!CHIP_IS_E1x(bp)) {
5609                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5610                         CHIP_INT_MODE_IS_BC(bp) ?
5611                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5612         }
5613 }
5614
5615 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5616 {
5617         switch (load_code) {
5618         case FW_MSG_CODE_DRV_LOAD_COMMON:
5619         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5620                 bnx2x_init_internal_common(bp);
5621                 /* no break */
5622
5623         case FW_MSG_CODE_DRV_LOAD_PORT:
5624                 /* nothing to do */
5625                 /* no break */
5626
5627         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5628                 /* internal memory per function is
5629                    initialized inside bnx2x_pf_init */
5630                 break;
5631
5632         default:
5633                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5634                 break;
5635         }
5636 }
5637
5638 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5639 {
5640         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5641 }
5642
5643 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5644 {
5645         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5646 }
5647
5648 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5649 {
5650         if (CHIP_IS_E1x(fp->bp))
5651                 return BP_L_ID(fp->bp) + fp->index;
5652         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
5653                 return bnx2x_fp_igu_sb_id(fp);
5654 }
5655
5656 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5657 {
5658         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5659         u8 cos;
5660         unsigned long q_type = 0;
5661         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5662         fp->rx_queue = fp_idx;
5663         fp->cid = fp_idx;
5664         fp->cl_id = bnx2x_fp_cl_id(fp);
5665         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5666         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5667         /* qZone id equals to FW (per path) client id */
5668         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
5669
5670         /* init shortcut */
5671         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5672
5673         /* Setup SB indicies */
5674         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5675
5676         /* Configure Queue State object */
5677         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5678         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5679
5680         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5681
5682         /* init tx data */
5683         for_each_cos_in_tx_queue(fp, cos) {
5684                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5685                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5686                                   FP_COS_TO_TXQ(fp, cos, bp),
5687                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
5688                 cids[cos] = fp->txdata_ptr[cos]->cid;
5689         }
5690
5691         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5692                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5693                              bnx2x_sp_mapping(bp, q_rdata), q_type);
5694
5695         /**
5696          * Configure classification DBs: Always enable Tx switching
5697          */
5698         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5699
5700         DP(NETIF_MSG_IFUP, "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
5701                    fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5702                    fp->igu_sb_id);
5703         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5704                       fp->fw_sb_id, fp->igu_sb_id);
5705
5706         bnx2x_update_fpsb_idx(fp);
5707 }
5708
5709 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5710 {
5711         int i;
5712
5713         for (i = 1; i <= NUM_TX_RINGS; i++) {
5714                 struct eth_tx_next_bd *tx_next_bd =
5715                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5716
5717                 tx_next_bd->addr_hi =
5718                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5719                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5720                 tx_next_bd->addr_lo =
5721                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5722                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5723         }
5724
5725         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5726         txdata->tx_db.data.zero_fill1 = 0;
5727         txdata->tx_db.data.prod = 0;
5728
5729         txdata->tx_pkt_prod = 0;
5730         txdata->tx_pkt_cons = 0;
5731         txdata->tx_bd_prod = 0;
5732         txdata->tx_bd_cons = 0;
5733         txdata->tx_pkt = 0;
5734 }
5735
5736 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5737 {
5738         int i;
5739
5740         for_each_tx_queue_cnic(bp, i)
5741                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5742 }
5743 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5744 {
5745         int i;
5746         u8 cos;
5747
5748         for_each_eth_queue(bp, i)
5749                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5750                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5751 }
5752
5753 void bnx2x_nic_init_cnic(struct bnx2x *bp)
5754 {
5755         if (!NO_FCOE(bp))
5756                 bnx2x_init_fcoe_fp(bp);
5757
5758         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5759                       BNX2X_VF_ID_INVALID, false,
5760                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5761
5762         /* ensure status block indices were read */
5763         rmb();
5764         bnx2x_init_rx_rings_cnic(bp);
5765         bnx2x_init_tx_rings_cnic(bp);
5766
5767         /* flush all */
5768         mb();
5769         mmiowb();
5770 }
5771
5772 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5773 {
5774         int i;
5775
5776         for_each_eth_queue(bp, i)
5777                 bnx2x_init_eth_fp(bp, i);
5778         /* Initialize MOD_ABS interrupts */
5779         bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5780                                bp->common.shmem_base, bp->common.shmem2_base,
5781                                BP_PORT(bp));
5782         /* ensure status block indices were read */
5783         rmb();
5784
5785         bnx2x_init_def_sb(bp);
5786         bnx2x_update_dsb_idx(bp);
5787         bnx2x_init_rx_rings(bp);
5788         bnx2x_init_tx_rings(bp);
5789         bnx2x_init_sp_ring(bp);
5790         bnx2x_init_eq_ring(bp);
5791         bnx2x_init_internal(bp, load_code);
5792         bnx2x_pf_init(bp);
5793         bnx2x_stats_init(bp);
5794
5795         /* flush all before enabling interrupts */
5796         mb();
5797         mmiowb();
5798
5799         bnx2x_int_enable(bp);
5800
5801         /* Check for SPIO5 */
5802         bnx2x_attn_int_deasserted0(bp,
5803                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5804                                    AEU_INPUTS_ATTN_BITS_SPIO5);
5805 }
5806
5807 /* end of nic init */
5808
5809 /*
5810  * gzip service functions
5811  */
5812
5813 static int bnx2x_gunzip_init(struct bnx2x *bp)
5814 {
5815         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5816                                             &bp->gunzip_mapping, GFP_KERNEL);
5817         if (bp->gunzip_buf  == NULL)
5818                 goto gunzip_nomem1;
5819
5820         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5821         if (bp->strm  == NULL)
5822                 goto gunzip_nomem2;
5823
5824         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5825         if (bp->strm->workspace == NULL)
5826                 goto gunzip_nomem3;
5827
5828         return 0;
5829
5830 gunzip_nomem3:
5831         kfree(bp->strm);
5832         bp->strm = NULL;
5833
5834 gunzip_nomem2:
5835         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5836                           bp->gunzip_mapping);
5837         bp->gunzip_buf = NULL;
5838
5839 gunzip_nomem1:
5840         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5841         return -ENOMEM;
5842 }
5843
5844 static void bnx2x_gunzip_end(struct bnx2x *bp)
5845 {
5846         if (bp->strm) {
5847                 vfree(bp->strm->workspace);
5848                 kfree(bp->strm);
5849                 bp->strm = NULL;
5850         }
5851
5852         if (bp->gunzip_buf) {
5853                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5854                                   bp->gunzip_mapping);
5855                 bp->gunzip_buf = NULL;
5856         }
5857 }
5858
5859 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5860 {
5861         int n, rc;
5862
5863         /* check gzip header */
5864         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5865                 BNX2X_ERR("Bad gzip header\n");
5866                 return -EINVAL;
5867         }
5868
5869         n = 10;
5870
5871 #define FNAME                           0x8
5872
5873         if (zbuf[3] & FNAME)
5874                 while ((zbuf[n++] != 0) && (n < len));
5875
5876         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5877         bp->strm->avail_in = len - n;
5878         bp->strm->next_out = bp->gunzip_buf;
5879         bp->strm->avail_out = FW_BUF_SIZE;
5880
5881         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5882         if (rc != Z_OK)
5883                 return rc;
5884
5885         rc = zlib_inflate(bp->strm, Z_FINISH);
5886         if ((rc != Z_OK) && (rc != Z_STREAM_END))
5887                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5888                            bp->strm->msg);
5889
5890         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5891         if (bp->gunzip_outlen & 0x3)
5892                 netdev_err(bp->dev,
5893                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5894                                 bp->gunzip_outlen);
5895         bp->gunzip_outlen >>= 2;
5896
5897         zlib_inflateEnd(bp->strm);
5898
5899         if (rc == Z_STREAM_END)
5900                 return 0;
5901
5902         return rc;
5903 }
5904
5905 /* nic load/unload */
5906
5907 /*
5908  * General service functions
5909  */
5910
5911 /* send a NIG loopback debug packet */
5912 static void bnx2x_lb_pckt(struct bnx2x *bp)
5913 {
5914         u32 wb_write[3];
5915
5916         /* Ethernet source and destination addresses */
5917         wb_write[0] = 0x55555555;
5918         wb_write[1] = 0x55555555;
5919         wb_write[2] = 0x20;             /* SOP */
5920         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5921
5922         /* NON-IP protocol */
5923         wb_write[0] = 0x09000000;
5924         wb_write[1] = 0x55555555;
5925         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
5926         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5927 }
5928
5929 /* some of the internal memories
5930  * are not directly readable from the driver
5931  * to test them we send debug packets
5932  */
5933 static int bnx2x_int_mem_test(struct bnx2x *bp)
5934 {
5935         int factor;
5936         int count, i;
5937         u32 val = 0;
5938
5939         if (CHIP_REV_IS_FPGA(bp))
5940                 factor = 120;
5941         else if (CHIP_REV_IS_EMUL(bp))
5942                 factor = 200;
5943         else
5944                 factor = 1;
5945
5946         /* Disable inputs of parser neighbor blocks */
5947         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5948         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5949         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5950         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5951
5952         /*  Write 0 to parser credits for CFC search request */
5953         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5954
5955         /* send Ethernet packet */
5956         bnx2x_lb_pckt(bp);
5957
5958         /* TODO do i reset NIG statistic? */
5959         /* Wait until NIG register shows 1 packet of size 0x10 */
5960         count = 1000 * factor;
5961         while (count) {
5962
5963                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5964                 val = *bnx2x_sp(bp, wb_data[0]);
5965                 if (val == 0x10)
5966                         break;
5967
5968                 msleep(10);
5969                 count--;
5970         }
5971         if (val != 0x10) {
5972                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5973                 return -1;
5974         }
5975
5976         /* Wait until PRS register shows 1 packet */
5977         count = 1000 * factor;
5978         while (count) {
5979                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5980                 if (val == 1)
5981                         break;
5982
5983                 msleep(10);
5984                 count--;
5985         }
5986         if (val != 0x1) {
5987                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5988                 return -2;
5989         }
5990
5991         /* Reset and init BRB, PRS */
5992         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5993         msleep(50);
5994         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5995         msleep(50);
5996         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5997         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5998
5999         DP(NETIF_MSG_HW, "part2\n");
6000
6001         /* Disable inputs of parser neighbor blocks */
6002         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6003         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6004         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6005         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6006
6007         /* Write 0 to parser credits for CFC search request */
6008         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6009
6010         /* send 10 Ethernet packets */
6011         for (i = 0; i < 10; i++)
6012                 bnx2x_lb_pckt(bp);
6013
6014         /* Wait until NIG register shows 10 + 1
6015            packets of size 11*0x10 = 0xb0 */
6016         count = 1000 * factor;
6017         while (count) {
6018
6019                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6020                 val = *bnx2x_sp(bp, wb_data[0]);
6021                 if (val == 0xb0)
6022                         break;
6023
6024                 msleep(10);
6025                 count--;
6026         }
6027         if (val != 0xb0) {
6028                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6029                 return -3;
6030         }
6031
6032         /* Wait until PRS register shows 2 packets */
6033         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6034         if (val != 2)
6035                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6036
6037         /* Write 1 to parser credits for CFC search request */
6038         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6039
6040         /* Wait until PRS register shows 3 packets */
6041         msleep(10 * factor);
6042         /* Wait until NIG register shows 1 packet of size 0x10 */
6043         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6044         if (val != 3)
6045                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6046
6047         /* clear NIG EOP FIFO */
6048         for (i = 0; i < 11; i++)
6049                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6050         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6051         if (val != 1) {
6052                 BNX2X_ERR("clear of NIG failed\n");
6053                 return -4;
6054         }
6055
6056         /* Reset and init BRB, PRS, NIG */
6057         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6058         msleep(50);
6059         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6060         msleep(50);
6061         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6062         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6063         if (!CNIC_SUPPORT(bp))
6064                 /* set NIC mode */
6065                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6066
6067         /* Enable inputs of parser neighbor blocks */
6068         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6069         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6070         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6071         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6072
6073         DP(NETIF_MSG_HW, "done\n");
6074
6075         return 0; /* OK */
6076 }
6077
6078 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6079 {
6080         u32 val;
6081
6082         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6083         if (!CHIP_IS_E1x(bp))
6084                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6085         else
6086                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6087         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6088         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6089         /*
6090          * mask read length error interrupts in brb for parser
6091          * (parsing unit and 'checksum and crc' unit)
6092          * these errors are legal (PU reads fixed length and CAC can cause
6093          * read length error on truncated packets)
6094          */
6095         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6096         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6097         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6098         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6099         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6100         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6101 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6102 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6103         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6104         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6105         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6106 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6107 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6108         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6109         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6110         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6111         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6112 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6113 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6114
6115         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6116                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6117                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6118         if (!CHIP_IS_E1x(bp))
6119                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6120                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6121         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6122
6123         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6124         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6125         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6126 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6127
6128         if (!CHIP_IS_E1x(bp))
6129                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6130                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6131
6132         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6133         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6134 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6135         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6136 }
6137
6138 static void bnx2x_reset_common(struct bnx2x *bp)
6139 {
6140         u32 val = 0x1400;
6141
6142         /* reset_common */
6143         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6144                0xd3ffff7f);
6145
6146         if (CHIP_IS_E3(bp)) {
6147                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6148                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6149         }
6150
6151         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6152 }
6153
6154 static void bnx2x_setup_dmae(struct bnx2x *bp)
6155 {
6156         bp->dmae_ready = 0;
6157         spin_lock_init(&bp->dmae_lock);
6158 }
6159
6160 static void bnx2x_init_pxp(struct bnx2x *bp)
6161 {
6162         u16 devctl;
6163         int r_order, w_order;
6164
6165         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6166         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6167         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6168         if (bp->mrrs == -1)
6169                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6170         else {
6171                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6172                 r_order = bp->mrrs;
6173         }
6174
6175         bnx2x_init_pxp_arb(bp, r_order, w_order);
6176 }
6177
6178 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6179 {
6180         int is_required;
6181         u32 val;
6182         int port;
6183
6184         if (BP_NOMCP(bp))
6185                 return;
6186
6187         is_required = 0;
6188         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6189               SHARED_HW_CFG_FAN_FAILURE_MASK;
6190
6191         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6192                 is_required = 1;
6193
6194         /*
6195          * The fan failure mechanism is usually related to the PHY type since
6196          * the power consumption of the board is affected by the PHY. Currently,
6197          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6198          */
6199         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6200                 for (port = PORT_0; port < PORT_MAX; port++) {
6201                         is_required |=
6202                                 bnx2x_fan_failure_det_req(
6203                                         bp,
6204                                         bp->common.shmem_base,
6205                                         bp->common.shmem2_base,
6206                                         port);
6207                 }
6208
6209         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6210
6211         if (is_required == 0)
6212                 return;
6213
6214         /* Fan failure is indicated by SPIO 5 */
6215         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6216
6217         /* set to active low mode */
6218         val = REG_RD(bp, MISC_REG_SPIO_INT);
6219         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6220         REG_WR(bp, MISC_REG_SPIO_INT, val);
6221
6222         /* enable interrupt to signal the IGU */
6223         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6224         val |= MISC_SPIO_SPIO5;
6225         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6226 }
6227
6228 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6229 {
6230         u32 offset = 0;
6231
6232         if (CHIP_IS_E1(bp))
6233                 return;
6234         if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6235                 return;
6236
6237         switch (BP_ABS_FUNC(bp)) {
6238         case 0:
6239                 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6240                 break;
6241         case 1:
6242                 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6243                 break;
6244         case 2:
6245                 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6246                 break;
6247         case 3:
6248                 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6249                 break;
6250         case 4:
6251                 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6252                 break;
6253         case 5:
6254                 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6255                 break;
6256         case 6:
6257                 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6258                 break;
6259         case 7:
6260                 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6261                 break;
6262         default:
6263                 return;
6264         }
6265
6266         REG_WR(bp, offset, pretend_func_num);
6267         REG_RD(bp, offset);
6268         DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6269 }
6270
6271 void bnx2x_pf_disable(struct bnx2x *bp)
6272 {
6273         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6274         val &= ~IGU_PF_CONF_FUNC_EN;
6275
6276         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6277         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6278         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6279 }
6280
6281 static void bnx2x__common_init_phy(struct bnx2x *bp)
6282 {
6283         u32 shmem_base[2], shmem2_base[2];
6284         /* Avoid common init in case MFW supports LFA */
6285         if (SHMEM2_RD(bp, size) >
6286             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6287                 return;
6288         shmem_base[0] =  bp->common.shmem_base;
6289         shmem2_base[0] = bp->common.shmem2_base;
6290         if (!CHIP_IS_E1x(bp)) {
6291                 shmem_base[1] =
6292                         SHMEM2_RD(bp, other_shmem_base_addr);
6293                 shmem2_base[1] =
6294                         SHMEM2_RD(bp, other_shmem2_base_addr);
6295         }
6296         bnx2x_acquire_phy_lock(bp);
6297         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6298                               bp->common.chip_id);
6299         bnx2x_release_phy_lock(bp);
6300 }
6301
6302 /**
6303  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6304  *
6305  * @bp:         driver handle
6306  */
6307 static int bnx2x_init_hw_common(struct bnx2x *bp)
6308 {
6309         u32 val;
6310
6311         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6312
6313         /*
6314          * take the UNDI lock to protect undi_unload flow from accessing
6315          * registers while we're resetting the chip
6316          */
6317         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6318
6319         bnx2x_reset_common(bp);
6320         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6321
6322         val = 0xfffc;
6323         if (CHIP_IS_E3(bp)) {
6324                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6325                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6326         }
6327         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6328
6329         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6330
6331         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6332
6333         if (!CHIP_IS_E1x(bp)) {
6334                 u8 abs_func_id;
6335
6336                 /**
6337                  * 4-port mode or 2-port mode we need to turn of master-enable
6338                  * for everyone, after that, turn it back on for self.
6339                  * so, we disregard multi-function or not, and always disable
6340                  * for all functions on the given path, this means 0,2,4,6 for
6341                  * path 0 and 1,3,5,7 for path 1
6342                  */
6343                 for (abs_func_id = BP_PATH(bp);
6344                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6345                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6346                                 REG_WR(bp,
6347                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6348                                     1);
6349                                 continue;
6350                         }
6351
6352                         bnx2x_pretend_func(bp, abs_func_id);
6353                         /* clear pf enable */
6354                         bnx2x_pf_disable(bp);
6355                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6356                 }
6357         }
6358
6359         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6360         if (CHIP_IS_E1(bp)) {
6361                 /* enable HW interrupt from PXP on USDM overflow
6362                    bit 16 on INT_MASK_0 */
6363                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6364         }
6365
6366         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6367         bnx2x_init_pxp(bp);
6368
6369 #ifdef __BIG_ENDIAN
6370         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6371         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6372         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6373         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6374         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6375         /* make sure this value is 0 */
6376         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6377
6378 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6379         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6380         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6381         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6382         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6383 #endif
6384
6385         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6386
6387         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6388                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6389
6390         /* let the HW do it's magic ... */
6391         msleep(100);
6392         /* finish PXP init */
6393         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6394         if (val != 1) {
6395                 BNX2X_ERR("PXP2 CFG failed\n");
6396                 return -EBUSY;
6397         }
6398         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6399         if (val != 1) {
6400                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6401                 return -EBUSY;
6402         }
6403
6404         /* Timers bug workaround E2 only. We need to set the entire ILT to
6405          * have entries with value "0" and valid bit on.
6406          * This needs to be done by the first PF that is loaded in a path
6407          * (i.e. common phase)
6408          */
6409         if (!CHIP_IS_E1x(bp)) {
6410 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6411  * (i.e. vnic3) to start even if it is marked as "scan-off".
6412  * This occurs when a different function (func2,3) is being marked
6413  * as "scan-off". Real-life scenario for example: if a driver is being
6414  * load-unloaded while func6,7 are down. This will cause the timer to access
6415  * the ilt, translate to a logical address and send a request to read/write.
6416  * Since the ilt for the function that is down is not valid, this will cause
6417  * a translation error which is unrecoverable.
6418  * The Workaround is intended to make sure that when this happens nothing fatal
6419  * will occur. The workaround:
6420  *      1.  First PF driver which loads on a path will:
6421  *              a.  After taking the chip out of reset, by using pretend,
6422  *                  it will write "0" to the following registers of
6423  *                  the other vnics.
6424  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6425  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6426  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6427  *                  And for itself it will write '1' to
6428  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6429  *                  dmae-operations (writing to pram for example.)
6430  *                  note: can be done for only function 6,7 but cleaner this
6431  *                        way.
6432  *              b.  Write zero+valid to the entire ILT.
6433  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6434  *                  VNIC3 (of that port). The range allocated will be the
6435  *                  entire ILT. This is needed to prevent  ILT range error.
6436  *      2.  Any PF driver load flow:
6437  *              a.  ILT update with the physical addresses of the allocated
6438  *                  logical pages.
6439  *              b.  Wait 20msec. - note that this timeout is needed to make
6440  *                  sure there are no requests in one of the PXP internal
6441  *                  queues with "old" ILT addresses.
6442  *              c.  PF enable in the PGLC.
6443  *              d.  Clear the was_error of the PF in the PGLC. (could have
6444  *                  occured while driver was down)
6445  *              e.  PF enable in the CFC (WEAK + STRONG)
6446  *              f.  Timers scan enable
6447  *      3.  PF driver unload flow:
6448  *              a.  Clear the Timers scan_en.
6449  *              b.  Polling for scan_on=0 for that PF.
6450  *              c.  Clear the PF enable bit in the PXP.
6451  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6452  *              e.  Write zero+valid to all ILT entries (The valid bit must
6453  *                  stay set)
6454  *              f.  If this is VNIC 3 of a port then also init
6455  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6456  *                  to the last enrty in the ILT.
6457  *
6458  *      Notes:
6459  *      Currently the PF error in the PGLC is non recoverable.
6460  *      In the future the there will be a recovery routine for this error.
6461  *      Currently attention is masked.
6462  *      Having an MCP lock on the load/unload process does not guarantee that
6463  *      there is no Timer disable during Func6/7 enable. This is because the
6464  *      Timers scan is currently being cleared by the MCP on FLR.
6465  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6466  *      there is error before clearing it. But the flow above is simpler and
6467  *      more general.
6468  *      All ILT entries are written by zero+valid and not just PF6/7
6469  *      ILT entries since in the future the ILT entries allocation for
6470  *      PF-s might be dynamic.
6471  */
6472                 struct ilt_client_info ilt_cli;
6473                 struct bnx2x_ilt ilt;
6474                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6475                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6476
6477                 /* initialize dummy TM client */
6478                 ilt_cli.start = 0;
6479                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6480                 ilt_cli.client_num = ILT_CLIENT_TM;
6481
6482                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6483                  * Step 2: set the timers first/last ilt entry to point
6484                  * to the entire range to prevent ILT range error for 3rd/4th
6485                  * vnic (this code assumes existance of the vnic)
6486                  *
6487                  * both steps performed by call to bnx2x_ilt_client_init_op()
6488                  * with dummy TM client
6489                  *
6490                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6491                  * and his brother are split registers
6492                  */
6493                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6494                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6495                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6496
6497                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6498                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6499                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6500         }
6501
6502
6503         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6504         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6505
6506         if (!CHIP_IS_E1x(bp)) {
6507                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6508                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6509                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6510
6511                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6512
6513                 /* let the HW do it's magic ... */
6514                 do {
6515                         msleep(200);
6516                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6517                 } while (factor-- && (val != 1));
6518
6519                 if (val != 1) {
6520                         BNX2X_ERR("ATC_INIT failed\n");
6521                         return -EBUSY;
6522                 }
6523         }
6524
6525         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6526
6527         /* clean the DMAE memory */
6528         bp->dmae_ready = 1;
6529         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6530
6531         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6532
6533         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6534
6535         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6536
6537         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6538
6539         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6540         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6541         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6542         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6543
6544         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6545
6546
6547         /* QM queues pointers table */
6548         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6549
6550         /* soft reset pulse */
6551         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6552         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6553
6554         if (CNIC_SUPPORT(bp))
6555                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6556
6557         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6558         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6559         if (!CHIP_REV_IS_SLOW(bp))
6560                 /* enable hw interrupt from doorbell Q */
6561                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6562
6563         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6564
6565         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6566         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6567
6568         if (!CHIP_IS_E1(bp))
6569                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6570
6571         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6572                 if (IS_MF_AFEX(bp)) {
6573                         /* configure that VNTag and VLAN headers must be
6574                          * received in afex mode
6575                          */
6576                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6577                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6578                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6579                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6580                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6581                 } else {
6582                         /* Bit-map indicating which L2 hdrs may appear
6583                          * after the basic Ethernet header
6584                          */
6585                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6586                                bp->path_has_ovlan ? 7 : 6);
6587                 }
6588         }
6589
6590         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6591         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6592         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6593         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6594
6595         if (!CHIP_IS_E1x(bp)) {
6596                 /* reset VFC memories */
6597                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6598                            VFC_MEMORIES_RST_REG_CAM_RST |
6599                            VFC_MEMORIES_RST_REG_RAM_RST);
6600                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6601                            VFC_MEMORIES_RST_REG_CAM_RST |
6602                            VFC_MEMORIES_RST_REG_RAM_RST);
6603
6604                 msleep(20);
6605         }
6606
6607         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6608         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6609         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6610         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6611
6612         /* sync semi rtc */
6613         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6614                0x80000000);
6615         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6616                0x80000000);
6617
6618         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6619         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6620         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6621
6622         if (!CHIP_IS_E1x(bp)) {
6623                 if (IS_MF_AFEX(bp)) {
6624                         /* configure that VNTag and VLAN headers must be
6625                          * sent in afex mode
6626                          */
6627                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6628                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6629                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6630                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6631                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6632                 } else {
6633                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6634                                bp->path_has_ovlan ? 7 : 6);
6635                 }
6636         }
6637
6638         REG_WR(bp, SRC_REG_SOFT_RST, 1);
6639
6640         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6641
6642         if (CNIC_SUPPORT(bp)) {
6643                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6644                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6645                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6646                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6647                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6648                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6649                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6650                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6651                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6652                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6653         }
6654         REG_WR(bp, SRC_REG_SOFT_RST, 0);
6655
6656         if (sizeof(union cdu_context) != 1024)
6657                 /* we currently assume that a context is 1024 bytes */
6658                 dev_alert(&bp->pdev->dev,
6659                           "please adjust the size of cdu_context(%ld)\n",
6660                           (long)sizeof(union cdu_context));
6661
6662         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6663         val = (4 << 24) + (0 << 12) + 1024;
6664         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6665
6666         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6667         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6668         /* enable context validation interrupt from CFC */
6669         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6670
6671         /* set the thresholds to prevent CFC/CDU race */
6672         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6673
6674         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6675
6676         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6677                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6678
6679         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6680         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6681
6682         /* Reset PCIE errors for debug */
6683         REG_WR(bp, 0x2814, 0xffffffff);
6684         REG_WR(bp, 0x3820, 0xffffffff);
6685
6686         if (!CHIP_IS_E1x(bp)) {
6687                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6688                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6689                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6690                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6691                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6692                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6693                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6694                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6695                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6696                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6697                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6698         }
6699
6700         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6701         if (!CHIP_IS_E1(bp)) {
6702                 /* in E3 this done in per-port section */
6703                 if (!CHIP_IS_E3(bp))
6704                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6705         }
6706         if (CHIP_IS_E1H(bp))
6707                 /* not applicable for E2 (and above ...) */
6708                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6709
6710         if (CHIP_REV_IS_SLOW(bp))
6711                 msleep(200);
6712
6713         /* finish CFC init */
6714         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6715         if (val != 1) {
6716                 BNX2X_ERR("CFC LL_INIT failed\n");
6717                 return -EBUSY;
6718         }
6719         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6720         if (val != 1) {
6721                 BNX2X_ERR("CFC AC_INIT failed\n");
6722                 return -EBUSY;
6723         }
6724         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6725         if (val != 1) {
6726                 BNX2X_ERR("CFC CAM_INIT failed\n");
6727                 return -EBUSY;
6728         }
6729         REG_WR(bp, CFC_REG_DEBUG0, 0);
6730
6731         if (CHIP_IS_E1(bp)) {
6732                 /* read NIG statistic
6733                    to see if this is our first up since powerup */
6734                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6735                 val = *bnx2x_sp(bp, wb_data[0]);
6736
6737                 /* do internal memory self test */
6738                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6739                         BNX2X_ERR("internal mem self test failed\n");
6740                         return -EBUSY;
6741                 }
6742         }
6743
6744         bnx2x_setup_fan_failure_detection(bp);
6745
6746         /* clear PXP2 attentions */
6747         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6748
6749         bnx2x_enable_blocks_attention(bp);
6750         bnx2x_enable_blocks_parity(bp);
6751
6752         if (!BP_NOMCP(bp)) {
6753                 if (CHIP_IS_E1x(bp))
6754                         bnx2x__common_init_phy(bp);
6755         } else
6756                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6757
6758         return 0;
6759 }
6760
6761 /**
6762  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6763  *
6764  * @bp:         driver handle
6765  */
6766 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6767 {
6768         int rc = bnx2x_init_hw_common(bp);
6769
6770         if (rc)
6771                 return rc;
6772
6773         /* In E2 2-PORT mode, same ext phy is used for the two paths */
6774         if (!BP_NOMCP(bp))
6775                 bnx2x__common_init_phy(bp);
6776
6777         return 0;
6778 }
6779
6780 static int bnx2x_init_hw_port(struct bnx2x *bp)
6781 {
6782         int port = BP_PORT(bp);
6783         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6784         u32 low, high;
6785         u32 val;
6786
6787
6788         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
6789
6790         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6791
6792         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6793         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6794         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6795
6796         /* Timers bug workaround: disables the pf_master bit in pglue at
6797          * common phase, we need to enable it here before any dmae access are
6798          * attempted. Therefore we manually added the enable-master to the
6799          * port phase (it also happens in the function phase)
6800          */
6801         if (!CHIP_IS_E1x(bp))
6802                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6803
6804         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6805         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6806         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6807         bnx2x_init_block(bp, BLOCK_QM, init_phase);
6808
6809         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6810         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6811         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6812         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6813
6814         /* QM cid (connection) count */
6815         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6816
6817         if (CNIC_SUPPORT(bp)) {
6818                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6819                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6820                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6821         }
6822
6823         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6824
6825         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6826
6827         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6828
6829                 if (IS_MF(bp))
6830                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6831                 else if (bp->dev->mtu > 4096) {
6832                         if (bp->flags & ONE_PORT_FLAG)
6833                                 low = 160;
6834                         else {
6835                                 val = bp->dev->mtu;
6836                                 /* (24*1024 + val*4)/256 */
6837                                 low = 96 + (val/64) +
6838                                                 ((val % 64) ? 1 : 0);
6839                         }
6840                 } else
6841                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6842                 high = low + 56;        /* 14*1024/256 */
6843                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6844                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6845         }
6846
6847         if (CHIP_MODE_IS_4_PORT(bp))
6848                 REG_WR(bp, (BP_PORT(bp) ?
6849                             BRB1_REG_MAC_GUARANTIED_1 :
6850                             BRB1_REG_MAC_GUARANTIED_0), 40);
6851
6852
6853         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6854         if (CHIP_IS_E3B0(bp)) {
6855                 if (IS_MF_AFEX(bp)) {
6856                         /* configure headers for AFEX mode */
6857                         REG_WR(bp, BP_PORT(bp) ?
6858                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6859                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6860                         REG_WR(bp, BP_PORT(bp) ?
6861                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6862                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6863                         REG_WR(bp, BP_PORT(bp) ?
6864                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6865                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6866                 } else {
6867                         /* Ovlan exists only if we are in multi-function +
6868                          * switch-dependent mode, in switch-independent there
6869                          * is no ovlan headers
6870                          */
6871                         REG_WR(bp, BP_PORT(bp) ?
6872                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6873                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6874                                (bp->path_has_ovlan ? 7 : 6));
6875                 }
6876         }
6877
6878         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6879         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6880         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6881         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6882
6883         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6884         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6885         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6886         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6887
6888         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6889         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6890
6891         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6892
6893         if (CHIP_IS_E1x(bp)) {
6894                 /* configure PBF to work without PAUSE mtu 9000 */
6895                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6896
6897                 /* update threshold */
6898                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6899                 /* update init credit */
6900                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6901
6902                 /* probe changes */
6903                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6904                 udelay(50);
6905                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6906         }
6907
6908         if (CNIC_SUPPORT(bp))
6909                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6910
6911         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6912         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6913
6914         if (CHIP_IS_E1(bp)) {
6915                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6916                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6917         }
6918         bnx2x_init_block(bp, BLOCK_HC, init_phase);
6919
6920         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6921
6922         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6923         /* init aeu_mask_attn_func_0/1:
6924          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6925          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6926          *             bits 4-7 are used for "per vn group attention" */
6927         val = IS_MF(bp) ? 0xF7 : 0x7;
6928         /* Enable DCBX attention for all but E1 */
6929         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6930         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6931
6932         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6933
6934         if (!CHIP_IS_E1x(bp)) {
6935                 /* Bit-map indicating which L2 hdrs may appear after the
6936                  * basic Ethernet header
6937                  */
6938                 if (IS_MF_AFEX(bp))
6939                         REG_WR(bp, BP_PORT(bp) ?
6940                                NIG_REG_P1_HDRS_AFTER_BASIC :
6941                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6942                 else
6943                         REG_WR(bp, BP_PORT(bp) ?
6944                                NIG_REG_P1_HDRS_AFTER_BASIC :
6945                                NIG_REG_P0_HDRS_AFTER_BASIC,
6946                                IS_MF_SD(bp) ? 7 : 6);
6947
6948                 if (CHIP_IS_E3(bp))
6949                         REG_WR(bp, BP_PORT(bp) ?
6950                                    NIG_REG_LLH1_MF_MODE :
6951                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
6952         }
6953         if (!CHIP_IS_E3(bp))
6954                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6955
6956         if (!CHIP_IS_E1(bp)) {
6957                 /* 0x2 disable mf_ov, 0x1 enable */
6958                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6959                        (IS_MF_SD(bp) ? 0x1 : 0x2));
6960
6961                 if (!CHIP_IS_E1x(bp)) {
6962                         val = 0;
6963                         switch (bp->mf_mode) {
6964                         case MULTI_FUNCTION_SD:
6965                                 val = 1;
6966                                 break;
6967                         case MULTI_FUNCTION_SI:
6968                         case MULTI_FUNCTION_AFEX:
6969                                 val = 2;
6970                                 break;
6971                         }
6972
6973                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6974                                                   NIG_REG_LLH0_CLS_TYPE), val);
6975                 }
6976                 {
6977                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6978                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6979                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6980                 }
6981         }
6982
6983
6984         /* If SPIO5 is set to generate interrupts, enable it for this port */
6985         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6986         if (val & MISC_SPIO_SPIO5) {
6987                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6988                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6989                 val = REG_RD(bp, reg_addr);
6990                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6991                 REG_WR(bp, reg_addr, val);
6992         }
6993
6994         return 0;
6995 }
6996
6997 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6998 {
6999         int reg;
7000         u32 wb_write[2];
7001
7002         if (CHIP_IS_E1(bp))
7003                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7004         else
7005                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7006
7007         wb_write[0] = ONCHIP_ADDR1(addr);
7008         wb_write[1] = ONCHIP_ADDR2(addr);
7009         REG_WR_DMAE(bp, reg, wb_write, 2);
7010 }
7011
7012 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
7013                                    u8 idu_sb_id, bool is_Pf)
7014 {
7015         u32 data, ctl, cnt = 100;
7016         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7017         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7018         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7019         u32 sb_bit =  1 << (idu_sb_id%32);
7020         u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7021         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7022
7023         /* Not supported in BC mode */
7024         if (CHIP_INT_MODE_IS_BC(bp))
7025                 return;
7026
7027         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7028                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7029                 IGU_REGULAR_CLEANUP_SET                         |
7030                 IGU_REGULAR_BCLEANUP;
7031
7032         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7033               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7034               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7035
7036         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7037                          data, igu_addr_data);
7038         REG_WR(bp, igu_addr_data, data);
7039         mmiowb();
7040         barrier();
7041         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7042                           ctl, igu_addr_ctl);
7043         REG_WR(bp, igu_addr_ctl, ctl);
7044         mmiowb();
7045         barrier();
7046
7047         /* wait for clean up to finish */
7048         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7049                 msleep(20);
7050
7051
7052         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7053                 DP(NETIF_MSG_HW,
7054                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7055                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7056         }
7057 }
7058
7059 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7060 {
7061         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7062 }
7063
7064 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7065 {
7066         u32 i, base = FUNC_ILT_BASE(func);
7067         for (i = base; i < base + ILT_PER_FUNC; i++)
7068                 bnx2x_ilt_wr(bp, i, 0);
7069 }
7070
7071
7072 static void bnx2x_init_searcher(struct bnx2x *bp)
7073 {
7074         int port = BP_PORT(bp);
7075         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7076         /* T1 hash bits value determines the T1 number of entries */
7077         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7078 }
7079
7080 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7081 {
7082         int rc;
7083         struct bnx2x_func_state_params func_params = {NULL};
7084         struct bnx2x_func_switch_update_params *switch_update_params =
7085                 &func_params.params.switch_update;
7086
7087         /* Prepare parameters for function state transitions */
7088         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7089         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7090
7091         func_params.f_obj = &bp->func_obj;
7092         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7093
7094         /* Function parameters */
7095         switch_update_params->suspend = suspend;
7096
7097         rc = bnx2x_func_state_change(bp, &func_params);
7098
7099         return rc;
7100 }
7101
7102 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7103 {
7104         int rc, i, port = BP_PORT(bp);
7105         int vlan_en = 0, mac_en[NUM_MACS];
7106
7107
7108         /* Close input from network */
7109         if (bp->mf_mode == SINGLE_FUNCTION) {
7110                 bnx2x_set_rx_filter(&bp->link_params, 0);
7111         } else {
7112                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7113                                    NIG_REG_LLH0_FUNC_EN);
7114                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7115                           NIG_REG_LLH0_FUNC_EN, 0);
7116                 for (i = 0; i < NUM_MACS; i++) {
7117                         mac_en[i] = REG_RD(bp, port ?
7118                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7119                                               4 * i) :
7120                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7121                                               4 * i));
7122                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7123                                               4 * i) :
7124                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7125                 }
7126         }
7127
7128         /* Close BMC to host */
7129         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7130                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7131
7132         /* Suspend Tx switching to the PF. Completion of this ramrod
7133          * further guarantees that all the packets of that PF / child
7134          * VFs in BRB were processed by the Parser, so it is safe to
7135          * change the NIC_MODE register.
7136          */
7137         rc = bnx2x_func_switch_update(bp, 1);
7138         if (rc) {
7139                 BNX2X_ERR("Can't suspend tx-switching!\n");
7140                 return rc;
7141         }
7142
7143         /* Change NIC_MODE register */
7144         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7145
7146         /* Open input from network */
7147         if (bp->mf_mode == SINGLE_FUNCTION) {
7148                 bnx2x_set_rx_filter(&bp->link_params, 1);
7149         } else {
7150                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7151                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7152                 for (i = 0; i < NUM_MACS; i++) {
7153                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7154                                               4 * i) :
7155                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7156                                   mac_en[i]);
7157                 }
7158         }
7159
7160         /* Enable BMC to host */
7161         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7162                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7163
7164         /* Resume Tx switching to the PF */
7165         rc = bnx2x_func_switch_update(bp, 0);
7166         if (rc) {
7167                 BNX2X_ERR("Can't resume tx-switching!\n");
7168                 return rc;
7169         }
7170
7171         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7172         return 0;
7173 }
7174
7175 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7176 {
7177         int rc;
7178
7179         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7180
7181         if (CONFIGURE_NIC_MODE(bp)) {
7182                 /* Configrue searcher as part of function hw init */
7183                 bnx2x_init_searcher(bp);
7184
7185                 /* Reset NIC mode */
7186                 rc = bnx2x_reset_nic_mode(bp);
7187                 if (rc)
7188                         BNX2X_ERR("Can't change NIC mode!\n");
7189                 return rc;
7190         }
7191
7192         return 0;
7193 }
7194
7195 static int bnx2x_init_hw_func(struct bnx2x *bp)
7196 {
7197         int port = BP_PORT(bp);
7198         int func = BP_FUNC(bp);
7199         int init_phase = PHASE_PF0 + func;
7200         struct bnx2x_ilt *ilt = BP_ILT(bp);
7201         u16 cdu_ilt_start;
7202         u32 addr, val;
7203         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7204         int i, main_mem_width, rc;
7205
7206         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7207
7208         /* FLR cleanup - hmmm */
7209         if (!CHIP_IS_E1x(bp)) {
7210                 rc = bnx2x_pf_flr_clnup(bp);
7211                 if (rc)
7212                         return rc;
7213         }
7214
7215         /* set MSI reconfigure capability */
7216         if (bp->common.int_block == INT_BLOCK_HC) {
7217                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7218                 val = REG_RD(bp, addr);
7219                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7220                 REG_WR(bp, addr, val);
7221         }
7222
7223         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7224         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7225
7226         ilt = BP_ILT(bp);
7227         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7228
7229         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7230                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7231                 ilt->lines[cdu_ilt_start + i].page_mapping =
7232                         bp->context[i].cxt_mapping;
7233                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7234         }
7235         bnx2x_ilt_init_op(bp, INITOP_SET);
7236
7237         if (!CONFIGURE_NIC_MODE(bp)) {
7238                 bnx2x_init_searcher(bp);
7239                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7240                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7241         } else {
7242                 /* Set NIC mode */
7243                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7244                 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7245
7246         }
7247
7248         if (!CHIP_IS_E1x(bp)) {
7249                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7250
7251                 /* Turn on a single ISR mode in IGU if driver is going to use
7252                  * INT#x or MSI
7253                  */
7254                 if (!(bp->flags & USING_MSIX_FLAG))
7255                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7256                 /*
7257                  * Timers workaround bug: function init part.
7258                  * Need to wait 20msec after initializing ILT,
7259                  * needed to make sure there are no requests in
7260                  * one of the PXP internal queues with "old" ILT addresses
7261                  */
7262                 msleep(20);
7263                 /*
7264                  * Master enable - Due to WB DMAE writes performed before this
7265                  * register is re-initialized as part of the regular function
7266                  * init
7267                  */
7268                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7269                 /* Enable the function in IGU */
7270                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7271         }
7272
7273         bp->dmae_ready = 1;
7274
7275         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7276
7277         if (!CHIP_IS_E1x(bp))
7278                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7279
7280         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7281         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7282         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7283         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7284         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7285         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7286         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7287         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7288         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7289         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7290         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7291         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7292         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7293
7294         if (!CHIP_IS_E1x(bp))
7295                 REG_WR(bp, QM_REG_PF_EN, 1);
7296
7297         if (!CHIP_IS_E1x(bp)) {
7298                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7299                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7300                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7301                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7302         }
7303         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7304
7305         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7306         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7307         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7308         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7309         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7310         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7311         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7312         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7313         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7314         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7315         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7316         if (!CHIP_IS_E1x(bp))
7317                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7318
7319         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7320
7321         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7322
7323         if (!CHIP_IS_E1x(bp))
7324                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7325
7326         if (IS_MF(bp)) {
7327                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7328                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7329         }
7330
7331         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7332
7333         /* HC init per function */
7334         if (bp->common.int_block == INT_BLOCK_HC) {
7335                 if (CHIP_IS_E1H(bp)) {
7336                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7337
7338                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7339                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7340                 }
7341                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7342
7343         } else {
7344                 int num_segs, sb_idx, prod_offset;
7345
7346                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7347
7348                 if (!CHIP_IS_E1x(bp)) {
7349                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7350                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7351                 }
7352
7353                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7354
7355                 if (!CHIP_IS_E1x(bp)) {
7356                         int dsb_idx = 0;
7357                         /**
7358                          * Producer memory:
7359                          * E2 mode: address 0-135 match to the mapping memory;
7360                          * 136 - PF0 default prod; 137 - PF1 default prod;
7361                          * 138 - PF2 default prod; 139 - PF3 default prod;
7362                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7363                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7364                          * 144-147 reserved.
7365                          *
7366                          * E1.5 mode - In backward compatible mode;
7367                          * for non default SB; each even line in the memory
7368                          * holds the U producer and each odd line hold
7369                          * the C producer. The first 128 producers are for
7370                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7371                          * producers are for the DSB for each PF.
7372                          * Each PF has five segments: (the order inside each
7373                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7374                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7375                          * 144-147 attn prods;
7376                          */
7377                         /* non-default-status-blocks */
7378                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7379                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7380                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7381                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7382                                         num_segs;
7383
7384                                 for (i = 0; i < num_segs; i++) {
7385                                         addr = IGU_REG_PROD_CONS_MEMORY +
7386                                                         (prod_offset + i) * 4;
7387                                         REG_WR(bp, addr, 0);
7388                                 }
7389                                 /* send consumer update with value 0 */
7390                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7391                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7392                                 bnx2x_igu_clear_sb(bp,
7393                                                    bp->igu_base_sb + sb_idx);
7394                         }
7395
7396                         /* default-status-blocks */
7397                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7398                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7399
7400                         if (CHIP_MODE_IS_4_PORT(bp))
7401                                 dsb_idx = BP_FUNC(bp);
7402                         else
7403                                 dsb_idx = BP_VN(bp);
7404
7405                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7406                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7407                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7408
7409                         /*
7410                          * igu prods come in chunks of E1HVN_MAX (4) -
7411                          * does not matters what is the current chip mode
7412                          */
7413                         for (i = 0; i < (num_segs * E1HVN_MAX);
7414                              i += E1HVN_MAX) {
7415                                 addr = IGU_REG_PROD_CONS_MEMORY +
7416                                                         (prod_offset + i)*4;
7417                                 REG_WR(bp, addr, 0);
7418                         }
7419                         /* send consumer update with 0 */
7420                         if (CHIP_INT_MODE_IS_BC(bp)) {
7421                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7422                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7423                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7424                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7425                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7426                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7427                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7428                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7429                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7430                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7431                         } else {
7432                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7433                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7434                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7435                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7436                         }
7437                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7438
7439                         /* !!! these should become driver const once
7440                            rf-tool supports split-68 const */
7441                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7442                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7443                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7444                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7445                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7446                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7447                 }
7448         }
7449
7450         /* Reset PCIE errors for debug */
7451         REG_WR(bp, 0x2114, 0xffffffff);
7452         REG_WR(bp, 0x2120, 0xffffffff);
7453
7454         if (CHIP_IS_E1x(bp)) {
7455                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7456                 main_mem_base = HC_REG_MAIN_MEMORY +
7457                                 BP_PORT(bp) * (main_mem_size * 4);
7458                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7459                 main_mem_width = 8;
7460
7461                 val = REG_RD(bp, main_mem_prty_clr);
7462                 if (val)
7463                         DP(NETIF_MSG_HW,
7464                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7465                            val);
7466
7467                 /* Clear "false" parity errors in MSI-X table */
7468                 for (i = main_mem_base;
7469                      i < main_mem_base + main_mem_size * 4;
7470                      i += main_mem_width) {
7471                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7472                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7473                                          i, main_mem_width / 4);
7474                 }
7475                 /* Clear HC parity attention */
7476                 REG_RD(bp, main_mem_prty_clr);
7477         }
7478
7479 #ifdef BNX2X_STOP_ON_ERROR
7480         /* Enable STORMs SP logging */
7481         REG_WR8(bp, BAR_USTRORM_INTMEM +
7482                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7483         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7484                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7485         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7486                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7487         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7488                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7489 #endif
7490
7491         bnx2x_phy_probe(&bp->link_params);
7492
7493         return 0;
7494 }
7495
7496
7497 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7498 {
7499         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7500
7501         if (!CHIP_IS_E1x(bp))
7502                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7503                                sizeof(struct host_hc_status_block_e2));
7504         else
7505                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7506                                sizeof(struct host_hc_status_block_e1x));
7507
7508         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7509 }
7510
7511 void bnx2x_free_mem(struct bnx2x *bp)
7512 {
7513         int i;
7514
7515         /* fastpath */
7516         bnx2x_free_fp_mem(bp);
7517         /* end of fastpath */
7518
7519         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7520                        sizeof(struct host_sp_status_block));
7521
7522         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7523                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7524
7525         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7526                        sizeof(struct bnx2x_slowpath));
7527
7528         for (i = 0; i < L2_ILT_LINES(bp); i++)
7529                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7530                                bp->context[i].size);
7531         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7532
7533         BNX2X_FREE(bp->ilt->lines);
7534
7535         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7536
7537         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7538                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7539 }
7540
7541 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7542 {
7543         int num_groups;
7544         int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7545
7546         /* number of queues for statistics is number of eth queues + FCoE */
7547         u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7548
7549         /* Total number of FW statistics requests =
7550          * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7551          * num of queues
7552          */
7553         bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7554
7555
7556         /* Request is built from stats_query_header and an array of
7557          * stats_query_cmd_group each of which contains
7558          * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7559          * configured in the stats_query_header.
7560          */
7561         num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7562                      (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7563
7564         bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7565                         num_groups * sizeof(struct stats_query_cmd_group);
7566
7567         /* Data for statistics requests + stats_conter
7568          *
7569          * stats_counter holds per-STORM counters that are incremented
7570          * when STORM has finished with the current request.
7571          *
7572          * memory for FCoE offloaded statistics are counted anyway,
7573          * even if they will not be sent.
7574          */
7575         bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7576                 sizeof(struct per_pf_stats) +
7577                 sizeof(struct fcoe_statistics_params) +
7578                 sizeof(struct per_queue_stats) * num_queue_stats +
7579                 sizeof(struct stats_counter);
7580
7581         BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7582                         bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7583
7584         /* Set shortcuts */
7585         bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7586         bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7587
7588         bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7589                 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7590
7591         bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7592                                    bp->fw_stats_req_sz;
7593         return 0;
7594
7595 alloc_mem_err:
7596         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7597                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7598         BNX2X_ERR("Can't allocate memory\n");
7599         return -ENOMEM;
7600 }
7601
7602 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7603 {
7604         if (!CHIP_IS_E1x(bp))
7605                 /* size = the status block + ramrod buffers */
7606                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7607                                 sizeof(struct host_hc_status_block_e2));
7608         else
7609                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7610                                 &bp->cnic_sb_mapping,
7611                                 sizeof(struct
7612                                        host_hc_status_block_e1x));
7613
7614         if (CONFIGURE_NIC_MODE(bp))
7615                 /* allocate searcher T2 table, as it wan't allocated before */
7616                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7617
7618         /* write address to which L5 should insert its values */
7619         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7620                 &bp->slowpath->drv_info_to_mcp;
7621
7622         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7623                 goto alloc_mem_err;
7624
7625         return 0;
7626
7627 alloc_mem_err:
7628         bnx2x_free_mem_cnic(bp);
7629         BNX2X_ERR("Can't allocate memory\n");
7630         return -ENOMEM;
7631 }
7632
7633 int bnx2x_alloc_mem(struct bnx2x *bp)
7634 {
7635         int i, allocated, context_size;
7636
7637         if (!CONFIGURE_NIC_MODE(bp))
7638                 /* allocate searcher T2 table */
7639                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7640
7641         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7642                         sizeof(struct host_sp_status_block));
7643
7644         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7645                         sizeof(struct bnx2x_slowpath));
7646
7647         /* Allocated memory for FW statistics  */
7648         if (bnx2x_alloc_fw_stats_mem(bp))
7649                 goto alloc_mem_err;
7650
7651         /* Allocate memory for CDU context:
7652          * This memory is allocated separately and not in the generic ILT
7653          * functions because CDU differs in few aspects:
7654          * 1. There are multiple entities allocating memory for context -
7655          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7656          * its own ILT lines.
7657          * 2. Since CDU page-size is not a single 4KB page (which is the case
7658          * for the other ILT clients), to be efficient we want to support
7659          * allocation of sub-page-size in the last entry.
7660          * 3. Context pointers are used by the driver to pass to FW / update
7661          * the context (for the other ILT clients the pointers are used just to
7662          * free the memory during unload).
7663          */
7664         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7665
7666         for (i = 0, allocated = 0; allocated < context_size; i++) {
7667                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7668                                           (context_size - allocated));
7669                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7670                                 &bp->context[i].cxt_mapping,
7671                                 bp->context[i].size);
7672                 allocated += bp->context[i].size;
7673         }
7674         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7675
7676         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7677                 goto alloc_mem_err;
7678
7679         /* Slow path ring */
7680         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7681
7682         /* EQ */
7683         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7684                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7685
7686
7687         /* fastpath */
7688         /* need to be done at the end, since it's self adjusting to amount
7689          * of memory available for RSS queues
7690          */
7691         if (bnx2x_alloc_fp_mem(bp))
7692                 goto alloc_mem_err;
7693         return 0;
7694
7695 alloc_mem_err:
7696         bnx2x_free_mem(bp);
7697         BNX2X_ERR("Can't allocate memory\n");
7698         return -ENOMEM;
7699 }
7700
7701 /*
7702  * Init service functions
7703  */
7704
7705 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7706                       struct bnx2x_vlan_mac_obj *obj, bool set,
7707                       int mac_type, unsigned long *ramrod_flags)
7708 {
7709         int rc;
7710         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7711
7712         memset(&ramrod_param, 0, sizeof(ramrod_param));
7713
7714         /* Fill general parameters */
7715         ramrod_param.vlan_mac_obj = obj;
7716         ramrod_param.ramrod_flags = *ramrod_flags;
7717
7718         /* Fill a user request section if needed */
7719         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7720                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7721
7722                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7723
7724                 /* Set the command: ADD or DEL */
7725                 if (set)
7726                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7727                 else
7728                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7729         }
7730
7731         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7732
7733         if (rc == -EEXIST) {
7734                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7735                 /* do not treat adding same MAC as error */
7736                 rc = 0;
7737         } else if (rc < 0)
7738                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7739
7740         return rc;
7741 }
7742
7743 int bnx2x_del_all_macs(struct bnx2x *bp,
7744                        struct bnx2x_vlan_mac_obj *mac_obj,
7745                        int mac_type, bool wait_for_comp)
7746 {
7747         int rc;
7748         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7749
7750         /* Wait for completion of requested */
7751         if (wait_for_comp)
7752                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7753
7754         /* Set the mac type of addresses we want to clear */
7755         __set_bit(mac_type, &vlan_mac_flags);
7756
7757         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7758         if (rc < 0)
7759                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7760
7761         return rc;
7762 }
7763
7764 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7765 {
7766         unsigned long ramrod_flags = 0;
7767
7768         if (is_zero_ether_addr(bp->dev->dev_addr) &&
7769             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7770                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7771                    "Ignoring Zero MAC for STORAGE SD mode\n");
7772                 return 0;
7773         }
7774
7775         DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7776
7777         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7778         /* Eth MAC is set on RSS leading client (fp[0]) */
7779         return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7780                                  set, BNX2X_ETH_MAC, &ramrod_flags);
7781 }
7782
7783 int bnx2x_setup_leading(struct bnx2x *bp)
7784 {
7785         return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7786 }
7787
7788 /**
7789  * bnx2x_set_int_mode - configure interrupt mode
7790  *
7791  * @bp:         driver handle
7792  *
7793  * In case of MSI-X it will also try to enable MSI-X.
7794  */
7795 void bnx2x_set_int_mode(struct bnx2x *bp)
7796 {
7797         switch (int_mode) {
7798         case INT_MODE_MSI:
7799                 bnx2x_enable_msi(bp);
7800                 /* falling through... */
7801         case INT_MODE_INTx:
7802                 bp->num_ethernet_queues = 1;
7803                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7804                 BNX2X_DEV_INFO("set number of queues to 1\n");
7805                 break;
7806         default:
7807                 /* if we can't use MSI-X we only need one fp,
7808                  * so try to enable MSI-X with the requested number of fp's
7809                  * and fallback to MSI or legacy INTx with one fp
7810                  */
7811                 if (bnx2x_enable_msix(bp) ||
7812                     bp->flags & USING_SINGLE_MSIX_FLAG) {
7813                         /* failed to enable multiple MSI-X */
7814                         BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7815                                        bp->num_queues,
7816                                        1 + bp->num_cnic_queues);
7817
7818                         bp->num_queues = 1 + bp->num_cnic_queues;
7819
7820                         /* Try to enable MSI */
7821                         if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7822                             !(bp->flags & DISABLE_MSI_FLAG))
7823                                 bnx2x_enable_msi(bp);
7824                 }
7825                 break;
7826         }
7827 }
7828
7829 /* must be called prioir to any HW initializations */
7830 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7831 {
7832         return L2_ILT_LINES(bp);
7833 }
7834
7835 void bnx2x_ilt_set_info(struct bnx2x *bp)
7836 {
7837         struct ilt_client_info *ilt_client;
7838         struct bnx2x_ilt *ilt = BP_ILT(bp);
7839         u16 line = 0;
7840
7841         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7842         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7843
7844         /* CDU */
7845         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7846         ilt_client->client_num = ILT_CLIENT_CDU;
7847         ilt_client->page_size = CDU_ILT_PAGE_SZ;
7848         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7849         ilt_client->start = line;
7850         line += bnx2x_cid_ilt_lines(bp);
7851
7852         if (CNIC_SUPPORT(bp))
7853                 line += CNIC_ILT_LINES;
7854         ilt_client->end = line - 1;
7855
7856         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7857            ilt_client->start,
7858            ilt_client->end,
7859            ilt_client->page_size,
7860            ilt_client->flags,
7861            ilog2(ilt_client->page_size >> 12));
7862
7863         /* QM */
7864         if (QM_INIT(bp->qm_cid_count)) {
7865                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7866                 ilt_client->client_num = ILT_CLIENT_QM;
7867                 ilt_client->page_size = QM_ILT_PAGE_SZ;
7868                 ilt_client->flags = 0;
7869                 ilt_client->start = line;
7870
7871                 /* 4 bytes for each cid */
7872                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7873                                                          QM_ILT_PAGE_SZ);
7874
7875                 ilt_client->end = line - 1;
7876
7877                 DP(NETIF_MSG_IFUP,
7878                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7879                    ilt_client->start,
7880                    ilt_client->end,
7881                    ilt_client->page_size,
7882                    ilt_client->flags,
7883                    ilog2(ilt_client->page_size >> 12));
7884
7885         }
7886
7887         if (CNIC_SUPPORT(bp)) {
7888                 /* SRC */
7889                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7890                 ilt_client->client_num = ILT_CLIENT_SRC;
7891                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7892                 ilt_client->flags = 0;
7893                 ilt_client->start = line;
7894                 line += SRC_ILT_LINES;
7895                 ilt_client->end = line - 1;
7896
7897                 DP(NETIF_MSG_IFUP,
7898                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7899                    ilt_client->start,
7900                    ilt_client->end,
7901                    ilt_client->page_size,
7902                    ilt_client->flags,
7903                    ilog2(ilt_client->page_size >> 12));
7904
7905                 /* TM */
7906                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7907                 ilt_client->client_num = ILT_CLIENT_TM;
7908                 ilt_client->page_size = TM_ILT_PAGE_SZ;
7909                 ilt_client->flags = 0;
7910                 ilt_client->start = line;
7911                 line += TM_ILT_LINES;
7912                 ilt_client->end = line - 1;
7913
7914                 DP(NETIF_MSG_IFUP,
7915                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7916                    ilt_client->start,
7917                    ilt_client->end,
7918                    ilt_client->page_size,
7919                    ilt_client->flags,
7920                    ilog2(ilt_client->page_size >> 12));
7921         }
7922
7923         BUG_ON(line > ILT_MAX_LINES);
7924 }
7925
7926 /**
7927  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7928  *
7929  * @bp:                 driver handle
7930  * @fp:                 pointer to fastpath
7931  * @init_params:        pointer to parameters structure
7932  *
7933  * parameters configured:
7934  *      - HC configuration
7935  *      - Queue's CDU context
7936  */
7937 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7938         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7939 {
7940
7941         u8 cos;
7942         int cxt_index, cxt_offset;
7943
7944         /* FCoE Queue uses Default SB, thus has no HC capabilities */
7945         if (!IS_FCOE_FP(fp)) {
7946                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7947                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7948
7949                 /* If HC is supporterd, enable host coalescing in the transition
7950                  * to INIT state.
7951                  */
7952                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7953                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7954
7955                 /* HC rate */
7956                 init_params->rx.hc_rate = bp->rx_ticks ?
7957                         (1000000 / bp->rx_ticks) : 0;
7958                 init_params->tx.hc_rate = bp->tx_ticks ?
7959                         (1000000 / bp->tx_ticks) : 0;
7960
7961                 /* FW SB ID */
7962                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7963                         fp->fw_sb_id;
7964
7965                 /*
7966                  * CQ index among the SB indices: FCoE clients uses the default
7967                  * SB, therefore it's different.
7968                  */
7969                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7970                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7971         }
7972
7973         /* set maximum number of COSs supported by this queue */
7974         init_params->max_cos = fp->max_cos;
7975
7976         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7977             fp->index, init_params->max_cos);
7978
7979         /* set the context pointers queue object */
7980         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
7981                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
7982                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
7983                                 ILT_PAGE_CIDS);
7984                 init_params->cxts[cos] =
7985                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
7986         }
7987 }
7988
7989 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7990                         struct bnx2x_queue_state_params *q_params,
7991                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7992                         int tx_index, bool leading)
7993 {
7994         memset(tx_only_params, 0, sizeof(*tx_only_params));
7995
7996         /* Set the command */
7997         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7998
7999         /* Set tx-only QUEUE flags: don't zero statistics */
8000         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8001
8002         /* choose the index of the cid to send the slow path on */
8003         tx_only_params->cid_index = tx_index;
8004
8005         /* Set general TX_ONLY_SETUP parameters */
8006         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8007
8008         /* Set Tx TX_ONLY_SETUP parameters */
8009         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8010
8011         DP(NETIF_MSG_IFUP,
8012            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8013            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8014            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8015            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8016
8017         /* send the ramrod */
8018         return bnx2x_queue_state_change(bp, q_params);
8019 }
8020
8021
8022 /**
8023  * bnx2x_setup_queue - setup queue
8024  *
8025  * @bp:         driver handle
8026  * @fp:         pointer to fastpath
8027  * @leading:    is leading
8028  *
8029  * This function performs 2 steps in a Queue state machine
8030  *      actually: 1) RESET->INIT 2) INIT->SETUP
8031  */
8032
8033 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8034                        bool leading)
8035 {
8036         struct bnx2x_queue_state_params q_params = {NULL};
8037         struct bnx2x_queue_setup_params *setup_params =
8038                                                 &q_params.params.setup;
8039         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8040                                                 &q_params.params.tx_only;
8041         int rc;
8042         u8 tx_index;
8043
8044         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8045
8046         /* reset IGU state skip FCoE L2 queue */
8047         if (!IS_FCOE_FP(fp))
8048                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8049                              IGU_INT_ENABLE, 0);
8050
8051         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8052         /* We want to wait for completion in this context */
8053         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8054
8055         /* Prepare the INIT parameters */
8056         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8057
8058         /* Set the command */
8059         q_params.cmd = BNX2X_Q_CMD_INIT;
8060
8061         /* Change the state to INIT */
8062         rc = bnx2x_queue_state_change(bp, &q_params);
8063         if (rc) {
8064                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8065                 return rc;
8066         }
8067
8068         DP(NETIF_MSG_IFUP, "init complete\n");
8069
8070
8071         /* Now move the Queue to the SETUP state... */
8072         memset(setup_params, 0, sizeof(*setup_params));
8073
8074         /* Set QUEUE flags */
8075         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8076
8077         /* Set general SETUP parameters */
8078         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8079                                 FIRST_TX_COS_INDEX);
8080
8081         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8082                             &setup_params->rxq_params);
8083
8084         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8085                            FIRST_TX_COS_INDEX);
8086
8087         /* Set the command */
8088         q_params.cmd = BNX2X_Q_CMD_SETUP;
8089
8090         if (IS_FCOE_FP(fp))
8091                 bp->fcoe_init = true;
8092
8093         /* Change the state to SETUP */
8094         rc = bnx2x_queue_state_change(bp, &q_params);
8095         if (rc) {
8096                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8097                 return rc;
8098         }
8099
8100         /* loop through the relevant tx-only indices */
8101         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8102               tx_index < fp->max_cos;
8103               tx_index++) {
8104
8105                 /* prepare and send tx-only ramrod*/
8106                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8107                                           tx_only_params, tx_index, leading);
8108                 if (rc) {
8109                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8110                                   fp->index, tx_index);
8111                         return rc;
8112                 }
8113         }
8114
8115         return rc;
8116 }
8117
8118 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8119 {
8120         struct bnx2x_fastpath *fp = &bp->fp[index];
8121         struct bnx2x_fp_txdata *txdata;
8122         struct bnx2x_queue_state_params q_params = {NULL};
8123         int rc, tx_index;
8124
8125         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8126
8127         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8128         /* We want to wait for completion in this context */
8129         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8130
8131
8132         /* close tx-only connections */
8133         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8134              tx_index < fp->max_cos;
8135              tx_index++){
8136
8137                 /* ascertain this is a normal queue*/
8138                 txdata = fp->txdata_ptr[tx_index];
8139
8140                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8141                                                         txdata->txq_index);
8142
8143                 /* send halt terminate on tx-only connection */
8144                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8145                 memset(&q_params.params.terminate, 0,
8146                        sizeof(q_params.params.terminate));
8147                 q_params.params.terminate.cid_index = tx_index;
8148
8149                 rc = bnx2x_queue_state_change(bp, &q_params);
8150                 if (rc)
8151                         return rc;
8152
8153                 /* send halt terminate on tx-only connection */
8154                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8155                 memset(&q_params.params.cfc_del, 0,
8156                        sizeof(q_params.params.cfc_del));
8157                 q_params.params.cfc_del.cid_index = tx_index;
8158                 rc = bnx2x_queue_state_change(bp, &q_params);
8159                 if (rc)
8160                         return rc;
8161         }
8162         /* Stop the primary connection: */
8163         /* ...halt the connection */
8164         q_params.cmd = BNX2X_Q_CMD_HALT;
8165         rc = bnx2x_queue_state_change(bp, &q_params);
8166         if (rc)
8167                 return rc;
8168
8169         /* ...terminate the connection */
8170         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8171         memset(&q_params.params.terminate, 0,
8172                sizeof(q_params.params.terminate));
8173         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8174         rc = bnx2x_queue_state_change(bp, &q_params);
8175         if (rc)
8176                 return rc;
8177         /* ...delete cfc entry */
8178         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8179         memset(&q_params.params.cfc_del, 0,
8180                sizeof(q_params.params.cfc_del));
8181         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8182         return bnx2x_queue_state_change(bp, &q_params);
8183 }
8184
8185
8186 static void bnx2x_reset_func(struct bnx2x *bp)
8187 {
8188         int port = BP_PORT(bp);
8189         int func = BP_FUNC(bp);
8190         int i;
8191
8192         /* Disable the function in the FW */
8193         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8194         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8195         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8196         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8197
8198         /* FP SBs */
8199         for_each_eth_queue(bp, i) {
8200                 struct bnx2x_fastpath *fp = &bp->fp[i];
8201                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8202                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8203                            SB_DISABLED);
8204         }
8205
8206         if (CNIC_LOADED(bp))
8207                 /* CNIC SB */
8208                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8209                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8210                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8211
8212         /* SP SB */
8213         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8214                    CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8215                    SB_DISABLED);
8216
8217         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8218                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8219                        0);
8220
8221         /* Configure IGU */
8222         if (bp->common.int_block == INT_BLOCK_HC) {
8223                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8224                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8225         } else {
8226                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8227                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8228         }
8229
8230         if (CNIC_LOADED(bp)) {
8231                 /* Disable Timer scan */
8232                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8233                 /*
8234                  * Wait for at least 10ms and up to 2 second for the timers
8235                  * scan to complete
8236                  */
8237                 for (i = 0; i < 200; i++) {
8238                         msleep(10);
8239                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8240                                 break;
8241                 }
8242         }
8243         /* Clear ILT */
8244         bnx2x_clear_func_ilt(bp, func);
8245
8246         /* Timers workaround bug for E2: if this is vnic-3,
8247          * we need to set the entire ilt range for this timers.
8248          */
8249         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8250                 struct ilt_client_info ilt_cli;
8251                 /* use dummy TM client */
8252                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8253                 ilt_cli.start = 0;
8254                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8255                 ilt_cli.client_num = ILT_CLIENT_TM;
8256
8257                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8258         }
8259
8260         /* this assumes that reset_port() called before reset_func()*/
8261         if (!CHIP_IS_E1x(bp))
8262                 bnx2x_pf_disable(bp);
8263
8264         bp->dmae_ready = 0;
8265 }
8266
8267 static void bnx2x_reset_port(struct bnx2x *bp)
8268 {
8269         int port = BP_PORT(bp);
8270         u32 val;
8271
8272         /* Reset physical Link */
8273         bnx2x__link_reset(bp);
8274
8275         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8276
8277         /* Do not rcv packets to BRB */
8278         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8279         /* Do not direct rcv packets that are not for MCP to the BRB */
8280         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8281                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8282
8283         /* Configure AEU */
8284         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8285
8286         msleep(100);
8287         /* Check for BRB port occupancy */
8288         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8289         if (val)
8290                 DP(NETIF_MSG_IFDOWN,
8291                    "BRB1 is not empty  %d blocks are occupied\n", val);
8292
8293         /* TODO: Close Doorbell port? */
8294 }
8295
8296 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8297 {
8298         struct bnx2x_func_state_params func_params = {NULL};
8299
8300         /* Prepare parameters for function state transitions */
8301         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8302
8303         func_params.f_obj = &bp->func_obj;
8304         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8305
8306         func_params.params.hw_init.load_phase = load_code;
8307
8308         return bnx2x_func_state_change(bp, &func_params);
8309 }
8310
8311 static int bnx2x_func_stop(struct bnx2x *bp)
8312 {
8313         struct bnx2x_func_state_params func_params = {NULL};
8314         int rc;
8315
8316         /* Prepare parameters for function state transitions */
8317         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8318         func_params.f_obj = &bp->func_obj;
8319         func_params.cmd = BNX2X_F_CMD_STOP;
8320
8321         /*
8322          * Try to stop the function the 'good way'. If fails (in case
8323          * of a parity error during bnx2x_chip_cleanup()) and we are
8324          * not in a debug mode, perform a state transaction in order to
8325          * enable further HW_RESET transaction.
8326          */
8327         rc = bnx2x_func_state_change(bp, &func_params);
8328         if (rc) {
8329 #ifdef BNX2X_STOP_ON_ERROR
8330                 return rc;
8331 #else
8332                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8333                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8334                 return bnx2x_func_state_change(bp, &func_params);
8335 #endif
8336         }
8337
8338         return 0;
8339 }
8340
8341 /**
8342  * bnx2x_send_unload_req - request unload mode from the MCP.
8343  *
8344  * @bp:                 driver handle
8345  * @unload_mode:        requested function's unload mode
8346  *
8347  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8348  */
8349 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8350 {
8351         u32 reset_code = 0;
8352         int port = BP_PORT(bp);
8353
8354         /* Select the UNLOAD request mode */
8355         if (unload_mode == UNLOAD_NORMAL)
8356                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8357
8358         else if (bp->flags & NO_WOL_FLAG)
8359                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8360
8361         else if (bp->wol) {
8362                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8363                 u8 *mac_addr = bp->dev->dev_addr;
8364                 u32 val;
8365                 u16 pmc;
8366
8367                 /* The mac address is written to entries 1-4 to
8368                  * preserve entry 0 which is used by the PMF
8369                  */
8370                 u8 entry = (BP_VN(bp) + 1)*8;
8371
8372                 val = (mac_addr[0] << 8) | mac_addr[1];
8373                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8374
8375                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8376                       (mac_addr[4] << 8) | mac_addr[5];
8377                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8378
8379                 /* Enable the PME and clear the status */
8380                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8381                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8382                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8383
8384                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8385
8386         } else
8387                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8388
8389         /* Send the request to the MCP */
8390         if (!BP_NOMCP(bp))
8391                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8392         else {
8393                 int path = BP_PATH(bp);
8394
8395                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8396                    path, load_count[path][0], load_count[path][1],
8397                    load_count[path][2]);
8398                 load_count[path][0]--;
8399                 load_count[path][1 + port]--;
8400                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8401                    path, load_count[path][0], load_count[path][1],
8402                    load_count[path][2]);
8403                 if (load_count[path][0] == 0)
8404                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8405                 else if (load_count[path][1 + port] == 0)
8406                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8407                 else
8408                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8409         }
8410
8411         return reset_code;
8412 }
8413
8414 /**
8415  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8416  *
8417  * @bp:         driver handle
8418  * @keep_link:          true iff link should be kept up
8419  */
8420 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8421 {
8422         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8423
8424         /* Report UNLOAD_DONE to MCP */
8425         if (!BP_NOMCP(bp))
8426                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8427 }
8428
8429 static int bnx2x_func_wait_started(struct bnx2x *bp)
8430 {
8431         int tout = 50;
8432         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8433
8434         if (!bp->port.pmf)
8435                 return 0;
8436
8437         /*
8438          * (assumption: No Attention from MCP at this stage)
8439          * PMF probably in the middle of TXdisable/enable transaction
8440          * 1. Sync IRS for default SB
8441          * 2. Sync SP queue - this guarantes us that attention handling started
8442          * 3. Wait, that TXdisable/enable transaction completes
8443          *
8444          * 1+2 guranty that if DCBx attention was scheduled it already changed
8445          * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8446          * received complettion for the transaction the state is TX_STOPPED.
8447          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8448          * transaction.
8449          */
8450
8451         /* make sure default SB ISR is done */
8452         if (msix)
8453                 synchronize_irq(bp->msix_table[0].vector);
8454         else
8455                 synchronize_irq(bp->pdev->irq);
8456
8457         flush_workqueue(bnx2x_wq);
8458
8459         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8460                                 BNX2X_F_STATE_STARTED && tout--)
8461                 msleep(20);
8462
8463         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8464                                                 BNX2X_F_STATE_STARTED) {
8465 #ifdef BNX2X_STOP_ON_ERROR
8466                 BNX2X_ERR("Wrong function state\n");
8467                 return -EBUSY;
8468 #else
8469                 /*
8470                  * Failed to complete the transaction in a "good way"
8471                  * Force both transactions with CLR bit
8472                  */
8473                 struct bnx2x_func_state_params func_params = {NULL};
8474
8475                 DP(NETIF_MSG_IFDOWN,
8476                    "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8477
8478                 func_params.f_obj = &bp->func_obj;
8479                 __set_bit(RAMROD_DRV_CLR_ONLY,
8480                                         &func_params.ramrod_flags);
8481
8482                 /* STARTED-->TX_ST0PPED */
8483                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8484                 bnx2x_func_state_change(bp, &func_params);
8485
8486                 /* TX_ST0PPED-->STARTED */
8487                 func_params.cmd = BNX2X_F_CMD_TX_START;
8488                 return bnx2x_func_state_change(bp, &func_params);
8489 #endif
8490         }
8491
8492         return 0;
8493 }
8494
8495 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8496 {
8497         int port = BP_PORT(bp);
8498         int i, rc = 0;
8499         u8 cos;
8500         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8501         u32 reset_code;
8502
8503         /* Wait until tx fastpath tasks complete */
8504         for_each_tx_queue(bp, i) {
8505                 struct bnx2x_fastpath *fp = &bp->fp[i];
8506
8507                 for_each_cos_in_tx_queue(fp, cos)
8508                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8509 #ifdef BNX2X_STOP_ON_ERROR
8510                 if (rc)
8511                         return;
8512 #endif
8513         }
8514
8515         /* Give HW time to discard old tx messages */
8516         usleep_range(1000, 1000);
8517
8518         /* Clean all ETH MACs */
8519         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8520                                 false);
8521         if (rc < 0)
8522                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8523
8524         /* Clean up UC list  */
8525         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8526                                 true);
8527         if (rc < 0)
8528                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8529                           rc);
8530
8531         /* Disable LLH */
8532         if (!CHIP_IS_E1(bp))
8533                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8534
8535         /* Set "drop all" (stop Rx).
8536          * We need to take a netif_addr_lock() here in order to prevent
8537          * a race between the completion code and this code.
8538          */
8539         netif_addr_lock_bh(bp->dev);
8540         /* Schedule the rx_mode command */
8541         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8542                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8543         else
8544                 bnx2x_set_storm_rx_mode(bp);
8545
8546         /* Cleanup multicast configuration */
8547         rparam.mcast_obj = &bp->mcast_obj;
8548         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8549         if (rc < 0)
8550                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8551
8552         netif_addr_unlock_bh(bp->dev);
8553
8554
8555
8556         /*
8557          * Send the UNLOAD_REQUEST to the MCP. This will return if
8558          * this function should perform FUNC, PORT or COMMON HW
8559          * reset.
8560          */
8561         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8562
8563         /*
8564          * (assumption: No Attention from MCP at this stage)
8565          * PMF probably in the middle of TXdisable/enable transaction
8566          */
8567         rc = bnx2x_func_wait_started(bp);
8568         if (rc) {
8569                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8570 #ifdef BNX2X_STOP_ON_ERROR
8571                 return;
8572 #endif
8573         }
8574
8575         /* Close multi and leading connections
8576          * Completions for ramrods are collected in a synchronous way
8577          */
8578         for_each_eth_queue(bp, i)
8579                 if (bnx2x_stop_queue(bp, i))
8580 #ifdef BNX2X_STOP_ON_ERROR
8581                         return;
8582 #else
8583                         goto unload_error;
8584 #endif
8585
8586         if (CNIC_LOADED(bp)) {
8587                 for_each_cnic_queue(bp, i)
8588                         if (bnx2x_stop_queue(bp, i))
8589 #ifdef BNX2X_STOP_ON_ERROR
8590                                 return;
8591 #else
8592                                 goto unload_error;
8593 #endif
8594         }
8595
8596         /* If SP settings didn't get completed so far - something
8597          * very wrong has happen.
8598          */
8599         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8600                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8601
8602 #ifndef BNX2X_STOP_ON_ERROR
8603 unload_error:
8604 #endif
8605         rc = bnx2x_func_stop(bp);
8606         if (rc) {
8607                 BNX2X_ERR("Function stop failed!\n");
8608 #ifdef BNX2X_STOP_ON_ERROR
8609                 return;
8610 #endif
8611         }
8612
8613         /* Disable HW interrupts, NAPI */
8614         bnx2x_netif_stop(bp, 1);
8615         /* Delete all NAPI objects */
8616         bnx2x_del_all_napi(bp);
8617         if (CNIC_LOADED(bp))
8618                 bnx2x_del_all_napi_cnic(bp);
8619
8620         /* Release IRQs */
8621         bnx2x_free_irq(bp);
8622
8623         /* Reset the chip */
8624         rc = bnx2x_reset_hw(bp, reset_code);
8625         if (rc)
8626                 BNX2X_ERR("HW_RESET failed\n");
8627
8628
8629         /* Report UNLOAD_DONE to MCP */
8630         bnx2x_send_unload_done(bp, keep_link);
8631 }
8632
8633 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8634 {
8635         u32 val;
8636
8637         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8638
8639         if (CHIP_IS_E1(bp)) {
8640                 int port = BP_PORT(bp);
8641                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8642                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8643
8644                 val = REG_RD(bp, addr);
8645                 val &= ~(0x300);
8646                 REG_WR(bp, addr, val);
8647         } else {
8648                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8649                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8650                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8651                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8652         }
8653 }
8654
8655 /* Close gates #2, #3 and #4: */
8656 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8657 {
8658         u32 val;
8659
8660         /* Gates #2 and #4a are closed/opened for "not E1" only */
8661         if (!CHIP_IS_E1(bp)) {
8662                 /* #4 */
8663                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8664                 /* #2 */
8665                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8666         }
8667
8668         /* #3 */
8669         if (CHIP_IS_E1x(bp)) {
8670                 /* Prevent interrupts from HC on both ports */
8671                 val = REG_RD(bp, HC_REG_CONFIG_1);
8672                 REG_WR(bp, HC_REG_CONFIG_1,
8673                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8674                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8675
8676                 val = REG_RD(bp, HC_REG_CONFIG_0);
8677                 REG_WR(bp, HC_REG_CONFIG_0,
8678                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8679                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8680         } else {
8681                 /* Prevent incomming interrupts in IGU */
8682                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8683
8684                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8685                        (!close) ?
8686                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8687                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8688         }
8689
8690         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8691                 close ? "closing" : "opening");
8692         mmiowb();
8693 }
8694
8695 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
8696
8697 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8698 {
8699         /* Do some magic... */
8700         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8701         *magic_val = val & SHARED_MF_CLP_MAGIC;
8702         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8703 }
8704
8705 /**
8706  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8707  *
8708  * @bp:         driver handle
8709  * @magic_val:  old value of the `magic' bit.
8710  */
8711 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8712 {
8713         /* Restore the `magic' bit value... */
8714         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8715         MF_CFG_WR(bp, shared_mf_config.clp_mb,
8716                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8717 }
8718
8719 /**
8720  * bnx2x_reset_mcp_prep - prepare for MCP reset.
8721  *
8722  * @bp:         driver handle
8723  * @magic_val:  old value of 'magic' bit.
8724  *
8725  * Takes care of CLP configurations.
8726  */
8727 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8728 {
8729         u32 shmem;
8730         u32 validity_offset;
8731
8732         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8733
8734         /* Set `magic' bit in order to save MF config */
8735         if (!CHIP_IS_E1(bp))
8736                 bnx2x_clp_reset_prep(bp, magic_val);
8737
8738         /* Get shmem offset */
8739         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8740         validity_offset =
8741                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8742
8743         /* Clear validity map flags */
8744         if (shmem > 0)
8745                 REG_WR(bp, shmem + validity_offset, 0);
8746 }
8747
8748 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
8749 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
8750
8751 /**
8752  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8753  *
8754  * @bp: driver handle
8755  */
8756 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8757 {
8758         /* special handling for emulation and FPGA,
8759            wait 10 times longer */
8760         if (CHIP_REV_IS_SLOW(bp))
8761                 msleep(MCP_ONE_TIMEOUT*10);
8762         else
8763                 msleep(MCP_ONE_TIMEOUT);
8764 }
8765
8766 /*
8767  * initializes bp->common.shmem_base and waits for validity signature to appear
8768  */
8769 static int bnx2x_init_shmem(struct bnx2x *bp)
8770 {
8771         int cnt = 0;
8772         u32 val = 0;
8773
8774         do {
8775                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8776                 if (bp->common.shmem_base) {
8777                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8778                         if (val & SHR_MEM_VALIDITY_MB)
8779                                 return 0;
8780                 }
8781
8782                 bnx2x_mcp_wait_one(bp);
8783
8784         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8785
8786         BNX2X_ERR("BAD MCP validity signature\n");
8787
8788         return -ENODEV;
8789 }
8790
8791 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8792 {
8793         int rc = bnx2x_init_shmem(bp);
8794
8795         /* Restore the `magic' bit value */
8796         if (!CHIP_IS_E1(bp))
8797                 bnx2x_clp_reset_done(bp, magic_val);
8798
8799         return rc;
8800 }
8801
8802 static void bnx2x_pxp_prep(struct bnx2x *bp)
8803 {
8804         if (!CHIP_IS_E1(bp)) {
8805                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8806                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8807                 mmiowb();
8808         }
8809 }
8810
8811 /*
8812  * Reset the whole chip except for:
8813  *      - PCIE core
8814  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8815  *              one reset bit)
8816  *      - IGU
8817  *      - MISC (including AEU)
8818  *      - GRC
8819  *      - RBCN, RBCP
8820  */
8821 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8822 {
8823         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8824         u32 global_bits2, stay_reset2;
8825
8826         /*
8827          * Bits that have to be set in reset_mask2 if we want to reset 'global'
8828          * (per chip) blocks.
8829          */
8830         global_bits2 =
8831                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8832                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8833
8834         /* Don't reset the following blocks.
8835          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8836          *            reset, as in 4 port device they might still be owned
8837          *            by the MCP (there is only one leader per path).
8838          */
8839         not_reset_mask1 =
8840                 MISC_REGISTERS_RESET_REG_1_RST_HC |
8841                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8842                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8843
8844         not_reset_mask2 =
8845                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8846                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8847                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8848                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8849                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8850                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
8851                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8852                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8853                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8854                 MISC_REGISTERS_RESET_REG_2_PGLC |
8855                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8856                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8857                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8858                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8859                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8860                 MISC_REGISTERS_RESET_REG_2_UMAC1;
8861
8862         /*
8863          * Keep the following blocks in reset:
8864          *  - all xxMACs are handled by the bnx2x_link code.
8865          */
8866         stay_reset2 =
8867                 MISC_REGISTERS_RESET_REG_2_XMAC |
8868                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8869
8870         /* Full reset masks according to the chip */
8871         reset_mask1 = 0xffffffff;
8872
8873         if (CHIP_IS_E1(bp))
8874                 reset_mask2 = 0xffff;
8875         else if (CHIP_IS_E1H(bp))
8876                 reset_mask2 = 0x1ffff;
8877         else if (CHIP_IS_E2(bp))
8878                 reset_mask2 = 0xfffff;
8879         else /* CHIP_IS_E3 */
8880                 reset_mask2 = 0x3ffffff;
8881
8882         /* Don't reset global blocks unless we need to */
8883         if (!global)
8884                 reset_mask2 &= ~global_bits2;
8885
8886         /*
8887          * In case of attention in the QM, we need to reset PXP
8888          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8889          * because otherwise QM reset would release 'close the gates' shortly
8890          * before resetting the PXP, then the PSWRQ would send a write
8891          * request to PGLUE. Then when PXP is reset, PGLUE would try to
8892          * read the payload data from PSWWR, but PSWWR would not
8893          * respond. The write queue in PGLUE would stuck, dmae commands
8894          * would not return. Therefore it's important to reset the second
8895          * reset register (containing the
8896          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8897          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8898          * bit).
8899          */
8900         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8901                reset_mask2 & (~not_reset_mask2));
8902
8903         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8904                reset_mask1 & (~not_reset_mask1));
8905
8906         barrier();
8907         mmiowb();
8908
8909         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8910                reset_mask2 & (~stay_reset2));
8911
8912         barrier();
8913         mmiowb();
8914
8915         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8916         mmiowb();
8917 }
8918
8919 /**
8920  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8921  * It should get cleared in no more than 1s.
8922  *
8923  * @bp: driver handle
8924  *
8925  * It should get cleared in no more than 1s. Returns 0 if
8926  * pending writes bit gets cleared.
8927  */
8928 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8929 {
8930         u32 cnt = 1000;
8931         u32 pend_bits = 0;
8932
8933         do {
8934                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8935
8936                 if (pend_bits == 0)
8937                         break;
8938
8939                 usleep_range(1000, 1000);
8940         } while (cnt-- > 0);
8941
8942         if (cnt <= 0) {
8943                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8944                           pend_bits);
8945                 return -EBUSY;
8946         }
8947
8948         return 0;
8949 }
8950
8951 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8952 {
8953         int cnt = 1000;
8954         u32 val = 0;
8955         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8956                 u32 tags_63_32 = 0;
8957
8958
8959         /* Empty the Tetris buffer, wait for 1s */
8960         do {
8961                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8962                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8963                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8964                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8965                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8966                 if (CHIP_IS_E3(bp))
8967                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
8968
8969                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8970                     ((port_is_idle_0 & 0x1) == 0x1) &&
8971                     ((port_is_idle_1 & 0x1) == 0x1) &&
8972                     (pgl_exp_rom2 == 0xffffffff) &&
8973                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
8974                         break;
8975                 usleep_range(1000, 1000);
8976         } while (cnt-- > 0);
8977
8978         if (cnt <= 0) {
8979                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8980                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8981                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8982                           pgl_exp_rom2);
8983                 return -EAGAIN;
8984         }
8985
8986         barrier();
8987
8988         /* Close gates #2, #3 and #4 */
8989         bnx2x_set_234_gates(bp, true);
8990
8991         /* Poll for IGU VQs for 57712 and newer chips */
8992         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8993                 return -EAGAIN;
8994
8995
8996         /* TBD: Indicate that "process kill" is in progress to MCP */
8997
8998         /* Clear "unprepared" bit */
8999         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9000         barrier();
9001
9002         /* Make sure all is written to the chip before the reset */
9003         mmiowb();
9004
9005         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9006          * PSWHST, GRC and PSWRD Tetris buffer.
9007          */
9008         usleep_range(1000, 1000);
9009
9010         /* Prepare to chip reset: */
9011         /* MCP */
9012         if (global)
9013                 bnx2x_reset_mcp_prep(bp, &val);
9014
9015         /* PXP */
9016         bnx2x_pxp_prep(bp);
9017         barrier();
9018
9019         /* reset the chip */
9020         bnx2x_process_kill_chip_reset(bp, global);
9021         barrier();
9022
9023         /* Recover after reset: */
9024         /* MCP */
9025         if (global && bnx2x_reset_mcp_comp(bp, val))
9026                 return -EAGAIN;
9027
9028         /* TBD: Add resetting the NO_MCP mode DB here */
9029
9030         /* Open the gates #2, #3 and #4 */
9031         bnx2x_set_234_gates(bp, false);
9032
9033         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9034          * reset state, re-enable attentions. */
9035
9036         return 0;
9037 }
9038
9039 static int bnx2x_leader_reset(struct bnx2x *bp)
9040 {
9041         int rc = 0;
9042         bool global = bnx2x_reset_is_global(bp);
9043         u32 load_code;
9044
9045         /* if not going to reset MCP - load "fake" driver to reset HW while
9046          * driver is owner of the HW
9047          */
9048         if (!global && !BP_NOMCP(bp)) {
9049                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9050                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9051                 if (!load_code) {
9052                         BNX2X_ERR("MCP response failure, aborting\n");
9053                         rc = -EAGAIN;
9054                         goto exit_leader_reset;
9055                 }
9056                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9057                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9058                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9059                         rc = -EAGAIN;
9060                         goto exit_leader_reset2;
9061                 }
9062                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9063                 if (!load_code) {
9064                         BNX2X_ERR("MCP response failure, aborting\n");
9065                         rc = -EAGAIN;
9066                         goto exit_leader_reset2;
9067                 }
9068         }
9069
9070         /* Try to recover after the failure */
9071         if (bnx2x_process_kill(bp, global)) {
9072                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9073                           BP_PATH(bp));
9074                 rc = -EAGAIN;
9075                 goto exit_leader_reset2;
9076         }
9077
9078         /*
9079          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9080          * state.
9081          */
9082         bnx2x_set_reset_done(bp);
9083         if (global)
9084                 bnx2x_clear_reset_global(bp);
9085
9086 exit_leader_reset2:
9087         /* unload "fake driver" if it was loaded */
9088         if (!global && !BP_NOMCP(bp)) {
9089                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9090                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9091         }
9092 exit_leader_reset:
9093         bp->is_leader = 0;
9094         bnx2x_release_leader_lock(bp);
9095         smp_mb();
9096         return rc;
9097 }
9098
9099 static void bnx2x_recovery_failed(struct bnx2x *bp)
9100 {
9101         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9102
9103         /* Disconnect this device */
9104         netif_device_detach(bp->dev);
9105
9106         /*
9107          * Block ifup for all function on this engine until "process kill"
9108          * or power cycle.
9109          */
9110         bnx2x_set_reset_in_progress(bp);
9111
9112         /* Shut down the power */
9113         bnx2x_set_power_state(bp, PCI_D3hot);
9114
9115         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9116
9117         smp_mb();
9118 }
9119
9120 /*
9121  * Assumption: runs under rtnl lock. This together with the fact
9122  * that it's called only from bnx2x_sp_rtnl() ensure that it
9123  * will never be called when netif_running(bp->dev) is false.
9124  */
9125 static void bnx2x_parity_recover(struct bnx2x *bp)
9126 {
9127         bool global = false;
9128         u32 error_recovered, error_unrecovered;
9129         bool is_parity;
9130
9131         DP(NETIF_MSG_HW, "Handling parity\n");
9132         while (1) {
9133                 switch (bp->recovery_state) {
9134                 case BNX2X_RECOVERY_INIT:
9135                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9136                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9137                         WARN_ON(!is_parity);
9138
9139                         /* Try to get a LEADER_LOCK HW lock */
9140                         if (bnx2x_trylock_leader_lock(bp)) {
9141                                 bnx2x_set_reset_in_progress(bp);
9142                                 /*
9143                                  * Check if there is a global attention and if
9144                                  * there was a global attention, set the global
9145                                  * reset bit.
9146                                  */
9147
9148                                 if (global)
9149                                         bnx2x_set_reset_global(bp);
9150
9151                                 bp->is_leader = 1;
9152                         }
9153
9154                         /* Stop the driver */
9155                         /* If interface has been removed - break */
9156                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9157                                 return;
9158
9159                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9160
9161                         /* Ensure "is_leader", MCP command sequence and
9162                          * "recovery_state" update values are seen on other
9163                          * CPUs.
9164                          */
9165                         smp_mb();
9166                         break;
9167
9168                 case BNX2X_RECOVERY_WAIT:
9169                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9170                         if (bp->is_leader) {
9171                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9172                                 bool other_load_status =
9173                                         bnx2x_get_load_status(bp, other_engine);
9174                                 bool load_status =
9175                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9176                                 global = bnx2x_reset_is_global(bp);
9177
9178                                 /*
9179                                  * In case of a parity in a global block, let
9180                                  * the first leader that performs a
9181                                  * leader_reset() reset the global blocks in
9182                                  * order to clear global attentions. Otherwise
9183                                  * the the gates will remain closed for that
9184                                  * engine.
9185                                  */
9186                                 if (load_status ||
9187                                     (global && other_load_status)) {
9188                                         /* Wait until all other functions get
9189                                          * down.
9190                                          */
9191                                         schedule_delayed_work(&bp->sp_rtnl_task,
9192                                                                 HZ/10);
9193                                         return;
9194                                 } else {
9195                                         /* If all other functions got down -
9196                                          * try to bring the chip back to
9197                                          * normal. In any case it's an exit
9198                                          * point for a leader.
9199                                          */
9200                                         if (bnx2x_leader_reset(bp)) {
9201                                                 bnx2x_recovery_failed(bp);
9202                                                 return;
9203                                         }
9204
9205                                         /* If we are here, means that the
9206                                          * leader has succeeded and doesn't
9207                                          * want to be a leader any more. Try
9208                                          * to continue as a none-leader.
9209                                          */
9210                                         break;
9211                                 }
9212                         } else { /* non-leader */
9213                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9214                                         /* Try to get a LEADER_LOCK HW lock as
9215                                          * long as a former leader may have
9216                                          * been unloaded by the user or
9217                                          * released a leadership by another
9218                                          * reason.
9219                                          */
9220                                         if (bnx2x_trylock_leader_lock(bp)) {
9221                                                 /* I'm a leader now! Restart a
9222                                                  * switch case.
9223                                                  */
9224                                                 bp->is_leader = 1;
9225                                                 break;
9226                                         }
9227
9228                                         schedule_delayed_work(&bp->sp_rtnl_task,
9229                                                                 HZ/10);
9230                                         return;
9231
9232                                 } else {
9233                                         /*
9234                                          * If there was a global attention, wait
9235                                          * for it to be cleared.
9236                                          */
9237                                         if (bnx2x_reset_is_global(bp)) {
9238                                                 schedule_delayed_work(
9239                                                         &bp->sp_rtnl_task,
9240                                                         HZ/10);
9241                                                 return;
9242                                         }
9243
9244                                         error_recovered =
9245                                           bp->eth_stats.recoverable_error;
9246                                         error_unrecovered =
9247                                           bp->eth_stats.unrecoverable_error;
9248                                         bp->recovery_state =
9249                                                 BNX2X_RECOVERY_NIC_LOADING;
9250                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9251                                                 error_unrecovered++;
9252                                                 netdev_err(bp->dev,
9253                                                            "Recovery failed. Power cycle needed\n");
9254                                                 /* Disconnect this device */
9255                                                 netif_device_detach(bp->dev);
9256                                                 /* Shut down the power */
9257                                                 bnx2x_set_power_state(
9258                                                         bp, PCI_D3hot);
9259                                                 smp_mb();
9260                                         } else {
9261                                                 bp->recovery_state =
9262                                                         BNX2X_RECOVERY_DONE;
9263                                                 error_recovered++;
9264                                                 smp_mb();
9265                                         }
9266                                         bp->eth_stats.recoverable_error =
9267                                                 error_recovered;
9268                                         bp->eth_stats.unrecoverable_error =
9269                                                 error_unrecovered;
9270
9271                                         return;
9272                                 }
9273                         }
9274                 default:
9275                         return;
9276                 }
9277         }
9278 }
9279
9280 static int bnx2x_close(struct net_device *dev);
9281
9282 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9283  * scheduled on a general queue in order to prevent a dead lock.
9284  */
9285 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9286 {
9287         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9288
9289         rtnl_lock();
9290
9291         if (!netif_running(bp->dev))
9292                 goto sp_rtnl_exit;
9293
9294         /* if stop on error is defined no recovery flows should be executed */
9295 #ifdef BNX2X_STOP_ON_ERROR
9296         BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9297                   "you will need to reboot when done\n");
9298         goto sp_rtnl_not_reset;
9299 #endif
9300
9301         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9302                 /*
9303                  * Clear all pending SP commands as we are going to reset the
9304                  * function anyway.
9305                  */
9306                 bp->sp_rtnl_state = 0;
9307                 smp_mb();
9308
9309                 bnx2x_parity_recover(bp);
9310
9311                 goto sp_rtnl_exit;
9312         }
9313
9314         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9315                 /*
9316                  * Clear all pending SP commands as we are going to reset the
9317                  * function anyway.
9318                  */
9319                 bp->sp_rtnl_state = 0;
9320                 smp_mb();
9321
9322                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9323                 bnx2x_nic_load(bp, LOAD_NORMAL);
9324
9325                 goto sp_rtnl_exit;
9326         }
9327 #ifdef BNX2X_STOP_ON_ERROR
9328 sp_rtnl_not_reset:
9329 #endif
9330         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9331                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9332         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9333                 bnx2x_after_function_update(bp);
9334         /*
9335          * in case of fan failure we need to reset id if the "stop on error"
9336          * debug flag is set, since we trying to prevent permanent overheating
9337          * damage
9338          */
9339         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9340                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9341                 netif_device_detach(bp->dev);
9342                 bnx2x_close(bp->dev);
9343         }
9344
9345 sp_rtnl_exit:
9346         rtnl_unlock();
9347 }
9348
9349 /* end of nic load/unload */
9350
9351 static void bnx2x_period_task(struct work_struct *work)
9352 {
9353         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9354
9355         if (!netif_running(bp->dev))
9356                 goto period_task_exit;
9357
9358         if (CHIP_REV_IS_SLOW(bp)) {
9359                 BNX2X_ERR("period task called on emulation, ignoring\n");
9360                 goto period_task_exit;
9361         }
9362
9363         bnx2x_acquire_phy_lock(bp);
9364         /*
9365          * The barrier is needed to ensure the ordering between the writing to
9366          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9367          * the reading here.
9368          */
9369         smp_mb();
9370         if (bp->port.pmf) {
9371                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9372
9373                 /* Re-queue task in 1 sec */
9374                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9375         }
9376
9377         bnx2x_release_phy_lock(bp);
9378 period_task_exit:
9379         return;
9380 }
9381
9382 /*
9383  * Init service functions
9384  */
9385
9386 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9387 {
9388         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9389         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9390         return base + (BP_ABS_FUNC(bp)) * stride;
9391 }
9392
9393 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9394 {
9395         u32 reg = bnx2x_get_pretend_reg(bp);
9396
9397         /* Flush all outstanding writes */
9398         mmiowb();
9399
9400         /* Pretend to be function 0 */
9401         REG_WR(bp, reg, 0);
9402         REG_RD(bp, reg);        /* Flush the GRC transaction (in the chip) */
9403
9404         /* From now we are in the "like-E1" mode */
9405         bnx2x_int_disable(bp);
9406
9407         /* Flush all outstanding writes */
9408         mmiowb();
9409
9410         /* Restore the original function */
9411         REG_WR(bp, reg, BP_ABS_FUNC(bp));
9412         REG_RD(bp, reg);
9413 }
9414
9415 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9416 {
9417         if (CHIP_IS_E1(bp))
9418                 bnx2x_int_disable(bp);
9419         else
9420                 bnx2x_undi_int_disable_e1h(bp);
9421 }
9422
9423 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9424 {
9425         u32 val, base_addr, offset, mask, reset_reg;
9426         bool mac_stopped = false;
9427         u8 port = BP_PORT(bp);
9428
9429         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9430
9431         if (!CHIP_IS_E3(bp)) {
9432                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9433                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9434                 if ((mask & reset_reg) && val) {
9435                         u32 wb_data[2];
9436                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9437                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9438                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9439                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9440                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9441
9442                         /*
9443                          * use rd/wr since we cannot use dmae. This is safe
9444                          * since MCP won't access the bus due to the request
9445                          * to unload, and no function on the path can be
9446                          * loaded at this time.
9447                          */
9448                         wb_data[0] = REG_RD(bp, base_addr + offset);
9449                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9450                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9451                         REG_WR(bp, base_addr + offset, wb_data[0]);
9452                         REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9453
9454                 }
9455                 BNX2X_DEV_INFO("Disable emac Rx\n");
9456                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9457
9458                 mac_stopped = true;
9459         } else {
9460                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9461                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9462                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9463                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9464                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9465                                val & ~(1 << 1));
9466                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9467                                val | (1 << 1));
9468                         REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9469                         mac_stopped = true;
9470                 }
9471                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9472                 if (mask & reset_reg) {
9473                         BNX2X_DEV_INFO("Disable umac Rx\n");
9474                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9475                         REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9476                         mac_stopped = true;
9477                 }
9478         }
9479
9480         if (mac_stopped)
9481                 msleep(20);
9482
9483 }
9484
9485 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9486 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9487 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9488 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9489
9490 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9491 {
9492         u16 rcq, bd;
9493         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9494
9495         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9496         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9497
9498         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9499         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9500
9501         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9502                        port, bd, rcq);
9503 }
9504
9505 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9506 {
9507         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9508                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9509         if (!rc) {
9510                 BNX2X_ERR("MCP response failure, aborting\n");
9511                 return -EBUSY;
9512         }
9513
9514         return 0;
9515 }
9516
9517 static struct bnx2x_prev_path_list *
9518                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9519 {
9520         struct bnx2x_prev_path_list *tmp_list;
9521
9522         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9523                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9524                     bp->pdev->bus->number == tmp_list->bus &&
9525                     BP_PATH(bp) == tmp_list->path)
9526                         return tmp_list;
9527
9528         return NULL;
9529 }
9530
9531 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9532 {
9533         struct bnx2x_prev_path_list *tmp_list;
9534         int rc = false;
9535
9536         if (down_trylock(&bnx2x_prev_sem))
9537                 return false;
9538
9539         list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9540                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9541                     bp->pdev->bus->number == tmp_list->bus &&
9542                     BP_PATH(bp) == tmp_list->path) {
9543                         rc = true;
9544                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9545                                        BP_PATH(bp));
9546                         break;
9547                 }
9548         }
9549
9550         up(&bnx2x_prev_sem);
9551
9552         return rc;
9553 }
9554
9555 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9556 {
9557         struct bnx2x_prev_path_list *tmp_list;
9558         int rc;
9559
9560         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9561         if (!tmp_list) {
9562                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9563                 return -ENOMEM;
9564         }
9565
9566         tmp_list->bus = bp->pdev->bus->number;
9567         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9568         tmp_list->path = BP_PATH(bp);
9569         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9570
9571         rc = down_interruptible(&bnx2x_prev_sem);
9572         if (rc) {
9573                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9574                 kfree(tmp_list);
9575         } else {
9576                 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9577                                 BP_PATH(bp));
9578                 list_add(&tmp_list->list, &bnx2x_prev_list);
9579                 up(&bnx2x_prev_sem);
9580         }
9581
9582         return rc;
9583 }
9584
9585 static int bnx2x_do_flr(struct bnx2x *bp)
9586 {
9587         int i;
9588         u16 status;
9589         struct pci_dev *dev = bp->pdev;
9590
9591
9592         if (CHIP_IS_E1x(bp)) {
9593                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9594                 return -EINVAL;
9595         }
9596
9597         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9598         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9599                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9600                           bp->common.bc_ver);
9601                 return -EINVAL;
9602         }
9603
9604         /* Wait for Transaction Pending bit clean */
9605         for (i = 0; i < 4; i++) {
9606                 if (i)
9607                         msleep((1 << (i - 1)) * 100);
9608
9609                 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9610                 if (!(status & PCI_EXP_DEVSTA_TRPND))
9611                         goto clear;
9612         }
9613
9614         dev_err(&dev->dev,
9615                 "transaction is not cleared; proceeding with reset anyway\n");
9616
9617 clear:
9618
9619         BNX2X_DEV_INFO("Initiating FLR\n");
9620         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9621
9622         return 0;
9623 }
9624
9625 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9626 {
9627         int rc;
9628
9629         BNX2X_DEV_INFO("Uncommon unload Flow\n");
9630
9631         /* Test if previous unload process was already finished for this path */
9632         if (bnx2x_prev_is_path_marked(bp))
9633                 return bnx2x_prev_mcp_done(bp);
9634
9635         /* If function has FLR capabilities, and existing FW version matches
9636          * the one required, then FLR will be sufficient to clean any residue
9637          * left by previous driver
9638          */
9639         rc = bnx2x_test_firmware_version(bp, false);
9640
9641         if (!rc) {
9642                 /* fw version is good */
9643                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9644                 rc = bnx2x_do_flr(bp);
9645         }
9646
9647         if (!rc) {
9648                 /* FLR was performed */
9649                 BNX2X_DEV_INFO("FLR successful\n");
9650                 return 0;
9651         }
9652
9653         BNX2X_DEV_INFO("Could not FLR\n");
9654
9655         /* Close the MCP request, return failure*/
9656         rc = bnx2x_prev_mcp_done(bp);
9657         if (!rc)
9658                 rc = BNX2X_PREV_WAIT_NEEDED;
9659
9660         return rc;
9661 }
9662
9663 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9664 {
9665         u32 reset_reg, tmp_reg = 0, rc;
9666         bool prev_undi = false;
9667         /* It is possible a previous function received 'common' answer,
9668          * but hasn't loaded yet, therefore creating a scenario of
9669          * multiple functions receiving 'common' on the same path.
9670          */
9671         BNX2X_DEV_INFO("Common unload Flow\n");
9672
9673         if (bnx2x_prev_is_path_marked(bp))
9674                 return bnx2x_prev_mcp_done(bp);
9675
9676         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9677
9678         /* Reset should be performed after BRB is emptied */
9679         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9680                 u32 timer_count = 1000;
9681
9682                 /* Close the MAC Rx to prevent BRB from filling up */
9683                 bnx2x_prev_unload_close_mac(bp);
9684
9685                 /* Check if the UNDI driver was previously loaded
9686                  * UNDI driver initializes CID offset for normal bell to 0x7
9687                  */
9688                 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9689                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9690                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9691                         if (tmp_reg == 0x7) {
9692                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
9693                                 prev_undi = true;
9694                                 /* clear the UNDI indication */
9695                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9696                         }
9697                 }
9698                 /* wait until BRB is empty */
9699                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9700                 while (timer_count) {
9701                         u32 prev_brb = tmp_reg;
9702
9703                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9704                         if (!tmp_reg)
9705                                 break;
9706
9707                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9708
9709                         /* reset timer as long as BRB actually gets emptied */
9710                         if (prev_brb > tmp_reg)
9711                                 timer_count = 1000;
9712                         else
9713                                 timer_count--;
9714
9715                         /* If UNDI resides in memory, manually increment it */
9716                         if (prev_undi)
9717                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9718
9719                         udelay(10);
9720                 }
9721
9722                 if (!timer_count)
9723                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9724
9725         }
9726
9727         /* No packets are in the pipeline, path is ready for reset */
9728         bnx2x_reset_common(bp);
9729
9730         rc = bnx2x_prev_mark_path(bp, prev_undi);
9731         if (rc) {
9732                 bnx2x_prev_mcp_done(bp);
9733                 return rc;
9734         }
9735
9736         return bnx2x_prev_mcp_done(bp);
9737 }
9738
9739 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9740  * and boot began, or when kdump kernel was loaded. Either case would invalidate
9741  * the addresses of the transaction, resulting in was-error bit set in the pci
9742  * causing all hw-to-host pcie transactions to timeout. If this happened we want
9743  * to clear the interrupt which detected this from the pglueb and the was done
9744  * bit
9745  */
9746 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9747 {
9748         if (!CHIP_IS_E1x(bp)) {
9749                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9750                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9751                         BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9752                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9753                                1 << BP_FUNC(bp));
9754                 }
9755         }
9756 }
9757
9758 static int bnx2x_prev_unload(struct bnx2x *bp)
9759 {
9760         int time_counter = 10;
9761         u32 rc, fw, hw_lock_reg, hw_lock_val;
9762         struct bnx2x_prev_path_list *prev_list;
9763         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9764
9765         /* clear hw from errors which may have resulted from an interrupted
9766          * dmae transaction.
9767          */
9768         bnx2x_prev_interrupted_dmae(bp);
9769
9770         /* Release previously held locks */
9771         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9772                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9773                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9774
9775         hw_lock_val = (REG_RD(bp, hw_lock_reg));
9776         if (hw_lock_val) {
9777                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9778                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9779                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9780                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9781                 }
9782
9783                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9784                 REG_WR(bp, hw_lock_reg, 0xffffffff);
9785         } else
9786                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9787
9788         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9789                 BNX2X_DEV_INFO("Release previously held alr\n");
9790                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9791         }
9792
9793
9794         do {
9795                 /* Lock MCP using an unload request */
9796                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9797                 if (!fw) {
9798                         BNX2X_ERR("MCP response failure, aborting\n");
9799                         rc = -EBUSY;
9800                         break;
9801                 }
9802
9803                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9804                         rc = bnx2x_prev_unload_common(bp);
9805                         break;
9806                 }
9807
9808                 /* non-common reply from MCP night require looping */
9809                 rc = bnx2x_prev_unload_uncommon(bp);
9810                 if (rc != BNX2X_PREV_WAIT_NEEDED)
9811                         break;
9812
9813                 msleep(20);
9814         } while (--time_counter);
9815
9816         if (!time_counter || rc) {
9817                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9818                 rc = -EBUSY;
9819         }
9820
9821         /* Mark function if its port was used to boot from SAN */
9822         prev_list = bnx2x_prev_path_get_entry(bp);
9823         if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
9824                 bp->link_params.feature_config_flags |=
9825                         FEATURE_CONFIG_BOOT_FROM_SAN;
9826
9827         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9828
9829         return rc;
9830 }
9831
9832 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
9833 {
9834         u32 val, val2, val3, val4, id, boot_mode;
9835         u16 pmc;
9836
9837         /* Get the chip revision id and number. */
9838         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9839         val = REG_RD(bp, MISC_REG_CHIP_NUM);
9840         id = ((val & 0xffff) << 16);
9841         val = REG_RD(bp, MISC_REG_CHIP_REV);
9842         id |= ((val & 0xf) << 12);
9843         val = REG_RD(bp, MISC_REG_CHIP_METAL);
9844         id |= ((val & 0xff) << 4);
9845         val = REG_RD(bp, MISC_REG_BOND_ID);
9846         id |= (val & 0xf);
9847         bp->common.chip_id = id;
9848
9849         /* force 57811 according to MISC register */
9850         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9851                 if (CHIP_IS_57810(bp))
9852                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9853                                 (bp->common.chip_id & 0x0000FFFF);
9854                 else if (CHIP_IS_57810_MF(bp))
9855                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9856                                 (bp->common.chip_id & 0x0000FFFF);
9857                 bp->common.chip_id |= 0x1;
9858         }
9859
9860         /* Set doorbell size */
9861         bp->db_size = (1 << BNX2X_DB_SHIFT);
9862
9863         if (!CHIP_IS_E1x(bp)) {
9864                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9865                 if ((val & 1) == 0)
9866                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9867                 else
9868                         val = (val >> 1) & 1;
9869                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9870                                                        "2_PORT_MODE");
9871                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9872                                                  CHIP_2_PORT_MODE;
9873
9874                 if (CHIP_MODE_IS_4_PORT(bp))
9875                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
9876                 else
9877                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
9878         } else {
9879                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9880                 bp->pfid = bp->pf_num;                  /* 0..7 */
9881         }
9882
9883         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9884
9885         bp->link_params.chip_id = bp->common.chip_id;
9886         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9887
9888         val = (REG_RD(bp, 0x2874) & 0x55);
9889         if ((bp->common.chip_id & 0x1) ||
9890             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9891                 bp->flags |= ONE_PORT_FLAG;
9892                 BNX2X_DEV_INFO("single port device\n");
9893         }
9894
9895         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9896         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9897                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
9898         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9899                        bp->common.flash_size, bp->common.flash_size);
9900
9901         bnx2x_init_shmem(bp);
9902
9903
9904
9905         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9906                                         MISC_REG_GENERIC_CR_1 :
9907                                         MISC_REG_GENERIC_CR_0));
9908
9909         bp->link_params.shmem_base = bp->common.shmem_base;
9910         bp->link_params.shmem2_base = bp->common.shmem2_base;
9911         if (SHMEM2_RD(bp, size) >
9912             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
9913                 bp->link_params.lfa_base =
9914                 REG_RD(bp, bp->common.shmem2_base +
9915                        (u32)offsetof(struct shmem2_region,
9916                                      lfa_host_addr[BP_PORT(bp)]));
9917         else
9918                 bp->link_params.lfa_base = 0;
9919         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
9920                        bp->common.shmem_base, bp->common.shmem2_base);
9921
9922         if (!bp->common.shmem_base) {
9923                 BNX2X_DEV_INFO("MCP not active\n");
9924                 bp->flags |= NO_MCP_FLAG;
9925                 return;
9926         }
9927
9928         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9929         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9930
9931         bp->link_params.hw_led_mode = ((bp->common.hw_config &
9932                                         SHARED_HW_CFG_LED_MODE_MASK) >>
9933                                        SHARED_HW_CFG_LED_MODE_SHIFT);
9934
9935         bp->link_params.feature_config_flags = 0;
9936         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9937         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9938                 bp->link_params.feature_config_flags |=
9939                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9940         else
9941                 bp->link_params.feature_config_flags &=
9942                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9943
9944         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9945         bp->common.bc_ver = val;
9946         BNX2X_DEV_INFO("bc_ver %X\n", val);
9947         if (val < BNX2X_BC_VER) {
9948                 /* for now only warn
9949                  * later we might need to enforce this */
9950                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9951                           BNX2X_BC_VER, val);
9952         }
9953         bp->link_params.feature_config_flags |=
9954                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9955                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9956
9957         bp->link_params.feature_config_flags |=
9958                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9959                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9960         bp->link_params.feature_config_flags |=
9961                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
9962                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
9963         bp->link_params.feature_config_flags |=
9964                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9965                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9966
9967         bp->link_params.feature_config_flags |=
9968                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
9969                 FEATURE_CONFIG_MT_SUPPORT : 0;
9970
9971         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9972                         BC_SUPPORTS_PFC_STATS : 0;
9973
9974         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
9975                         BC_SUPPORTS_FCOE_FEATURES : 0;
9976
9977         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
9978                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
9979         boot_mode = SHMEM_RD(bp,
9980                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9981                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9982         switch (boot_mode) {
9983         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9984                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9985                 break;
9986         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9987                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9988                 break;
9989         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9990                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9991                 break;
9992         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9993                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9994                 break;
9995         }
9996
9997         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9998         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9999
10000         BNX2X_DEV_INFO("%sWoL capable\n",
10001                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10002
10003         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10004         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10005         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10006         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10007
10008         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10009                  val, val2, val3, val4);
10010 }
10011
10012 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10013 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10014
10015 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10016 {
10017         int pfid = BP_FUNC(bp);
10018         int igu_sb_id;
10019         u32 val;
10020         u8 fid, igu_sb_cnt = 0;
10021
10022         bp->igu_base_sb = 0xff;
10023         if (CHIP_INT_MODE_IS_BC(bp)) {
10024                 int vn = BP_VN(bp);
10025                 igu_sb_cnt = bp->igu_sb_cnt;
10026                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10027                         FP_SB_MAX_E1x;
10028
10029                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10030                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10031
10032                 return 0;
10033         }
10034
10035         /* IGU in normal mode - read CAM */
10036         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10037              igu_sb_id++) {
10038                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10039                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10040                         continue;
10041                 fid = IGU_FID(val);
10042                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10043                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10044                                 continue;
10045                         if (IGU_VEC(val) == 0)
10046                                 /* default status block */
10047                                 bp->igu_dsb_id = igu_sb_id;
10048                         else {
10049                                 if (bp->igu_base_sb == 0xff)
10050                                         bp->igu_base_sb = igu_sb_id;
10051                                 igu_sb_cnt++;
10052                         }
10053                 }
10054         }
10055
10056 #ifdef CONFIG_PCI_MSI
10057         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10058          * optional that number of CAM entries will not be equal to the value
10059          * advertised in PCI.
10060          * Driver should use the minimal value of both as the actual status
10061          * block count
10062          */
10063         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10064 #endif
10065
10066         if (igu_sb_cnt == 0) {
10067                 BNX2X_ERR("CAM configuration error\n");
10068                 return -EINVAL;
10069         }
10070
10071         return 0;
10072 }
10073
10074 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10075 {
10076         int cfg_size = 0, idx, port = BP_PORT(bp);
10077
10078         /* Aggregation of supported attributes of all external phys */
10079         bp->port.supported[0] = 0;
10080         bp->port.supported[1] = 0;
10081         switch (bp->link_params.num_phys) {
10082         case 1:
10083                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10084                 cfg_size = 1;
10085                 break;
10086         case 2:
10087                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10088                 cfg_size = 1;
10089                 break;
10090         case 3:
10091                 if (bp->link_params.multi_phy_config &
10092                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10093                         bp->port.supported[1] =
10094                                 bp->link_params.phy[EXT_PHY1].supported;
10095                         bp->port.supported[0] =
10096                                 bp->link_params.phy[EXT_PHY2].supported;
10097                 } else {
10098                         bp->port.supported[0] =
10099                                 bp->link_params.phy[EXT_PHY1].supported;
10100                         bp->port.supported[1] =
10101                                 bp->link_params.phy[EXT_PHY2].supported;
10102                 }
10103                 cfg_size = 2;
10104                 break;
10105         }
10106
10107         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10108                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10109                            SHMEM_RD(bp,
10110                            dev_info.port_hw_config[port].external_phy_config),
10111                            SHMEM_RD(bp,
10112                            dev_info.port_hw_config[port].external_phy_config2));
10113                         return;
10114         }
10115
10116         if (CHIP_IS_E3(bp))
10117                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10118         else {
10119                 switch (switch_cfg) {
10120                 case SWITCH_CFG_1G:
10121                         bp->port.phy_addr = REG_RD(
10122                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10123                         break;
10124                 case SWITCH_CFG_10G:
10125                         bp->port.phy_addr = REG_RD(
10126                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10127                         break;
10128                 default:
10129                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10130                                   bp->port.link_config[0]);
10131                         return;
10132                 }
10133         }
10134         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10135         /* mask what we support according to speed_cap_mask per configuration */
10136         for (idx = 0; idx < cfg_size; idx++) {
10137                 if (!(bp->link_params.speed_cap_mask[idx] &
10138                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10139                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10140
10141                 if (!(bp->link_params.speed_cap_mask[idx] &
10142                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10143                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10144
10145                 if (!(bp->link_params.speed_cap_mask[idx] &
10146                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10147                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10148
10149                 if (!(bp->link_params.speed_cap_mask[idx] &
10150                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10151                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10152
10153                 if (!(bp->link_params.speed_cap_mask[idx] &
10154                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10155                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10156                                                      SUPPORTED_1000baseT_Full);
10157
10158                 if (!(bp->link_params.speed_cap_mask[idx] &
10159                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10160                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10161
10162                 if (!(bp->link_params.speed_cap_mask[idx] &
10163                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10164                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10165
10166         }
10167
10168         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10169                        bp->port.supported[1]);
10170 }
10171
10172 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10173 {
10174         u32 link_config, idx, cfg_size = 0;
10175         bp->port.advertising[0] = 0;
10176         bp->port.advertising[1] = 0;
10177         switch (bp->link_params.num_phys) {
10178         case 1:
10179         case 2:
10180                 cfg_size = 1;
10181                 break;
10182         case 3:
10183                 cfg_size = 2;
10184                 break;
10185         }
10186         for (idx = 0; idx < cfg_size; idx++) {
10187                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10188                 link_config = bp->port.link_config[idx];
10189                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10190                 case PORT_FEATURE_LINK_SPEED_AUTO:
10191                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10192                                 bp->link_params.req_line_speed[idx] =
10193                                         SPEED_AUTO_NEG;
10194                                 bp->port.advertising[idx] |=
10195                                         bp->port.supported[idx];
10196                                 if (bp->link_params.phy[EXT_PHY1].type ==
10197                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10198                                         bp->port.advertising[idx] |=
10199                                         (SUPPORTED_100baseT_Half |
10200                                          SUPPORTED_100baseT_Full);
10201                         } else {
10202                                 /* force 10G, no AN */
10203                                 bp->link_params.req_line_speed[idx] =
10204                                         SPEED_10000;
10205                                 bp->port.advertising[idx] |=
10206                                         (ADVERTISED_10000baseT_Full |
10207                                          ADVERTISED_FIBRE);
10208                                 continue;
10209                         }
10210                         break;
10211
10212                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10213                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10214                                 bp->link_params.req_line_speed[idx] =
10215                                         SPEED_10;
10216                                 bp->port.advertising[idx] |=
10217                                         (ADVERTISED_10baseT_Full |
10218                                          ADVERTISED_TP);
10219                         } else {
10220                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10221                                             link_config,
10222                                     bp->link_params.speed_cap_mask[idx]);
10223                                 return;
10224                         }
10225                         break;
10226
10227                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10228                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10229                                 bp->link_params.req_line_speed[idx] =
10230                                         SPEED_10;
10231                                 bp->link_params.req_duplex[idx] =
10232                                         DUPLEX_HALF;
10233                                 bp->port.advertising[idx] |=
10234                                         (ADVERTISED_10baseT_Half |
10235                                          ADVERTISED_TP);
10236                         } else {
10237                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10238                                             link_config,
10239                                           bp->link_params.speed_cap_mask[idx]);
10240                                 return;
10241                         }
10242                         break;
10243
10244                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10245                         if (bp->port.supported[idx] &
10246                             SUPPORTED_100baseT_Full) {
10247                                 bp->link_params.req_line_speed[idx] =
10248                                         SPEED_100;
10249                                 bp->port.advertising[idx] |=
10250                                         (ADVERTISED_100baseT_Full |
10251                                          ADVERTISED_TP);
10252                         } else {
10253                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10254                                             link_config,
10255                                           bp->link_params.speed_cap_mask[idx]);
10256                                 return;
10257                         }
10258                         break;
10259
10260                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10261                         if (bp->port.supported[idx] &
10262                             SUPPORTED_100baseT_Half) {
10263                                 bp->link_params.req_line_speed[idx] =
10264                                                                 SPEED_100;
10265                                 bp->link_params.req_duplex[idx] =
10266                                                                 DUPLEX_HALF;
10267                                 bp->port.advertising[idx] |=
10268                                         (ADVERTISED_100baseT_Half |
10269                                          ADVERTISED_TP);
10270                         } else {
10271                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10272                                     link_config,
10273                                     bp->link_params.speed_cap_mask[idx]);
10274                                 return;
10275                         }
10276                         break;
10277
10278                 case PORT_FEATURE_LINK_SPEED_1G:
10279                         if (bp->port.supported[idx] &
10280                             SUPPORTED_1000baseT_Full) {
10281                                 bp->link_params.req_line_speed[idx] =
10282                                         SPEED_1000;
10283                                 bp->port.advertising[idx] |=
10284                                         (ADVERTISED_1000baseT_Full |
10285                                          ADVERTISED_TP);
10286                         } else {
10287                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10288                                     link_config,
10289                                     bp->link_params.speed_cap_mask[idx]);
10290                                 return;
10291                         }
10292                         break;
10293
10294                 case PORT_FEATURE_LINK_SPEED_2_5G:
10295                         if (bp->port.supported[idx] &
10296                             SUPPORTED_2500baseX_Full) {
10297                                 bp->link_params.req_line_speed[idx] =
10298                                         SPEED_2500;
10299                                 bp->port.advertising[idx] |=
10300                                         (ADVERTISED_2500baseX_Full |
10301                                                 ADVERTISED_TP);
10302                         } else {
10303                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10304                                     link_config,
10305                                     bp->link_params.speed_cap_mask[idx]);
10306                                 return;
10307                         }
10308                         break;
10309
10310                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10311                         if (bp->port.supported[idx] &
10312                             SUPPORTED_10000baseT_Full) {
10313                                 bp->link_params.req_line_speed[idx] =
10314                                         SPEED_10000;
10315                                 bp->port.advertising[idx] |=
10316                                         (ADVERTISED_10000baseT_Full |
10317                                                 ADVERTISED_FIBRE);
10318                         } else {
10319                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10320                                     link_config,
10321                                     bp->link_params.speed_cap_mask[idx]);
10322                                 return;
10323                         }
10324                         break;
10325                 case PORT_FEATURE_LINK_SPEED_20G:
10326                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10327
10328                         break;
10329                 default:
10330                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10331                                   link_config);
10332                                 bp->link_params.req_line_speed[idx] =
10333                                                         SPEED_AUTO_NEG;
10334                                 bp->port.advertising[idx] =
10335                                                 bp->port.supported[idx];
10336                         break;
10337                 }
10338
10339                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10340                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10341                 if (bp->link_params.req_flow_ctrl[idx] ==
10342                     BNX2X_FLOW_CTRL_AUTO) {
10343                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10344                                 bp->link_params.req_flow_ctrl[idx] =
10345                                                         BNX2X_FLOW_CTRL_NONE;
10346                         else
10347                                 bnx2x_set_requested_fc(bp);
10348                 }
10349
10350                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10351                                bp->link_params.req_line_speed[idx],
10352                                bp->link_params.req_duplex[idx],
10353                                bp->link_params.req_flow_ctrl[idx],
10354                                bp->port.advertising[idx]);
10355         }
10356 }
10357
10358 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10359 {
10360         mac_hi = cpu_to_be16(mac_hi);
10361         mac_lo = cpu_to_be32(mac_lo);
10362         memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10363         memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10364 }
10365
10366 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10367 {
10368         int port = BP_PORT(bp);
10369         u32 config;
10370         u32 ext_phy_type, ext_phy_config, eee_mode;
10371
10372         bp->link_params.bp = bp;
10373         bp->link_params.port = port;
10374
10375         bp->link_params.lane_config =
10376                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10377
10378         bp->link_params.speed_cap_mask[0] =
10379                 SHMEM_RD(bp,
10380                          dev_info.port_hw_config[port].speed_capability_mask);
10381         bp->link_params.speed_cap_mask[1] =
10382                 SHMEM_RD(bp,
10383                          dev_info.port_hw_config[port].speed_capability_mask2);
10384         bp->port.link_config[0] =
10385                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10386
10387         bp->port.link_config[1] =
10388                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10389
10390         bp->link_params.multi_phy_config =
10391                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10392         /* If the device is capable of WoL, set the default state according
10393          * to the HW
10394          */
10395         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10396         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10397                    (config & PORT_FEATURE_WOL_ENABLED));
10398
10399         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10400                        bp->link_params.lane_config,
10401                        bp->link_params.speed_cap_mask[0],
10402                        bp->port.link_config[0]);
10403
10404         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10405                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10406         bnx2x_phy_probe(&bp->link_params);
10407         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10408
10409         bnx2x_link_settings_requested(bp);
10410
10411         /*
10412          * If connected directly, work with the internal PHY, otherwise, work
10413          * with the external PHY
10414          */
10415         ext_phy_config =
10416                 SHMEM_RD(bp,
10417                          dev_info.port_hw_config[port].external_phy_config);
10418         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10419         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10420                 bp->mdio.prtad = bp->port.phy_addr;
10421
10422         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10423                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10424                 bp->mdio.prtad =
10425                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10426
10427         /* Configure link feature according to nvram value */
10428         eee_mode = (((SHMEM_RD(bp, dev_info.
10429                       port_feature_config[port].eee_power_mode)) &
10430                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10431                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10432         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10433                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10434                                            EEE_MODE_ENABLE_LPI |
10435                                            EEE_MODE_OUTPUT_TIME;
10436         } else {
10437                 bp->link_params.eee_mode = 0;
10438         }
10439 }
10440
10441 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10442 {
10443         u32 no_flags = NO_ISCSI_FLAG;
10444         int port = BP_PORT(bp);
10445         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10446                                 drv_lic_key[port].max_iscsi_conn);
10447
10448         if (!CNIC_SUPPORT(bp)) {
10449                 bp->flags |= no_flags;
10450                 return;
10451         }
10452
10453         /* Get the number of maximum allowed iSCSI connections */
10454         bp->cnic_eth_dev.max_iscsi_conn =
10455                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10456                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10457
10458         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10459                        bp->cnic_eth_dev.max_iscsi_conn);
10460
10461         /*
10462          * If maximum allowed number of connections is zero -
10463          * disable the feature.
10464          */
10465         if (!bp->cnic_eth_dev.max_iscsi_conn)
10466                 bp->flags |= no_flags;
10467
10468 }
10469
10470 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10471 {
10472         /* Port info */
10473         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10474                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10475         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10476                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10477
10478         /* Node info */
10479         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10480                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10481         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10482                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10483 }
10484 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10485 {
10486         int port = BP_PORT(bp);
10487         int func = BP_ABS_FUNC(bp);
10488         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10489                                 drv_lic_key[port].max_fcoe_conn);
10490
10491         if (!CNIC_SUPPORT(bp)) {
10492                 bp->flags |= NO_FCOE_FLAG;
10493                 return;
10494         }
10495
10496         /* Get the number of maximum allowed FCoE connections */
10497         bp->cnic_eth_dev.max_fcoe_conn =
10498                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10499                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10500
10501         /* Read the WWN: */
10502         if (!IS_MF(bp)) {
10503                 /* Port info */
10504                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10505                         SHMEM_RD(bp,
10506                                 dev_info.port_hw_config[port].
10507                                  fcoe_wwn_port_name_upper);
10508                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10509                         SHMEM_RD(bp,
10510                                 dev_info.port_hw_config[port].
10511                                  fcoe_wwn_port_name_lower);
10512
10513                 /* Node info */
10514                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10515                         SHMEM_RD(bp,
10516                                 dev_info.port_hw_config[port].
10517                                  fcoe_wwn_node_name_upper);
10518                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10519                         SHMEM_RD(bp,
10520                                 dev_info.port_hw_config[port].
10521                                  fcoe_wwn_node_name_lower);
10522         } else if (!IS_MF_SD(bp)) {
10523                 /*
10524                  * Read the WWN info only if the FCoE feature is enabled for
10525                  * this function.
10526                  */
10527                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10528                         bnx2x_get_ext_wwn_info(bp, func);
10529
10530         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10531                 bnx2x_get_ext_wwn_info(bp, func);
10532         }
10533
10534         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10535
10536         /*
10537          * If maximum allowed number of connections is zero -
10538          * disable the feature.
10539          */
10540         if (!bp->cnic_eth_dev.max_fcoe_conn)
10541                 bp->flags |= NO_FCOE_FLAG;
10542 }
10543
10544 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10545 {
10546         /*
10547          * iSCSI may be dynamically disabled but reading
10548          * info here we will decrease memory usage by driver
10549          * if the feature is disabled for good
10550          */
10551         bnx2x_get_iscsi_info(bp);
10552         bnx2x_get_fcoe_info(bp);
10553 }
10554
10555 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10556 {
10557         u32 val, val2;
10558         int func = BP_ABS_FUNC(bp);
10559         int port = BP_PORT(bp);
10560         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10561         u8 *fip_mac = bp->fip_mac;
10562
10563         if (IS_MF(bp)) {
10564                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10565                  * FCoE MAC then the appropriate feature should be disabled.
10566                  * In non SD mode features configuration comes from struct
10567                  * func_ext_config.
10568                  */
10569                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10570                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10571                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10572                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10573                                                  iscsi_mac_addr_upper);
10574                                 val = MF_CFG_RD(bp, func_ext_config[func].
10575                                                 iscsi_mac_addr_lower);
10576                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10577                                 BNX2X_DEV_INFO
10578                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10579                         } else {
10580                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10581                         }
10582
10583                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10584                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10585                                                  fcoe_mac_addr_upper);
10586                                 val = MF_CFG_RD(bp, func_ext_config[func].
10587                                                 fcoe_mac_addr_lower);
10588                                 bnx2x_set_mac_buf(fip_mac, val, val2);
10589                                 BNX2X_DEV_INFO
10590                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
10591                         } else {
10592                                 bp->flags |= NO_FCOE_FLAG;
10593                         }
10594
10595                         bp->mf_ext_config = cfg;
10596
10597                 } else { /* SD MODE */
10598                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10599                                 /* use primary mac as iscsi mac */
10600                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10601
10602                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10603                                 BNX2X_DEV_INFO
10604                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10605                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10606                                 /* use primary mac as fip mac */
10607                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10608                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
10609                                 BNX2X_DEV_INFO
10610                                         ("Read FIP MAC: %pM\n", fip_mac);
10611                         }
10612                 }
10613
10614                 if (IS_MF_STORAGE_SD(bp))
10615                         /* Zero primary MAC configuration */
10616                         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10617
10618                 if (IS_MF_FCOE_AFEX(bp))
10619                         /* use FIP MAC as primary MAC */
10620                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10621
10622         } else {
10623                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10624                                 iscsi_mac_upper);
10625                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10626                                iscsi_mac_lower);
10627                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10628
10629                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10630                                 fcoe_fip_mac_upper);
10631                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10632                                fcoe_fip_mac_lower);
10633                 bnx2x_set_mac_buf(fip_mac, val, val2);
10634         }
10635
10636         /* Disable iSCSI OOO if MAC configuration is invalid. */
10637         if (!is_valid_ether_addr(iscsi_mac)) {
10638                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10639                 memset(iscsi_mac, 0, ETH_ALEN);
10640         }
10641
10642         /* Disable FCoE if MAC configuration is invalid. */
10643         if (!is_valid_ether_addr(fip_mac)) {
10644                 bp->flags |= NO_FCOE_FLAG;
10645                 memset(bp->fip_mac, 0, ETH_ALEN);
10646         }
10647 }
10648
10649 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10650 {
10651         u32 val, val2;
10652         int func = BP_ABS_FUNC(bp);
10653         int port = BP_PORT(bp);
10654
10655         /* Zero primary MAC configuration */
10656         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10657
10658         if (BP_NOMCP(bp)) {
10659                 BNX2X_ERROR("warning: random MAC workaround active\n");
10660                 eth_hw_addr_random(bp->dev);
10661         } else if (IS_MF(bp)) {
10662                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10663                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10664                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10665                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10666                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10667
10668                 if (CNIC_SUPPORT(bp))
10669                         bnx2x_get_cnic_mac_hwinfo(bp);
10670         } else {
10671                 /* in SF read MACs from port configuration */
10672                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10673                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10674                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10675
10676                 if (CNIC_SUPPORT(bp))
10677                         bnx2x_get_cnic_mac_hwinfo(bp);
10678         }
10679
10680         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10681         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10682
10683         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10684                 dev_err(&bp->pdev->dev,
10685                         "bad Ethernet MAC address configuration: %pM\n"
10686                         "change it manually before bringing up the appropriate network interface\n",
10687                         bp->dev->dev_addr);
10688 }
10689
10690 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10691 {
10692         int tmp;
10693         u32 cfg;
10694
10695         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10696                 /* Take function: tmp = func */
10697                 tmp = BP_ABS_FUNC(bp);
10698                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10699                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10700         } else {
10701                 /* Take port: tmp = port */
10702                 tmp = BP_PORT(bp);
10703                 cfg = SHMEM_RD(bp,
10704                                dev_info.port_hw_config[tmp].generic_features);
10705                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10706         }
10707         return cfg;
10708 }
10709
10710 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10711 {
10712         int /*abs*/func = BP_ABS_FUNC(bp);
10713         int vn;
10714         u32 val = 0;
10715         int rc = 0;
10716
10717         bnx2x_get_common_hwinfo(bp);
10718
10719         /*
10720          * initialize IGU parameters
10721          */
10722         if (CHIP_IS_E1x(bp)) {
10723                 bp->common.int_block = INT_BLOCK_HC;
10724
10725                 bp->igu_dsb_id = DEF_SB_IGU_ID;
10726                 bp->igu_base_sb = 0;
10727         } else {
10728                 bp->common.int_block = INT_BLOCK_IGU;
10729
10730                 /* do not allow device reset during IGU info preocessing */
10731                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10732
10733                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10734
10735                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10736                         int tout = 5000;
10737
10738                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
10739
10740                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10741                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10742                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10743
10744                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10745                                 tout--;
10746                                 usleep_range(1000, 1000);
10747                         }
10748
10749                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10750                                 dev_err(&bp->pdev->dev,
10751                                         "FORCING Normal Mode failed!!!\n");
10752                                 bnx2x_release_hw_lock(bp,
10753                                                       HW_LOCK_RESOURCE_RESET);
10754                                 return -EPERM;
10755                         }
10756                 }
10757
10758                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10759                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10760                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10761                 } else
10762                         BNX2X_DEV_INFO("IGU Normal Mode\n");
10763
10764                 rc = bnx2x_get_igu_cam_info(bp);
10765                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10766                 if (rc)
10767                         return rc;
10768         }
10769
10770         /*
10771          * set base FW non-default (fast path) status block id, this value is
10772          * used to initialize the fw_sb_id saved on the fp/queue structure to
10773          * determine the id used by the FW.
10774          */
10775         if (CHIP_IS_E1x(bp))
10776                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10777         else /*
10778               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10779               * the same queue are indicated on the same IGU SB). So we prefer
10780               * FW and IGU SBs to be the same value.
10781               */
10782                 bp->base_fw_ndsb = bp->igu_base_sb;
10783
10784         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
10785                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10786                        bp->igu_sb_cnt, bp->base_fw_ndsb);
10787
10788         /*
10789          * Initialize MF configuration
10790          */
10791
10792         bp->mf_ov = 0;
10793         bp->mf_mode = 0;
10794         vn = BP_VN(bp);
10795
10796         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10797                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10798                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
10799                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10800
10801                 if (SHMEM2_HAS(bp, mf_cfg_addr))
10802                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10803                 else
10804                         bp->common.mf_cfg_base = bp->common.shmem_base +
10805                                 offsetof(struct shmem_region, func_mb) +
10806                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10807                 /*
10808                  * get mf configuration:
10809                  * 1. existence of MF configuration
10810                  * 2. MAC address must be legal (check only upper bytes)
10811                  *    for  Switch-Independent mode;
10812                  *    OVLAN must be legal for Switch-Dependent mode
10813                  * 3. SF_MODE configures specific MF mode
10814                  */
10815                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10816                         /* get mf configuration */
10817                         val = SHMEM_RD(bp,
10818                                        dev_info.shared_feature_config.config);
10819                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10820
10821                         switch (val) {
10822                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10823                                 val = MF_CFG_RD(bp, func_mf_config[func].
10824                                                 mac_upper);
10825                                 /* check for legal mac (upper bytes)*/
10826                                 if (val != 0xffff) {
10827                                         bp->mf_mode = MULTI_FUNCTION_SI;
10828                                         bp->mf_config[vn] = MF_CFG_RD(bp,
10829                                                    func_mf_config[func].config);
10830                                 } else
10831                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
10832                                 break;
10833                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10834                                 if ((!CHIP_IS_E1x(bp)) &&
10835                                     (MF_CFG_RD(bp, func_mf_config[func].
10836                                                mac_upper) != 0xffff) &&
10837                                     (SHMEM2_HAS(bp,
10838                                                 afex_driver_support))) {
10839                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
10840                                         bp->mf_config[vn] = MF_CFG_RD(bp,
10841                                                 func_mf_config[func].config);
10842                                 } else {
10843                                         BNX2X_DEV_INFO("can not configure afex mode\n");
10844                                 }
10845                                 break;
10846                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10847                                 /* get OV configuration */
10848                                 val = MF_CFG_RD(bp,
10849                                         func_mf_config[FUNC_0].e1hov_tag);
10850                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10851
10852                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10853                                         bp->mf_mode = MULTI_FUNCTION_SD;
10854                                         bp->mf_config[vn] = MF_CFG_RD(bp,
10855                                                 func_mf_config[func].config);
10856                                 } else
10857                                         BNX2X_DEV_INFO("illegal OV for SD\n");
10858                                 break;
10859                         default:
10860                                 /* Unknown configuration: reset mf_config */
10861                                 bp->mf_config[vn] = 0;
10862                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10863                         }
10864                 }
10865
10866                 BNX2X_DEV_INFO("%s function mode\n",
10867                                IS_MF(bp) ? "multi" : "single");
10868
10869                 switch (bp->mf_mode) {
10870                 case MULTI_FUNCTION_SD:
10871                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10872                               FUNC_MF_CFG_E1HOV_TAG_MASK;
10873                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10874                                 bp->mf_ov = val;
10875                                 bp->path_has_ovlan = true;
10876
10877                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10878                                                func, bp->mf_ov, bp->mf_ov);
10879                         } else {
10880                                 dev_err(&bp->pdev->dev,
10881                                         "No valid MF OV for func %d, aborting\n",
10882                                         func);
10883                                 return -EPERM;
10884                         }
10885                         break;
10886                 case MULTI_FUNCTION_AFEX:
10887                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10888                         break;
10889                 case MULTI_FUNCTION_SI:
10890                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10891                                        func);
10892                         break;
10893                 default:
10894                         if (vn) {
10895                                 dev_err(&bp->pdev->dev,
10896                                         "VN %d is in a single function mode, aborting\n",
10897                                         vn);
10898                                 return -EPERM;
10899                         }
10900                         break;
10901                 }
10902
10903                 /* check if other port on the path needs ovlan:
10904                  * Since MF configuration is shared between ports
10905                  * Possible mixed modes are only
10906                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10907                  */
10908                 if (CHIP_MODE_IS_4_PORT(bp) &&
10909                     !bp->path_has_ovlan &&
10910                     !IS_MF(bp) &&
10911                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10912                         u8 other_port = !BP_PORT(bp);
10913                         u8 other_func = BP_PATH(bp) + 2*other_port;
10914                         val = MF_CFG_RD(bp,
10915                                         func_mf_config[other_func].e1hov_tag);
10916                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10917                                 bp->path_has_ovlan = true;
10918                 }
10919         }
10920
10921         /* adjust igu_sb_cnt to MF for E1x */
10922         if (CHIP_IS_E1x(bp) && IS_MF(bp))
10923                 bp->igu_sb_cnt /= E1HVN_MAX;
10924
10925         /* port info */
10926         bnx2x_get_port_hwinfo(bp);
10927
10928         /* Get MAC addresses */
10929         bnx2x_get_mac_hwinfo(bp);
10930
10931         bnx2x_get_cnic_info(bp);
10932
10933         return rc;
10934 }
10935
10936 static void bnx2x_read_fwinfo(struct bnx2x *bp)
10937 {
10938         int cnt, i, block_end, rodi;
10939         char vpd_start[BNX2X_VPD_LEN+1];
10940         char str_id_reg[VENDOR_ID_LEN+1];
10941         char str_id_cap[VENDOR_ID_LEN+1];
10942         char *vpd_data;
10943         char *vpd_extended_data = NULL;
10944         u8 len;
10945
10946         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10947         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10948
10949         if (cnt < BNX2X_VPD_LEN)
10950                 goto out_not_found;
10951
10952         /* VPD RO tag should be first tag after identifier string, hence
10953          * we should be able to find it in first BNX2X_VPD_LEN chars
10954          */
10955         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10956                              PCI_VPD_LRDT_RO_DATA);
10957         if (i < 0)
10958                 goto out_not_found;
10959
10960         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10961                     pci_vpd_lrdt_size(&vpd_start[i]);
10962
10963         i += PCI_VPD_LRDT_TAG_SIZE;
10964
10965         if (block_end > BNX2X_VPD_LEN) {
10966                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10967                 if (vpd_extended_data  == NULL)
10968                         goto out_not_found;
10969
10970                 /* read rest of vpd image into vpd_extended_data */
10971                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10972                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10973                                    block_end - BNX2X_VPD_LEN,
10974                                    vpd_extended_data + BNX2X_VPD_LEN);
10975                 if (cnt < (block_end - BNX2X_VPD_LEN))
10976                         goto out_not_found;
10977                 vpd_data = vpd_extended_data;
10978         } else
10979                 vpd_data = vpd_start;
10980
10981         /* now vpd_data holds full vpd content in both cases */
10982
10983         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10984                                    PCI_VPD_RO_KEYWORD_MFR_ID);
10985         if (rodi < 0)
10986                 goto out_not_found;
10987
10988         len = pci_vpd_info_field_size(&vpd_data[rodi]);
10989
10990         if (len != VENDOR_ID_LEN)
10991                 goto out_not_found;
10992
10993         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10994
10995         /* vendor specific info */
10996         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10997         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10998         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10999             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11000
11001                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11002                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11003                 if (rodi >= 0) {
11004                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11005
11006                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11007
11008                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11009                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11010                                 bp->fw_ver[len] = ' ';
11011                         }
11012                 }
11013                 kfree(vpd_extended_data);
11014                 return;
11015         }
11016 out_not_found:
11017         kfree(vpd_extended_data);
11018         return;
11019 }
11020
11021 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11022 {
11023         u32 flags = 0;
11024
11025         if (CHIP_REV_IS_FPGA(bp))
11026                 SET_FLAGS(flags, MODE_FPGA);
11027         else if (CHIP_REV_IS_EMUL(bp))
11028                 SET_FLAGS(flags, MODE_EMUL);
11029         else
11030                 SET_FLAGS(flags, MODE_ASIC);
11031
11032         if (CHIP_MODE_IS_4_PORT(bp))
11033                 SET_FLAGS(flags, MODE_PORT4);
11034         else
11035                 SET_FLAGS(flags, MODE_PORT2);
11036
11037         if (CHIP_IS_E2(bp))
11038                 SET_FLAGS(flags, MODE_E2);
11039         else if (CHIP_IS_E3(bp)) {
11040                 SET_FLAGS(flags, MODE_E3);
11041                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11042                         SET_FLAGS(flags, MODE_E3_A0);
11043                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11044                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11045         }
11046
11047         if (IS_MF(bp)) {
11048                 SET_FLAGS(flags, MODE_MF);
11049                 switch (bp->mf_mode) {
11050                 case MULTI_FUNCTION_SD:
11051                         SET_FLAGS(flags, MODE_MF_SD);
11052                         break;
11053                 case MULTI_FUNCTION_SI:
11054                         SET_FLAGS(flags, MODE_MF_SI);
11055                         break;
11056                 case MULTI_FUNCTION_AFEX:
11057                         SET_FLAGS(flags, MODE_MF_AFEX);
11058                         break;
11059                 }
11060         } else
11061                 SET_FLAGS(flags, MODE_SF);
11062
11063 #if defined(__LITTLE_ENDIAN)
11064         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11065 #else /*(__BIG_ENDIAN)*/
11066         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11067 #endif
11068         INIT_MODE_FLAGS(bp) = flags;
11069 }
11070
11071 static int bnx2x_init_bp(struct bnx2x *bp)
11072 {
11073         int func;
11074         int rc;
11075
11076         mutex_init(&bp->port.phy_mutex);
11077         mutex_init(&bp->fw_mb_mutex);
11078         spin_lock_init(&bp->stats_lock);
11079
11080
11081         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11082         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11083         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11084         rc = bnx2x_get_hwinfo(bp);
11085         if (rc)
11086                 return rc;
11087
11088         bnx2x_set_modes_bitmap(bp);
11089
11090         rc = bnx2x_alloc_mem_bp(bp);
11091         if (rc)
11092                 return rc;
11093
11094         bnx2x_read_fwinfo(bp);
11095
11096         func = BP_FUNC(bp);
11097
11098         /* need to reset chip if undi was active */
11099         if (!BP_NOMCP(bp)) {
11100                 /* init fw_seq */
11101                 bp->fw_seq =
11102                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11103                                                         DRV_MSG_SEQ_NUMBER_MASK;
11104                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11105
11106                 bnx2x_prev_unload(bp);
11107         }
11108
11109
11110         if (CHIP_REV_IS_FPGA(bp))
11111                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11112
11113         if (BP_NOMCP(bp) && (func == 0))
11114                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11115
11116         bp->disable_tpa = disable_tpa;
11117         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11118
11119         /* Set TPA flags */
11120         if (bp->disable_tpa) {
11121                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11122                 bp->dev->features &= ~NETIF_F_LRO;
11123         } else {
11124                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11125                 bp->dev->features |= NETIF_F_LRO;
11126         }
11127
11128         if (CHIP_IS_E1(bp))
11129                 bp->dropless_fc = 0;
11130         else
11131                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11132
11133         bp->mrrs = mrrs;
11134
11135         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11136
11137         /* make sure that the numbers are in the right granularity */
11138         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11139         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11140
11141         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11142
11143         init_timer(&bp->timer);
11144         bp->timer.expires = jiffies + bp->current_interval;
11145         bp->timer.data = (unsigned long) bp;
11146         bp->timer.function = bnx2x_timer;
11147
11148         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11149             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11150             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11151             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11152                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11153                 bnx2x_dcbx_init_params(bp);
11154         } else {
11155                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11156         }
11157
11158         if (CHIP_IS_E1x(bp))
11159                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11160         else
11161                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11162
11163         /* multiple tx priority */
11164         if (CHIP_IS_E1x(bp))
11165                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11166         if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11167                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11168         if (CHIP_IS_E3B0(bp))
11169                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11170
11171         /* We need at least one default status block for slow-path events,
11172          * second status block for the L2 queue, and a third status block for
11173          * CNIC if supproted.
11174          */
11175         if (CNIC_SUPPORT(bp))
11176                 bp->min_msix_vec_cnt = 3;
11177         else
11178                 bp->min_msix_vec_cnt = 2;
11179         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11180
11181         return rc;
11182 }
11183
11184
11185 /****************************************************************************
11186 * General service functions
11187 ****************************************************************************/
11188
11189 /*
11190  * net_device service functions
11191  */
11192
11193 /* called with rtnl_lock */
11194 static int bnx2x_open(struct net_device *dev)
11195 {
11196         struct bnx2x *bp = netdev_priv(dev);
11197         bool global = false;
11198         int other_engine = BP_PATH(bp) ? 0 : 1;
11199         bool other_load_status, load_status;
11200
11201         bp->stats_init = true;
11202
11203         netif_carrier_off(dev);
11204
11205         bnx2x_set_power_state(bp, PCI_D0);
11206
11207         other_load_status = bnx2x_get_load_status(bp, other_engine);
11208         load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11209
11210         /*
11211          * If parity had happen during the unload, then attentions
11212          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11213          * want the first function loaded on the current engine to
11214          * complete the recovery.
11215          */
11216         if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11217             bnx2x_chk_parity_attn(bp, &global, true))
11218                 do {
11219                         /*
11220                          * If there are attentions and they are in a global
11221                          * blocks, set the GLOBAL_RESET bit regardless whether
11222                          * it will be this function that will complete the
11223                          * recovery or not.
11224                          */
11225                         if (global)
11226                                 bnx2x_set_reset_global(bp);
11227
11228                         /*
11229                          * Only the first function on the current engine should
11230                          * try to recover in open. In case of attentions in
11231                          * global blocks only the first in the chip should try
11232                          * to recover.
11233                          */
11234                         if ((!load_status &&
11235                              (!global || !other_load_status)) &&
11236                             bnx2x_trylock_leader_lock(bp) &&
11237                             !bnx2x_leader_reset(bp)) {
11238                                 netdev_info(bp->dev, "Recovered in open\n");
11239                                 break;
11240                         }
11241
11242                         /* recovery has failed... */
11243                         bnx2x_set_power_state(bp, PCI_D3hot);
11244                         bp->recovery_state = BNX2X_RECOVERY_FAILED;
11245
11246                         BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11247                                   "If you still see this message after a few retries then power cycle is required.\n");
11248
11249                         return -EAGAIN;
11250                 } while (0);
11251
11252         bp->recovery_state = BNX2X_RECOVERY_DONE;
11253         return bnx2x_nic_load(bp, LOAD_OPEN);
11254 }
11255
11256 /* called with rtnl_lock */
11257 static int bnx2x_close(struct net_device *dev)
11258 {
11259         struct bnx2x *bp = netdev_priv(dev);
11260
11261         /* Unload the driver, release IRQs */
11262         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11263
11264         /* Power off */
11265         bnx2x_set_power_state(bp, PCI_D3hot);
11266
11267         return 0;
11268 }
11269
11270 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11271                                       struct bnx2x_mcast_ramrod_params *p)
11272 {
11273         int mc_count = netdev_mc_count(bp->dev);
11274         struct bnx2x_mcast_list_elem *mc_mac =
11275                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11276         struct netdev_hw_addr *ha;
11277
11278         if (!mc_mac)
11279                 return -ENOMEM;
11280
11281         INIT_LIST_HEAD(&p->mcast_list);
11282
11283         netdev_for_each_mc_addr(ha, bp->dev) {
11284                 mc_mac->mac = bnx2x_mc_addr(ha);
11285                 list_add_tail(&mc_mac->link, &p->mcast_list);
11286                 mc_mac++;
11287         }
11288
11289         p->mcast_list_len = mc_count;
11290
11291         return 0;
11292 }
11293
11294 static void bnx2x_free_mcast_macs_list(
11295         struct bnx2x_mcast_ramrod_params *p)
11296 {
11297         struct bnx2x_mcast_list_elem *mc_mac =
11298                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11299                                  link);
11300
11301         WARN_ON(!mc_mac);
11302         kfree(mc_mac);
11303 }
11304
11305 /**
11306  * bnx2x_set_uc_list - configure a new unicast MACs list.
11307  *
11308  * @bp: driver handle
11309  *
11310  * We will use zero (0) as a MAC type for these MACs.
11311  */
11312 static int bnx2x_set_uc_list(struct bnx2x *bp)
11313 {
11314         int rc;
11315         struct net_device *dev = bp->dev;
11316         struct netdev_hw_addr *ha;
11317         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11318         unsigned long ramrod_flags = 0;
11319
11320         /* First schedule a cleanup up of old configuration */
11321         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11322         if (rc < 0) {
11323                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11324                 return rc;
11325         }
11326
11327         netdev_for_each_uc_addr(ha, dev) {
11328                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11329                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11330                 if (rc == -EEXIST) {
11331                         DP(BNX2X_MSG_SP,
11332                            "Failed to schedule ADD operations: %d\n", rc);
11333                         /* do not treat adding same MAC as error */
11334                         rc = 0;
11335
11336                 } else if (rc < 0) {
11337
11338                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11339                                   rc);
11340                         return rc;
11341                 }
11342         }
11343
11344         /* Execute the pending commands */
11345         __set_bit(RAMROD_CONT, &ramrod_flags);
11346         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11347                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11348 }
11349
11350 static int bnx2x_set_mc_list(struct bnx2x *bp)
11351 {
11352         struct net_device *dev = bp->dev;
11353         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11354         int rc = 0;
11355
11356         rparam.mcast_obj = &bp->mcast_obj;
11357
11358         /* first, clear all configured multicast MACs */
11359         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11360         if (rc < 0) {
11361                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11362                 return rc;
11363         }
11364
11365         /* then, configure a new MACs list */
11366         if (netdev_mc_count(dev)) {
11367                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11368                 if (rc) {
11369                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11370                                   rc);
11371                         return rc;
11372                 }
11373
11374                 /* Now add the new MACs */
11375                 rc = bnx2x_config_mcast(bp, &rparam,
11376                                         BNX2X_MCAST_CMD_ADD);
11377                 if (rc < 0)
11378                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11379                                   rc);
11380
11381                 bnx2x_free_mcast_macs_list(&rparam);
11382         }
11383
11384         return rc;
11385 }
11386
11387
11388 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11389 void bnx2x_set_rx_mode(struct net_device *dev)
11390 {
11391         struct bnx2x *bp = netdev_priv(dev);
11392         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11393
11394         if (bp->state != BNX2X_STATE_OPEN) {
11395                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11396                 return;
11397         }
11398
11399         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11400
11401         if (dev->flags & IFF_PROMISC)
11402                 rx_mode = BNX2X_RX_MODE_PROMISC;
11403         else if ((dev->flags & IFF_ALLMULTI) ||
11404                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11405                   CHIP_IS_E1(bp)))
11406                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11407         else {
11408                 /* some multicasts */
11409                 if (bnx2x_set_mc_list(bp) < 0)
11410                         rx_mode = BNX2X_RX_MODE_ALLMULTI;
11411
11412                 if (bnx2x_set_uc_list(bp) < 0)
11413                         rx_mode = BNX2X_RX_MODE_PROMISC;
11414         }
11415
11416         bp->rx_mode = rx_mode;
11417         /* handle ISCSI SD mode */
11418         if (IS_MF_ISCSI_SD(bp))
11419                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11420
11421         /* Schedule the rx_mode command */
11422         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11423                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11424                 return;
11425         }
11426
11427         bnx2x_set_storm_rx_mode(bp);
11428 }
11429
11430 /* called with rtnl_lock */
11431 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11432                            int devad, u16 addr)
11433 {
11434         struct bnx2x *bp = netdev_priv(netdev);
11435         u16 value;
11436         int rc;
11437
11438         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11439            prtad, devad, addr);
11440
11441         /* The HW expects different devad if CL22 is used */
11442         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11443
11444         bnx2x_acquire_phy_lock(bp);
11445         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11446         bnx2x_release_phy_lock(bp);
11447         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11448
11449         if (!rc)
11450                 rc = value;
11451         return rc;
11452 }
11453
11454 /* called with rtnl_lock */
11455 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11456                             u16 addr, u16 value)
11457 {
11458         struct bnx2x *bp = netdev_priv(netdev);
11459         int rc;
11460
11461         DP(NETIF_MSG_LINK,
11462            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11463            prtad, devad, addr, value);
11464
11465         /* The HW expects different devad if CL22 is used */
11466         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11467
11468         bnx2x_acquire_phy_lock(bp);
11469         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11470         bnx2x_release_phy_lock(bp);
11471         return rc;
11472 }
11473
11474 /* called with rtnl_lock */
11475 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11476 {
11477         struct bnx2x *bp = netdev_priv(dev);
11478         struct mii_ioctl_data *mdio = if_mii(ifr);
11479
11480         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11481            mdio->phy_id, mdio->reg_num, mdio->val_in);
11482
11483         if (!netif_running(dev))
11484                 return -EAGAIN;
11485
11486         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11487 }
11488
11489 #ifdef CONFIG_NET_POLL_CONTROLLER
11490 static void poll_bnx2x(struct net_device *dev)
11491 {
11492         struct bnx2x *bp = netdev_priv(dev);
11493         int i;
11494
11495         for_each_eth_queue(bp, i) {
11496                 struct bnx2x_fastpath *fp = &bp->fp[i];
11497                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11498         }
11499 }
11500 #endif
11501
11502 static int bnx2x_validate_addr(struct net_device *dev)
11503 {
11504         struct bnx2x *bp = netdev_priv(dev);
11505
11506         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11507                 BNX2X_ERR("Non-valid Ethernet address\n");
11508                 return -EADDRNOTAVAIL;
11509         }
11510         return 0;
11511 }
11512
11513 static const struct net_device_ops bnx2x_netdev_ops = {
11514         .ndo_open               = bnx2x_open,
11515         .ndo_stop               = bnx2x_close,
11516         .ndo_start_xmit         = bnx2x_start_xmit,
11517         .ndo_select_queue       = bnx2x_select_queue,
11518         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
11519         .ndo_set_mac_address    = bnx2x_change_mac_addr,
11520         .ndo_validate_addr      = bnx2x_validate_addr,
11521         .ndo_do_ioctl           = bnx2x_ioctl,
11522         .ndo_change_mtu         = bnx2x_change_mtu,
11523         .ndo_fix_features       = bnx2x_fix_features,
11524         .ndo_set_features       = bnx2x_set_features,
11525         .ndo_tx_timeout         = bnx2x_tx_timeout,
11526 #ifdef CONFIG_NET_POLL_CONTROLLER
11527         .ndo_poll_controller    = poll_bnx2x,
11528 #endif
11529         .ndo_setup_tc           = bnx2x_setup_tc,
11530
11531 #ifdef NETDEV_FCOE_WWNN
11532         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
11533 #endif
11534 };
11535
11536 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11537 {
11538         struct device *dev = &bp->pdev->dev;
11539
11540         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11541                 bp->flags |= USING_DAC_FLAG;
11542                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11543                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11544                         return -EIO;
11545                 }
11546         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11547                 dev_err(dev, "System does not support DMA, aborting\n");
11548                 return -EIO;
11549         }
11550
11551         return 0;
11552 }
11553
11554 static int bnx2x_init_dev(struct pci_dev *pdev, struct net_device *dev,
11555                           unsigned long board_type)
11556 {
11557         struct bnx2x *bp;
11558         int rc;
11559         u32 pci_cfg_dword;
11560         bool chip_is_e1x = (board_type == BCM57710 ||
11561                             board_type == BCM57711 ||
11562                             board_type == BCM57711E);
11563
11564         SET_NETDEV_DEV(dev, &pdev->dev);
11565         bp = netdev_priv(dev);
11566
11567         bp->dev = dev;
11568         bp->pdev = pdev;
11569         bp->flags = 0;
11570
11571         rc = pci_enable_device(pdev);
11572         if (rc) {
11573                 dev_err(&bp->pdev->dev,
11574                         "Cannot enable PCI device, aborting\n");
11575                 goto err_out;
11576         }
11577
11578         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11579                 dev_err(&bp->pdev->dev,
11580                         "Cannot find PCI device base address, aborting\n");
11581                 rc = -ENODEV;
11582                 goto err_out_disable;
11583         }
11584
11585         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11586                 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
11587                        " base address, aborting\n");
11588                 rc = -ENODEV;
11589                 goto err_out_disable;
11590         }
11591
11592         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11593         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11594             PCICFG_REVESION_ID_ERROR_VAL) {
11595                 pr_err("PCI device error, probably due to fan failure, aborting\n");
11596                 rc = -ENODEV;
11597                 goto err_out_disable;
11598         }
11599
11600         if (atomic_read(&pdev->enable_cnt) == 1) {
11601                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11602                 if (rc) {
11603                         dev_err(&bp->pdev->dev,
11604                                 "Cannot obtain PCI resources, aborting\n");
11605                         goto err_out_disable;
11606                 }
11607
11608                 pci_set_master(pdev);
11609                 pci_save_state(pdev);
11610         }
11611
11612         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11613         if (bp->pm_cap == 0) {
11614                 dev_err(&bp->pdev->dev,
11615                         "Cannot find power management capability, aborting\n");
11616                 rc = -EIO;
11617                 goto err_out_release;
11618         }
11619
11620         if (!pci_is_pcie(pdev)) {
11621                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11622                 rc = -EIO;
11623                 goto err_out_release;
11624         }
11625
11626         rc = bnx2x_set_coherency_mask(bp);
11627         if (rc)
11628                 goto err_out_release;
11629
11630         dev->mem_start = pci_resource_start(pdev, 0);
11631         dev->base_addr = dev->mem_start;
11632         dev->mem_end = pci_resource_end(pdev, 0);
11633
11634         dev->irq = pdev->irq;
11635
11636         bp->regview = pci_ioremap_bar(pdev, 0);
11637         if (!bp->regview) {
11638                 dev_err(&bp->pdev->dev,
11639                         "Cannot map register space, aborting\n");
11640                 rc = -ENOMEM;
11641                 goto err_out_release;
11642         }
11643
11644         /* In E1/E1H use pci device function given by kernel.
11645          * In E2/E3 read physical function from ME register since these chips
11646          * support Physical Device Assignment where kernel BDF maybe arbitrary
11647          * (depending on hypervisor).
11648          */
11649         if (chip_is_e1x)
11650                 bp->pf_num = PCI_FUNC(pdev->devfn);
11651         else {/* chip is E2/3*/
11652                 pci_read_config_dword(bp->pdev,
11653                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
11654                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11655                     ME_REG_ABS_PF_NUM_SHIFT);
11656         }
11657         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11658
11659         bnx2x_set_power_state(bp, PCI_D0);
11660
11661         /* clean indirect addresses */
11662         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11663                                PCICFG_VENDOR_ID_OFFSET);
11664         /*
11665          * Clean the following indirect addresses for all functions since it
11666          * is not used by the driver.
11667          */
11668         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11669         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11670         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11671         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11672
11673         if (chip_is_e1x) {
11674                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11675                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11676                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11677                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11678         }
11679
11680         /*
11681          * Enable internal target-read (in case we are probed after PF FLR).
11682          * Must be done prior to any BAR read access. Only for 57712 and up
11683          */
11684         if (!chip_is_e1x)
11685                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11686
11687         dev->watchdog_timeo = TX_TIMEOUT;
11688
11689         dev->netdev_ops = &bnx2x_netdev_ops;
11690         bnx2x_set_ethtool_ops(dev);
11691
11692         dev->priv_flags |= IFF_UNICAST_FLT;
11693
11694         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11695                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11696                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11697                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11698
11699         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11700                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11701
11702         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11703         if (bp->flags & USING_DAC_FLAG)
11704                 dev->features |= NETIF_F_HIGHDMA;
11705
11706         /* Add Loopback capability to the device */
11707         dev->hw_features |= NETIF_F_LOOPBACK;
11708
11709 #ifdef BCM_DCBNL
11710         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11711 #endif
11712
11713         /* get_port_hwinfo() will set prtad and mmds properly */
11714         bp->mdio.prtad = MDIO_PRTAD_NONE;
11715         bp->mdio.mmds = 0;
11716         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11717         bp->mdio.dev = dev;
11718         bp->mdio.mdio_read = bnx2x_mdio_read;
11719         bp->mdio.mdio_write = bnx2x_mdio_write;
11720
11721         return 0;
11722
11723 err_out_release:
11724         if (atomic_read(&pdev->enable_cnt) == 1)
11725                 pci_release_regions(pdev);
11726
11727 err_out_disable:
11728         pci_disable_device(pdev);
11729         pci_set_drvdata(pdev, NULL);
11730
11731 err_out:
11732         return rc;
11733 }
11734
11735 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
11736 {
11737         u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11738
11739         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11740
11741         /* return value of 1=2.5GHz 2=5GHz */
11742         *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11743 }
11744
11745 static int bnx2x_check_firmware(struct bnx2x *bp)
11746 {
11747         const struct firmware *firmware = bp->firmware;
11748         struct bnx2x_fw_file_hdr *fw_hdr;
11749         struct bnx2x_fw_file_section *sections;
11750         u32 offset, len, num_ops;
11751         u16 *ops_offsets;
11752         int i;
11753         const u8 *fw_ver;
11754
11755         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11756                 BNX2X_ERR("Wrong FW size\n");
11757                 return -EINVAL;
11758         }
11759
11760         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11761         sections = (struct bnx2x_fw_file_section *)fw_hdr;
11762
11763         /* Make sure none of the offsets and sizes make us read beyond
11764          * the end of the firmware data */
11765         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11766                 offset = be32_to_cpu(sections[i].offset);
11767                 len = be32_to_cpu(sections[i].len);
11768                 if (offset + len > firmware->size) {
11769                         BNX2X_ERR("Section %d length is out of bounds\n", i);
11770                         return -EINVAL;
11771                 }
11772         }
11773
11774         /* Likewise for the init_ops offsets */
11775         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11776         ops_offsets = (u16 *)(firmware->data + offset);
11777         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11778
11779         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11780                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11781                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
11782                         return -EINVAL;
11783                 }
11784         }
11785
11786         /* Check FW version */
11787         offset = be32_to_cpu(fw_hdr->fw_version.offset);
11788         fw_ver = firmware->data + offset;
11789         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11790             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11791             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11792             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11793                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11794                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11795                        BCM_5710_FW_MAJOR_VERSION,
11796                        BCM_5710_FW_MINOR_VERSION,
11797                        BCM_5710_FW_REVISION_VERSION,
11798                        BCM_5710_FW_ENGINEERING_VERSION);
11799                 return -EINVAL;
11800         }
11801
11802         return 0;
11803 }
11804
11805 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11806 {
11807         const __be32 *source = (const __be32 *)_source;
11808         u32 *target = (u32 *)_target;
11809         u32 i;
11810
11811         for (i = 0; i < n/4; i++)
11812                 target[i] = be32_to_cpu(source[i]);
11813 }
11814
11815 /*
11816    Ops array is stored in the following format:
11817    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11818  */
11819 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11820 {
11821         const __be32 *source = (const __be32 *)_source;
11822         struct raw_op *target = (struct raw_op *)_target;
11823         u32 i, j, tmp;
11824
11825         for (i = 0, j = 0; i < n/8; i++, j += 2) {
11826                 tmp = be32_to_cpu(source[j]);
11827                 target[i].op = (tmp >> 24) & 0xff;
11828                 target[i].offset = tmp & 0xffffff;
11829                 target[i].raw_data = be32_to_cpu(source[j + 1]);
11830         }
11831 }
11832
11833 /* IRO array is stored in the following format:
11834  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11835  */
11836 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11837 {
11838         const __be32 *source = (const __be32 *)_source;
11839         struct iro *target = (struct iro *)_target;
11840         u32 i, j, tmp;
11841
11842         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11843                 target[i].base = be32_to_cpu(source[j]);
11844                 j++;
11845                 tmp = be32_to_cpu(source[j]);
11846                 target[i].m1 = (tmp >> 16) & 0xffff;
11847                 target[i].m2 = tmp & 0xffff;
11848                 j++;
11849                 tmp = be32_to_cpu(source[j]);
11850                 target[i].m3 = (tmp >> 16) & 0xffff;
11851                 target[i].size = tmp & 0xffff;
11852                 j++;
11853         }
11854 }
11855
11856 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11857 {
11858         const __be16 *source = (const __be16 *)_source;
11859         u16 *target = (u16 *)_target;
11860         u32 i;
11861
11862         for (i = 0; i < n/2; i++)
11863                 target[i] = be16_to_cpu(source[i]);
11864 }
11865
11866 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
11867 do {                                                                    \
11868         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
11869         bp->arr = kmalloc(len, GFP_KERNEL);                             \
11870         if (!bp->arr)                                                   \
11871                 goto lbl;                                               \
11872         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
11873              (u8 *)bp->arr, len);                                       \
11874 } while (0)
11875
11876 static int bnx2x_init_firmware(struct bnx2x *bp)
11877 {
11878         const char *fw_file_name;
11879         struct bnx2x_fw_file_hdr *fw_hdr;
11880         int rc;
11881
11882         if (bp->firmware)
11883                 return 0;
11884
11885         if (CHIP_IS_E1(bp))
11886                 fw_file_name = FW_FILE_NAME_E1;
11887         else if (CHIP_IS_E1H(bp))
11888                 fw_file_name = FW_FILE_NAME_E1H;
11889         else if (!CHIP_IS_E1x(bp))
11890                 fw_file_name = FW_FILE_NAME_E2;
11891         else {
11892                 BNX2X_ERR("Unsupported chip revision\n");
11893                 return -EINVAL;
11894         }
11895         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11896
11897         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11898         if (rc) {
11899                 BNX2X_ERR("Can't load firmware file %s\n",
11900                           fw_file_name);
11901                 goto request_firmware_exit;
11902         }
11903
11904         rc = bnx2x_check_firmware(bp);
11905         if (rc) {
11906                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11907                 goto request_firmware_exit;
11908         }
11909
11910         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11911
11912         /* Initialize the pointers to the init arrays */
11913         /* Blob */
11914         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11915
11916         /* Opcodes */
11917         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11918
11919         /* Offsets */
11920         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11921                             be16_to_cpu_n);
11922
11923         /* STORMs firmware */
11924         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11925                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11926         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
11927                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11928         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11929                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11930         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
11931                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
11932         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11933                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11934         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
11935                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11936         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11937                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11938         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
11939                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
11940         /* IRO */
11941         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11942
11943         return 0;
11944
11945 iro_alloc_err:
11946         kfree(bp->init_ops_offsets);
11947 init_offsets_alloc_err:
11948         kfree(bp->init_ops);
11949 init_ops_alloc_err:
11950         kfree(bp->init_data);
11951 request_firmware_exit:
11952         release_firmware(bp->firmware);
11953         bp->firmware = NULL;
11954
11955         return rc;
11956 }
11957
11958 static void bnx2x_release_firmware(struct bnx2x *bp)
11959 {
11960         kfree(bp->init_ops_offsets);
11961         kfree(bp->init_ops);
11962         kfree(bp->init_data);
11963         release_firmware(bp->firmware);
11964         bp->firmware = NULL;
11965 }
11966
11967
11968 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11969         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11970         .init_hw_cmn      = bnx2x_init_hw_common,
11971         .init_hw_port     = bnx2x_init_hw_port,
11972         .init_hw_func     = bnx2x_init_hw_func,
11973
11974         .reset_hw_cmn     = bnx2x_reset_common,
11975         .reset_hw_port    = bnx2x_reset_port,
11976         .reset_hw_func    = bnx2x_reset_func,
11977
11978         .gunzip_init      = bnx2x_gunzip_init,
11979         .gunzip_end       = bnx2x_gunzip_end,
11980
11981         .init_fw          = bnx2x_init_firmware,
11982         .release_fw       = bnx2x_release_firmware,
11983 };
11984
11985 void bnx2x__init_func_obj(struct bnx2x *bp)
11986 {
11987         /* Prepare DMAE related driver resources */
11988         bnx2x_setup_dmae(bp);
11989
11990         bnx2x_init_func_obj(bp, &bp->func_obj,
11991                             bnx2x_sp(bp, func_rdata),
11992                             bnx2x_sp_mapping(bp, func_rdata),
11993                             bnx2x_sp(bp, func_afex_rdata),
11994                             bnx2x_sp_mapping(bp, func_afex_rdata),
11995                             &bnx2x_func_sp_drv);
11996 }
11997
11998 /* must be called after sriov-enable */
11999 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12000 {
12001         int cid_count = BNX2X_L2_MAX_CID(bp);
12002
12003         if (CNIC_SUPPORT(bp))
12004                 cid_count += CNIC_CID_MAX;
12005         return roundup(cid_count, QM_CID_ROUND);
12006 }
12007
12008 /**
12009  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12010  *
12011  * @dev:        pci device
12012  *
12013  */
12014 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12015                                      int cnic_cnt)
12016 {
12017         int pos;
12018         u16 control;
12019
12020         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12021
12022         /*
12023          * If MSI-X is not supported - return number of SBs needed to support
12024          * one fast path queue: one FP queue + SB for CNIC
12025          */
12026         if (!pos)
12027                 return 1 + cnic_cnt;
12028
12029         /*
12030          * The value in the PCI configuration space is the index of the last
12031          * entry, namely one less than the actual size of the table, which is
12032          * exactly what we want to return from this function: number of all SBs
12033          * without the default SB.
12034          */
12035         pci_read_config_word(pdev, pos  + PCI_MSI_FLAGS, &control);
12036         return control & PCI_MSIX_FLAGS_QSIZE;
12037 }
12038
12039 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *);
12040
12041 static int bnx2x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
12042 {
12043         struct net_device *dev = NULL;
12044         struct bnx2x *bp;
12045         int pcie_width, pcie_speed;
12046         int rc, max_non_def_sbs;
12047         int rx_count, tx_count, rss_count, doorbell_size;
12048         int cnic_cnt;
12049         /*
12050          * An estimated maximum supported CoS number according to the chip
12051          * version.
12052          * We will try to roughly estimate the maximum number of CoSes this chip
12053          * may support in order to minimize the memory allocated for Tx
12054          * netdev_queue's. This number will be accurately calculated during the
12055          * initialization of bp->max_cos based on the chip versions AND chip
12056          * revision in the bnx2x_init_bp().
12057          */
12058         u8 max_cos_est = 0;
12059
12060         switch (ent->driver_data) {
12061         case BCM57710:
12062         case BCM57711:
12063         case BCM57711E:
12064                 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
12065                 break;
12066
12067         case BCM57712:
12068         case BCM57712_MF:
12069                 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
12070                 break;
12071
12072         case BCM57800:
12073         case BCM57800_MF:
12074         case BCM57810:
12075         case BCM57810_MF:
12076         case BCM57840_O:
12077         case BCM57840_4_10:
12078         case BCM57840_2_20:
12079         case BCM57840_MFO:
12080         case BCM57840_MF:
12081         case BCM57811:
12082         case BCM57811_MF:
12083                 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
12084                 break;
12085
12086         default:
12087                 pr_err("Unknown board_type (%ld), aborting\n",
12088                            ent->driver_data);
12089                 return -ENODEV;
12090         }
12091
12092         cnic_cnt = 1;
12093         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12094
12095         WARN_ON(!max_non_def_sbs);
12096
12097         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12098         rss_count = max_non_def_sbs - cnic_cnt;
12099
12100         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12101         rx_count = rss_count + cnic_cnt;
12102
12103         /*
12104          * Maximum number of netdev Tx queues:
12105          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12106          */
12107         tx_count = rss_count * max_cos_est + cnic_cnt;
12108
12109         /* dev zeroed in init_etherdev */
12110         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12111         if (!dev)
12112                 return -ENOMEM;
12113
12114         bp = netdev_priv(dev);
12115
12116         bp->igu_sb_cnt = max_non_def_sbs;
12117         bp->msg_enable = debug;
12118         bp->cnic_support = cnic_cnt;
12119         bp->cnic_probe = bnx2x_cnic_probe;
12120
12121         pci_set_drvdata(pdev, dev);
12122
12123         rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
12124         if (rc < 0) {
12125                 free_netdev(dev);
12126                 return rc;
12127         }
12128
12129         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12130         BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
12131
12132         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12133                           tx_count, rx_count);
12134
12135         rc = bnx2x_init_bp(bp);
12136         if (rc)
12137                 goto init_one_exit;
12138
12139         /*
12140          * Map doorbels here as we need the real value of bp->max_cos which
12141          * is initialized in bnx2x_init_bp().
12142          */
12143         doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12144         if (doorbell_size > pci_resource_len(pdev, 2)) {
12145                 dev_err(&bp->pdev->dev,
12146                         "Cannot map doorbells, bar size too small, aborting\n");
12147                 rc = -ENOMEM;
12148                 goto init_one_exit;
12149         }
12150         bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12151                                         doorbell_size);
12152         if (!bp->doorbells) {
12153                 dev_err(&bp->pdev->dev,
12154                         "Cannot map doorbell space, aborting\n");
12155                 rc = -ENOMEM;
12156                 goto init_one_exit;
12157         }
12158
12159         /* calc qm_cid_count */
12160         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12161
12162         /* disable FCOE L2 queue for E1x*/
12163         if (CHIP_IS_E1x(bp))
12164                 bp->flags |= NO_FCOE_FLAG;
12165
12166         /* disable FCOE for 57840 device, until FW supports it */
12167         switch (ent->driver_data) {
12168         case BCM57840_O:
12169         case BCM57840_4_10:
12170         case BCM57840_2_20:
12171         case BCM57840_MFO:
12172         case BCM57840_MF:
12173                 bp->flags |= NO_FCOE_FLAG;
12174         }
12175
12176         /* Set bp->num_queues for MSI-X mode*/
12177         bnx2x_set_num_queues(bp);
12178
12179         /* Configure interrupt mode: try to enable MSI-X/MSI if
12180          * needed.
12181          */
12182         bnx2x_set_int_mode(bp);
12183
12184         rc = register_netdev(dev);
12185         if (rc) {
12186                 dev_err(&pdev->dev, "Cannot register net device\n");
12187                 goto init_one_exit;
12188         }
12189
12190
12191         if (!NO_FCOE(bp)) {
12192                 /* Add storage MAC address */
12193                 rtnl_lock();
12194                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12195                 rtnl_unlock();
12196         }
12197
12198         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12199
12200         BNX2X_DEV_INFO(
12201                 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12202                     board_info[ent->driver_data].name,
12203                     (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12204                     pcie_width,
12205                     ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12206                      (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12207                     "5GHz (Gen2)" : "2.5GHz",
12208                     dev->base_addr, bp->pdev->irq, dev->dev_addr);
12209
12210         return 0;
12211
12212 init_one_exit:
12213         if (bp->regview)
12214                 iounmap(bp->regview);
12215
12216         if (bp->doorbells)
12217                 iounmap(bp->doorbells);
12218
12219         free_netdev(dev);
12220
12221         if (atomic_read(&pdev->enable_cnt) == 1)
12222                 pci_release_regions(pdev);
12223
12224         pci_disable_device(pdev);
12225         pci_set_drvdata(pdev, NULL);
12226
12227         return rc;
12228 }
12229
12230 static void bnx2x_remove_one(struct pci_dev *pdev)
12231 {
12232         struct net_device *dev = pci_get_drvdata(pdev);
12233         struct bnx2x *bp;
12234
12235         if (!dev) {
12236                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12237                 return;
12238         }
12239         bp = netdev_priv(dev);
12240
12241         /* Delete storage MAC address */
12242         if (!NO_FCOE(bp)) {
12243                 rtnl_lock();
12244                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12245                 rtnl_unlock();
12246         }
12247
12248 #ifdef BCM_DCBNL
12249         /* Delete app tlvs from dcbnl */
12250         bnx2x_dcbnl_update_applist(bp, true);
12251 #endif
12252
12253         unregister_netdev(dev);
12254
12255         /* Power on: we can't let PCI layer write to us while we are in D3 */
12256         bnx2x_set_power_state(bp, PCI_D0);
12257
12258         /* Disable MSI/MSI-X */
12259         bnx2x_disable_msi(bp);
12260
12261         /* Power off */
12262         bnx2x_set_power_state(bp, PCI_D3hot);
12263
12264         /* Make sure RESET task is not scheduled before continuing */
12265         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12266
12267         if (bp->regview)
12268                 iounmap(bp->regview);
12269
12270         if (bp->doorbells)
12271                 iounmap(bp->doorbells);
12272
12273         bnx2x_release_firmware(bp);
12274
12275         bnx2x_free_mem_bp(bp);
12276
12277         free_netdev(dev);
12278
12279         if (atomic_read(&pdev->enable_cnt) == 1)
12280                 pci_release_regions(pdev);
12281
12282         pci_disable_device(pdev);
12283         pci_set_drvdata(pdev, NULL);
12284 }
12285
12286 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12287 {
12288         int i;
12289
12290         bp->state = BNX2X_STATE_ERROR;
12291
12292         bp->rx_mode = BNX2X_RX_MODE_NONE;
12293
12294         if (CNIC_LOADED(bp))
12295                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12296
12297         /* Stop Tx */
12298         bnx2x_tx_disable(bp);
12299
12300         bnx2x_netif_stop(bp, 0);
12301         /* Delete all NAPI objects */
12302         bnx2x_del_all_napi(bp);
12303         if (CNIC_LOADED(bp))
12304                 bnx2x_del_all_napi_cnic(bp);
12305
12306         del_timer_sync(&bp->timer);
12307
12308         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12309
12310         /* Release IRQs */
12311         bnx2x_free_irq(bp);
12312
12313         /* Free SKBs, SGEs, TPA pool and driver internals */
12314         bnx2x_free_skbs(bp);
12315
12316         for_each_rx_queue(bp, i)
12317                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12318
12319         bnx2x_free_mem(bp);
12320
12321         bp->state = BNX2X_STATE_CLOSED;
12322
12323         netif_carrier_off(bp->dev);
12324
12325         return 0;
12326 }
12327
12328 static void bnx2x_eeh_recover(struct bnx2x *bp)
12329 {
12330         u32 val;
12331
12332         mutex_init(&bp->port.phy_mutex);
12333
12334
12335         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12336         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12337                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12338                 BNX2X_ERR("BAD MCP validity signature\n");
12339 }
12340
12341 /**
12342  * bnx2x_io_error_detected - called when PCI error is detected
12343  * @pdev: Pointer to PCI device
12344  * @state: The current pci connection state
12345  *
12346  * This function is called after a PCI bus error affecting
12347  * this device has been detected.
12348  */
12349 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12350                                                 pci_channel_state_t state)
12351 {
12352         struct net_device *dev = pci_get_drvdata(pdev);
12353         struct bnx2x *bp = netdev_priv(dev);
12354
12355         rtnl_lock();
12356
12357         netif_device_detach(dev);
12358
12359         if (state == pci_channel_io_perm_failure) {
12360                 rtnl_unlock();
12361                 return PCI_ERS_RESULT_DISCONNECT;
12362         }
12363
12364         if (netif_running(dev))
12365                 bnx2x_eeh_nic_unload(bp);
12366
12367         pci_disable_device(pdev);
12368
12369         rtnl_unlock();
12370
12371         /* Request a slot reset */
12372         return PCI_ERS_RESULT_NEED_RESET;
12373 }
12374
12375 /**
12376  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12377  * @pdev: Pointer to PCI device
12378  *
12379  * Restart the card from scratch, as if from a cold-boot.
12380  */
12381 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12382 {
12383         struct net_device *dev = pci_get_drvdata(pdev);
12384         struct bnx2x *bp = netdev_priv(dev);
12385
12386         rtnl_lock();
12387
12388         if (pci_enable_device(pdev)) {
12389                 dev_err(&pdev->dev,
12390                         "Cannot re-enable PCI device after reset\n");
12391                 rtnl_unlock();
12392                 return PCI_ERS_RESULT_DISCONNECT;
12393         }
12394
12395         pci_set_master(pdev);
12396         pci_restore_state(pdev);
12397
12398         if (netif_running(dev))
12399                 bnx2x_set_power_state(bp, PCI_D0);
12400
12401         rtnl_unlock();
12402
12403         return PCI_ERS_RESULT_RECOVERED;
12404 }
12405
12406 /**
12407  * bnx2x_io_resume - called when traffic can start flowing again
12408  * @pdev: Pointer to PCI device
12409  *
12410  * This callback is called when the error recovery driver tells us that
12411  * its OK to resume normal operation.
12412  */
12413 static void bnx2x_io_resume(struct pci_dev *pdev)
12414 {
12415         struct net_device *dev = pci_get_drvdata(pdev);
12416         struct bnx2x *bp = netdev_priv(dev);
12417
12418         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12419                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12420                 return;
12421         }
12422
12423         rtnl_lock();
12424
12425         bnx2x_eeh_recover(bp);
12426
12427         if (netif_running(dev))
12428                 bnx2x_nic_load(bp, LOAD_NORMAL);
12429
12430         netif_device_attach(dev);
12431
12432         rtnl_unlock();
12433 }
12434
12435 static const struct pci_error_handlers bnx2x_err_handler = {
12436         .error_detected = bnx2x_io_error_detected,
12437         .slot_reset     = bnx2x_io_slot_reset,
12438         .resume         = bnx2x_io_resume,
12439 };
12440
12441 static struct pci_driver bnx2x_pci_driver = {
12442         .name        = DRV_MODULE_NAME,
12443         .id_table    = bnx2x_pci_tbl,
12444         .probe       = bnx2x_init_one,
12445         .remove      = bnx2x_remove_one,
12446         .suspend     = bnx2x_suspend,
12447         .resume      = bnx2x_resume,
12448         .err_handler = &bnx2x_err_handler,
12449 };
12450
12451 static int __init bnx2x_init(void)
12452 {
12453         int ret;
12454
12455         pr_info("%s", version);
12456
12457         bnx2x_wq = create_singlethread_workqueue("bnx2x");
12458         if (bnx2x_wq == NULL) {
12459                 pr_err("Cannot create workqueue\n");
12460                 return -ENOMEM;
12461         }
12462
12463         ret = pci_register_driver(&bnx2x_pci_driver);
12464         if (ret) {
12465                 pr_err("Cannot register driver\n");
12466                 destroy_workqueue(bnx2x_wq);
12467         }
12468         return ret;
12469 }
12470
12471 static void __exit bnx2x_cleanup(void)
12472 {
12473         struct list_head *pos, *q;
12474         pci_unregister_driver(&bnx2x_pci_driver);
12475
12476         destroy_workqueue(bnx2x_wq);
12477
12478         /* Free globablly allocated resources */
12479         list_for_each_safe(pos, q, &bnx2x_prev_list) {
12480                 struct bnx2x_prev_path_list *tmp =
12481                         list_entry(pos, struct bnx2x_prev_path_list, list);
12482                 list_del(pos);
12483                 kfree(tmp);
12484         }
12485 }
12486
12487 void bnx2x_notify_link_changed(struct bnx2x *bp)
12488 {
12489         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12490 }
12491
12492 module_init(bnx2x_init);
12493 module_exit(bnx2x_cleanup);
12494
12495 /**
12496  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12497  *
12498  * @bp:         driver handle
12499  * @set:        set or clear the CAM entry
12500  *
12501  * This function will wait until the ramdord completion returns.
12502  * Return 0 if success, -ENODEV if ramrod doesn't return.
12503  */
12504 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12505 {
12506         unsigned long ramrod_flags = 0;
12507
12508         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12509         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12510                                  &bp->iscsi_l2_mac_obj, true,
12511                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12512 }
12513
12514 /* count denotes the number of new completions we have seen */
12515 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12516 {
12517         struct eth_spe *spe;
12518         int cxt_index, cxt_offset;
12519
12520 #ifdef BNX2X_STOP_ON_ERROR
12521         if (unlikely(bp->panic))
12522                 return;
12523 #endif
12524
12525         spin_lock_bh(&bp->spq_lock);
12526         BUG_ON(bp->cnic_spq_pending < count);
12527         bp->cnic_spq_pending -= count;
12528
12529
12530         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12531                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12532                                 & SPE_HDR_CONN_TYPE) >>
12533                                 SPE_HDR_CONN_TYPE_SHIFT;
12534                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12535                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12536
12537                 /* Set validation for iSCSI L2 client before sending SETUP
12538                  *  ramrod
12539                  */
12540                 if (type == ETH_CONNECTION_TYPE) {
12541                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12542                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12543                                         ILT_PAGE_CIDS;
12544                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12545                                         (cxt_index * ILT_PAGE_CIDS);
12546                                 bnx2x_set_ctx_validation(bp,
12547                                         &bp->context[cxt_index].
12548                                                          vcxt[cxt_offset].eth,
12549                                         BNX2X_ISCSI_ETH_CID(bp));
12550                         }
12551                 }
12552
12553                 /*
12554                  * There may be not more than 8 L2, not more than 8 L5 SPEs
12555                  * and in the air. We also check that number of outstanding
12556                  * COMMON ramrods is not more than the EQ and SPQ can
12557                  * accommodate.
12558                  */
12559                 if (type == ETH_CONNECTION_TYPE) {
12560                         if (!atomic_read(&bp->cq_spq_left))
12561                                 break;
12562                         else
12563                                 atomic_dec(&bp->cq_spq_left);
12564                 } else if (type == NONE_CONNECTION_TYPE) {
12565                         if (!atomic_read(&bp->eq_spq_left))
12566                                 break;
12567                         else
12568                                 atomic_dec(&bp->eq_spq_left);
12569                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12570                            (type == FCOE_CONNECTION_TYPE)) {
12571                         if (bp->cnic_spq_pending >=
12572                             bp->cnic_eth_dev.max_kwqe_pending)
12573                                 break;
12574                         else
12575                                 bp->cnic_spq_pending++;
12576                 } else {
12577                         BNX2X_ERR("Unknown SPE type: %d\n", type);
12578                         bnx2x_panic();
12579                         break;
12580                 }
12581
12582                 spe = bnx2x_sp_get_next(bp);
12583                 *spe = *bp->cnic_kwq_cons;
12584
12585                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12586                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12587
12588                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12589                         bp->cnic_kwq_cons = bp->cnic_kwq;
12590                 else
12591                         bp->cnic_kwq_cons++;
12592         }
12593         bnx2x_sp_prod_update(bp);
12594         spin_unlock_bh(&bp->spq_lock);
12595 }
12596
12597 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12598                                struct kwqe_16 *kwqes[], u32 count)
12599 {
12600         struct bnx2x *bp = netdev_priv(dev);
12601         int i;
12602
12603 #ifdef BNX2X_STOP_ON_ERROR
12604         if (unlikely(bp->panic)) {
12605                 BNX2X_ERR("Can't post to SP queue while panic\n");
12606                 return -EIO;
12607         }
12608 #endif
12609
12610         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12611             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12612                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12613                 return -EAGAIN;
12614         }
12615
12616         spin_lock_bh(&bp->spq_lock);
12617
12618         for (i = 0; i < count; i++) {
12619                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12620
12621                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12622                         break;
12623
12624                 *bp->cnic_kwq_prod = *spe;
12625
12626                 bp->cnic_kwq_pending++;
12627
12628                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12629                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
12630                    spe->data.update_data_addr.hi,
12631                    spe->data.update_data_addr.lo,
12632                    bp->cnic_kwq_pending);
12633
12634                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12635                         bp->cnic_kwq_prod = bp->cnic_kwq;
12636                 else
12637                         bp->cnic_kwq_prod++;
12638         }
12639
12640         spin_unlock_bh(&bp->spq_lock);
12641
12642         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12643                 bnx2x_cnic_sp_post(bp, 0);
12644
12645         return i;
12646 }
12647
12648 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12649 {
12650         struct cnic_ops *c_ops;
12651         int rc = 0;
12652
12653         mutex_lock(&bp->cnic_mutex);
12654         c_ops = rcu_dereference_protected(bp->cnic_ops,
12655                                           lockdep_is_held(&bp->cnic_mutex));
12656         if (c_ops)
12657                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12658         mutex_unlock(&bp->cnic_mutex);
12659
12660         return rc;
12661 }
12662
12663 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12664 {
12665         struct cnic_ops *c_ops;
12666         int rc = 0;
12667
12668         rcu_read_lock();
12669         c_ops = rcu_dereference(bp->cnic_ops);
12670         if (c_ops)
12671                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12672         rcu_read_unlock();
12673
12674         return rc;
12675 }
12676
12677 /*
12678  * for commands that have no data
12679  */
12680 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12681 {
12682         struct cnic_ctl_info ctl = {0};
12683
12684         ctl.cmd = cmd;
12685
12686         return bnx2x_cnic_ctl_send(bp, &ctl);
12687 }
12688
12689 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12690 {
12691         struct cnic_ctl_info ctl = {0};
12692
12693         /* first we tell CNIC and only then we count this as a completion */
12694         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12695         ctl.data.comp.cid = cid;
12696         ctl.data.comp.error = err;
12697
12698         bnx2x_cnic_ctl_send_bh(bp, &ctl);
12699         bnx2x_cnic_sp_post(bp, 0);
12700 }
12701
12702
12703 /* Called with netif_addr_lock_bh() taken.
12704  * Sets an rx_mode config for an iSCSI ETH client.
12705  * Doesn't block.
12706  * Completion should be checked outside.
12707  */
12708 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12709 {
12710         unsigned long accept_flags = 0, ramrod_flags = 0;
12711         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12712         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12713
12714         if (start) {
12715                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12716                  * because it's the only way for UIO Queue to accept
12717                  * multicasts (in non-promiscuous mode only one Queue per
12718                  * function will receive multicast packets (leading in our
12719                  * case).
12720                  */
12721                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12722                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12723                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12724                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12725
12726                 /* Clear STOP_PENDING bit if START is requested */
12727                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12728
12729                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12730         } else
12731                 /* Clear START_PENDING bit if STOP is requested */
12732                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12733
12734         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12735                 set_bit(sched_state, &bp->sp_state);
12736         else {
12737                 __set_bit(RAMROD_RX, &ramrod_flags);
12738                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12739                                     ramrod_flags);
12740         }
12741 }
12742
12743
12744 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12745 {
12746         struct bnx2x *bp = netdev_priv(dev);
12747         int rc = 0;
12748
12749         switch (ctl->cmd) {
12750         case DRV_CTL_CTXTBL_WR_CMD: {
12751                 u32 index = ctl->data.io.offset;
12752                 dma_addr_t addr = ctl->data.io.dma_addr;
12753
12754                 bnx2x_ilt_wr(bp, index, addr);
12755                 break;
12756         }
12757
12758         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12759                 int count = ctl->data.credit.credit_count;
12760
12761                 bnx2x_cnic_sp_post(bp, count);
12762                 break;
12763         }
12764
12765         /* rtnl_lock is held.  */
12766         case DRV_CTL_START_L2_CMD: {
12767                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12768                 unsigned long sp_bits = 0;
12769
12770                 /* Configure the iSCSI classification object */
12771                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12772                                    cp->iscsi_l2_client_id,
12773                                    cp->iscsi_l2_cid, BP_FUNC(bp),
12774                                    bnx2x_sp(bp, mac_rdata),
12775                                    bnx2x_sp_mapping(bp, mac_rdata),
12776                                    BNX2X_FILTER_MAC_PENDING,
12777                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12778                                    &bp->macs_pool);
12779
12780                 /* Set iSCSI MAC address */
12781                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12782                 if (rc)
12783                         break;
12784
12785                 mmiowb();
12786                 barrier();
12787
12788                 /* Start accepting on iSCSI L2 ring */
12789
12790                 netif_addr_lock_bh(dev);
12791                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12792                 netif_addr_unlock_bh(dev);
12793
12794                 /* bits to wait on */
12795                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12796                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12797
12798                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12799                         BNX2X_ERR("rx_mode completion timed out!\n");
12800
12801                 break;
12802         }
12803
12804         /* rtnl_lock is held.  */
12805         case DRV_CTL_STOP_L2_CMD: {
12806                 unsigned long sp_bits = 0;
12807
12808                 /* Stop accepting on iSCSI L2 ring */
12809                 netif_addr_lock_bh(dev);
12810                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12811                 netif_addr_unlock_bh(dev);
12812
12813                 /* bits to wait on */
12814                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12815                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12816
12817                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12818                         BNX2X_ERR("rx_mode completion timed out!\n");
12819
12820                 mmiowb();
12821                 barrier();
12822
12823                 /* Unset iSCSI L2 MAC */
12824                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12825                                         BNX2X_ISCSI_ETH_MAC, true);
12826                 break;
12827         }
12828         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
12829                 int count = ctl->data.credit.credit_count;
12830
12831                 smp_mb__before_atomic_inc();
12832                 atomic_add(count, &bp->cq_spq_left);
12833                 smp_mb__after_atomic_inc();
12834                 break;
12835         }
12836         case DRV_CTL_ULP_REGISTER_CMD: {
12837                 int ulp_type = ctl->data.register_data.ulp_type;
12838
12839                 if (CHIP_IS_E3(bp)) {
12840                         int idx = BP_FW_MB_IDX(bp);
12841                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12842                         int path = BP_PATH(bp);
12843                         int port = BP_PORT(bp);
12844                         int i;
12845                         u32 scratch_offset;
12846                         u32 *host_addr;
12847
12848                         /* first write capability to shmem2 */
12849                         if (ulp_type == CNIC_ULP_ISCSI)
12850                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12851                         else if (ulp_type == CNIC_ULP_FCOE)
12852                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12853                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12854
12855                         if ((ulp_type != CNIC_ULP_FCOE) ||
12856                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
12857                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
12858                                 break;
12859
12860                         /* if reached here - should write fcoe capabilities */
12861                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
12862                         if (!scratch_offset)
12863                                 break;
12864                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
12865                                                    fcoe_features[path][port]);
12866                         host_addr = (u32 *) &(ctl->data.register_data.
12867                                               fcoe_features);
12868                         for (i = 0; i < sizeof(struct fcoe_capabilities);
12869                              i += 4)
12870                                 REG_WR(bp, scratch_offset + i,
12871                                        *(host_addr + i/4));
12872                 }
12873                 break;
12874         }
12875
12876         case DRV_CTL_ULP_UNREGISTER_CMD: {
12877                 int ulp_type = ctl->data.ulp_type;
12878
12879                 if (CHIP_IS_E3(bp)) {
12880                         int idx = BP_FW_MB_IDX(bp);
12881                         u32 cap;
12882
12883                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12884                         if (ulp_type == CNIC_ULP_ISCSI)
12885                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12886                         else if (ulp_type == CNIC_ULP_FCOE)
12887                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12888                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12889                 }
12890                 break;
12891         }
12892
12893         default:
12894                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
12895                 rc = -EINVAL;
12896         }
12897
12898         return rc;
12899 }
12900
12901 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
12902 {
12903         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12904
12905         if (bp->flags & USING_MSIX_FLAG) {
12906                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
12907                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
12908                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
12909         } else {
12910                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
12911                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
12912         }
12913         if (!CHIP_IS_E1x(bp))
12914                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
12915         else
12916                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
12917
12918         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
12919         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
12920         cp->irq_arr[1].status_blk = bp->def_status_blk;
12921         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
12922         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
12923
12924         cp->num_irq = 2;
12925 }
12926
12927 void bnx2x_setup_cnic_info(struct bnx2x *bp)
12928 {
12929         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12930
12931
12932         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12933                              bnx2x_cid_ilt_lines(bp);
12934         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12935         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12936         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12937
12938         if (NO_ISCSI_OOO(bp))
12939                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12940 }
12941
12942 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
12943                                void *data)
12944 {
12945         struct bnx2x *bp = netdev_priv(dev);
12946         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12947         int rc;
12948
12949         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
12950
12951         if (ops == NULL) {
12952                 BNX2X_ERR("NULL ops received\n");
12953                 return -EINVAL;
12954         }
12955
12956         if (!CNIC_SUPPORT(bp)) {
12957                 BNX2X_ERR("Can't register CNIC when not supported\n");
12958                 return -EOPNOTSUPP;
12959         }
12960
12961         if (!CNIC_LOADED(bp)) {
12962                 rc = bnx2x_load_cnic(bp);
12963                 if (rc) {
12964                         BNX2X_ERR("CNIC-related load failed\n");
12965                         return rc;
12966                 }
12967
12968         }
12969
12970         bp->cnic_enabled = true;
12971
12972         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12973         if (!bp->cnic_kwq)
12974                 return -ENOMEM;
12975
12976         bp->cnic_kwq_cons = bp->cnic_kwq;
12977         bp->cnic_kwq_prod = bp->cnic_kwq;
12978         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12979
12980         bp->cnic_spq_pending = 0;
12981         bp->cnic_kwq_pending = 0;
12982
12983         bp->cnic_data = data;
12984
12985         cp->num_irq = 0;
12986         cp->drv_state |= CNIC_DRV_STATE_REGD;
12987         cp->iro_arr = bp->iro_arr;
12988
12989         bnx2x_setup_cnic_irq_info(bp);
12990
12991         rcu_assign_pointer(bp->cnic_ops, ops);
12992
12993         return 0;
12994 }
12995
12996 static int bnx2x_unregister_cnic(struct net_device *dev)
12997 {
12998         struct bnx2x *bp = netdev_priv(dev);
12999         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13000
13001         mutex_lock(&bp->cnic_mutex);
13002         cp->drv_state = 0;
13003         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13004         mutex_unlock(&bp->cnic_mutex);
13005         synchronize_rcu();
13006         kfree(bp->cnic_kwq);
13007         bp->cnic_kwq = NULL;
13008
13009         return 0;
13010 }
13011
13012 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13013 {
13014         struct bnx2x *bp = netdev_priv(dev);
13015         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13016
13017         /* If both iSCSI and FCoE are disabled - return NULL in
13018          * order to indicate CNIC that it should not try to work
13019          * with this device.
13020          */
13021         if (NO_ISCSI(bp) && NO_FCOE(bp))
13022                 return NULL;
13023
13024         cp->drv_owner = THIS_MODULE;
13025         cp->chip_id = CHIP_ID(bp);
13026         cp->pdev = bp->pdev;
13027         cp->io_base = bp->regview;
13028         cp->io_base2 = bp->doorbells;
13029         cp->max_kwqe_pending = 8;
13030         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13031         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13032                              bnx2x_cid_ilt_lines(bp);
13033         cp->ctx_tbl_len = CNIC_ILT_LINES;
13034         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13035         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13036         cp->drv_ctl = bnx2x_drv_ctl;
13037         cp->drv_register_cnic = bnx2x_register_cnic;
13038         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13039         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13040         cp->iscsi_l2_client_id =
13041                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13042         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13043
13044         if (NO_ISCSI_OOO(bp))
13045                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13046
13047         if (NO_ISCSI(bp))
13048                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13049
13050         if (NO_FCOE(bp))
13051                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13052
13053         BNX2X_DEV_INFO(
13054                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13055            cp->ctx_blk_size,
13056            cp->ctx_tbl_offset,
13057            cp->ctx_tbl_len,
13058            cp->starting_cid);
13059         return cp;
13060 }
13061
13062