drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __HNS_DSAF_MAIN_H
  11 #define __HNS_DSAF_MAIN_H
  12 #include "hnae.h"
  13
  14 #include "hns_dsaf_reg.h"
  15 #include "hns_dsaf_mac.h"
  16
  17 struct hns_mac_cb;
  18
  19 #define DSAF_DRV_NAME "hns_dsaf"
  20 #define DSAF_MOD_VERSION "v1.0"
  21
  22 #define ENABLE          (0x1)
  23 #define DISABLE         (0x0)
  24
  25 #define HNS_DSAF_DEBUG_NW_REG_OFFSET (0x100000)
  26
  27 #define DSAF_BASE_INNER_PORT_NUM (127)  /* mac tbl qid*/
  28
  29 #define DSAF_MAX_CHIP_NUM (2)  /*max 2 chips */
  30
  31 #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE (22)
  32
  33 #define HNS_DSAF_MAX_DESC_CNT (1024)
  34 #define HNS_DSAF_MIN_DESC_CNT (16)
  35
  36 #define DSAF_INVALID_ENTRY_IDX (0xffff)
  37
  38 #define DSAF_CFG_READ_CNT   (30)
  39 #define DSAF_SRAM_INIT_FINISH_FLAG (0xff)
  40
  41 #define MAC_NUM_OCTETS_PER_ADDR 6
  42
  43 #define DSAF_DUMP_REGS_NUM 504
  44 #define DSAF_STATIC_NUM 28
  45
  46 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  47
  48 enum hal_dsaf_mode {
  49         HRD_DSAF_NO_DSAF_MODE   = 0x0,
  50         HRD_DSAF_MODE           = 0x1,
  51 };
  52
  53 enum hal_dsaf_tc_mode {
  54         HRD_DSAF_4TC_MODE               = 0X0,
  55         HRD_DSAF_8TC_MODE               = 0X1,
  56 };
  57
  58 struct dsaf_vm_def_vlan {
  59         u32 vm_def_vlan_id;
  60         u32 vm_def_vlan_cfi;
  61         u32 vm_def_vlan_pri;
  62 };
  63
  64 struct dsaf_tbl_tcam_data {
  65         u32 tbl_tcam_data_high;
  66         u32 tbl_tcam_data_low;
  67 };
  68
  69 #define DSAF_PORT_MSK_NUM \
  70         ((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1)
  71 struct dsaf_tbl_tcam_mcast_cfg {
  72         u8 tbl_mcast_old_en;
  73         u8 tbl_mcast_item_vld;
  74         u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
  75 };
  76
  77 struct dsaf_tbl_tcam_ucast_cfg {
  78         u32 tbl_ucast_old_en;
  79         u32 tbl_ucast_item_vld;
  80         u32 tbl_ucast_mac_discard;
  81         u32 tbl_ucast_dvc;
  82         u32 tbl_ucast_out_port;
  83 };
  84
  85 struct dsaf_tbl_line_cfg {
  86         u32 tbl_line_mac_discard;
  87         u32 tbl_line_dvc;
  88         u32 tbl_line_out_port;
  89 };
  90
  91 enum dsaf_port_rate_mode {
  92         DSAF_PORT_RATE_1000 = 0,
  93         DSAF_PORT_RATE_2500,
  94         DSAF_PORT_RATE_10000
  95 };
  96
  97 enum dsaf_stp_port_type {
  98         DSAF_STP_PORT_TYPE_DISCARD = 0,
  99         DSAF_STP_PORT_TYPE_BLOCK = 1,
 100         DSAF_STP_PORT_TYPE_LISTEN = 2,
 101         DSAF_STP_PORT_TYPE_LEARN = 3,
 102         DSAF_STP_PORT_TYPE_FORWARD = 4
 103 };
 104
 105 enum dsaf_sw_port_type {
 106         DSAF_SW_PORT_TYPE_NON_VLAN = 0,
 107         DSAF_SW_PORT_TYPE_ACCESS = 1,
 108         DSAF_SW_PORT_TYPE_TRUNK = 2,
 109 };
 110
 111 #define DSAF_SUB_BASE_SIZE                        (0x10000)
 112
 113 /* dsaf mode define */
 114 enum dsaf_mode {
 115         DSAF_MODE_INVALID = 0,  /**< Invalid dsaf mode */
 116         DSAF_MODE_ENABLE_FIX,   /**< en DSAF-mode, fixed to queue*/
 117         DSAF_MODE_ENABLE_0VM,   /**< en DSAF-mode, support 0 VM */
 118         DSAF_MODE_ENABLE_8VM,   /**< en DSAF-mode, support 8 VM */
 119         DSAF_MODE_ENABLE_16VM,  /**< en DSAF-mode, support 16 VM */
 120         DSAF_MODE_ENABLE_32VM,  /**< en DSAF-mode, support 32 VM */
 121         DSAF_MODE_ENABLE_128VM, /**< en DSAF-mode, support 128 VM */
 122         DSAF_MODE_ENABLE,               /**< before is enable DSAF mode*/
 123         DSAF_MODE_DISABLE_FIX,  /**< non-dasf, fixed to queue*/
 124         DSAF_MODE_DISABLE_2PORT_8VM,    /**< non-dasf, 2port 8VM */
 125         DSAF_MODE_DISABLE_2PORT_16VM,   /**< non-dasf, 2port 16VM */
 126         DSAF_MODE_DISABLE_2PORT_64VM,   /**< non-dasf, 2port 64VM */
 127         DSAF_MODE_DISABLE_6PORT_0VM,    /**< non-dasf, 6port 0VM */
 128         DSAF_MODE_DISABLE_6PORT_2VM,    /**< non-dasf, 6port 2VM */
 129         DSAF_MODE_DISABLE_6PORT_4VM,    /**< non-dasf, 6port 4VM */
 130         DSAF_MODE_DISABLE_6PORT_16VM,   /**< non-dasf, 6port 16VM */
 131         DSAF_MODE_MAX           /**< the last one, use as the num */
 132 };
 133
 134 #define DSAF_DEST_PORT_NUM 256  /* DSAF max port num */
 135 #define DSAF_WORD_BIT_CNT 32  /* the num bit of word */
 136
 137 /*mac entry, mc or uc entry*/
 138 struct dsaf_drv_mac_single_dest_entry {
 139         /* mac addr, match the entry*/
 140         u8 addr[MAC_NUM_OCTETS_PER_ADDR];
 141         u16 in_vlan_id; /* value of VlanId */
 142
 143         /* the vld input port num, dsaf-mode fix 0, */
 144         /*      non-dasf is the entry whitch port vld*/
 145         u8 in_port_num;
 146
 147         u8 port_num; /*output port num*/
 148         u8 rsv[6];
 149 };
 150
 151 /*only mc entry*/
 152 struct dsaf_drv_mac_multi_dest_entry {
 153         /* mac addr, match the entry*/
 154         u8 addr[MAC_NUM_OCTETS_PER_ADDR];
 155         u16 in_vlan_id;
 156         /* this mac addr output port,*/
 157         /*      bit0-bit5 means Port0-Port5(1bit is vld)**/
 158         u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];
 159
 160         /* the vld input port num, dsaf-mode fix 0,*/
 161         /*      non-dasf is the entry whitch port vld*/
 162         u8 in_port_num;
 163         u8 rsv[7];
 164 };
 165
 166 struct dsaf_hw_stats {
 167         u64 pad_drop;
 168         u64 man_pkts;
 169         u64 rx_pkts;
 170         u64 rx_pkt_id;
 171         u64 rx_pause_frame;
 172         u64 release_buf_num;
 173         u64 sbm_drop;
 174         u64 crc_false;
 175         u64 bp_drop;
 176         u64 rslt_drop;
 177         u64 local_addr_false;
 178         u64 vlan_drop;
 179         u64 stp_drop;
 180         u64 tx_pkts;
 181 };
 182
 183 struct hnae_vf_cb {
 184         u8 port_index;
 185         struct hns_mac_cb *mac_cb;
 186         struct dsaf_device *dsaf_dev;
 187         struct hnae_handle  ae_handle; /* must be the last number */
 188 };
 189
 190 struct dsaf_int_xge_src {
 191         u32    xid_xge_ecc_err_int_src;
 192         u32    xid_xge_fsm_timout_int_src;
 193         u32    sbm_xge_lnk_fsm_timout_int_src;
 194         u32    sbm_xge_lnk_ecc_2bit_int_src;
 195         u32    sbm_xge_mib_req_failed_int_src;
 196         u32    sbm_xge_mib_req_fsm_timout_int_src;
 197         u32    sbm_xge_mib_rels_fsm_timout_int_src;
 198         u32    sbm_xge_sram_ecc_2bit_int_src;
 199         u32    sbm_xge_mib_buf_sum_err_int_src;
 200         u32    sbm_xge_mib_req_extra_int_src;
 201         u32    sbm_xge_mib_rels_extra_int_src;
 202         u32    voq_xge_start_to_over_0_int_src;
 203         u32    voq_xge_start_to_over_1_int_src;
 204         u32    voq_xge_ecc_err_int_src;
 205 };
 206
 207 struct dsaf_int_ppe_src {
 208         u32    xid_ppe_fsm_timout_int_src;
 209         u32    sbm_ppe_lnk_fsm_timout_int_src;
 210         u32    sbm_ppe_lnk_ecc_2bit_int_src;
 211         u32    sbm_ppe_mib_req_failed_int_src;
 212         u32    sbm_ppe_mib_req_fsm_timout_int_src;
 213         u32    sbm_ppe_mib_rels_fsm_timout_int_src;
 214         u32    sbm_ppe_sram_ecc_2bit_int_src;
 215         u32    sbm_ppe_mib_buf_sum_err_int_src;
 216         u32    sbm_ppe_mib_req_extra_int_src;
 217         u32    sbm_ppe_mib_rels_extra_int_src;
 218         u32    voq_ppe_start_to_over_0_int_src;
 219         u32    voq_ppe_ecc_err_int_src;
 220         u32    xod_ppe_fifo_rd_empty_int_src;
 221         u32    xod_ppe_fifo_wr_full_int_src;
 222 };
 223
 224 struct dsaf_int_rocee_src {
 225         u32    xid_rocee_fsm_timout_int_src;
 226         u32    sbm_rocee_lnk_fsm_timout_int_src;
 227         u32    sbm_rocee_lnk_ecc_2bit_int_src;
 228         u32    sbm_rocee_mib_req_failed_int_src;
 229         u32    sbm_rocee_mib_req_fsm_timout_int_src;
 230         u32    sbm_rocee_mib_rels_fsm_timout_int_src;
 231         u32    sbm_rocee_sram_ecc_2bit_int_src;
 232         u32    sbm_rocee_mib_buf_sum_err_int_src;
 233         u32    sbm_rocee_mib_req_extra_int_src;
 234         u32    sbm_rocee_mib_rels_extra_int_src;
 235         u32    voq_rocee_start_to_over_0_int_src;
 236         u32    voq_rocee_ecc_err_int_src;
 237 };
 238
 239 struct dsaf_int_tbl_src {
 240         u32    tbl_da0_mis_src;
 241         u32    tbl_da1_mis_src;
 242         u32    tbl_da2_mis_src;
 243         u32    tbl_da3_mis_src;
 244         u32    tbl_da4_mis_src;
 245         u32    tbl_da5_mis_src;
 246         u32    tbl_da6_mis_src;
 247         u32    tbl_da7_mis_src;
 248         u32    tbl_sa_mis_src;
 249         u32    tbl_old_sech_end_src;
 250         u32    lram_ecc_err1_src;
 251         u32    lram_ecc_err2_src;
 252         u32    tram_ecc_err1_src;
 253         u32    tram_ecc_err2_src;
 254         u32    tbl_ucast_bcast_xge0_src;
 255         u32    tbl_ucast_bcast_xge1_src;
 256         u32    tbl_ucast_bcast_xge2_src;
 257         u32    tbl_ucast_bcast_xge3_src;
 258         u32    tbl_ucast_bcast_xge4_src;
 259         u32    tbl_ucast_bcast_xge5_src;
 260         u32    tbl_ucast_bcast_ppe_src;
 261         u32    tbl_ucast_bcast_rocee_src;
 262 };
 263
 264 struct dsaf_int_stat {
 265         struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN];
 266         struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN];
 267         struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN];
 268         struct dsaf_int_tbl_src dsaf_int_tbl_stat[1];
 269
 270 };
 271
 272 /* Dsaf device struct define ,and mac ->  dsaf */
 273 struct dsaf_device {
 274         struct device *dev;
 275         struct hnae_ae_dev ae_dev;
 276
 277         void *priv;
 278
 279         int virq[DSAF_IRQ_NUM];
 280
 281         u8 __iomem *sc_base;
 282         u8 __iomem *sds_base;
 283         u8 __iomem *ppe_base;
 284         u8 __iomem *io_base;
 285         u8 __iomem *cpld_base;
 286
 287         u32 desc_num; /*  desc num per queue*/
 288         u32 buf_size; /*  ring buffer size */
 289         int buf_size_type; /* ring buffer size-type */
 290         enum dsaf_mode dsaf_mode;        /* dsaf mode  */
 291         enum hal_dsaf_mode dsaf_en;
 292         enum hal_dsaf_tc_mode dsaf_tc_mode;
 293         u32 dsaf_ver;
 294
 295         struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM];
 296         struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM];
 297         struct hns_mac_cb *mac_cb;
 298
 299         struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM];
 300         struct dsaf_int_stat int_stat;
 301 };
 302
 303 static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev)
 304 {
 305         return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev));
 306 }
 307
 308 struct dsaf_drv_tbl_tcam_key {
 309         union {
 310                 struct {
 311                         u8 mac_3;
 312                         u8 mac_2;
 313                         u8 mac_1;
 314                         u8 mac_0;
 315                 } bits;
 316
 317                 u32 val;
 318         } high;
 319         union {
 320                 struct {
 321                         u32 port:4; /* port id, */
 322                         /* dsaf-mode fixed 0, non-dsaf-mode port id*/
 323                         u32 vlan:12; /* vlan id */
 324                         u32 mac_5:8;
 325                         u32 mac_4:8;
 326                 } bits;
 327
 328                 u32 val;
 329         } low;
 330 };
 331
 332 struct dsaf_drv_soft_mac_tbl {
 333         struct dsaf_drv_tbl_tcam_key tcam_key;
 334         u16 index; /*the entry's index in tcam tab*/
 335 };
 336
 337 struct dsaf_drv_priv {
 338         /* soft tab Mac key, for hardware tab*/
 339         struct dsaf_drv_soft_mac_tbl *soft_mac_tbl;
 340 };
 341
 342 static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev,
 343                                               u32 tab_tcam_addr)
 344 {
 345         dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG,
 346                            DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S,
 347                            tab_tcam_addr);
 348 }
 349
 350 static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev)
 351 {
 352         u32 o_tbl_pul;
 353
 354         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 355         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1);
 356         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 357         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0);
 358         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 359 }
 360
 361 static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev,
 362                                               u32 tab_line_addr)
 363 {
 364         dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG,
 365                            DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S,
 366                            tab_line_addr);
 367 }
 368
 369 static inline int hns_dsaf_get_comm_idx_by_port(int port)
 370 {
 371         if ((port < DSAF_COMM_CHN) || (port == DSAF_MAX_PORT_NUM_PER_CHIP))
 372                 return 0;
 373         else
 374                 return (port - DSAF_COMM_CHN + 1);
 375 }
 376
 377 static inline struct hnae_vf_cb *hns_ae_get_vf_cb(
 378         struct hnae_handle *handle)
 379 {
 380         return container_of(handle, struct hnae_vf_cb, ae_handle);
 381 }
 382
 383 int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev,
 384                               struct dsaf_drv_mac_single_dest_entry *mac_entry);
 385 int hns_dsaf_set_mac_mc_entry(struct dsaf_device *dsaf_dev,
 386                               struct dsaf_drv_mac_multi_dest_entry *mac_entry);
 387 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
 388                              struct dsaf_drv_mac_single_dest_entry *mac_entry);
 389 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
 390                            u8 in_port_num, u8 *addr);
 391 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
 392                              struct dsaf_drv_mac_single_dest_entry *mac_entry);
 393 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
 394                               struct dsaf_drv_mac_single_dest_entry *mac_entry);
 395 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
 396                               struct dsaf_drv_mac_multi_dest_entry *mac_entry);
 397 int hns_dsaf_get_mac_entry_by_index(
 398         struct dsaf_device *dsaf_dev,
 399         u16 entry_index,
 400         struct dsaf_drv_mac_multi_dest_entry *mac_entry);
 401
 402 void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val);
 403
 404 void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
 405
 406 void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val);
 407
 408 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);
 409
 410 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev);
 411 void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev);
 412
 413 void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
 414 void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val);
 415 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
 416                                     u32 port, u32 val);
 417
 418 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num);
 419
 420 int hns_dsaf_get_sset_count(int stringset);
 421 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port);
 422 void hns_dsaf_get_strings(int stringset, u8 *data, int port);
 423
 424 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data);
 425 int hns_dsaf_get_regs_count(void);
 426 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);
 427
 428 #endif /* __HNS_DSAF_MAIN_H__ */