1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_VF 0x154C
48 #define I40E_DEV_ID_VF_HV 0x1571
50 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
51 (d) == I40E_DEV_ID_QSFP_B || \
52 (d) == I40E_DEV_ID_QSFP_C)
54 /* I40E_MASK is a macro used on 32 bit registers */
55 #define I40E_MASK(mask, shift) (mask << shift)
57 #define I40E_MAX_VSI_QP 16
58 #define I40E_MAX_VF_VSI 3
59 #define I40E_MAX_CHAINED_RX_BUFFERS 5
60 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
62 /* Max default timeout in ms, */
63 #define I40E_MAX_NVM_TIMEOUT 18000
65 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
66 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
68 /* forward declaration */
70 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
72 /* Data type manipulation macros. */
74 #define I40E_DESC_UNUSED(R) \
75 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
76 (R)->next_to_clean - (R)->next_to_use - 1)
78 /* bitfields for Tx queue mapping in QTX_CTL */
79 #define I40E_QTX_CTL_VF_QUEUE 0x0
80 #define I40E_QTX_CTL_VM_QUEUE 0x1
81 #define I40E_QTX_CTL_PF_QUEUE 0x2
83 /* debug masks - set these bits in hw->debug_mask to control output */
84 enum i40e_debug_mask {
85 I40E_DEBUG_INIT = 0x00000001,
86 I40E_DEBUG_RELEASE = 0x00000002,
88 I40E_DEBUG_LINK = 0x00000010,
89 I40E_DEBUG_PHY = 0x00000020,
90 I40E_DEBUG_HMC = 0x00000040,
91 I40E_DEBUG_NVM = 0x00000080,
92 I40E_DEBUG_LAN = 0x00000100,
93 I40E_DEBUG_FLOW = 0x00000200,
94 I40E_DEBUG_DCB = 0x00000400,
95 I40E_DEBUG_DIAG = 0x00000800,
96 I40E_DEBUG_FD = 0x00001000,
98 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
99 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
100 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
101 I40E_DEBUG_AQ_COMMAND = 0x06000000,
102 I40E_DEBUG_AQ = 0x0F000000,
104 I40E_DEBUG_USER = 0xF0000000,
106 I40E_DEBUG_ALL = 0xFFFFFFFF
109 /* These are structs for managing the hardware information and the operations.
110 * The structures of function pointers are filled out at init time when we
111 * know for sure exactly which hardware we're working with. This gives us the
112 * flexibility of using the same main driver code but adapting to slightly
113 * different hardware needs as new parts are developed. For this architecture,
114 * the Firmware and AdminQ are intended to insulate the driver from most of the
115 * future changes, but these structures will also do part of the job.
118 I40E_MAC_UNKNOWN = 0,
125 enum i40e_media_type {
126 I40E_MEDIA_TYPE_UNKNOWN = 0,
127 I40E_MEDIA_TYPE_FIBER,
128 I40E_MEDIA_TYPE_BASET,
129 I40E_MEDIA_TYPE_BACKPLANE,
132 I40E_MEDIA_TYPE_VIRTUAL
144 enum i40e_set_fc_aq_failures {
145 I40E_SET_FC_AQ_FAIL_NONE = 0,
146 I40E_SET_FC_AQ_FAIL_GET = 1,
147 I40E_SET_FC_AQ_FAIL_SET = 2,
148 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
149 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
161 I40E_VSI_TYPE_UNKNOWN
164 enum i40e_queue_type {
165 I40E_QUEUE_TYPE_RX = 0,
167 I40E_QUEUE_TYPE_PE_CEQ,
168 I40E_QUEUE_TYPE_UNKNOWN
171 struct i40e_link_status {
172 enum i40e_aq_phy_type phy_type;
173 enum i40e_aq_link_speed link_speed;
179 /* is Link Status Event notification to SW enabled */
186 struct i40e_phy_info {
187 struct i40e_link_status link_info;
188 struct i40e_link_status link_info_old;
189 u32 autoneg_advertised;
193 enum i40e_media_type media_type;
196 #define I40E_HW_CAP_MAX_GPIO 30
197 /* Capabilities of a PF or a VF or the whole device */
198 struct i40e_hw_capabilities {
200 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
201 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
202 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
210 bool evb_802_1_qbg; /* Edge Virtual Bridging */
211 bool evb_802_1_qbh; /* Bridge Port Extension */
219 u32 fd_filters_guaranteed;
220 u32 fd_filters_best_effort;
223 u32 rss_table_entry_width;
224 bool led[I40E_HW_CAP_MAX_GPIO];
225 bool sdp[I40E_HW_CAP_MAX_GPIO];
227 u32 num_flow_director_filters;
234 u32 num_msix_vectors;
235 u32 num_msix_vectors_vf;
245 struct i40e_mac_info {
246 enum i40e_mac_type type;
248 u8 perm_addr[ETH_ALEN];
249 u8 san_addr[ETH_ALEN];
250 u8 port_addr[ETH_ALEN];
254 enum i40e_aq_resources_ids {
255 I40E_NVM_RESOURCE_ID = 1
258 enum i40e_aq_resource_access_type {
259 I40E_RESOURCE_READ = 1,
263 struct i40e_nvm_info {
264 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
265 u64 hw_semaphore_wait; /* - || - */
266 u32 timeout; /* [ms] */
267 u16 sr_size; /* Shadow RAM size in words */
268 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
269 u16 version; /* NVM package version */
270 u32 eetrack; /* NVM data version */
273 /* definitions used in NVM update support */
275 enum i40e_nvmupd_cmd {
277 I40E_NVMUPD_READ_CON,
278 I40E_NVMUPD_READ_SNT,
279 I40E_NVMUPD_READ_LCB,
281 I40E_NVMUPD_WRITE_ERA,
282 I40E_NVMUPD_WRITE_CON,
283 I40E_NVMUPD_WRITE_SNT,
284 I40E_NVMUPD_WRITE_LCB,
285 I40E_NVMUPD_WRITE_SA,
286 I40E_NVMUPD_CSUM_CON,
288 I40E_NVMUPD_CSUM_LCB,
291 enum i40e_nvmupd_state {
292 I40E_NVMUPD_STATE_INIT,
293 I40E_NVMUPD_STATE_READING,
294 I40E_NVMUPD_STATE_WRITING
297 /* nvm_access definition and its masks/shifts need to be accessible to
298 * application, core driver, and shared code. Where is the right file?
300 #define I40E_NVM_READ 0xB
301 #define I40E_NVM_WRITE 0xC
303 #define I40E_NVM_MOD_PNT_MASK 0xFF
305 #define I40E_NVM_TRANS_SHIFT 8
306 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
307 #define I40E_NVM_CON 0x0
308 #define I40E_NVM_SNT 0x1
309 #define I40E_NVM_LCB 0x2
310 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
311 #define I40E_NVM_ERA 0x4
312 #define I40E_NVM_CSUM 0x8
314 #define I40E_NVM_ADAPT_SHIFT 16
315 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
317 #define I40E_NVMUPD_MAX_DATA 4096
318 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
320 struct i40e_nvm_access {
323 u32 offset; /* in bytes */
324 u32 data_size; /* in bytes */
330 i40e_bus_type_unknown = 0,
333 i40e_bus_type_pci_express,
334 i40e_bus_type_reserved
338 enum i40e_bus_speed {
339 i40e_bus_speed_unknown = 0,
340 i40e_bus_speed_33 = 33,
341 i40e_bus_speed_66 = 66,
342 i40e_bus_speed_100 = 100,
343 i40e_bus_speed_120 = 120,
344 i40e_bus_speed_133 = 133,
345 i40e_bus_speed_2500 = 2500,
346 i40e_bus_speed_5000 = 5000,
347 i40e_bus_speed_8000 = 8000,
348 i40e_bus_speed_reserved
352 enum i40e_bus_width {
353 i40e_bus_width_unknown = 0,
354 i40e_bus_width_pcie_x1 = 1,
355 i40e_bus_width_pcie_x2 = 2,
356 i40e_bus_width_pcie_x4 = 4,
357 i40e_bus_width_pcie_x8 = 8,
358 i40e_bus_width_32 = 32,
359 i40e_bus_width_64 = 64,
360 i40e_bus_width_reserved
364 struct i40e_bus_info {
365 enum i40e_bus_speed speed;
366 enum i40e_bus_width width;
367 enum i40e_bus_type type;
374 /* Flow control (FC) parameters */
375 struct i40e_fc_info {
376 enum i40e_fc_mode current_mode; /* FC mode in effect */
377 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
380 #define I40E_MAX_TRAFFIC_CLASS 8
381 #define I40E_MAX_USER_PRIORITY 8
382 #define I40E_DCBX_MAX_APPS 32
383 #define I40E_LLDPDU_SIZE 1500
384 #define I40E_TLV_STATUS_OPER 0x1
385 #define I40E_TLV_STATUS_SYNC 0x2
386 #define I40E_TLV_STATUS_ERR 0x4
387 #define I40E_CEE_OPER_MAX_APPS 3
388 #define I40E_APP_PROTOID_FCOE 0x8906
389 #define I40E_APP_PROTOID_ISCSI 0x0cbc
390 #define I40E_APP_PROTOID_FIP 0x8914
391 #define I40E_APP_SEL_ETHTYPE 0x1
392 #define I40E_APP_SEL_TCPIP 0x2
394 /* CEE or IEEE 802.1Qaz ETS Configuration data */
395 struct i40e_dcb_ets_config {
399 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
400 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
401 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
404 /* CEE or IEEE 802.1Qaz PFC Configuration data */
405 struct i40e_dcb_pfc_config {
412 /* CEE or IEEE 802.1Qaz Application Priority data */
413 struct i40e_dcb_app_priority_table {
419 struct i40e_dcbx_config {
421 #define I40E_DCBX_MODE_CEE 0x1
422 #define I40E_DCBX_MODE_IEEE 0x2
424 struct i40e_dcb_ets_config etscfg;
425 struct i40e_dcb_ets_config etsrec;
426 struct i40e_dcb_pfc_config pfc;
427 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
430 /* Port hardware description */
435 /* function pointer structs */
436 struct i40e_phy_info phy;
437 struct i40e_mac_info mac;
438 struct i40e_bus_info bus;
439 struct i40e_nvm_info nvm;
440 struct i40e_fc_info fc;
445 u16 subsystem_device_id;
446 u16 subsystem_vendor_id;
449 bool adapter_stopped;
451 /* capabilities for entire device and PCI func */
452 struct i40e_hw_capabilities dev_caps;
453 struct i40e_hw_capabilities func_caps;
455 /* Flow Director shared filter space */
456 u16 fdir_shared_filter_count;
458 /* device profile info */
462 /* Closest numa node to the device */
465 /* Admin Queue info */
466 struct i40e_adminq_info aq;
468 /* state of nvm update process */
469 enum i40e_nvmupd_state nvmupd_state;
472 struct i40e_hmc_info hmc; /* HMC info struct */
474 /* LLDP/DCBX Status */
478 struct i40e_dcbx_config local_dcbx_config;
479 struct i40e_dcbx_config remote_dcbx_config;
485 #define i40e_is_vf(_hw) ((_hw)->mac.type == I40E_MAC_VF)
487 struct i40e_driver_version {
492 u8 driver_string[32];
496 union i40e_16byte_rx_desc {
498 __le64 pkt_addr; /* Packet buffer address */
499 __le64 hdr_addr; /* Header buffer address */
505 __le16 mirroring_status;
511 __le32 rss; /* RSS Hash */
512 __le32 fd_id; /* Flow director filter id */
513 __le32 fcoe_param; /* FCoE DDP Context id */
517 /* ext status/error/pktype/length */
518 __le64 status_error_len;
520 } wb; /* writeback */
523 union i40e_32byte_rx_desc {
525 __le64 pkt_addr; /* Packet buffer address */
526 __le64 hdr_addr; /* Header buffer address */
527 /* bit 0 of hdr_buffer_addr is DD bit */
535 __le16 mirroring_status;
541 __le32 rss; /* RSS Hash */
542 __le32 fcoe_param; /* FCoE DDP Context id */
543 /* Flow director filter id in case of
544 * Programming status desc WB
550 /* status/error/pktype/length */
551 __le64 status_error_len;
554 __le16 ext_status; /* extended status */
561 __le32 flex_bytes_lo;
565 __le32 flex_bytes_hi;
569 } wb; /* writeback */
572 enum i40e_rx_desc_status_bits {
573 /* Note: These are predefined bit offsets */
574 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
575 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
576 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
577 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
578 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
579 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
580 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
581 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
582 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
583 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
584 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
585 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
586 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
587 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
588 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
589 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
592 #define I40E_RXD_QW1_STATUS_SHIFT 0
593 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
594 << I40E_RXD_QW1_STATUS_SHIFT)
596 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
597 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
598 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
600 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
601 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
602 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
604 enum i40e_rx_desc_fltstat_values {
605 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
606 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
607 I40E_RX_DESC_FLTSTAT_RSV = 2,
608 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
611 #define I40E_RXD_QW1_ERROR_SHIFT 19
612 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
614 enum i40e_rx_desc_error_bits {
615 /* Note: These are predefined bit offsets */
616 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
617 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
618 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
619 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
620 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
621 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
622 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
623 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
624 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
627 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
628 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
629 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
630 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
631 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
632 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
635 #define I40E_RXD_QW1_PTYPE_SHIFT 30
636 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
638 /* Packet type non-ip values */
639 enum i40e_rx_l2_ptype {
640 I40E_RX_PTYPE_L2_RESERVED = 0,
641 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
642 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
643 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
644 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
645 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
646 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
647 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
648 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
649 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
650 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
651 I40E_RX_PTYPE_L2_ARP = 11,
652 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
653 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
654 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
655 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
656 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
657 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
658 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
659 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
660 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
661 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
662 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
663 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
664 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
665 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
668 struct i40e_rx_ptype_decoded {
675 u32 tunnel_end_prot:2;
676 u32 tunnel_end_frag:1;
681 enum i40e_rx_ptype_outer_ip {
682 I40E_RX_PTYPE_OUTER_L2 = 0,
683 I40E_RX_PTYPE_OUTER_IP = 1
686 enum i40e_rx_ptype_outer_ip_ver {
687 I40E_RX_PTYPE_OUTER_NONE = 0,
688 I40E_RX_PTYPE_OUTER_IPV4 = 0,
689 I40E_RX_PTYPE_OUTER_IPV6 = 1
692 enum i40e_rx_ptype_outer_fragmented {
693 I40E_RX_PTYPE_NOT_FRAG = 0,
694 I40E_RX_PTYPE_FRAG = 1
697 enum i40e_rx_ptype_tunnel_type {
698 I40E_RX_PTYPE_TUNNEL_NONE = 0,
699 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
700 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
701 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
702 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
705 enum i40e_rx_ptype_tunnel_end_prot {
706 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
707 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
708 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
711 enum i40e_rx_ptype_inner_prot {
712 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
713 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
714 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
715 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
716 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
717 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
720 enum i40e_rx_ptype_payload_layer {
721 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
722 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
723 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
724 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
727 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
728 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
729 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
731 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
732 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
733 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
735 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
736 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
737 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
739 enum i40e_rx_desc_ext_status_bits {
740 /* Note: These are predefined bit offsets */
741 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
742 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
743 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
744 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
745 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
746 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
747 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
750 enum i40e_rx_desc_pe_status_bits {
751 /* Note: These are predefined bit offsets */
752 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
753 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
754 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
755 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
756 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
757 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
758 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
759 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
760 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
763 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
764 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
766 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
767 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
768 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
770 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
771 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
772 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
774 enum i40e_rx_prog_status_desc_status_bits {
775 /* Note: These are predefined bit offsets */
776 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
777 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
780 enum i40e_rx_prog_status_desc_prog_id_masks {
781 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
782 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
783 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
786 enum i40e_rx_prog_status_desc_error_bits {
787 /* Note: These are predefined bit offsets */
788 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
789 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
790 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
791 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
795 struct i40e_tx_desc {
796 __le64 buffer_addr; /* Address of descriptor's data buf */
797 __le64 cmd_type_offset_bsz;
800 #define I40E_TXD_QW1_DTYPE_SHIFT 0
801 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
803 enum i40e_tx_desc_dtype_value {
804 I40E_TX_DESC_DTYPE_DATA = 0x0,
805 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
806 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
807 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
808 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
809 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
810 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
811 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
812 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
813 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
816 #define I40E_TXD_QW1_CMD_SHIFT 4
817 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
819 enum i40e_tx_desc_cmd_bits {
820 I40E_TX_DESC_CMD_EOP = 0x0001,
821 I40E_TX_DESC_CMD_RS = 0x0002,
822 I40E_TX_DESC_CMD_ICRC = 0x0004,
823 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
824 I40E_TX_DESC_CMD_DUMMY = 0x0010,
825 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
826 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
827 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
828 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
829 I40E_TX_DESC_CMD_FCOET = 0x0080,
830 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
831 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
832 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
833 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
834 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
835 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
836 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
837 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
840 #define I40E_TXD_QW1_OFFSET_SHIFT 16
841 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
842 I40E_TXD_QW1_OFFSET_SHIFT)
844 enum i40e_tx_desc_length_fields {
845 /* Note: These are predefined bit offsets */
846 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
847 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
848 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
851 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
852 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
853 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
855 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
856 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
858 /* Context descriptors */
859 struct i40e_tx_context_desc {
860 __le32 tunneling_params;
863 __le64 type_cmd_tso_mss;
866 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
867 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
869 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
870 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
872 enum i40e_tx_ctx_desc_cmd_bits {
873 I40E_TX_CTX_DESC_TSO = 0x01,
874 I40E_TX_CTX_DESC_TSYN = 0x02,
875 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
876 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
877 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
878 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
879 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
880 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
881 I40E_TX_CTX_DESC_SWPE = 0x40
884 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
885 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
886 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
888 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
889 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
890 I40E_TXD_CTX_QW1_MSS_SHIFT)
892 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
893 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
895 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
896 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
897 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
899 enum i40e_tx_ctx_desc_eipt_offload {
900 I40E_TX_CTX_EXT_IP_NONE = 0x0,
901 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
902 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
903 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
906 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
907 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
908 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
910 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
911 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
913 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
914 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
916 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
917 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
918 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
920 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
922 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
923 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
924 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
926 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
927 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
928 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
930 struct i40e_filter_program_desc {
931 __le32 qindex_flex_ptype_vsi;
933 __le32 dtype_cmd_cntindex;
936 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
937 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
938 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
939 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
940 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
941 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
942 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
943 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
944 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
946 /* Packet Classifier Types for filters */
947 enum i40e_filter_pctype {
948 /* Note: Values 0-30 are reserved for future use */
949 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
950 /* Note: Value 32 is reserved for future use */
951 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
952 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
953 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
954 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
955 /* Note: Values 37-40 are reserved for future use */
956 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
957 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
958 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
959 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
960 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
961 /* Note: Value 47 is reserved for future use */
962 I40E_FILTER_PCTYPE_FCOE_OX = 48,
963 I40E_FILTER_PCTYPE_FCOE_RX = 49,
964 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
965 /* Note: Values 51-62 are reserved for future use */
966 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
969 enum i40e_filter_program_desc_dest {
970 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
971 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
972 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
975 enum i40e_filter_program_desc_fd_status {
976 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
977 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
978 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
979 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
982 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
983 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
984 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
986 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
987 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
988 I40E_TXD_FLTR_QW1_CMD_SHIFT)
990 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
991 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
993 enum i40e_filter_program_desc_pcmd {
994 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
995 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
998 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
999 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1001 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1002 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
1003 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1005 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1006 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1007 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1008 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1010 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1011 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1012 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1014 enum i40e_filter_type {
1015 I40E_FLOW_DIRECTOR_FLTR = 0,
1016 I40E_PE_QUAD_HASH_FLTR = 1,
1017 I40E_ETHERTYPE_FLTR,
1023 struct i40e_vsi_context {
1028 u16 vsis_unallocated;
1033 struct i40e_aqc_vsi_properties_data info;
1036 struct i40e_veb_context {
1041 u16 vebs_unallocated;
1043 struct i40e_aqc_get_veb_parameters_completion info;
1046 /* Statistics collected by each port, VSI, VEB, and S-channel */
1047 struct i40e_eth_stats {
1048 u64 rx_bytes; /* gorc */
1049 u64 rx_unicast; /* uprc */
1050 u64 rx_multicast; /* mprc */
1051 u64 rx_broadcast; /* bprc */
1052 u64 rx_discards; /* rdpc */
1053 u64 rx_unknown_protocol; /* rupp */
1054 u64 tx_bytes; /* gotc */
1055 u64 tx_unicast; /* uptc */
1056 u64 tx_multicast; /* mptc */
1057 u64 tx_broadcast; /* bptc */
1058 u64 tx_discards; /* tdpc */
1059 u64 tx_errors; /* tepc */
1063 /* Statistics collected per function for FCoE */
1064 struct i40e_fcoe_stats {
1065 u64 rx_fcoe_packets; /* fcoeprc */
1066 u64 rx_fcoe_dwords; /* focedwrc */
1067 u64 rx_fcoe_dropped; /* fcoerpdc */
1068 u64 tx_fcoe_packets; /* fcoeptc */
1069 u64 tx_fcoe_dwords; /* focedwtc */
1070 u64 fcoe_bad_fccrc; /* fcoecrc */
1071 u64 fcoe_last_error; /* fcoelast */
1072 u64 fcoe_ddp_count; /* fcoeddpc */
1075 /* offset to per function FCoE statistics block */
1076 #define I40E_FCOE_VF_STAT_OFFSET 0
1077 #define I40E_FCOE_PF_STAT_OFFSET 128
1078 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1081 /* Statistics collected by the MAC */
1082 struct i40e_hw_port_stats {
1083 /* eth stats collected by the port */
1084 struct i40e_eth_stats eth;
1086 /* additional port specific stats */
1087 u64 tx_dropped_link_down; /* tdold */
1088 u64 crc_errors; /* crcerrs */
1089 u64 illegal_bytes; /* illerrc */
1090 u64 error_bytes; /* errbc */
1091 u64 mac_local_faults; /* mlfc */
1092 u64 mac_remote_faults; /* mrfc */
1093 u64 rx_length_errors; /* rlec */
1094 u64 link_xon_rx; /* lxonrxc */
1095 u64 link_xoff_rx; /* lxoffrxc */
1096 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1097 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1098 u64 link_xon_tx; /* lxontxc */
1099 u64 link_xoff_tx; /* lxofftxc */
1100 u64 priority_xon_tx[8]; /* pxontxc[8] */
1101 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1102 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1103 u64 rx_size_64; /* prc64 */
1104 u64 rx_size_127; /* prc127 */
1105 u64 rx_size_255; /* prc255 */
1106 u64 rx_size_511; /* prc511 */
1107 u64 rx_size_1023; /* prc1023 */
1108 u64 rx_size_1522; /* prc1522 */
1109 u64 rx_size_big; /* prc9522 */
1110 u64 rx_undersize; /* ruc */
1111 u64 rx_fragments; /* rfc */
1112 u64 rx_oversize; /* roc */
1113 u64 rx_jabber; /* rjc */
1114 u64 tx_size_64; /* ptc64 */
1115 u64 tx_size_127; /* ptc127 */
1116 u64 tx_size_255; /* ptc255 */
1117 u64 tx_size_511; /* ptc511 */
1118 u64 tx_size_1023; /* ptc1023 */
1119 u64 tx_size_1522; /* ptc1522 */
1120 u64 tx_size_big; /* ptc9522 */
1121 u64 mac_short_packet_dropped; /* mspdc */
1122 u64 checksum_error; /* xec */
1123 /* flow director stats */
1129 u64 tx_lpi_count; /* etlpic */
1130 u64 rx_lpi_count; /* erlpic */
1133 /* Checksum and Shadow RAM pointers */
1134 #define I40E_SR_NVM_CONTROL_WORD 0x00
1135 #define I40E_SR_EMP_MODULE_PTR 0x0F
1136 #define I40E_SR_NVM_IMAGE_VERSION 0x18
1137 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1138 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1139 #define I40E_SR_NVM_EETRACK_LO 0x2D
1140 #define I40E_SR_NVM_EETRACK_HI 0x2E
1141 #define I40E_SR_VPD_PTR 0x2F
1142 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1143 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1145 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1146 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1147 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1148 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1149 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1151 /* Shadow RAM related */
1152 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1153 #define I40E_SR_WORDS_IN_1KB 512
1154 /* Checksum should be calculated such that after adding all the words,
1155 * including the checksum word itself, the sum should be 0xBABA.
1157 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1159 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1162 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1164 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1165 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1166 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1167 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1168 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1169 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1170 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1171 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1172 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1173 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1174 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1175 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1176 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1177 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1180 /* FCoE DDP Context descriptor */
1181 struct i40e_fcoe_ddp_context_desc {
1183 __le64 type_cmd_foff_lsize;
1186 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1187 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1188 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1190 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1191 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1192 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1194 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1195 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1196 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1197 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1198 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1199 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1200 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1203 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1204 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1205 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1207 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1208 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1209 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1211 /* FCoE DDP/DWO Queue Context descriptor */
1212 struct i40e_fcoe_queue_context_desc {
1213 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1214 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1217 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1218 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1219 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1221 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1222 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1223 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1225 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1226 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1227 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1229 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1230 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1231 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1233 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1234 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1235 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1238 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1239 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1240 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1242 /* FCoE DDP/DWO Filter Context descriptor */
1243 struct i40e_fcoe_filter_context_desc {
1247 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1248 __le16 rsvd_dmaindx;
1250 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1251 __le64 flags_rsvd_lanq;
1254 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1255 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1256 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1258 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1259 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1260 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1261 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1262 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1263 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1264 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1267 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1268 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1269 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1271 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1272 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1273 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1275 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1276 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1277 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1279 #endif /* I40E_FCOE */
1280 enum i40e_switch_element_types {
1281 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1282 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1283 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1284 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1285 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1286 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1287 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1288 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1289 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1292 /* Supported EtherType filters */
1293 enum i40e_ether_type_index {
1294 I40E_ETHER_TYPE_1588 = 0,
1295 I40E_ETHER_TYPE_FIP = 1,
1296 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1297 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1298 I40E_ETHER_TYPE_LLDP = 4,
1299 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1300 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1301 I40E_ETHER_TYPE_QCN_CNM = 7,
1302 I40E_ETHER_TYPE_8021X = 8,
1303 I40E_ETHER_TYPE_ARP = 9,
1304 I40E_ETHER_TYPE_RSV1 = 10,
1305 I40E_ETHER_TYPE_RSV2 = 11,
1308 /* Filter context base size is 1K */
1309 #define I40E_HASH_FILTER_BASE_SIZE 1024
1310 /* Supported Hash filter values */
1311 enum i40e_hash_filter_size {
1312 I40E_HASH_FILTER_SIZE_1K = 0,
1313 I40E_HASH_FILTER_SIZE_2K = 1,
1314 I40E_HASH_FILTER_SIZE_4K = 2,
1315 I40E_HASH_FILTER_SIZE_8K = 3,
1316 I40E_HASH_FILTER_SIZE_16K = 4,
1317 I40E_HASH_FILTER_SIZE_32K = 5,
1318 I40E_HASH_FILTER_SIZE_64K = 6,
1319 I40E_HASH_FILTER_SIZE_128K = 7,
1320 I40E_HASH_FILTER_SIZE_256K = 8,
1321 I40E_HASH_FILTER_SIZE_512K = 9,
1322 I40E_HASH_FILTER_SIZE_1M = 10,
1325 /* DMA context base size is 0.5K */
1326 #define I40E_DMA_CNTX_BASE_SIZE 512
1327 /* Supported DMA context values */
1328 enum i40e_dma_cntx_size {
1329 I40E_DMA_CNTX_SIZE_512 = 0,
1330 I40E_DMA_CNTX_SIZE_1K = 1,
1331 I40E_DMA_CNTX_SIZE_2K = 2,
1332 I40E_DMA_CNTX_SIZE_4K = 3,
1333 I40E_DMA_CNTX_SIZE_8K = 4,
1334 I40E_DMA_CNTX_SIZE_16K = 5,
1335 I40E_DMA_CNTX_SIZE_32K = 6,
1336 I40E_DMA_CNTX_SIZE_64K = 7,
1337 I40E_DMA_CNTX_SIZE_128K = 8,
1338 I40E_DMA_CNTX_SIZE_256K = 9,
1341 /* Supported Hash look up table (LUT) sizes */
1342 enum i40e_hash_lut_size {
1343 I40E_HASH_LUT_SIZE_128 = 0,
1344 I40E_HASH_LUT_SIZE_512 = 1,
1347 /* Structure to hold a per PF filter control settings */
1348 struct i40e_filter_control_settings {
1349 /* number of PE Quad Hash filter buckets */
1350 enum i40e_hash_filter_size pe_filt_num;
1351 /* number of PE Quad Hash contexts */
1352 enum i40e_dma_cntx_size pe_cntx_num;
1353 /* number of FCoE filter buckets */
1354 enum i40e_hash_filter_size fcoe_filt_num;
1355 /* number of FCoE DDP contexts */
1356 enum i40e_dma_cntx_size fcoe_cntx_num;
1357 /* size of the Hash LUT */
1358 enum i40e_hash_lut_size hash_lut_size;
1359 /* enable FDIR filters for PF and its VFs */
1361 /* enable Ethertype filters for PF and its VFs */
1362 bool enable_ethtype;
1363 /* enable MAC/VLAN filters for PF and its VFs */
1364 bool enable_macvlan;
1367 /* Structure to hold device level control filter counts */
1368 struct i40e_control_filter_stats {
1369 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1370 u16 etype_used; /* Used perfect EtherType filters */
1371 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1372 u16 etype_free; /* Un-used perfect EtherType filters */
1375 enum i40e_reset_type {
1377 I40E_RESET_CORER = 1,
1378 I40E_RESET_GLOBR = 2,
1379 I40E_RESET_EMPR = 3,
1382 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1383 #define I40E_NVM_LLDP_CFG_PTR 0xD
1384 struct i40e_lldp_variables {
1394 /* RSS Hash Table Size */
1395 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1396 #endif /* _I40E_TYPE_H_ */