drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2015 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36
  37 /* Device IDs */
  38 #define I40E_DEV_ID_SFP_XL710           0x1572
  39 #define I40E_DEV_ID_QEMU                0x1574
  40 #define I40E_DEV_ID_KX_A                0x157F
  41 #define I40E_DEV_ID_KX_B                0x1580
  42 #define I40E_DEV_ID_KX_C                0x1581
  43 #define I40E_DEV_ID_QSFP_A              0x1583
  44 #define I40E_DEV_ID_QSFP_B              0x1584
  45 #define I40E_DEV_ID_QSFP_C              0x1585
  46 #define I40E_DEV_ID_10G_BASE_T          0x1586
  47 #define I40E_DEV_ID_20G_KR2             0x1587
  48 #define I40E_DEV_ID_VF                  0x154C
  49 #define I40E_DEV_ID_VF_HV               0x1571
  50 #define I40E_DEV_ID_SFP_X722            0x37D0
  51 #define I40E_DEV_ID_1G_BASE_T_X722      0x37D1
  52 #define I40E_DEV_ID_10G_BASE_T_X722     0x37D2
  53 #define I40E_DEV_ID_X722_VF             0x37CD
  54 #define I40E_DEV_ID_X722_VF_HV          0x37D9
  55
  56 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  57                                          (d) == I40E_DEV_ID_QSFP_B  || \
  58                                          (d) == I40E_DEV_ID_QSFP_C)
  59
  60 /* I40E_MASK is a macro used on 32 bit registers */
  61 #define I40E_MASK(mask, shift) (mask << shift)
  62
  63 #define I40E_MAX_VSI_QP                 16
  64 #define I40E_MAX_VF_VSI                 3
  65 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  66 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  67
  68 /* Max default timeout in ms, */
  69 #define I40E_MAX_NVM_TIMEOUT            18000
  70
  71 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  72 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  73
  74 /* forward declaration */
  75 struct i40e_hw;
  76 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  77
  78 /* Data type manipulation macros. */
  79
  80 #define I40E_DESC_UNUSED(R)     \
  81         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  82         (R)->next_to_clean - (R)->next_to_use - 1)
  83
  84 /* bitfields for Tx queue mapping in QTX_CTL */
  85 #define I40E_QTX_CTL_VF_QUEUE   0x0
  86 #define I40E_QTX_CTL_VM_QUEUE   0x1
  87 #define I40E_QTX_CTL_PF_QUEUE   0x2
  88
  89 /* debug masks - set these bits in hw->debug_mask to control output */
  90 enum i40e_debug_mask {
  91         I40E_DEBUG_INIT                 = 0x00000001,
  92         I40E_DEBUG_RELEASE              = 0x00000002,
  93
  94         I40E_DEBUG_LINK                 = 0x00000010,
  95         I40E_DEBUG_PHY                  = 0x00000020,
  96         I40E_DEBUG_HMC                  = 0x00000040,
  97         I40E_DEBUG_NVM                  = 0x00000080,
  98         I40E_DEBUG_LAN                  = 0x00000100,
  99         I40E_DEBUG_FLOW                 = 0x00000200,
 100         I40E_DEBUG_DCB                  = 0x00000400,
 101         I40E_DEBUG_DIAG                 = 0x00000800,
 102         I40E_DEBUG_FD                   = 0x00001000,
 103
 104         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 105         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 106         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 107         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 108         I40E_DEBUG_AQ                   = 0x0F000000,
 109
 110         I40E_DEBUG_USER                 = 0xF0000000,
 111
 112         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 113 };
 114
 115 /* These are structs for managing the hardware information and the operations.
 116  * The structures of function pointers are filled out at init time when we
 117  * know for sure exactly which hardware we're working with.  This gives us the
 118  * flexibility of using the same main driver code but adapting to slightly
 119  * different hardware needs as new parts are developed.  For this architecture,
 120  * the Firmware and AdminQ are intended to insulate the driver from most of the
 121  * future changes, but these structures will also do part of the job.
 122  */
 123 enum i40e_mac_type {
 124         I40E_MAC_UNKNOWN = 0,
 125         I40E_MAC_X710,
 126         I40E_MAC_XL710,
 127         I40E_MAC_VF,
 128         I40E_MAC_X722,
 129         I40E_MAC_X722_VF,
 130         I40E_MAC_GENERIC,
 131 };
 132
 133 enum i40e_media_type {
 134         I40E_MEDIA_TYPE_UNKNOWN = 0,
 135         I40E_MEDIA_TYPE_FIBER,
 136         I40E_MEDIA_TYPE_BASET,
 137         I40E_MEDIA_TYPE_BACKPLANE,
 138         I40E_MEDIA_TYPE_CX4,
 139         I40E_MEDIA_TYPE_DA,
 140         I40E_MEDIA_TYPE_VIRTUAL
 141 };
 142
 143 enum i40e_fc_mode {
 144         I40E_FC_NONE = 0,
 145         I40E_FC_RX_PAUSE,
 146         I40E_FC_TX_PAUSE,
 147         I40E_FC_FULL,
 148         I40E_FC_PFC,
 149         I40E_FC_DEFAULT
 150 };
 151
 152 enum i40e_set_fc_aq_failures {
 153         I40E_SET_FC_AQ_FAIL_NONE = 0,
 154         I40E_SET_FC_AQ_FAIL_GET = 1,
 155         I40E_SET_FC_AQ_FAIL_SET = 2,
 156         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 157         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 158 };
 159
 160 enum i40e_vsi_type {
 161         I40E_VSI_MAIN = 0,
 162         I40E_VSI_VMDQ1,
 163         I40E_VSI_VMDQ2,
 164         I40E_VSI_CTRL,
 165         I40E_VSI_FCOE,
 166         I40E_VSI_MIRROR,
 167         I40E_VSI_SRIOV,
 168         I40E_VSI_FDIR,
 169         I40E_VSI_TYPE_UNKNOWN
 170 };
 171
 172 enum i40e_queue_type {
 173         I40E_QUEUE_TYPE_RX = 0,
 174         I40E_QUEUE_TYPE_TX,
 175         I40E_QUEUE_TYPE_PE_CEQ,
 176         I40E_QUEUE_TYPE_UNKNOWN
 177 };
 178
 179 struct i40e_link_status {
 180         enum i40e_aq_phy_type phy_type;
 181         enum i40e_aq_link_speed link_speed;
 182         u8 link_info;
 183         u8 an_info;
 184         u8 ext_info;
 185         u8 loopback;
 186         /* is Link Status Event notification to SW enabled */
 187         bool lse_enable;
 188         u16 max_frame_size;
 189         bool crc_enable;
 190         u8 pacing;
 191         u8 requested_speeds;
 192 };
 193
 194 struct i40e_phy_info {
 195         struct i40e_link_status link_info;
 196         struct i40e_link_status link_info_old;
 197         u32 autoneg_advertised;
 198         u32 phy_id;
 199         u32 module_type;
 200         bool get_link_info;
 201         enum i40e_media_type media_type;
 202 };
 203
 204 #define I40E_HW_CAP_MAX_GPIO                    30
 205 /* Capabilities of a PF or a VF or the whole device */
 206 struct i40e_hw_capabilities {
 207         u32  switch_mode;
 208 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 209 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 210 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 211
 212         u32  management_mode;
 213         u32  npar_enable;
 214         u32  os2bmc;
 215         u32  valid_functions;
 216         bool sr_iov_1_1;
 217         bool vmdq;
 218         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 219         bool evb_802_1_qbh; /* Bridge Port Extension */
 220         bool dcb;
 221         bool fcoe;
 222         bool iscsi; /* Indicates iSCSI enabled */
 223         bool flex10_enable;
 224         bool flex10_capable;
 225         u32  flex10_mode;
 226 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 227 #define I40E_FLEX10_MODE_DCC            0x1
 228 #define I40E_FLEX10_MODE_DCI            0x2
 229
 230         u32 flex10_status;
 231 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 232 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 233
 234         bool mgmt_cem;
 235         bool ieee_1588;
 236         bool iwarp;
 237         bool fd;
 238         u32 fd_filters_guaranteed;
 239         u32 fd_filters_best_effort;
 240         bool rss;
 241         u32 rss_table_size;
 242         u32 rss_table_entry_width;
 243         bool led[I40E_HW_CAP_MAX_GPIO];
 244         bool sdp[I40E_HW_CAP_MAX_GPIO];
 245         u32 nvm_image_type;
 246         u32 num_flow_director_filters;
 247         u32 num_vfs;
 248         u32 vf_base_id;
 249         u32 num_vsis;
 250         u32 num_rx_qp;
 251         u32 num_tx_qp;
 252         u32 base_queue;
 253         u32 num_msix_vectors;
 254         u32 num_msix_vectors_vf;
 255         u32 led_pin_num;
 256         u32 sdp_pin_num;
 257         u32 mdio_port_num;
 258         u32 mdio_port_mode;
 259         u8 rx_buf_chain_len;
 260         u32 enabled_tcmap;
 261         u32 maxtc;
 262         u64 wr_csr_prot;
 263 };
 264
 265 struct i40e_mac_info {
 266         enum i40e_mac_type type;
 267         u8 addr[ETH_ALEN];
 268         u8 perm_addr[ETH_ALEN];
 269         u8 san_addr[ETH_ALEN];
 270         u8 port_addr[ETH_ALEN];
 271         u16 max_fcoeq;
 272 };
 273
 274 enum i40e_aq_resources_ids {
 275         I40E_NVM_RESOURCE_ID = 1
 276 };
 277
 278 enum i40e_aq_resource_access_type {
 279         I40E_RESOURCE_READ = 1,
 280         I40E_RESOURCE_WRITE
 281 };
 282
 283 struct i40e_nvm_info {
 284         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 285         u32 timeout;              /* [ms] */
 286         u16 sr_size;              /* Shadow RAM size in words */
 287         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 288         u16 version;              /* NVM package version */
 289         u32 eetrack;              /* NVM data version */
 290 };
 291
 292 /* definitions used in NVM update support */
 293
 294 enum i40e_nvmupd_cmd {
 295         I40E_NVMUPD_INVALID,
 296         I40E_NVMUPD_READ_CON,
 297         I40E_NVMUPD_READ_SNT,
 298         I40E_NVMUPD_READ_LCB,
 299         I40E_NVMUPD_READ_SA,
 300         I40E_NVMUPD_WRITE_ERA,
 301         I40E_NVMUPD_WRITE_CON,
 302         I40E_NVMUPD_WRITE_SNT,
 303         I40E_NVMUPD_WRITE_LCB,
 304         I40E_NVMUPD_WRITE_SA,
 305         I40E_NVMUPD_CSUM_CON,
 306         I40E_NVMUPD_CSUM_SA,
 307         I40E_NVMUPD_CSUM_LCB,
 308 };
 309
 310 enum i40e_nvmupd_state {
 311         I40E_NVMUPD_STATE_INIT,
 312         I40E_NVMUPD_STATE_READING,
 313         I40E_NVMUPD_STATE_WRITING
 314 };
 315
 316 /* nvm_access definition and its masks/shifts need to be accessible to
 317  * application, core driver, and shared code.  Where is the right file?
 318  */
 319 #define I40E_NVM_READ   0xB
 320 #define I40E_NVM_WRITE  0xC
 321
 322 #define I40E_NVM_MOD_PNT_MASK 0xFF
 323
 324 #define I40E_NVM_TRANS_SHIFT    8
 325 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 326 #define I40E_NVM_CON            0x0
 327 #define I40E_NVM_SNT            0x1
 328 #define I40E_NVM_LCB            0x2
 329 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 330 #define I40E_NVM_ERA            0x4
 331 #define I40E_NVM_CSUM           0x8
 332
 333 #define I40E_NVM_ADAPT_SHIFT    16
 334 #define I40E_NVM_ADAPT_MASK     (0xffff << I40E_NVM_ADAPT_SHIFT)
 335
 336 #define I40E_NVMUPD_MAX_DATA    4096
 337 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 338
 339 struct i40e_nvm_access {
 340         u32 command;
 341         u32 config;
 342         u32 offset;     /* in bytes */
 343         u32 data_size;  /* in bytes */
 344         u8 data[1];
 345 };
 346
 347 /* PCI bus types */
 348 enum i40e_bus_type {
 349         i40e_bus_type_unknown = 0,
 350         i40e_bus_type_pci,
 351         i40e_bus_type_pcix,
 352         i40e_bus_type_pci_express,
 353         i40e_bus_type_reserved
 354 };
 355
 356 /* PCI bus speeds */
 357 enum i40e_bus_speed {
 358         i40e_bus_speed_unknown  = 0,
 359         i40e_bus_speed_33       = 33,
 360         i40e_bus_speed_66       = 66,
 361         i40e_bus_speed_100      = 100,
 362         i40e_bus_speed_120      = 120,
 363         i40e_bus_speed_133      = 133,
 364         i40e_bus_speed_2500     = 2500,
 365         i40e_bus_speed_5000     = 5000,
 366         i40e_bus_speed_8000     = 8000,
 367         i40e_bus_speed_reserved
 368 };
 369
 370 /* PCI bus widths */
 371 enum i40e_bus_width {
 372         i40e_bus_width_unknown  = 0,
 373         i40e_bus_width_pcie_x1  = 1,
 374         i40e_bus_width_pcie_x2  = 2,
 375         i40e_bus_width_pcie_x4  = 4,
 376         i40e_bus_width_pcie_x8  = 8,
 377         i40e_bus_width_32       = 32,
 378         i40e_bus_width_64       = 64,
 379         i40e_bus_width_reserved
 380 };
 381
 382 /* Bus parameters */
 383 struct i40e_bus_info {
 384         enum i40e_bus_speed speed;
 385         enum i40e_bus_width width;
 386         enum i40e_bus_type type;
 387
 388         u16 func;
 389         u16 device;
 390         u16 lan_id;
 391 };
 392
 393 /* Flow control (FC) parameters */
 394 struct i40e_fc_info {
 395         enum i40e_fc_mode current_mode; /* FC mode in effect */
 396         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 397 };
 398
 399 #define I40E_MAX_TRAFFIC_CLASS          8
 400 #define I40E_MAX_USER_PRIORITY          8
 401 #define I40E_DCBX_MAX_APPS              32
 402 #define I40E_LLDPDU_SIZE                1500
 403 #define I40E_TLV_STATUS_OPER            0x1
 404 #define I40E_TLV_STATUS_SYNC            0x2
 405 #define I40E_TLV_STATUS_ERR             0x4
 406 #define I40E_CEE_OPER_MAX_APPS          3
 407 #define I40E_APP_PROTOID_FCOE           0x8906
 408 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 409 #define I40E_APP_PROTOID_FIP            0x8914
 410 #define I40E_APP_SEL_ETHTYPE            0x1
 411 #define I40E_APP_SEL_TCPIP              0x2
 412
 413 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 414 struct i40e_dcb_ets_config {
 415         u8 willing;
 416         u8 cbs;
 417         u8 maxtcs;
 418         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 419         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 420         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 421 };
 422
 423 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 424 struct i40e_dcb_pfc_config {
 425         u8 willing;
 426         u8 mbc;
 427         u8 pfccap;
 428         u8 pfcenable;
 429 };
 430
 431 /* CEE or IEEE 802.1Qaz Application Priority data */
 432 struct i40e_dcb_app_priority_table {
 433         u8  priority;
 434         u8  selector;
 435         u16 protocolid;
 436 };
 437
 438 struct i40e_dcbx_config {
 439         u8  dcbx_mode;
 440 #define I40E_DCBX_MODE_CEE      0x1
 441 #define I40E_DCBX_MODE_IEEE     0x2
 442         u32 numapps;
 443         u32 tlv_status; /* CEE mode TLV status */
 444         struct i40e_dcb_ets_config etscfg;
 445         struct i40e_dcb_ets_config etsrec;
 446         struct i40e_dcb_pfc_config pfc;
 447         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 448 };
 449
 450 /* Port hardware description */
 451 struct i40e_hw {
 452         u8 __iomem *hw_addr;
 453         void *back;
 454
 455         /* subsystem structs */
 456         struct i40e_phy_info phy;
 457         struct i40e_mac_info mac;
 458         struct i40e_bus_info bus;
 459         struct i40e_nvm_info nvm;
 460         struct i40e_fc_info fc;
 461
 462         /* pci info */
 463         u16 device_id;
 464         u16 vendor_id;
 465         u16 subsystem_device_id;
 466         u16 subsystem_vendor_id;
 467         u8 revision_id;
 468         u8 port;
 469         bool adapter_stopped;
 470
 471         /* capabilities for entire device and PCI func */
 472         struct i40e_hw_capabilities dev_caps;
 473         struct i40e_hw_capabilities func_caps;
 474
 475         /* Flow Director shared filter space */
 476         u16 fdir_shared_filter_count;
 477
 478         /* device profile info */
 479         u8  pf_id;
 480         u16 main_vsi_seid;
 481
 482         /* for multi-function MACs */
 483         u16 partition_id;
 484         u16 num_partitions;
 485         u16 num_ports;
 486
 487         /* Closest numa node to the device */
 488         u16 numa_node;
 489
 490         /* Admin Queue info */
 491         struct i40e_adminq_info aq;
 492
 493         /* state of nvm update process */
 494         enum i40e_nvmupd_state nvmupd_state;
 495         struct i40e_aq_desc nvm_wb_desc;
 496
 497         /* HMC info */
 498         struct i40e_hmc_info hmc; /* HMC info struct */
 499
 500         /* LLDP/DCBX Status */
 501         u16 dcbx_status;
 502
 503         /* DCBX info */
 504         struct i40e_dcbx_config local_dcbx_config;
 505         struct i40e_dcbx_config remote_dcbx_config;
 506
 507         /* debug mask */
 508         u32 debug_mask;
 509         char err_str[16];
 510 };
 511
 512 static inline bool i40e_is_vf(struct i40e_hw *hw)
 513 {
 514         return (hw->mac.type == I40E_MAC_VF ||
 515                 hw->mac.type == I40E_MAC_X722_VF);
 516 }
 517
 518 struct i40e_driver_version {
 519         u8 major_version;
 520         u8 minor_version;
 521         u8 build_version;
 522         u8 subbuild_version;
 523         u8 driver_string[32];
 524 };
 525
 526 /* RX Descriptors */
 527 union i40e_16byte_rx_desc {
 528         struct {
 529                 __le64 pkt_addr; /* Packet buffer address */
 530                 __le64 hdr_addr; /* Header buffer address */
 531         } read;
 532         struct {
 533                 struct {
 534                         struct {
 535                                 union {
 536                                         __le16 mirroring_status;
 537                                         __le16 fcoe_ctx_id;
 538                                 } mirr_fcoe;
 539                                 __le16 l2tag1;
 540                         } lo_dword;
 541                         union {
 542                                 __le32 rss; /* RSS Hash */
 543                                 __le32 fd_id; /* Flow director filter id */
 544                                 __le32 fcoe_param; /* FCoE DDP Context id */
 545                         } hi_dword;
 546                 } qword0;
 547                 struct {
 548                         /* ext status/error/pktype/length */
 549                         __le64 status_error_len;
 550                 } qword1;
 551         } wb;  /* writeback */
 552 };
 553
 554 union i40e_32byte_rx_desc {
 555         struct {
 556                 __le64  pkt_addr; /* Packet buffer address */
 557                 __le64  hdr_addr; /* Header buffer address */
 558                         /* bit 0 of hdr_buffer_addr is DD bit */
 559                 __le64  rsvd1;
 560                 __le64  rsvd2;
 561         } read;
 562         struct {
 563                 struct {
 564                         struct {
 565                                 union {
 566                                         __le16 mirroring_status;
 567                                         __le16 fcoe_ctx_id;
 568                                 } mirr_fcoe;
 569                                 __le16 l2tag1;
 570                         } lo_dword;
 571                         union {
 572                                 __le32 rss; /* RSS Hash */
 573                                 __le32 fcoe_param; /* FCoE DDP Context id */
 574                                 /* Flow director filter id in case of
 575                                  * Programming status desc WB
 576                                  */
 577                                 __le32 fd_id;
 578                         } hi_dword;
 579                 } qword0;
 580                 struct {
 581                         /* status/error/pktype/length */
 582                         __le64 status_error_len;
 583                 } qword1;
 584                 struct {
 585                         __le16 ext_status; /* extended status */
 586                         __le16 rsvd;
 587                         __le16 l2tag2_1;
 588                         __le16 l2tag2_2;
 589                 } qword2;
 590                 struct {
 591                         union {
 592                                 __le32 flex_bytes_lo;
 593                                 __le32 pe_status;
 594                         } lo_dword;
 595                         union {
 596                                 __le32 flex_bytes_hi;
 597                                 __le32 fd_id;
 598                         } hi_dword;
 599                 } qword3;
 600         } wb;  /* writeback */
 601 };
 602
 603 enum i40e_rx_desc_status_bits {
 604         /* Note: These are predefined bit offsets */
 605         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 606         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 607         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 608         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 609         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 610         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 611         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 612         /* Note: Bit 8 is reserved in X710 and XL710 */
 613         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 614         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 615         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 616         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 617         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 618         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 619         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 620         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 621          * UDP header
 622          */
 623         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 624         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 625 };
 626
 627 #define I40E_RXD_QW1_STATUS_SHIFT       0
 628 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 629                                          << I40E_RXD_QW1_STATUS_SHIFT)
 630
 631 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 632 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 633                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 634
 635 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 636 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 637                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 638
 639 enum i40e_rx_desc_fltstat_values {
 640         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 641         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 642         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 643         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 644 };
 645
 646 #define I40E_RXD_QW1_ERROR_SHIFT        19
 647 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 648
 649 enum i40e_rx_desc_error_bits {
 650         /* Note: These are predefined bit offsets */
 651         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 652         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 653         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 654         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 655         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 656         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 657         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 658         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 659         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 660 };
 661
 662 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 663         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 664         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 665         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 666         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 667         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 668 };
 669
 670 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 671 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 672
 673 /* Packet type non-ip values */
 674 enum i40e_rx_l2_ptype {
 675         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 676         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 677         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 678         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 679         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 680         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 681         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 682         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 683         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 684         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 685         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 686         I40E_RX_PTYPE_L2_ARP                            = 11,
 687         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 688         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 689         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 690         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 691         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 692         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 693         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 694         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 695         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 696         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 697         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 698         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 699         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 700         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 701 };
 702
 703 struct i40e_rx_ptype_decoded {
 704         u32 ptype:8;
 705         u32 known:1;
 706         u32 outer_ip:1;
 707         u32 outer_ip_ver:1;
 708         u32 outer_frag:1;
 709         u32 tunnel_type:3;
 710         u32 tunnel_end_prot:2;
 711         u32 tunnel_end_frag:1;
 712         u32 inner_prot:4;
 713         u32 payload_layer:3;
 714 };
 715
 716 enum i40e_rx_ptype_outer_ip {
 717         I40E_RX_PTYPE_OUTER_L2  = 0,
 718         I40E_RX_PTYPE_OUTER_IP  = 1
 719 };
 720
 721 enum i40e_rx_ptype_outer_ip_ver {
 722         I40E_RX_PTYPE_OUTER_NONE        = 0,
 723         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 724         I40E_RX_PTYPE_OUTER_IPV6        = 1
 725 };
 726
 727 enum i40e_rx_ptype_outer_fragmented {
 728         I40E_RX_PTYPE_NOT_FRAG  = 0,
 729         I40E_RX_PTYPE_FRAG      = 1
 730 };
 731
 732 enum i40e_rx_ptype_tunnel_type {
 733         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 734         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 735         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 736         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 737         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 738 };
 739
 740 enum i40e_rx_ptype_tunnel_end_prot {
 741         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 742         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 743         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 744 };
 745
 746 enum i40e_rx_ptype_inner_prot {
 747         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 748         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 749         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 750         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 751         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 752         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 753 };
 754
 755 enum i40e_rx_ptype_payload_layer {
 756         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 757         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 758         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 759         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 760 };
 761
 762 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 763 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 764                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 765
 766 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 767 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 768                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 769
 770 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 771 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 772
 773 enum i40e_rx_desc_ext_status_bits {
 774         /* Note: These are predefined bit offsets */
 775         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 776         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 777         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 778         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 779         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 780         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 781         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 782 };
 783
 784 enum i40e_rx_desc_pe_status_bits {
 785         /* Note: These are predefined bit offsets */
 786         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 787         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 788         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 789         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 790         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 791         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 792         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 793         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 794         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 795 };
 796
 797 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 798 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 799
 800 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 801 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 802                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 803
 804 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 805 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 806                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 807
 808 enum i40e_rx_prog_status_desc_status_bits {
 809         /* Note: These are predefined bit offsets */
 810         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 811         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 812 };
 813
 814 enum i40e_rx_prog_status_desc_prog_id_masks {
 815         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 816         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 817         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 818 };
 819
 820 enum i40e_rx_prog_status_desc_error_bits {
 821         /* Note: These are predefined bit offsets */
 822         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 823         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 824         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 825         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 826 };
 827
 828 /* TX Descriptor */
 829 struct i40e_tx_desc {
 830         __le64 buffer_addr; /* Address of descriptor's data buf */
 831         __le64 cmd_type_offset_bsz;
 832 };
 833
 834 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 835 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 836
 837 enum i40e_tx_desc_dtype_value {
 838         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 839         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 840         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 841         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 842         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 843         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 844         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 845         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 846         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 847         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 848 };
 849
 850 #define I40E_TXD_QW1_CMD_SHIFT  4
 851 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 852
 853 enum i40e_tx_desc_cmd_bits {
 854         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 855         I40E_TX_DESC_CMD_RS                     = 0x0002,
 856         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 857         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 858         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 859         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 860         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 861         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 862         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 863         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 864         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 865         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 866         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 867         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 868         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 869         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 870         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 871         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 872 };
 873
 874 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 875 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 876                                          I40E_TXD_QW1_OFFSET_SHIFT)
 877
 878 enum i40e_tx_desc_length_fields {
 879         /* Note: These are predefined bit offsets */
 880         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 881         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 882         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 883 };
 884
 885 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 886 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 887                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 888
 889 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 890 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 891
 892 /* Context descriptors */
 893 struct i40e_tx_context_desc {
 894         __le32 tunneling_params;
 895         __le16 l2tag2;
 896         __le16 rsvd;
 897         __le64 type_cmd_tso_mss;
 898 };
 899
 900 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 901 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 902
 903 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 904 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 905
 906 enum i40e_tx_ctx_desc_cmd_bits {
 907         I40E_TX_CTX_DESC_TSO            = 0x01,
 908         I40E_TX_CTX_DESC_TSYN           = 0x02,
 909         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 910         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 911         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 912         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 913         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 914         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 915         I40E_TX_CTX_DESC_SWPE           = 0x40
 916 };
 917
 918 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 919 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 920                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 921
 922 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 923 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 924                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 925
 926 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 927 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 928
 929 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 930 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 931                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 932
 933 enum i40e_tx_ctx_desc_eipt_offload {
 934         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 935         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 936         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 937         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 938 };
 939
 940 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 941 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 942                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 943
 944 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 945 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 946
 947 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
 948 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 949
 950 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 951 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
 952                                        BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 953
 954 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 955
 956 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 957 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 958                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 959
 960 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 961 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 962                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 963
 964 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
 965 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
 966 struct i40e_filter_program_desc {
 967         __le32 qindex_flex_ptype_vsi;
 968         __le32 rsvd;
 969         __le32 dtype_cmd_cntindex;
 970         __le32 fd_id;
 971 };
 972 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 973 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 974                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 975 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 976 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 977                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 978 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 979 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 980                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 981
 982 /* Packet Classifier Types for filters */
 983 enum i40e_filter_pctype {
 984         /* Note: Values 0-28 are reserved for future use.
 985          * Value 29, 30, 32 are not supported on XL710 and X710.
 986          */
 987         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
 988         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
 989         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 990         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
 991         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 992         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 993         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 994         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 995         /* Note: Values 37-38 are reserved for future use.
 996          * Value 39, 40, 42 are not supported on XL710 and X710.
 997          */
 998         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
 999         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1000         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1001         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1002         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1003         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1004         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1005         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1006         /* Note: Value 47 is reserved for future use */
1007         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1008         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1009         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1010         /* Note: Values 51-62 are reserved for future use */
1011         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1012 };
1013
1014 enum i40e_filter_program_desc_dest {
1015         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1016         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1017         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1018 };
1019
1020 enum i40e_filter_program_desc_fd_status {
1021         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1022         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1023         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1024         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1025 };
1026
1027 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1028 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1029                                        BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1030
1031 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1032 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1033                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1034
1035 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1036 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1037
1038 enum i40e_filter_program_desc_pcmd {
1039         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1040         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1041 };
1042
1043 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1044 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1045
1046 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1047 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1048
1049 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1050                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1051 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1052                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1053
1054 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1055                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1056 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1057
1058 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1059 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1060                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1061
1062 enum i40e_filter_type {
1063         I40E_FLOW_DIRECTOR_FLTR = 0,
1064         I40E_PE_QUAD_HASH_FLTR = 1,
1065         I40E_ETHERTYPE_FLTR,
1066         I40E_FCOE_CTX_FLTR,
1067         I40E_MAC_VLAN_FLTR,
1068         I40E_HASH_FLTR
1069 };
1070
1071 struct i40e_vsi_context {
1072         u16 seid;
1073         u16 uplink_seid;
1074         u16 vsi_number;
1075         u16 vsis_allocated;
1076         u16 vsis_unallocated;
1077         u16 flags;
1078         u8 pf_num;
1079         u8 vf_num;
1080         u8 connection_type;
1081         struct i40e_aqc_vsi_properties_data info;
1082 };
1083
1084 struct i40e_veb_context {
1085         u16 seid;
1086         u16 uplink_seid;
1087         u16 veb_number;
1088         u16 vebs_allocated;
1089         u16 vebs_unallocated;
1090         u16 flags;
1091         struct i40e_aqc_get_veb_parameters_completion info;
1092 };
1093
1094 /* Statistics collected by each port, VSI, VEB, and S-channel */
1095 struct i40e_eth_stats {
1096         u64 rx_bytes;                   /* gorc */
1097         u64 rx_unicast;                 /* uprc */
1098         u64 rx_multicast;               /* mprc */
1099         u64 rx_broadcast;               /* bprc */
1100         u64 rx_discards;                /* rdpc */
1101         u64 rx_unknown_protocol;        /* rupp */
1102         u64 tx_bytes;                   /* gotc */
1103         u64 tx_unicast;                 /* uptc */
1104         u64 tx_multicast;               /* mptc */
1105         u64 tx_broadcast;               /* bptc */
1106         u64 tx_discards;                /* tdpc */
1107         u64 tx_errors;                  /* tepc */
1108 };
1109
1110 /* Statistics collected per VEB per TC */
1111 struct i40e_veb_tc_stats {
1112         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1113         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1114         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1115         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1116 };
1117
1118 #ifdef I40E_FCOE
1119 /* Statistics collected per function for FCoE */
1120 struct i40e_fcoe_stats {
1121         u64 rx_fcoe_packets;            /* fcoeprc */
1122         u64 rx_fcoe_dwords;             /* focedwrc */
1123         u64 rx_fcoe_dropped;            /* fcoerpdc */
1124         u64 tx_fcoe_packets;            /* fcoeptc */
1125         u64 tx_fcoe_dwords;             /* focedwtc */
1126         u64 fcoe_bad_fccrc;             /* fcoecrc */
1127         u64 fcoe_last_error;            /* fcoelast */
1128         u64 fcoe_ddp_count;             /* fcoeddpc */
1129 };
1130
1131 /* offset to per function FCoE statistics block */
1132 #define I40E_FCOE_VF_STAT_OFFSET        0
1133 #define I40E_FCOE_PF_STAT_OFFSET        128
1134 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1135
1136 #endif
1137 /* Statistics collected by the MAC */
1138 struct i40e_hw_port_stats {
1139         /* eth stats collected by the port */
1140         struct i40e_eth_stats eth;
1141
1142         /* additional port specific stats */
1143         u64 tx_dropped_link_down;       /* tdold */
1144         u64 crc_errors;                 /* crcerrs */
1145         u64 illegal_bytes;              /* illerrc */
1146         u64 error_bytes;                /* errbc */
1147         u64 mac_local_faults;           /* mlfc */
1148         u64 mac_remote_faults;          /* mrfc */
1149         u64 rx_length_errors;           /* rlec */
1150         u64 link_xon_rx;                /* lxonrxc */
1151         u64 link_xoff_rx;               /* lxoffrxc */
1152         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1153         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1154         u64 link_xon_tx;                /* lxontxc */
1155         u64 link_xoff_tx;               /* lxofftxc */
1156         u64 priority_xon_tx[8];         /* pxontxc[8] */
1157         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1158         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1159         u64 rx_size_64;                 /* prc64 */
1160         u64 rx_size_127;                /* prc127 */
1161         u64 rx_size_255;                /* prc255 */
1162         u64 rx_size_511;                /* prc511 */
1163         u64 rx_size_1023;               /* prc1023 */
1164         u64 rx_size_1522;               /* prc1522 */
1165         u64 rx_size_big;                /* prc9522 */
1166         u64 rx_undersize;               /* ruc */
1167         u64 rx_fragments;               /* rfc */
1168         u64 rx_oversize;                /* roc */
1169         u64 rx_jabber;                  /* rjc */
1170         u64 tx_size_64;                 /* ptc64 */
1171         u64 tx_size_127;                /* ptc127 */
1172         u64 tx_size_255;                /* ptc255 */
1173         u64 tx_size_511;                /* ptc511 */
1174         u64 tx_size_1023;               /* ptc1023 */
1175         u64 tx_size_1522;               /* ptc1522 */
1176         u64 tx_size_big;                /* ptc9522 */
1177         u64 mac_short_packet_dropped;   /* mspdc */
1178         u64 checksum_error;             /* xec */
1179         /* flow director stats */
1180         u64 fd_atr_match;
1181         u64 fd_sb_match;
1182         u64 fd_atr_tunnel_match;
1183         u32 fd_atr_status;
1184         u32 fd_sb_status;
1185         /* EEE LPI */
1186         u32 tx_lpi_status;
1187         u32 rx_lpi_status;
1188         u64 tx_lpi_count;               /* etlpic */
1189         u64 rx_lpi_count;               /* erlpic */
1190 };
1191
1192 /* Checksum and Shadow RAM pointers */
1193 #define I40E_SR_NVM_CONTROL_WORD                0x00
1194 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1195 #define I40E_SR_PBA_FLAGS                       0x15
1196 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1197 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1198 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1199 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1200 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1201 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1202 #define I40E_SR_VPD_PTR                         0x2F
1203 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1204 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1205
1206 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1207 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1208 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1209 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1210 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1211
1212 /* Shadow RAM related */
1213 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1214 #define I40E_SR_WORDS_IN_1KB            512
1215 /* Checksum should be calculated such that after adding all the words,
1216  * including the checksum word itself, the sum should be 0xBABA.
1217  */
1218 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1219
1220 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1221
1222 #ifdef I40E_FCOE
1223 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1224
1225 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1226         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1227         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1228         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1229         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1230         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1231         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1232         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1233         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1234         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1235         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1236         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1237         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1238         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1239 };
1240
1241 /* FCoE DDP Context descriptor */
1242 struct i40e_fcoe_ddp_context_desc {
1243         __le64 rsvd;
1244         __le64 type_cmd_foff_lsize;
1245 };
1246
1247 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1248 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1249                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1250
1251 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1252 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1253                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1254
1255 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1256         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1257         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1258         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1259         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1260         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1261         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1262 };
1263
1264 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1265 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1266                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1267
1268 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1269 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1270                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1271
1272 /* FCoE DDP/DWO Queue Context descriptor */
1273 struct i40e_fcoe_queue_context_desc {
1274         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1275         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1276 };
1277
1278 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1279 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1280                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1281
1282 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1283 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1284                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1285
1286 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1287 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1288                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1289
1290 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1291 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1292                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1293
1294 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1295         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1296         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1297 };
1298
1299 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1300 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1301                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1302
1303 /* FCoE DDP/DWO Filter Context descriptor */
1304 struct i40e_fcoe_filter_context_desc {
1305         __le32 param;
1306         __le16 seqn;
1307
1308         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1309         __le16 rsvd_dmaindx;
1310
1311         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1312         __le64 flags_rsvd_lanq;
1313 };
1314
1315 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1316 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1317                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1318
1319 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1320         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1321         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1322         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1323         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1324         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1325         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1326 };
1327
1328 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1329 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1330                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1331
1332 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1333 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1334                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1335
1336 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1337 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1338                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1339
1340 #endif /* I40E_FCOE */
1341 enum i40e_switch_element_types {
1342         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1343         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1344         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1345         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1346         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1347         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1348         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1349         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1350         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1351 };
1352
1353 /* Supported EtherType filters */
1354 enum i40e_ether_type_index {
1355         I40E_ETHER_TYPE_1588            = 0,
1356         I40E_ETHER_TYPE_FIP             = 1,
1357         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1358         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1359         I40E_ETHER_TYPE_LLDP            = 4,
1360         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1361         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1362         I40E_ETHER_TYPE_QCN_CNM         = 7,
1363         I40E_ETHER_TYPE_8021X           = 8,
1364         I40E_ETHER_TYPE_ARP             = 9,
1365         I40E_ETHER_TYPE_RSV1            = 10,
1366         I40E_ETHER_TYPE_RSV2            = 11,
1367 };
1368
1369 /* Filter context base size is 1K */
1370 #define I40E_HASH_FILTER_BASE_SIZE      1024
1371 /* Supported Hash filter values */
1372 enum i40e_hash_filter_size {
1373         I40E_HASH_FILTER_SIZE_1K        = 0,
1374         I40E_HASH_FILTER_SIZE_2K        = 1,
1375         I40E_HASH_FILTER_SIZE_4K        = 2,
1376         I40E_HASH_FILTER_SIZE_8K        = 3,
1377         I40E_HASH_FILTER_SIZE_16K       = 4,
1378         I40E_HASH_FILTER_SIZE_32K       = 5,
1379         I40E_HASH_FILTER_SIZE_64K       = 6,
1380         I40E_HASH_FILTER_SIZE_128K      = 7,
1381         I40E_HASH_FILTER_SIZE_256K      = 8,
1382         I40E_HASH_FILTER_SIZE_512K      = 9,
1383         I40E_HASH_FILTER_SIZE_1M        = 10,
1384 };
1385
1386 /* DMA context base size is 0.5K */
1387 #define I40E_DMA_CNTX_BASE_SIZE         512
1388 /* Supported DMA context values */
1389 enum i40e_dma_cntx_size {
1390         I40E_DMA_CNTX_SIZE_512          = 0,
1391         I40E_DMA_CNTX_SIZE_1K           = 1,
1392         I40E_DMA_CNTX_SIZE_2K           = 2,
1393         I40E_DMA_CNTX_SIZE_4K           = 3,
1394         I40E_DMA_CNTX_SIZE_8K           = 4,
1395         I40E_DMA_CNTX_SIZE_16K          = 5,
1396         I40E_DMA_CNTX_SIZE_32K          = 6,
1397         I40E_DMA_CNTX_SIZE_64K          = 7,
1398         I40E_DMA_CNTX_SIZE_128K         = 8,
1399         I40E_DMA_CNTX_SIZE_256K         = 9,
1400 };
1401
1402 /* Supported Hash look up table (LUT) sizes */
1403 enum i40e_hash_lut_size {
1404         I40E_HASH_LUT_SIZE_128          = 0,
1405         I40E_HASH_LUT_SIZE_512          = 1,
1406 };
1407
1408 /* Structure to hold a per PF filter control settings */
1409 struct i40e_filter_control_settings {
1410         /* number of PE Quad Hash filter buckets */
1411         enum i40e_hash_filter_size pe_filt_num;
1412         /* number of PE Quad Hash contexts */
1413         enum i40e_dma_cntx_size pe_cntx_num;
1414         /* number of FCoE filter buckets */
1415         enum i40e_hash_filter_size fcoe_filt_num;
1416         /* number of FCoE DDP contexts */
1417         enum i40e_dma_cntx_size fcoe_cntx_num;
1418         /* size of the Hash LUT */
1419         enum i40e_hash_lut_size hash_lut_size;
1420         /* enable FDIR filters for PF and its VFs */
1421         bool enable_fdir;
1422         /* enable Ethertype filters for PF and its VFs */
1423         bool enable_ethtype;
1424         /* enable MAC/VLAN filters for PF and its VFs */
1425         bool enable_macvlan;
1426 };
1427
1428 /* Structure to hold device level control filter counts */
1429 struct i40e_control_filter_stats {
1430         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1431         u16 etype_used;       /* Used perfect EtherType filters */
1432         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1433         u16 etype_free;       /* Un-used perfect EtherType filters */
1434 };
1435
1436 enum i40e_reset_type {
1437         I40E_RESET_POR          = 0,
1438         I40E_RESET_CORER        = 1,
1439         I40E_RESET_GLOBR        = 2,
1440         I40E_RESET_EMPR         = 3,
1441 };
1442
1443 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1444 #define I40E_NVM_LLDP_CFG_PTR           0xD
1445 struct i40e_lldp_variables {
1446         u16 length;
1447         u16 adminstatus;
1448         u16 msgfasttx;
1449         u16 msgtxinterval;
1450         u16 txparams;
1451         u16 timers;
1452         u16 crc8;
1453 };
1454
1455 /* Offsets into Alternate Ram */
1456 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1457 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1458 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1459 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1460 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1461 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1462
1463 /* Alternate Ram Bandwidth Masks */
1464 #define I40E_ALT_BW_VALUE_MASK          0xFF
1465 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1466 #define I40E_ALT_BW_VALID_MASK          0x80000000
1467
1468 /* RSS Hash Table Size */
1469 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1470 #endif /* _I40E_TYPE_H_ */