1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_status.h"
28 #include "i40e_type.h"
29 #include "i40e_register.h"
30 #include "i40e_adminq.h"
31 #include "i40e_prototype.h"
34 * i40e_is_nvm_update_op - return true if this is an NVM update operation
35 * @desc: API request descriptor
37 static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
39 return (desc->opcode == i40e_aqc_opc_nvm_erase) ||
40 (desc->opcode == i40e_aqc_opc_nvm_update);
44 * i40e_adminq_init_regs - Initialize AdminQ registers
45 * @hw: pointer to the hardware structure
47 * This assumes the alloc_asq and alloc_arq functions have already been called
49 static void i40e_adminq_init_regs(struct i40e_hw *hw)
51 /* set head and tail registers in our local struct */
53 hw->aq.asq.tail = I40E_VF_ATQT1;
54 hw->aq.asq.head = I40E_VF_ATQH1;
55 hw->aq.asq.len = I40E_VF_ATQLEN1;
56 hw->aq.asq.bal = I40E_VF_ATQBAL1;
57 hw->aq.asq.bah = I40E_VF_ATQBAH1;
58 hw->aq.arq.tail = I40E_VF_ARQT1;
59 hw->aq.arq.head = I40E_VF_ARQH1;
60 hw->aq.arq.len = I40E_VF_ARQLEN1;
61 hw->aq.arq.bal = I40E_VF_ARQBAL1;
62 hw->aq.arq.bah = I40E_VF_ARQBAH1;
67 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
68 * @hw: pointer to the hardware structure
70 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
74 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
76 (hw->aq.num_asq_entries *
77 sizeof(struct i40e_aq_desc)),
78 I40E_ADMINQ_DESC_ALIGNMENT);
82 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
83 (hw->aq.num_asq_entries *
84 sizeof(struct i40e_asq_cmd_details)));
86 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
94 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
95 * @hw: pointer to the hardware structure
97 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
101 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
103 (hw->aq.num_arq_entries *
104 sizeof(struct i40e_aq_desc)),
105 I40E_ADMINQ_DESC_ALIGNMENT);
111 * i40e_free_adminq_asq - Free Admin Queue send rings
112 * @hw: pointer to the hardware structure
114 * This assumes the posted send buffers have already been cleaned
117 static void i40e_free_adminq_asq(struct i40e_hw *hw)
119 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
123 * i40e_free_adminq_arq - Free Admin Queue receive rings
124 * @hw: pointer to the hardware structure
126 * This assumes the posted receive buffers have already been cleaned
129 static void i40e_free_adminq_arq(struct i40e_hw *hw)
131 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
135 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
136 * @hw: pointer to the hardware structure
138 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
140 i40e_status ret_code;
141 struct i40e_aq_desc *desc;
142 struct i40e_dma_mem *bi;
145 /* We'll be allocating the buffer info memory first, then we can
146 * allocate the mapped buffers for the event processing
149 /* buffer_info structures do not need alignment */
150 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
151 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
154 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
156 /* allocate the mapped buffers */
157 for (i = 0; i < hw->aq.num_arq_entries; i++) {
158 bi = &hw->aq.arq.r.arq_bi[i];
159 ret_code = i40e_allocate_dma_mem(hw, bi,
162 I40E_ADMINQ_DESC_ALIGNMENT);
164 goto unwind_alloc_arq_bufs;
166 /* now configure the descriptors for use */
167 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
169 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
170 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
171 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
173 /* This is in accordance with Admin queue design, there is no
174 * register for buffer size configuration
176 desc->datalen = cpu_to_le16((u16)bi->size);
178 desc->cookie_high = 0;
179 desc->cookie_low = 0;
180 desc->params.external.addr_high =
181 cpu_to_le32(upper_32_bits(bi->pa));
182 desc->params.external.addr_low =
183 cpu_to_le32(lower_32_bits(bi->pa));
184 desc->params.external.param0 = 0;
185 desc->params.external.param1 = 0;
191 unwind_alloc_arq_bufs:
192 /* don't try to free the one that failed... */
195 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
196 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
202 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
203 * @hw: pointer to the hardware structure
205 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
207 i40e_status ret_code;
208 struct i40e_dma_mem *bi;
211 /* No mapped memory needed yet, just the buffer info structures */
212 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
213 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
216 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
218 /* allocate the mapped buffers */
219 for (i = 0; i < hw->aq.num_asq_entries; i++) {
220 bi = &hw->aq.asq.r.asq_bi[i];
221 ret_code = i40e_allocate_dma_mem(hw, bi,
224 I40E_ADMINQ_DESC_ALIGNMENT);
226 goto unwind_alloc_asq_bufs;
231 unwind_alloc_asq_bufs:
232 /* don't try to free the one that failed... */
235 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
236 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
242 * i40e_free_arq_bufs - Free receive queue buffer info elements
243 * @hw: pointer to the hardware structure
245 static void i40e_free_arq_bufs(struct i40e_hw *hw)
249 /* free descriptors */
250 for (i = 0; i < hw->aq.num_arq_entries; i++)
251 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
253 /* free the descriptor memory */
254 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
256 /* free the dma header */
257 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
261 * i40e_free_asq_bufs - Free send queue buffer info elements
262 * @hw: pointer to the hardware structure
264 static void i40e_free_asq_bufs(struct i40e_hw *hw)
268 /* only unmap if the address is non-NULL */
269 for (i = 0; i < hw->aq.num_asq_entries; i++)
270 if (hw->aq.asq.r.asq_bi[i].pa)
271 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
273 /* free the buffer info list */
274 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
276 /* free the descriptor memory */
277 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
279 /* free the dma header */
280 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
284 * i40e_config_asq_regs - configure ASQ registers
285 * @hw: pointer to the hardware structure
287 * Configure base address and length registers for the transmit queue
289 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
291 i40e_status ret_code = 0;
294 /* Clear Head and Tail */
295 wr32(hw, hw->aq.asq.head, 0);
296 wr32(hw, hw->aq.asq.tail, 0);
298 /* set starting point */
299 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
300 I40E_VF_ATQLEN1_ATQENABLE_MASK));
301 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
302 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
304 /* Check one register to verify that config was applied */
305 reg = rd32(hw, hw->aq.asq.bal);
306 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
307 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
313 * i40e_config_arq_regs - ARQ register configuration
314 * @hw: pointer to the hardware structure
316 * Configure base address and length registers for the receive (event queue)
318 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
320 i40e_status ret_code = 0;
323 /* Clear Head and Tail */
324 wr32(hw, hw->aq.arq.head, 0);
325 wr32(hw, hw->aq.arq.tail, 0);
327 /* set starting point */
328 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
329 I40E_VF_ARQLEN1_ARQENABLE_MASK));
330 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
331 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
333 /* Update tail in the HW to post pre-allocated buffers */
334 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
336 /* Check one register to verify that config was applied */
337 reg = rd32(hw, hw->aq.arq.bal);
338 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
339 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
345 * i40e_init_asq - main initialization routine for ASQ
346 * @hw: pointer to the hardware structure
348 * This is the main initialization routine for the Admin Send Queue
349 * Prior to calling this function, drivers *MUST* set the following fields
350 * in the hw->aq structure:
351 * - hw->aq.num_asq_entries
352 * - hw->aq.arq_buf_size
354 * Do *NOT* hold the lock when calling this as the memory allocation routines
355 * called are not going to be atomic context safe
357 static i40e_status i40e_init_asq(struct i40e_hw *hw)
359 i40e_status ret_code = 0;
361 if (hw->aq.asq.count > 0) {
362 /* queue already initialized */
363 ret_code = I40E_ERR_NOT_READY;
364 goto init_adminq_exit;
367 /* verify input for valid configuration */
368 if ((hw->aq.num_asq_entries == 0) ||
369 (hw->aq.asq_buf_size == 0)) {
370 ret_code = I40E_ERR_CONFIG;
371 goto init_adminq_exit;
374 hw->aq.asq.next_to_use = 0;
375 hw->aq.asq.next_to_clean = 0;
377 /* allocate the ring memory */
378 ret_code = i40e_alloc_adminq_asq_ring(hw);
380 goto init_adminq_exit;
382 /* allocate buffers in the rings */
383 ret_code = i40e_alloc_asq_bufs(hw);
385 goto init_adminq_free_rings;
387 /* initialize base registers */
388 ret_code = i40e_config_asq_regs(hw);
390 goto init_adminq_free_rings;
393 hw->aq.asq.count = hw->aq.num_asq_entries;
394 goto init_adminq_exit;
396 init_adminq_free_rings:
397 i40e_free_adminq_asq(hw);
404 * i40e_init_arq - initialize ARQ
405 * @hw: pointer to the hardware structure
407 * The main initialization routine for the Admin Receive (Event) Queue.
408 * Prior to calling this function, drivers *MUST* set the following fields
409 * in the hw->aq structure:
410 * - hw->aq.num_asq_entries
411 * - hw->aq.arq_buf_size
413 * Do *NOT* hold the lock when calling this as the memory allocation routines
414 * called are not going to be atomic context safe
416 static i40e_status i40e_init_arq(struct i40e_hw *hw)
418 i40e_status ret_code = 0;
420 if (hw->aq.arq.count > 0) {
421 /* queue already initialized */
422 ret_code = I40E_ERR_NOT_READY;
423 goto init_adminq_exit;
426 /* verify input for valid configuration */
427 if ((hw->aq.num_arq_entries == 0) ||
428 (hw->aq.arq_buf_size == 0)) {
429 ret_code = I40E_ERR_CONFIG;
430 goto init_adminq_exit;
433 hw->aq.arq.next_to_use = 0;
434 hw->aq.arq.next_to_clean = 0;
436 /* allocate the ring memory */
437 ret_code = i40e_alloc_adminq_arq_ring(hw);
439 goto init_adminq_exit;
441 /* allocate buffers in the rings */
442 ret_code = i40e_alloc_arq_bufs(hw);
444 goto init_adminq_free_rings;
446 /* initialize base registers */
447 ret_code = i40e_config_arq_regs(hw);
449 goto init_adminq_free_rings;
452 hw->aq.arq.count = hw->aq.num_arq_entries;
453 goto init_adminq_exit;
455 init_adminq_free_rings:
456 i40e_free_adminq_arq(hw);
463 * i40e_shutdown_asq - shutdown the ASQ
464 * @hw: pointer to the hardware structure
466 * The main shutdown routine for the Admin Send Queue
468 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
470 i40e_status ret_code = 0;
472 mutex_lock(&hw->aq.asq_mutex);
474 if (hw->aq.asq.count == 0) {
475 ret_code = I40E_ERR_NOT_READY;
476 goto shutdown_asq_out;
479 /* Stop firmware AdminQ processing */
480 wr32(hw, hw->aq.asq.head, 0);
481 wr32(hw, hw->aq.asq.tail, 0);
482 wr32(hw, hw->aq.asq.len, 0);
483 wr32(hw, hw->aq.asq.bal, 0);
484 wr32(hw, hw->aq.asq.bah, 0);
486 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
488 /* free ring buffers */
489 i40e_free_asq_bufs(hw);
492 mutex_unlock(&hw->aq.asq_mutex);
497 * i40e_shutdown_arq - shutdown ARQ
498 * @hw: pointer to the hardware structure
500 * The main shutdown routine for the Admin Receive Queue
502 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
504 i40e_status ret_code = 0;
506 mutex_lock(&hw->aq.arq_mutex);
508 if (hw->aq.arq.count == 0) {
509 ret_code = I40E_ERR_NOT_READY;
510 goto shutdown_arq_out;
513 /* Stop firmware AdminQ processing */
514 wr32(hw, hw->aq.arq.head, 0);
515 wr32(hw, hw->aq.arq.tail, 0);
516 wr32(hw, hw->aq.arq.len, 0);
517 wr32(hw, hw->aq.arq.bal, 0);
518 wr32(hw, hw->aq.arq.bah, 0);
520 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
522 /* free ring buffers */
523 i40e_free_arq_bufs(hw);
526 mutex_unlock(&hw->aq.arq_mutex);
531 * i40evf_init_adminq - main initialization routine for Admin Queue
532 * @hw: pointer to the hardware structure
534 * Prior to calling this function, drivers *MUST* set the following fields
535 * in the hw->aq structure:
536 * - hw->aq.num_asq_entries
537 * - hw->aq.num_arq_entries
538 * - hw->aq.arq_buf_size
539 * - hw->aq.asq_buf_size
541 i40e_status i40evf_init_adminq(struct i40e_hw *hw)
543 i40e_status ret_code;
545 /* verify input for valid configuration */
546 if ((hw->aq.num_arq_entries == 0) ||
547 (hw->aq.num_asq_entries == 0) ||
548 (hw->aq.arq_buf_size == 0) ||
549 (hw->aq.asq_buf_size == 0)) {
550 ret_code = I40E_ERR_CONFIG;
551 goto init_adminq_exit;
554 /* initialize locks */
555 mutex_init(&hw->aq.asq_mutex);
556 mutex_init(&hw->aq.arq_mutex);
558 /* Set up register offsets */
559 i40e_adminq_init_regs(hw);
561 /* setup ASQ command write back timeout */
562 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
564 /* allocate the ASQ */
565 ret_code = i40e_init_asq(hw);
567 goto init_adminq_destroy_locks;
569 /* allocate the ARQ */
570 ret_code = i40e_init_arq(hw);
572 goto init_adminq_free_asq;
575 goto init_adminq_exit;
577 init_adminq_free_asq:
578 i40e_shutdown_asq(hw);
579 init_adminq_destroy_locks:
586 * i40evf_shutdown_adminq - shutdown routine for the Admin Queue
587 * @hw: pointer to the hardware structure
589 i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw)
591 i40e_status ret_code = 0;
593 if (i40evf_check_asq_alive(hw))
594 i40evf_aq_queue_shutdown(hw, true);
596 i40e_shutdown_asq(hw);
597 i40e_shutdown_arq(hw);
599 /* destroy the locks */
602 i40e_free_virt_mem(hw, &hw->nvm_buff);
608 * i40e_clean_asq - cleans Admin send queue
609 * @hw: pointer to the hardware structure
611 * returns the number of free desc
613 static u16 i40e_clean_asq(struct i40e_hw *hw)
615 struct i40e_adminq_ring *asq = &(hw->aq.asq);
616 struct i40e_asq_cmd_details *details;
617 u16 ntc = asq->next_to_clean;
618 struct i40e_aq_desc desc_cb;
619 struct i40e_aq_desc *desc;
621 desc = I40E_ADMINQ_DESC(*asq, ntc);
622 details = I40E_ADMINQ_DETAILS(*asq, ntc);
623 while (rd32(hw, hw->aq.asq.head) != ntc) {
624 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
625 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
627 if (details->callback) {
628 I40E_ADMINQ_CALLBACK cb_func =
629 (I40E_ADMINQ_CALLBACK)details->callback;
631 cb_func(hw, &desc_cb);
633 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
634 memset((void *)details, 0,
635 sizeof(struct i40e_asq_cmd_details));
637 if (ntc == asq->count)
639 desc = I40E_ADMINQ_DESC(*asq, ntc);
640 details = I40E_ADMINQ_DETAILS(*asq, ntc);
643 asq->next_to_clean = ntc;
645 return I40E_DESC_UNUSED(asq);
649 * i40evf_asq_done - check if FW has processed the Admin Send Queue
650 * @hw: pointer to the hw struct
652 * Returns true if the firmware has processed all descriptors on the
653 * admin send queue. Returns false if there are still requests pending.
655 bool i40evf_asq_done(struct i40e_hw *hw)
657 /* AQ designers suggest use of head for better
658 * timing reliability than DD bit
660 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
665 * i40evf_asq_send_command - send command to Admin Queue
666 * @hw: pointer to the hw struct
667 * @desc: prefilled descriptor describing the command (non DMA mem)
668 * @buff: buffer to use for indirect commands
669 * @buff_size: size of buffer for indirect commands
670 * @cmd_details: pointer to command details structure
672 * This is the main send command driver routine for the Admin Queue send
673 * queue. It runs the queue, cleans the queue, etc
675 i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
676 struct i40e_aq_desc *desc,
677 void *buff, /* can be NULL */
679 struct i40e_asq_cmd_details *cmd_details)
681 i40e_status status = 0;
682 struct i40e_dma_mem *dma_buff = NULL;
683 struct i40e_asq_cmd_details *details;
684 struct i40e_aq_desc *desc_on_ring;
685 bool cmd_completed = false;
689 mutex_lock(&hw->aq.asq_mutex);
691 if (hw->aq.asq.count == 0) {
692 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
693 "AQTX: Admin queue not initialized.\n");
694 status = I40E_ERR_QUEUE_EMPTY;
695 goto asq_send_command_error;
698 hw->aq.asq_last_status = I40E_AQ_RC_OK;
700 val = rd32(hw, hw->aq.asq.head);
701 if (val >= hw->aq.num_asq_entries) {
702 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
703 "AQTX: head overrun at %d\n", val);
704 status = I40E_ERR_QUEUE_EMPTY;
705 goto asq_send_command_error;
708 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
710 *details = *cmd_details;
712 /* If the cmd_details are defined copy the cookie. The
713 * cpu_to_le32 is not needed here because the data is ignored
714 * by the FW, only used by the driver
716 if (details->cookie) {
718 cpu_to_le32(upper_32_bits(details->cookie));
720 cpu_to_le32(lower_32_bits(details->cookie));
723 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
726 /* clear requested flags and then set additional flags if defined */
727 desc->flags &= ~cpu_to_le16(details->flags_dis);
728 desc->flags |= cpu_to_le16(details->flags_ena);
730 if (buff_size > hw->aq.asq_buf_size) {
732 I40E_DEBUG_AQ_MESSAGE,
733 "AQTX: Invalid buffer size: %d.\n",
735 status = I40E_ERR_INVALID_SIZE;
736 goto asq_send_command_error;
739 if (details->postpone && !details->async) {
741 I40E_DEBUG_AQ_MESSAGE,
742 "AQTX: Async flag not set along with postpone flag");
743 status = I40E_ERR_PARAM;
744 goto asq_send_command_error;
747 /* call clean and check queue available function to reclaim the
748 * descriptors that were processed by FW, the function returns the
749 * number of desc available
751 /* the clean function called here could be called in a separate thread
752 * in case of asynchronous completions
754 if (i40e_clean_asq(hw) == 0) {
756 I40E_DEBUG_AQ_MESSAGE,
757 "AQTX: Error queue is full.\n");
758 status = I40E_ERR_ADMIN_QUEUE_FULL;
759 goto asq_send_command_error;
762 /* initialize the temp desc pointer with the right desc */
763 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
765 /* if the desc is available copy the temp desc to the right place */
766 *desc_on_ring = *desc;
768 /* if buff is not NULL assume indirect command */
770 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
771 /* copy the user buff into the respective DMA buff */
772 memcpy(dma_buff->va, buff, buff_size);
773 desc_on_ring->datalen = cpu_to_le16(buff_size);
775 /* Update the address values in the desc with the pa value
776 * for respective buffer
778 desc_on_ring->params.external.addr_high =
779 cpu_to_le32(upper_32_bits(dma_buff->pa));
780 desc_on_ring->params.external.addr_low =
781 cpu_to_le32(lower_32_bits(dma_buff->pa));
785 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
786 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
788 (hw->aq.asq.next_to_use)++;
789 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
790 hw->aq.asq.next_to_use = 0;
791 if (!details->postpone)
792 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
794 /* if cmd_details are not defined or async flag is not set,
795 * we need to wait for desc write back
797 if (!details->async && !details->postpone) {
801 /* AQ designers suggest use of head for better
802 * timing reliability than DD bit
804 if (i40evf_asq_done(hw))
806 usleep_range(1000, 2000);
808 } while (total_delay < hw->aq.asq_cmd_timeout);
811 /* if ready, copy the desc back to temp */
812 if (i40evf_asq_done(hw)) {
813 *desc = *desc_on_ring;
815 memcpy(buff, dma_buff->va, buff_size);
816 retval = le16_to_cpu(desc->retval);
819 I40E_DEBUG_AQ_MESSAGE,
820 "AQTX: Command completed with error 0x%X.\n",
823 /* strip off FW internal code */
826 cmd_completed = true;
827 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
830 status = I40E_ERR_ADMIN_QUEUE_ERROR;
831 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
834 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
835 "AQTX: desc and buffer writeback:\n");
836 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff,
839 /* save writeback aq if requested */
840 if (details->wb_desc)
841 *details->wb_desc = *desc_on_ring;
843 /* update the error if time out occurred */
844 if ((!cmd_completed) &&
845 (!details->async && !details->postpone)) {
847 I40E_DEBUG_AQ_MESSAGE,
848 "AQTX: Writeback timeout.\n");
849 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
852 asq_send_command_error:
853 mutex_unlock(&hw->aq.asq_mutex);
858 * i40evf_fill_default_direct_cmd_desc - AQ descriptor helper function
859 * @desc: pointer to the temp descriptor (non DMA mem)
860 * @opcode: the opcode can be used to decide which flags to turn off or on
862 * Fill the desc with default values
864 void i40evf_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
867 /* zero out the desc */
868 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
869 desc->opcode = cpu_to_le16(opcode);
870 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
874 * i40evf_clean_arq_element
875 * @hw: pointer to the hw struct
876 * @e: event info from the receive descriptor, includes any buffers
877 * @pending: number of events that could be left to process
879 * This function cleans one Admin Receive Queue element and returns
880 * the contents through e. It can also return how many events are
881 * left to process through 'pending'
883 i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
884 struct i40e_arq_event_info *e,
887 i40e_status ret_code = 0;
888 u16 ntc = hw->aq.arq.next_to_clean;
889 struct i40e_aq_desc *desc;
890 struct i40e_dma_mem *bi;
896 /* take the lock before we start messing with the ring */
897 mutex_lock(&hw->aq.arq_mutex);
899 if (hw->aq.arq.count == 0) {
900 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
901 "AQRX: Admin queue not initialized.\n");
902 ret_code = I40E_ERR_QUEUE_EMPTY;
903 goto clean_arq_element_err;
906 /* set next_to_use to head */
907 ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK);
909 /* nothing to do - shouldn't need to update ring's values */
910 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
911 goto clean_arq_element_out;
914 /* now clean the next descriptor */
915 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
918 flags = le16_to_cpu(desc->flags);
919 if (flags & I40E_AQ_FLAG_ERR) {
920 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
921 hw->aq.arq_last_status =
922 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
924 I40E_DEBUG_AQ_MESSAGE,
925 "AQRX: Event received with error 0x%X.\n",
926 hw->aq.arq_last_status);
930 datalen = le16_to_cpu(desc->datalen);
931 e->msg_len = min(datalen, e->buf_len);
932 if (e->msg_buf != NULL && (e->msg_len != 0))
933 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
936 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
937 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
938 hw->aq.arq_buf_size);
940 /* Restore the original datalen and buffer address in the desc,
941 * FW updates datalen to indicate the event message
944 bi = &hw->aq.arq.r.arq_bi[ntc];
945 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
947 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
948 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
949 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
950 desc->datalen = cpu_to_le16((u16)bi->size);
951 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
952 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
954 /* set tail = the last cleaned desc index. */
955 wr32(hw, hw->aq.arq.tail, ntc);
956 /* ntc is updated to tail + 1 */
958 if (ntc == hw->aq.num_arq_entries)
960 hw->aq.arq.next_to_clean = ntc;
961 hw->aq.arq.next_to_use = ntu;
963 clean_arq_element_out:
964 /* Set pending if needed, unlock and return */
966 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
968 clean_arq_element_err:
969 mutex_unlock(&hw->aq.arq_mutex);
974 void i40evf_resume_aq(struct i40e_hw *hw)
976 /* Registers are reset after PF reset */
977 hw->aq.asq.next_to_use = 0;
978 hw->aq.asq.next_to_clean = 0;
980 i40e_config_asq_regs(hw);
982 hw->aq.arq.next_to_use = 0;
983 hw->aq.arq.next_to_clean = 0;
985 i40e_config_arq_regs(hw);