drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  55                         kfree(tx_buffer->raw_buf);
  56                 else
  57                         dev_kfree_skb_any(tx_buffer->skb);
  58
  59                 if (dma_unmap_len(tx_buffer, len))
  60                         dma_unmap_single(ring->dev,
  61                                          dma_unmap_addr(tx_buffer, dma),
  62                                          dma_unmap_len(tx_buffer, len),
  63                                          DMA_TO_DEVICE);
  64         } else if (dma_unmap_len(tx_buffer, len)) {
  65                 dma_unmap_page(ring->dev,
  66                                dma_unmap_addr(tx_buffer, dma),
  67                                dma_unmap_len(tx_buffer, len),
  68                                DMA_TO_DEVICE);
  69         }
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 #define WB_STRIDE 0x3
 144
 145 /**
 146  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 147  * @tx_ring:  tx ring to clean
 148  * @budget:   how many cleans we're allowed
 149  *
 150  * Returns true if there's any budget left (e.g. the clean is finished)
 151  **/
 152 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 153 {
 154         u16 i = tx_ring->next_to_clean;
 155         struct i40e_tx_buffer *tx_buf;
 156         struct i40e_tx_desc *tx_head;
 157         struct i40e_tx_desc *tx_desc;
 158         unsigned int total_packets = 0;
 159         unsigned int total_bytes = 0;
 160
 161         tx_buf = &tx_ring->tx_bi[i];
 162         tx_desc = I40E_TX_DESC(tx_ring, i);
 163         i -= tx_ring->count;
 164
 165         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 166
 167         do {
 168                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 169
 170                 /* if next_to_watch is not set then there is no work pending */
 171                 if (!eop_desc)
 172                         break;
 173
 174                 /* prevent any other reads prior to eop_desc */
 175                 read_barrier_depends();
 176
 177                 /* we have caught up to head, no work left to do */
 178                 if (tx_head == tx_desc)
 179                         break;
 180
 181                 /* clear next_to_watch to prevent false hangs */
 182                 tx_buf->next_to_watch = NULL;
 183
 184                 /* update the statistics for this packet */
 185                 total_bytes += tx_buf->bytecount;
 186                 total_packets += tx_buf->gso_segs;
 187
 188                 /* free the skb */
 189                 dev_kfree_skb_any(tx_buf->skb);
 190
 191                 /* unmap skb header data */
 192                 dma_unmap_single(tx_ring->dev,
 193                                  dma_unmap_addr(tx_buf, dma),
 194                                  dma_unmap_len(tx_buf, len),
 195                                  DMA_TO_DEVICE);
 196
 197                 /* clear tx_buffer data */
 198                 tx_buf->skb = NULL;
 199                 dma_unmap_len_set(tx_buf, len, 0);
 200
 201                 /* unmap remaining buffers */
 202                 while (tx_desc != eop_desc) {
 203
 204                         tx_buf++;
 205                         tx_desc++;
 206                         i++;
 207                         if (unlikely(!i)) {
 208                                 i -= tx_ring->count;
 209                                 tx_buf = tx_ring->tx_bi;
 210                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 211                         }
 212
 213                         /* unmap any remaining paged data */
 214                         if (dma_unmap_len(tx_buf, len)) {
 215                                 dma_unmap_page(tx_ring->dev,
 216                                                dma_unmap_addr(tx_buf, dma),
 217                                                dma_unmap_len(tx_buf, len),
 218                                                DMA_TO_DEVICE);
 219                                 dma_unmap_len_set(tx_buf, len, 0);
 220                         }
 221                 }
 222
 223                 /* move us one more past the eop_desc for start of next pkt */
 224                 tx_buf++;
 225                 tx_desc++;
 226                 i++;
 227                 if (unlikely(!i)) {
 228                         i -= tx_ring->count;
 229                         tx_buf = tx_ring->tx_bi;
 230                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 231                 }
 232
 233                 prefetch(tx_desc);
 234
 235                 /* update budget accounting */
 236                 budget--;
 237         } while (likely(budget));
 238
 239         i += tx_ring->count;
 240         tx_ring->next_to_clean = i;
 241         u64_stats_update_begin(&tx_ring->syncp);
 242         tx_ring->stats.bytes += total_bytes;
 243         tx_ring->stats.packets += total_packets;
 244         u64_stats_update_end(&tx_ring->syncp);
 245         tx_ring->q_vector->tx.total_bytes += total_bytes;
 246         tx_ring->q_vector->tx.total_packets += total_packets;
 247
 248         /* check to see if there are any non-cache aligned descriptors
 249          * waiting to be written back, and kick the hardware to force
 250          * them to be written back in case of napi polling
 251          */
 252         if (budget &&
 253             !((i & WB_STRIDE) == WB_STRIDE) &&
 254             !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 255             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 256                 tx_ring->arm_wb = true;
 257
 258         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 259                                                       tx_ring->queue_index),
 260                                   total_packets, total_bytes);
 261
 262 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 263         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 264                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 265                 /* Make sure that anybody stopping the queue after this
 266                  * sees the new next_to_clean.
 267                  */
 268                 smp_mb();
 269                 if (__netif_subqueue_stopped(tx_ring->netdev,
 270                                              tx_ring->queue_index) &&
 271                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 272                         netif_wake_subqueue(tx_ring->netdev,
 273                                             tx_ring->queue_index);
 274                         ++tx_ring->tx_stats.restart_queue;
 275                 }
 276         }
 277
 278         return !!budget;
 279 }
 280
 281 /**
 282  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 283  * @vsi: the VSI we care about
 284  * @q_vector: the vector  on which to force writeback
 285  *
 286  **/
 287 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 288 {
 289         u16 flags = q_vector->tx.ring[0].flags;
 290
 291         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 292                 u32 val;
 293
 294                 if (q_vector->arm_wb_state)
 295                         return;
 296
 297                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
 298
 299                 wr32(&vsi->back->hw,
 300                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 301                                           vsi->base_vector - 1),
 302                      val);
 303                 q_vector->arm_wb_state = true;
 304         } else {
 305                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 306                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 307                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 308                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 309                           /* allow 00 to be written to the index */
 310
 311                 wr32(&vsi->back->hw,
 312                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 313                                           vsi->base_vector - 1), val);
 314         }
 315 }
 316
 317 /**
 318  * i40e_set_new_dynamic_itr - Find new ITR level
 319  * @rc: structure containing ring performance data
 320  *
 321  * Stores a new ITR value based on packets and byte counts during
 322  * the last interrupt.  The advantage of per interrupt computation
 323  * is faster updates and more accurate ITR for the current traffic
 324  * pattern.  Constants in this function were computed based on
 325  * theoretical maximum wire speed and thresholds were set based on
 326  * testing data as well as attempting to minimize response time
 327  * while increasing bulk throughput.
 328  **/
 329 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 330 {
 331         enum i40e_latency_range new_latency_range = rc->latency_range;
 332         u32 new_itr = rc->itr;
 333         int bytes_per_int;
 334
 335         if (rc->total_packets == 0 || !rc->itr)
 336                 return;
 337
 338         /* simple throttlerate management
 339          *   0-10MB/s   lowest (100000 ints/s)
 340          *  10-20MB/s   low    (20000 ints/s)
 341          *  20-1249MB/s bulk   (8000 ints/s)
 342          */
 343         bytes_per_int = rc->total_bytes / rc->itr;
 344         switch (new_latency_range) {
 345         case I40E_LOWEST_LATENCY:
 346                 if (bytes_per_int > 10)
 347                         new_latency_range = I40E_LOW_LATENCY;
 348                 break;
 349         case I40E_LOW_LATENCY:
 350                 if (bytes_per_int > 20)
 351                         new_latency_range = I40E_BULK_LATENCY;
 352                 else if (bytes_per_int <= 10)
 353                         new_latency_range = I40E_LOWEST_LATENCY;
 354                 break;
 355         case I40E_BULK_LATENCY:
 356                 if (bytes_per_int <= 20)
 357                         new_latency_range = I40E_LOW_LATENCY;
 358                 break;
 359         default:
 360                 if (bytes_per_int <= 20)
 361                         new_latency_range = I40E_LOW_LATENCY;
 362                 break;
 363         }
 364         rc->latency_range = new_latency_range;
 365
 366         switch (new_latency_range) {
 367         case I40E_LOWEST_LATENCY:
 368                 new_itr = I40E_ITR_100K;
 369                 break;
 370         case I40E_LOW_LATENCY:
 371                 new_itr = I40E_ITR_20K;
 372                 break;
 373         case I40E_BULK_LATENCY:
 374                 new_itr = I40E_ITR_8K;
 375                 break;
 376         default:
 377                 break;
 378         }
 379
 380         if (new_itr != rc->itr)
 381                 rc->itr = new_itr;
 382
 383         rc->total_bytes = 0;
 384         rc->total_packets = 0;
 385 }
 386
 387 /*
 388  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 389  * @tx_ring: the tx ring to set up
 390  *
 391  * Return 0 on success, negative on error
 392  **/
 393 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 394 {
 395         struct device *dev = tx_ring->dev;
 396         int bi_size;
 397
 398         if (!dev)
 399                 return -ENOMEM;
 400
 401         /* warn if we are about to overwrite the pointer */
 402         WARN_ON(tx_ring->tx_bi);
 403         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 404         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 405         if (!tx_ring->tx_bi)
 406                 goto err;
 407
 408         /* round up to nearest 4K */
 409         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 410         /* add u32 for head writeback, align after this takes care of
 411          * guaranteeing this is at least one cache line in size
 412          */
 413         tx_ring->size += sizeof(u32);
 414         tx_ring->size = ALIGN(tx_ring->size, 4096);
 415         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 416                                            &tx_ring->dma, GFP_KERNEL);
 417         if (!tx_ring->desc) {
 418                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 419                          tx_ring->size);
 420                 goto err;
 421         }
 422
 423         tx_ring->next_to_use = 0;
 424         tx_ring->next_to_clean = 0;
 425         return 0;
 426
 427 err:
 428         kfree(tx_ring->tx_bi);
 429         tx_ring->tx_bi = NULL;
 430         return -ENOMEM;
 431 }
 432
 433 /**
 434  * i40evf_clean_rx_ring - Free Rx buffers
 435  * @rx_ring: ring to be cleaned
 436  **/
 437 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 438 {
 439         struct device *dev = rx_ring->dev;
 440         struct i40e_rx_buffer *rx_bi;
 441         unsigned long bi_size;
 442         u16 i;
 443
 444         /* ring already cleared, nothing to do */
 445         if (!rx_ring->rx_bi)
 446                 return;
 447
 448         if (ring_is_ps_enabled(rx_ring)) {
 449                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 450
 451                 rx_bi = &rx_ring->rx_bi[0];
 452                 if (rx_bi->hdr_buf) {
 453                         dma_free_coherent(dev,
 454                                           bufsz,
 455                                           rx_bi->hdr_buf,
 456                                           rx_bi->dma);
 457                         for (i = 0; i < rx_ring->count; i++) {
 458                                 rx_bi = &rx_ring->rx_bi[i];
 459                                 rx_bi->dma = 0;
 460                                 rx_bi->hdr_buf = NULL;
 461                         }
 462                 }
 463         }
 464         /* Free all the Rx ring sk_buffs */
 465         for (i = 0; i < rx_ring->count; i++) {
 466                 rx_bi = &rx_ring->rx_bi[i];
 467                 if (rx_bi->dma) {
 468                         dma_unmap_single(dev,
 469                                          rx_bi->dma,
 470                                          rx_ring->rx_buf_len,
 471                                          DMA_FROM_DEVICE);
 472                         rx_bi->dma = 0;
 473                 }
 474                 if (rx_bi->skb) {
 475                         dev_kfree_skb(rx_bi->skb);
 476                         rx_bi->skb = NULL;
 477                 }
 478                 if (rx_bi->page) {
 479                         if (rx_bi->page_dma) {
 480                                 dma_unmap_page(dev,
 481                                                rx_bi->page_dma,
 482                                                PAGE_SIZE / 2,
 483                                                DMA_FROM_DEVICE);
 484                                 rx_bi->page_dma = 0;
 485                         }
 486                         __free_page(rx_bi->page);
 487                         rx_bi->page = NULL;
 488                         rx_bi->page_offset = 0;
 489                 }
 490         }
 491
 492         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 493         memset(rx_ring->rx_bi, 0, bi_size);
 494
 495         /* Zero out the descriptor ring */
 496         memset(rx_ring->desc, 0, rx_ring->size);
 497
 498         rx_ring->next_to_clean = 0;
 499         rx_ring->next_to_use = 0;
 500 }
 501
 502 /**
 503  * i40evf_free_rx_resources - Free Rx resources
 504  * @rx_ring: ring to clean the resources from
 505  *
 506  * Free all receive software resources
 507  **/
 508 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 509 {
 510         i40evf_clean_rx_ring(rx_ring);
 511         kfree(rx_ring->rx_bi);
 512         rx_ring->rx_bi = NULL;
 513
 514         if (rx_ring->desc) {
 515                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 516                                   rx_ring->desc, rx_ring->dma);
 517                 rx_ring->desc = NULL;
 518         }
 519 }
 520
 521 /**
 522  * i40evf_alloc_rx_headers - allocate rx header buffers
 523  * @rx_ring: ring to alloc buffers
 524  *
 525  * Allocate rx header buffers for the entire ring. As these are static,
 526  * this is only called when setting up a new ring.
 527  **/
 528 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 529 {
 530         struct device *dev = rx_ring->dev;
 531         struct i40e_rx_buffer *rx_bi;
 532         dma_addr_t dma;
 533         void *buffer;
 534         int buf_size;
 535         int i;
 536
 537         if (rx_ring->rx_bi[0].hdr_buf)
 538                 return;
 539         /* Make sure the buffers don't cross cache line boundaries. */
 540         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 541         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 542                                     &dma, GFP_KERNEL);
 543         if (!buffer)
 544                 return;
 545         for (i = 0; i < rx_ring->count; i++) {
 546                 rx_bi = &rx_ring->rx_bi[i];
 547                 rx_bi->dma = dma + (i * buf_size);
 548                 rx_bi->hdr_buf = buffer + (i * buf_size);
 549         }
 550 }
 551
 552 /**
 553  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 554  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 555  *
 556  * Returns 0 on success, negative on failure
 557  **/
 558 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 559 {
 560         struct device *dev = rx_ring->dev;
 561         int bi_size;
 562
 563         /* warn if we are about to overwrite the pointer */
 564         WARN_ON(rx_ring->rx_bi);
 565         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 566         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 567         if (!rx_ring->rx_bi)
 568                 goto err;
 569
 570         u64_stats_init(&rx_ring->syncp);
 571
 572         /* Round up to nearest 4K */
 573         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 574                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 575                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 576         rx_ring->size = ALIGN(rx_ring->size, 4096);
 577         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 578                                            &rx_ring->dma, GFP_KERNEL);
 579
 580         if (!rx_ring->desc) {
 581                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 582                          rx_ring->size);
 583                 goto err;
 584         }
 585
 586         rx_ring->next_to_clean = 0;
 587         rx_ring->next_to_use = 0;
 588
 589         return 0;
 590 err:
 591         kfree(rx_ring->rx_bi);
 592         rx_ring->rx_bi = NULL;
 593         return -ENOMEM;
 594 }
 595
 596 /**
 597  * i40e_release_rx_desc - Store the new tail and head values
 598  * @rx_ring: ring to bump
 599  * @val: new head index
 600  **/
 601 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 602 {
 603         rx_ring->next_to_use = val;
 604         /* Force memory writes to complete before letting h/w
 605          * know there are new descriptors to fetch.  (Only
 606          * applicable for weak-ordered memory model archs,
 607          * such as IA-64).
 608          */
 609         wmb();
 610         writel(val, rx_ring->tail);
 611 }
 612
 613 /**
 614  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 615  * @rx_ring: ring to place buffers on
 616  * @cleaned_count: number of buffers to replace
 617  **/
 618 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 619 {
 620         u16 i = rx_ring->next_to_use;
 621         union i40e_rx_desc *rx_desc;
 622         struct i40e_rx_buffer *bi;
 623
 624         /* do nothing if no valid netdev defined */
 625         if (!rx_ring->netdev || !cleaned_count)
 626                 return;
 627
 628         while (cleaned_count--) {
 629                 rx_desc = I40E_RX_DESC(rx_ring, i);
 630                 bi = &rx_ring->rx_bi[i];
 631
 632                 if (bi->skb) /* desc is in use */
 633                         goto no_buffers;
 634                 if (!bi->page) {
 635                         bi->page = alloc_page(GFP_ATOMIC);
 636                         if (!bi->page) {
 637                                 rx_ring->rx_stats.alloc_page_failed++;
 638                                 goto no_buffers;
 639                         }
 640                 }
 641
 642                 if (!bi->page_dma) {
 643                         /* use a half page if we're re-using */
 644                         bi->page_offset ^= PAGE_SIZE / 2;
 645                         bi->page_dma = dma_map_page(rx_ring->dev,
 646                                                     bi->page,
 647                                                     bi->page_offset,
 648                                                     PAGE_SIZE / 2,
 649                                                     DMA_FROM_DEVICE);
 650                         if (dma_mapping_error(rx_ring->dev,
 651                                               bi->page_dma)) {
 652                                 rx_ring->rx_stats.alloc_page_failed++;
 653                                 bi->page_dma = 0;
 654                                 goto no_buffers;
 655                         }
 656                 }
 657
 658                 dma_sync_single_range_for_device(rx_ring->dev,
 659                                                  bi->dma,
 660                                                  0,
 661                                                  rx_ring->rx_hdr_len,
 662                                                  DMA_FROM_DEVICE);
 663                 /* Refresh the desc even if buffer_addrs didn't change
 664                  * because each write-back erases this info.
 665                  */
 666                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 667                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 668                 i++;
 669                 if (i == rx_ring->count)
 670                         i = 0;
 671         }
 672
 673 no_buffers:
 674         if (rx_ring->next_to_use != i)
 675                 i40e_release_rx_desc(rx_ring, i);
 676 }
 677
 678 /**
 679  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 680  * @rx_ring: ring to place buffers on
 681  * @cleaned_count: number of buffers to replace
 682  **/
 683 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 684 {
 685         u16 i = rx_ring->next_to_use;
 686         union i40e_rx_desc *rx_desc;
 687         struct i40e_rx_buffer *bi;
 688         struct sk_buff *skb;
 689
 690         /* do nothing if no valid netdev defined */
 691         if (!rx_ring->netdev || !cleaned_count)
 692                 return;
 693
 694         while (cleaned_count--) {
 695                 rx_desc = I40E_RX_DESC(rx_ring, i);
 696                 bi = &rx_ring->rx_bi[i];
 697                 skb = bi->skb;
 698
 699                 if (!skb) {
 700                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 701                                                         rx_ring->rx_buf_len);
 702                         if (!skb) {
 703                                 rx_ring->rx_stats.alloc_buff_failed++;
 704                                 goto no_buffers;
 705                         }
 706                         /* initialize queue mapping */
 707                         skb_record_rx_queue(skb, rx_ring->queue_index);
 708                         bi->skb = skb;
 709                 }
 710
 711                 if (!bi->dma) {
 712                         bi->dma = dma_map_single(rx_ring->dev,
 713                                                  skb->data,
 714                                                  rx_ring->rx_buf_len,
 715                                                  DMA_FROM_DEVICE);
 716                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 717                                 rx_ring->rx_stats.alloc_buff_failed++;
 718                                 bi->dma = 0;
 719                                 goto no_buffers;
 720                         }
 721                 }
 722
 723                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 724                 rx_desc->read.hdr_addr = 0;
 725                 i++;
 726                 if (i == rx_ring->count)
 727                         i = 0;
 728         }
 729
 730 no_buffers:
 731         if (rx_ring->next_to_use != i)
 732                 i40e_release_rx_desc(rx_ring, i);
 733 }
 734
 735 /**
 736  * i40e_receive_skb - Send a completed packet up the stack
 737  * @rx_ring:  rx ring in play
 738  * @skb: packet to send up
 739  * @vlan_tag: vlan tag for packet
 740  **/
 741 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 742                              struct sk_buff *skb, u16 vlan_tag)
 743 {
 744         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 745         struct i40e_vsi *vsi = rx_ring->vsi;
 746         u64 flags = vsi->back->flags;
 747
 748         if (vlan_tag & VLAN_VID_MASK)
 749                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 750
 751         if (flags & I40E_FLAG_IN_NETPOLL)
 752                 netif_rx(skb);
 753         else
 754                 napi_gro_receive(&q_vector->napi, skb);
 755 }
 756
 757 /**
 758  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 759  * @vsi: the VSI we care about
 760  * @skb: skb currently being received and modified
 761  * @rx_status: status value of last descriptor in packet
 762  * @rx_error: error value of last descriptor in packet
 763  * @rx_ptype: ptype value of last descriptor in packet
 764  **/
 765 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 766                                     struct sk_buff *skb,
 767                                     u32 rx_status,
 768                                     u32 rx_error,
 769                                     u16 rx_ptype)
 770 {
 771         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 772         bool ipv4 = false, ipv6 = false;
 773         bool ipv4_tunnel, ipv6_tunnel;
 774         __wsum rx_udp_csum;
 775         struct iphdr *iph;
 776         __sum16 csum;
 777
 778         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 779                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 780         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 781                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 782
 783         skb->ip_summed = CHECKSUM_NONE;
 784
 785         /* Rx csum enabled and ip headers found? */
 786         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 787                 return;
 788
 789         /* did the hardware decode the packet and checksum? */
 790         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 791                 return;
 792
 793         /* both known and outer_ip must be set for the below code to work */
 794         if (!(decoded.known && decoded.outer_ip))
 795                 return;
 796
 797         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 798             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 799                 ipv4 = true;
 800         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 801                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 802                 ipv6 = true;
 803
 804         if (ipv4 &&
 805             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 806                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 807                 goto checksum_fail;
 808
 809         /* likely incorrect csum if alternate IP extension headers found */
 810         if (ipv6 &&
 811             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 812                 /* don't increment checksum err here, non-fatal err */
 813                 return;
 814
 815         /* there was some L4 error, count error and punt packet to the stack */
 816         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 817                 goto checksum_fail;
 818
 819         /* handle packets that were not able to be checksummed due
 820          * to arrival speed, in this case the stack can compute
 821          * the csum.
 822          */
 823         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 824                 return;
 825
 826         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 827          * it in the driver, hardware does not do it for us.
 828          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 829          * so the total length of IPv4 header is IHL*4 bytes
 830          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 831          */
 832         if (ipv4_tunnel) {
 833                 skb->transport_header = skb->mac_header +
 834                                         sizeof(struct ethhdr) +
 835                                         (ip_hdr(skb)->ihl * 4);
 836
 837                 /* Add 4 bytes for VLAN tagged packets */
 838                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 839                                           skb->protocol == htons(ETH_P_8021AD))
 840                                           ? VLAN_HLEN : 0;
 841
 842                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 843                     (udp_hdr(skb)->check != 0)) {
 844                         rx_udp_csum = udp_csum(skb);
 845                         iph = ip_hdr(skb);
 846                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 847                                                  (skb->len -
 848                                                   skb_transport_offset(skb)),
 849                                                  IPPROTO_UDP, rx_udp_csum);
 850
 851                         if (udp_hdr(skb)->check != csum)
 852                                 goto checksum_fail;
 853
 854                 } /* else its GRE and so no outer UDP header */
 855         }
 856
 857         skb->ip_summed = CHECKSUM_UNNECESSARY;
 858         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 859
 860         return;
 861
 862 checksum_fail:
 863         vsi->back->hw_csum_rx_error++;
 864 }
 865
 866 /**
 867  * i40e_rx_hash - returns the hash value from the Rx descriptor
 868  * @ring: descriptor ring
 869  * @rx_desc: specific descriptor
 870  **/
 871 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 872                                union i40e_rx_desc *rx_desc)
 873 {
 874         const __le64 rss_mask =
 875                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 876                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 877
 878         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 879             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 880                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 881         else
 882                 return 0;
 883 }
 884
 885 /**
 886  * i40e_ptype_to_hash - get a hash type
 887  * @ptype: the ptype value from the descriptor
 888  *
 889  * Returns a hash type to be used by skb_set_hash
 890  **/
 891 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 892 {
 893         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 894
 895         if (!decoded.known)
 896                 return PKT_HASH_TYPE_NONE;
 897
 898         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 899             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 900                 return PKT_HASH_TYPE_L4;
 901         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 902                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 903                 return PKT_HASH_TYPE_L3;
 904         else
 905                 return PKT_HASH_TYPE_L2;
 906 }
 907
 908 /**
 909  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 910  * @rx_ring:  rx ring to clean
 911  * @budget:   how many cleans we're allowed
 912  *
 913  * Returns true if there's any budget left (e.g. the clean is finished)
 914  **/
 915 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 916 {
 917         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 918         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 919         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 920         const int current_node = numa_mem_id();
 921         struct i40e_vsi *vsi = rx_ring->vsi;
 922         u16 i = rx_ring->next_to_clean;
 923         union i40e_rx_desc *rx_desc;
 924         u32 rx_error, rx_status;
 925         u8 rx_ptype;
 926         u64 qword;
 927
 928         do {
 929                 struct i40e_rx_buffer *rx_bi;
 930                 struct sk_buff *skb;
 931                 u16 vlan_tag;
 932                 /* return some buffers to hardware, one at a time is too slow */
 933                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 934                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
 935                         cleaned_count = 0;
 936                 }
 937
 938                 i = rx_ring->next_to_clean;
 939                 rx_desc = I40E_RX_DESC(rx_ring, i);
 940                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 941                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 942                         I40E_RXD_QW1_STATUS_SHIFT;
 943
 944                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
 945                         break;
 946
 947                 /* This memory barrier is needed to keep us from reading
 948                  * any other fields out of the rx_desc until we know the
 949                  * DD bit is set.
 950                  */
 951                 dma_rmb();
 952                 rx_bi = &rx_ring->rx_bi[i];
 953                 skb = rx_bi->skb;
 954                 if (likely(!skb)) {
 955                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 956                                                         rx_ring->rx_hdr_len);
 957                         if (!skb) {
 958                                 rx_ring->rx_stats.alloc_buff_failed++;
 959                                 break;
 960                         }
 961
 962                         /* initialize queue mapping */
 963                         skb_record_rx_queue(skb, rx_ring->queue_index);
 964                         /* we are reusing so sync this buffer for CPU use */
 965                         dma_sync_single_range_for_cpu(rx_ring->dev,
 966                                                       rx_bi->dma,
 967                                                       0,
 968                                                       rx_ring->rx_hdr_len,
 969                                                       DMA_FROM_DEVICE);
 970                 }
 971                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 972                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 973                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 974                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 975                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 976                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 977
 978                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 979                            I40E_RXD_QW1_ERROR_SHIFT;
 980                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 981                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 982
 983                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
 984                            I40E_RXD_QW1_PTYPE_SHIFT;
 985                 prefetch(rx_bi->page);
 986                 rx_bi->skb = NULL;
 987                 cleaned_count++;
 988                 if (rx_hbo || rx_sph) {
 989                         int len;
 990
 991                         if (rx_hbo)
 992                                 len = I40E_RX_HDR_SIZE;
 993                         else
 994                                 len = rx_header_len;
 995                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
 996                 } else if (skb->len == 0) {
 997                         int len;
 998
 999                         len = (rx_packet_len > skb_headlen(skb) ?
1000                                 skb_headlen(skb) : rx_packet_len);
1001                         memcpy(__skb_put(skb, len),
1002                                rx_bi->page + rx_bi->page_offset,
1003                                len);
1004                         rx_bi->page_offset += len;
1005                         rx_packet_len -= len;
1006                 }
1007
1008                 /* Get the rest of the data if this was a header split */
1009                 if (rx_packet_len) {
1010                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1011                                            rx_bi->page,
1012                                            rx_bi->page_offset,
1013                                            rx_packet_len);
1014
1015                         skb->len += rx_packet_len;
1016                         skb->data_len += rx_packet_len;
1017                         skb->truesize += rx_packet_len;
1018
1019                         if ((page_count(rx_bi->page) == 1) &&
1020                             (page_to_nid(rx_bi->page) == current_node))
1021                                 get_page(rx_bi->page);
1022                         else
1023                                 rx_bi->page = NULL;
1024
1025                         dma_unmap_page(rx_ring->dev,
1026                                        rx_bi->page_dma,
1027                                        PAGE_SIZE / 2,
1028                                        DMA_FROM_DEVICE);
1029                         rx_bi->page_dma = 0;
1030                 }
1031                 I40E_RX_INCREMENT(rx_ring, i);
1032
1033                 if (unlikely(
1034                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1035                         struct i40e_rx_buffer *next_buffer;
1036
1037                         next_buffer = &rx_ring->rx_bi[i];
1038                         next_buffer->skb = skb;
1039                         rx_ring->rx_stats.non_eop_descs++;
1040                         continue;
1041                 }
1042
1043                 /* ERR_MASK will only have valid bits if EOP set */
1044                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1045                         dev_kfree_skb_any(skb);
1046                         continue;
1047                 }
1048
1049                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1050                              i40e_ptype_to_hash(rx_ptype));
1051                 /* probably a little skewed due to removing CRC */
1052                 total_rx_bytes += skb->len;
1053                 total_rx_packets++;
1054
1055                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1056
1057                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1058
1059                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1060                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1061                          : 0;
1062 #ifdef I40E_FCOE
1063                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1064                         dev_kfree_skb_any(skb);
1065                         continue;
1066                 }
1067 #endif
1068                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1069                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1070
1071                 rx_desc->wb.qword1.status_error_len = 0;
1072
1073         } while (likely(total_rx_packets < budget));
1074
1075         u64_stats_update_begin(&rx_ring->syncp);
1076         rx_ring->stats.packets += total_rx_packets;
1077         rx_ring->stats.bytes += total_rx_bytes;
1078         u64_stats_update_end(&rx_ring->syncp);
1079         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1080         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1081
1082         return total_rx_packets;
1083 }
1084
1085 /**
1086  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1087  * @rx_ring:  rx ring to clean
1088  * @budget:   how many cleans we're allowed
1089  *
1090  * Returns number of packets cleaned
1091  **/
1092 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1093 {
1094         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1095         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1096         struct i40e_vsi *vsi = rx_ring->vsi;
1097         union i40e_rx_desc *rx_desc;
1098         u32 rx_error, rx_status;
1099         u16 rx_packet_len;
1100         u8 rx_ptype;
1101         u64 qword;
1102         u16 i;
1103
1104         do {
1105                 struct i40e_rx_buffer *rx_bi;
1106                 struct sk_buff *skb;
1107                 u16 vlan_tag;
1108                 /* return some buffers to hardware, one at a time is too slow */
1109                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1110                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1111                         cleaned_count = 0;
1112                 }
1113
1114                 i = rx_ring->next_to_clean;
1115                 rx_desc = I40E_RX_DESC(rx_ring, i);
1116                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1117                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1118                         I40E_RXD_QW1_STATUS_SHIFT;
1119
1120                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1121                         break;
1122
1123                 /* This memory barrier is needed to keep us from reading
1124                  * any other fields out of the rx_desc until we know the
1125                  * DD bit is set.
1126                  */
1127                 dma_rmb();
1128
1129                 rx_bi = &rx_ring->rx_bi[i];
1130                 skb = rx_bi->skb;
1131                 prefetch(skb->data);
1132
1133                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1134                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1135
1136                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1137                            I40E_RXD_QW1_ERROR_SHIFT;
1138                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1139
1140                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1141                            I40E_RXD_QW1_PTYPE_SHIFT;
1142                 rx_bi->skb = NULL;
1143                 cleaned_count++;
1144
1145                 /* Get the header and possibly the whole packet
1146                  * If this is an skb from previous receive dma will be 0
1147                  */
1148                 skb_put(skb, rx_packet_len);
1149                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1150                                  DMA_FROM_DEVICE);
1151                 rx_bi->dma = 0;
1152
1153                 I40E_RX_INCREMENT(rx_ring, i);
1154
1155                 if (unlikely(
1156                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1157                         rx_ring->rx_stats.non_eop_descs++;
1158                         continue;
1159                 }
1160
1161                 /* ERR_MASK will only have valid bits if EOP set */
1162                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1163                         dev_kfree_skb_any(skb);
1164                         continue;
1165                 }
1166
1167                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1168                              i40e_ptype_to_hash(rx_ptype));
1169                 /* probably a little skewed due to removing CRC */
1170                 total_rx_bytes += skb->len;
1171                 total_rx_packets++;
1172
1173                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1174
1175                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1176
1177                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1178                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1179                          : 0;
1180                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1181
1182                 rx_desc->wb.qword1.status_error_len = 0;
1183         } while (likely(total_rx_packets < budget));
1184
1185         u64_stats_update_begin(&rx_ring->syncp);
1186         rx_ring->stats.packets += total_rx_packets;
1187         rx_ring->stats.bytes += total_rx_bytes;
1188         u64_stats_update_end(&rx_ring->syncp);
1189         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1190         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1191
1192         return total_rx_packets;
1193 }
1194
1195 /**
1196  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1197  * @vsi: the VSI we care about
1198  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1199  *
1200  **/
1201 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1202                                           struct i40e_q_vector *q_vector)
1203 {
1204         struct i40e_hw *hw = &vsi->back->hw;
1205         u16 old_itr;
1206         int vector;
1207         u32 val;
1208
1209         vector = (q_vector->v_idx + vsi->base_vector);
1210         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1211                 old_itr = q_vector->rx.itr;
1212                 i40e_set_new_dynamic_itr(&q_vector->rx);
1213                 if (old_itr != q_vector->rx.itr) {
1214                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1215                         I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1216                         (I40E_RX_ITR <<
1217                                 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1218                         (q_vector->rx.itr <<
1219                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1220                 } else {
1221                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1222                         I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1223                         (I40E_ITR_NONE <<
1224                                 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
1225                 }
1226                 if (!test_bit(__I40E_DOWN, &vsi->state))
1227                         wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1228         } else {
1229                 i40evf_irq_enable_queues(vsi->back, 1
1230                         << q_vector->v_idx);
1231         }
1232         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1233                 old_itr = q_vector->tx.itr;
1234                 i40e_set_new_dynamic_itr(&q_vector->tx);
1235                 if (old_itr != q_vector->tx.itr) {
1236                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1237                                 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1238                                 (I40E_TX_ITR <<
1239                                    I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1240                                 (q_vector->tx.itr <<
1241                                    I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1242
1243                 } else {
1244                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1245                                 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1246                                 (I40E_ITR_NONE <<
1247                                    I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
1248                 }
1249                 if (!test_bit(__I40E_DOWN, &vsi->state))
1250                         wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1251         } else {
1252                 i40evf_irq_enable_queues(vsi->back, BIT(q_vector->v_idx));
1253         }
1254 }
1255
1256 /**
1257  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1258  * @napi: napi struct with our devices info in it
1259  * @budget: amount of work driver is allowed to do this pass, in packets
1260  *
1261  * This function will clean all queues associated with a q_vector.
1262  *
1263  * Returns the amount of work done
1264  **/
1265 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1266 {
1267         struct i40e_q_vector *q_vector =
1268                                container_of(napi, struct i40e_q_vector, napi);
1269         struct i40e_vsi *vsi = q_vector->vsi;
1270         struct i40e_ring *ring;
1271         bool clean_complete = true;
1272         bool arm_wb = false;
1273         int budget_per_ring;
1274         int cleaned;
1275
1276         if (test_bit(__I40E_DOWN, &vsi->state)) {
1277                 napi_complete(napi);
1278                 return 0;
1279         }
1280
1281         /* Since the actual Tx work is minimal, we can give the Tx a larger
1282          * budget and be more aggressive about cleaning up the Tx descriptors.
1283          */
1284         i40e_for_each_ring(ring, q_vector->tx) {
1285                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1286                 arm_wb |= ring->arm_wb;
1287                 ring->arm_wb = false;
1288         }
1289
1290         /* We attempt to distribute budget to each Rx queue fairly, but don't
1291          * allow the budget to go below 1 because that would exit polling early.
1292          */
1293         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1294
1295         i40e_for_each_ring(ring, q_vector->rx) {
1296                 if (ring_is_ps_enabled(ring))
1297                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1298                 else
1299                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1300                 /* if we didn't clean as many as budgeted, we must be done */
1301                 clean_complete &= (budget_per_ring != cleaned);
1302         }
1303
1304         /* If work not completed, return budget and polling will return */
1305         if (!clean_complete) {
1306                 if (arm_wb)
1307                         i40evf_force_wb(vsi, q_vector);
1308                 return budget;
1309         }
1310
1311         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1312                 q_vector->arm_wb_state = false;
1313
1314         /* Work is done so exit the polling mode and re-enable the interrupt */
1315         napi_complete(napi);
1316         i40e_update_enable_itr(vsi, q_vector);
1317         return 0;
1318 }
1319
1320 /**
1321  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1322  * @skb:     send buffer
1323  * @tx_ring: ring to send buffer on
1324  * @flags:   the tx flags to be set
1325  *
1326  * Checks the skb and set up correspondingly several generic transmit flags
1327  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1328  *
1329  * Returns error code indicate the frame should be dropped upon error and the
1330  * otherwise  returns 0 to indicate the flags has been set properly.
1331  **/
1332 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1333                                                struct i40e_ring *tx_ring,
1334                                                u32 *flags)
1335 {
1336         __be16 protocol = skb->protocol;
1337         u32  tx_flags = 0;
1338
1339         if (protocol == htons(ETH_P_8021Q) &&
1340             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1341                 /* When HW VLAN acceleration is turned off by the user the
1342                  * stack sets the protocol to 8021q so that the driver
1343                  * can take any steps required to support the SW only
1344                  * VLAN handling.  In our case the driver doesn't need
1345                  * to take any further steps so just set the protocol
1346                  * to the encapsulated ethertype.
1347                  */
1348                 skb->protocol = vlan_get_protocol(skb);
1349                 goto out;
1350         }
1351
1352         /* if we have a HW VLAN tag being added, default to the HW one */
1353         if (skb_vlan_tag_present(skb)) {
1354                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1355                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1356         /* else if it is a SW VLAN, check the next protocol and store the tag */
1357         } else if (protocol == htons(ETH_P_8021Q)) {
1358                 struct vlan_hdr *vhdr, _vhdr;
1359
1360                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1361                 if (!vhdr)
1362                         return -EINVAL;
1363
1364                 protocol = vhdr->h_vlan_encapsulated_proto;
1365                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1366                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1367         }
1368
1369 out:
1370         *flags = tx_flags;
1371         return 0;
1372 }
1373
1374 /**
1375  * i40e_tso - set up the tso context descriptor
1376  * @tx_ring:  ptr to the ring to send
1377  * @skb:      ptr to the skb we're sending
1378  * @hdr_len:  ptr to the size of the packet header
1379  * @cd_tunneling: ptr to context descriptor bits
1380  *
1381  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1382  **/
1383 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1384                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1385                     u32 *cd_tunneling)
1386 {
1387         u32 cd_cmd, cd_tso_len, cd_mss;
1388         struct ipv6hdr *ipv6h;
1389         struct tcphdr *tcph;
1390         struct iphdr *iph;
1391         u32 l4len;
1392         int err;
1393
1394         if (!skb_is_gso(skb))
1395                 return 0;
1396
1397         err = skb_cow_head(skb, 0);
1398         if (err < 0)
1399                 return err;
1400
1401         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1402         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1403
1404         if (iph->version == 4) {
1405                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1406                 iph->tot_len = 0;
1407                 iph->check = 0;
1408                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1409                                                  0, IPPROTO_TCP, 0);
1410         } else if (ipv6h->version == 6) {
1411                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1412                 ipv6h->payload_len = 0;
1413                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1414                                                0, IPPROTO_TCP, 0);
1415         }
1416
1417         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1418         *hdr_len = (skb->encapsulation
1419                     ? (skb_inner_transport_header(skb) - skb->data)
1420                     : skb_transport_offset(skb)) + l4len;
1421
1422         /* find the field values */
1423         cd_cmd = I40E_TX_CTX_DESC_TSO;
1424         cd_tso_len = skb->len - *hdr_len;
1425         cd_mss = skb_shinfo(skb)->gso_size;
1426         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1427                                 ((u64)cd_tso_len <<
1428                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1429                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1430         return 1;
1431 }
1432
1433 /**
1434  * i40e_tx_enable_csum - Enable Tx checksum offloads
1435  * @skb: send buffer
1436  * @tx_flags: pointer to Tx flags currently set
1437  * @td_cmd: Tx descriptor command bits to set
1438  * @td_offset: Tx descriptor header offsets to set
1439  * @cd_tunneling: ptr to context desc bits
1440  **/
1441 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1442                                 u32 *td_cmd, u32 *td_offset,
1443                                 struct i40e_ring *tx_ring,
1444                                 u32 *cd_tunneling)
1445 {
1446         struct ipv6hdr *this_ipv6_hdr;
1447         unsigned int this_tcp_hdrlen;
1448         struct iphdr *this_ip_hdr;
1449         u32 network_hdr_len;
1450         u8 l4_hdr = 0;
1451         struct udphdr *oudph;
1452         struct iphdr *oiph;
1453         u32 l4_tunnel = 0;
1454
1455         if (skb->encapsulation) {
1456                 switch (ip_hdr(skb)->protocol) {
1457                 case IPPROTO_UDP:
1458                         oudph = udp_hdr(skb);
1459                         oiph = ip_hdr(skb);
1460                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1461                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1462                         break;
1463                 default:
1464                         return;
1465                 }
1466                 network_hdr_len = skb_inner_network_header_len(skb);
1467                 this_ip_hdr = inner_ip_hdr(skb);
1468                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1469                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1470
1471                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1472                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1473                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1474                                 ip_hdr(skb)->check = 0;
1475                         } else {
1476                                 *cd_tunneling |=
1477                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1478                         }
1479                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1480                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1481                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1482                                 ip_hdr(skb)->check = 0;
1483                 }
1484
1485                 /* Now set the ctx descriptor fields */
1486                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1487                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1488                                    l4_tunnel                             |
1489                                    ((skb_inner_network_offset(skb) -
1490                                         skb_transport_offset(skb)) >> 1) <<
1491                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1492                 if (this_ip_hdr->version == 6) {
1493                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1494                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1495                 }
1496
1497
1498                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1499                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1500                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1501                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1502                                         oiph->daddr,
1503                                         (skb->len - skb_transport_offset(skb)),
1504                                         IPPROTO_UDP, 0);
1505                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1506                 }
1507         } else {
1508                 network_hdr_len = skb_network_header_len(skb);
1509                 this_ip_hdr = ip_hdr(skb);
1510                 this_ipv6_hdr = ipv6_hdr(skb);
1511                 this_tcp_hdrlen = tcp_hdrlen(skb);
1512         }
1513
1514         /* Enable IP checksum offloads */
1515         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1516                 l4_hdr = this_ip_hdr->protocol;
1517                 /* the stack computes the IP header already, the only time we
1518                  * need the hardware to recompute it is in the case of TSO.
1519                  */
1520                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1521                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1522                         this_ip_hdr->check = 0;
1523                 } else {
1524                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1525                 }
1526                 /* Now set the td_offset for IP header length */
1527                 *td_offset = (network_hdr_len >> 2) <<
1528                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1529         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1530                 l4_hdr = this_ipv6_hdr->nexthdr;
1531                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1532                 /* Now set the td_offset for IP header length */
1533                 *td_offset = (network_hdr_len >> 2) <<
1534                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1535         }
1536         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1537         *td_offset |= (skb_network_offset(skb) >> 1) <<
1538                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1539
1540         /* Enable L4 checksum offloads */
1541         switch (l4_hdr) {
1542         case IPPROTO_TCP:
1543                 /* enable checksum offloads */
1544                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1545                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1546                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1547                 break;
1548         case IPPROTO_SCTP:
1549                 /* enable SCTP checksum offload */
1550                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1551                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1552                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1553                 break;
1554         case IPPROTO_UDP:
1555                 /* enable UDP checksum offload */
1556                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1557                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1558                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1559                 break;
1560         default:
1561                 break;
1562         }
1563 }
1564
1565 /**
1566  * i40e_create_tx_ctx Build the Tx context descriptor
1567  * @tx_ring:  ring to create the descriptor on
1568  * @cd_type_cmd_tso_mss: Quad Word 1
1569  * @cd_tunneling: Quad Word 0 - bits 0-31
1570  * @cd_l2tag2: Quad Word 0 - bits 32-63
1571  **/
1572 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1573                                const u64 cd_type_cmd_tso_mss,
1574                                const u32 cd_tunneling, const u32 cd_l2tag2)
1575 {
1576         struct i40e_tx_context_desc *context_desc;
1577         int i = tx_ring->next_to_use;
1578
1579         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1580             !cd_tunneling && !cd_l2tag2)
1581                 return;
1582
1583         /* grab the next descriptor */
1584         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1585
1586         i++;
1587         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1588
1589         /* cpu_to_le32 and assign to struct fields */
1590         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1591         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1592         context_desc->rsvd = cpu_to_le16(0);
1593         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1594 }
1595
1596  /**
1597  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1598  * @skb:      send buffer
1599  * @tx_flags: collected send information
1600  *
1601  * Note: Our HW can't scatter-gather more than 8 fragments to build
1602  * a packet on the wire and so we need to figure out the cases where we
1603  * need to linearize the skb.
1604  **/
1605 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1606 {
1607         struct skb_frag_struct *frag;
1608         bool linearize = false;
1609         unsigned int size = 0;
1610         u16 num_frags;
1611         u16 gso_segs;
1612
1613         num_frags = skb_shinfo(skb)->nr_frags;
1614         gso_segs = skb_shinfo(skb)->gso_segs;
1615
1616         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1617                 u16 j = 0;
1618
1619                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1620                         goto linearize_chk_done;
1621                 /* try the simple math, if we have too many frags per segment */
1622                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1623                     I40E_MAX_BUFFER_TXD) {
1624                         linearize = true;
1625                         goto linearize_chk_done;
1626                 }
1627                 frag = &skb_shinfo(skb)->frags[0];
1628                 /* we might still have more fragments per segment */
1629                 do {
1630                         size += skb_frag_size(frag);
1631                         frag++; j++;
1632                         if ((size >= skb_shinfo(skb)->gso_size) &&
1633                             (j < I40E_MAX_BUFFER_TXD)) {
1634                                 size = (size % skb_shinfo(skb)->gso_size);
1635                                 j = (size) ? 1 : 0;
1636                         }
1637                         if (j == I40E_MAX_BUFFER_TXD) {
1638                                 linearize = true;
1639                                 break;
1640                         }
1641                         num_frags--;
1642                 } while (num_frags);
1643         } else {
1644                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1645                         linearize = true;
1646         }
1647
1648 linearize_chk_done:
1649         return linearize;
1650 }
1651
1652 /**
1653  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1654  * @tx_ring: the ring to be checked
1655  * @size:    the size buffer we want to assure is available
1656  *
1657  * Returns -EBUSY if a stop is needed, else 0
1658  **/
1659 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1660 {
1661         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1662         /* Memory barrier before checking head and tail */
1663         smp_mb();
1664
1665         /* Check again in a case another CPU has just made room available. */
1666         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1667                 return -EBUSY;
1668
1669         /* A reprieve! - use start_queue because it doesn't call schedule */
1670         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1671         ++tx_ring->tx_stats.restart_queue;
1672         return 0;
1673 }
1674
1675 /**
1676  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1677  * @tx_ring: the ring to be checked
1678  * @size:    the size buffer we want to assure is available
1679  *
1680  * Returns 0 if stop is not needed
1681  **/
1682 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1683 {
1684         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1685                 return 0;
1686         return __i40evf_maybe_stop_tx(tx_ring, size);
1687 }
1688
1689 /**
1690  * i40evf_tx_map - Build the Tx descriptor
1691  * @tx_ring:  ring to send buffer on
1692  * @skb:      send buffer
1693  * @first:    first buffer info buffer to use
1694  * @tx_flags: collected send information
1695  * @hdr_len:  size of the packet header
1696  * @td_cmd:   the command field in the descriptor
1697  * @td_offset: offset for checksum or crc
1698  **/
1699 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1700                                  struct i40e_tx_buffer *first, u32 tx_flags,
1701                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1702 {
1703         unsigned int data_len = skb->data_len;
1704         unsigned int size = skb_headlen(skb);
1705         struct skb_frag_struct *frag;
1706         struct i40e_tx_buffer *tx_bi;
1707         struct i40e_tx_desc *tx_desc;
1708         u16 i = tx_ring->next_to_use;
1709         u32 td_tag = 0;
1710         dma_addr_t dma;
1711         u16 gso_segs;
1712
1713         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1714                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1715                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1716                          I40E_TX_FLAGS_VLAN_SHIFT;
1717         }
1718
1719         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1720                 gso_segs = skb_shinfo(skb)->gso_segs;
1721         else
1722                 gso_segs = 1;
1723
1724         /* multiply data chunks by size of headers */
1725         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1726         first->gso_segs = gso_segs;
1727         first->skb = skb;
1728         first->tx_flags = tx_flags;
1729
1730         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1731
1732         tx_desc = I40E_TX_DESC(tx_ring, i);
1733         tx_bi = first;
1734
1735         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1736                 if (dma_mapping_error(tx_ring->dev, dma))
1737                         goto dma_error;
1738
1739                 /* record length, and DMA address */
1740                 dma_unmap_len_set(tx_bi, len, size);
1741                 dma_unmap_addr_set(tx_bi, dma, dma);
1742
1743                 tx_desc->buffer_addr = cpu_to_le64(dma);
1744
1745                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1746                         tx_desc->cmd_type_offset_bsz =
1747                                 build_ctob(td_cmd, td_offset,
1748                                            I40E_MAX_DATA_PER_TXD, td_tag);
1749
1750                         tx_desc++;
1751                         i++;
1752                         if (i == tx_ring->count) {
1753                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1754                                 i = 0;
1755                         }
1756
1757                         dma += I40E_MAX_DATA_PER_TXD;
1758                         size -= I40E_MAX_DATA_PER_TXD;
1759
1760                         tx_desc->buffer_addr = cpu_to_le64(dma);
1761                 }
1762
1763                 if (likely(!data_len))
1764                         break;
1765
1766                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1767                                                           size, td_tag);
1768
1769                 tx_desc++;
1770                 i++;
1771                 if (i == tx_ring->count) {
1772                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1773                         i = 0;
1774                 }
1775
1776                 size = skb_frag_size(frag);
1777                 data_len -= size;
1778
1779                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1780                                        DMA_TO_DEVICE);
1781
1782                 tx_bi = &tx_ring->tx_bi[i];
1783         }
1784
1785         /* Place RS bit on last descriptor of any packet that spans across the
1786          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1787          */
1788 #define WB_STRIDE 0x3
1789         if (((i & WB_STRIDE) != WB_STRIDE) &&
1790             (first <= &tx_ring->tx_bi[i]) &&
1791             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1792                 tx_desc->cmd_type_offset_bsz =
1793                         build_ctob(td_cmd, td_offset, size, td_tag) |
1794                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1795                                          I40E_TXD_QW1_CMD_SHIFT);
1796         } else {
1797                 tx_desc->cmd_type_offset_bsz =
1798                         build_ctob(td_cmd, td_offset, size, td_tag) |
1799                         cpu_to_le64((u64)I40E_TXD_CMD <<
1800                                          I40E_TXD_QW1_CMD_SHIFT);
1801         }
1802
1803         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1804                                                  tx_ring->queue_index),
1805                              first->bytecount);
1806
1807         /* Force memory writes to complete before letting h/w
1808          * know there are new descriptors to fetch.  (Only
1809          * applicable for weak-ordered memory model archs,
1810          * such as IA-64).
1811          */
1812         wmb();
1813
1814         /* set next_to_watch value indicating a packet is present */
1815         first->next_to_watch = tx_desc;
1816
1817         i++;
1818         if (i == tx_ring->count)
1819                 i = 0;
1820
1821         tx_ring->next_to_use = i;
1822
1823         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1824         /* notify HW of packet */
1825         if (!skb->xmit_more ||
1826             netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1827                                                    tx_ring->queue_index)))
1828                 writel(i, tx_ring->tail);
1829         else
1830                 prefetchw(tx_desc + 1);
1831
1832         return;
1833
1834 dma_error:
1835         dev_info(tx_ring->dev, "TX DMA map failed\n");
1836
1837         /* clear dma mappings for failed tx_bi map */
1838         for (;;) {
1839                 tx_bi = &tx_ring->tx_bi[i];
1840                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1841                 if (tx_bi == first)
1842                         break;
1843                 if (i == 0)
1844                         i = tx_ring->count;
1845                 i--;
1846         }
1847
1848         tx_ring->next_to_use = i;
1849 }
1850
1851 /**
1852  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1853  * @skb:     send buffer
1854  * @tx_ring: ring to send buffer on
1855  *
1856  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1857  * there is not enough descriptors available in this ring since we need at least
1858  * one descriptor.
1859  **/
1860 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1861                                                struct i40e_ring *tx_ring)
1862 {
1863         unsigned int f;
1864         int count = 0;
1865
1866         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1867          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1868          *       + 4 desc gap to avoid the cache line where head is,
1869          *       + 1 desc for context descriptor,
1870          * otherwise try next time
1871          */
1872         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1873                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1874
1875         count += TXD_USE_COUNT(skb_headlen(skb));
1876         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1877                 tx_ring->tx_stats.tx_busy++;
1878                 return 0;
1879         }
1880         return count;
1881 }
1882
1883 /**
1884  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1885  * @skb:     send buffer
1886  * @tx_ring: ring to send buffer on
1887  *
1888  * Returns NETDEV_TX_OK if sent, else an error code
1889  **/
1890 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1891                                         struct i40e_ring *tx_ring)
1892 {
1893         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1894         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1895         struct i40e_tx_buffer *first;
1896         u32 td_offset = 0;
1897         u32 tx_flags = 0;
1898         __be16 protocol;
1899         u32 td_cmd = 0;
1900         u8 hdr_len = 0;
1901         int tso;
1902
1903         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
1904                 return NETDEV_TX_BUSY;
1905
1906         /* prepare the xmit flags */
1907         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1908                 goto out_drop;
1909
1910         /* obtain protocol of skb */
1911         protocol = vlan_get_protocol(skb);
1912
1913         /* record the location of the first descriptor for this packet */
1914         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1915
1916         /* setup IPv4/IPv6 offloads */
1917         if (protocol == htons(ETH_P_IP))
1918                 tx_flags |= I40E_TX_FLAGS_IPV4;
1919         else if (protocol == htons(ETH_P_IPV6))
1920                 tx_flags |= I40E_TX_FLAGS_IPV6;
1921
1922         tso = i40e_tso(tx_ring, skb, &hdr_len,
1923                        &cd_type_cmd_tso_mss, &cd_tunneling);
1924
1925         if (tso < 0)
1926                 goto out_drop;
1927         else if (tso)
1928                 tx_flags |= I40E_TX_FLAGS_TSO;
1929
1930         if (i40e_chk_linearize(skb, tx_flags)) {
1931                 if (skb_linearize(skb))
1932                         goto out_drop;
1933                 tx_ring->tx_stats.tx_linearize++;
1934         }
1935         skb_tx_timestamp(skb);
1936
1937         /* always enable CRC insertion offload */
1938         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1939
1940         /* Always offload the checksum, since it's in the data descriptor */
1941         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1942                 tx_flags |= I40E_TX_FLAGS_CSUM;
1943
1944                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
1945                                     tx_ring, &cd_tunneling);
1946         }
1947
1948         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1949                            cd_tunneling, cd_l2tag2);
1950
1951         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1952                       td_cmd, td_offset);
1953
1954         return NETDEV_TX_OK;
1955
1956 out_drop:
1957         dev_kfree_skb_any(skb);
1958         return NETDEV_TX_OK;
1959 }
1960
1961 /**
1962  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1963  * @skb:    send buffer
1964  * @netdev: network interface device structure
1965  *
1966  * Returns NETDEV_TX_OK if sent, else an error code
1967  **/
1968 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1969 {
1970         struct i40evf_adapter *adapter = netdev_priv(netdev);
1971         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1972
1973         /* hardware can't handle really short frames, hardware padding works
1974          * beyond this point
1975          */
1976         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1977                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1978                         return NETDEV_TX_OK;
1979                 skb->len = I40E_MIN_TX_LEN;
1980                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1981         }
1982
1983         return i40e_xmit_frame_ring(skb, tx_ring);
1984 }