drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  55                         kfree(tx_buffer->raw_buf);
  56                 else
  57                         dev_kfree_skb_any(tx_buffer->skb);
  58
  59                 if (dma_unmap_len(tx_buffer, len))
  60                         dma_unmap_single(ring->dev,
  61                                          dma_unmap_addr(tx_buffer, dma),
  62                                          dma_unmap_len(tx_buffer, len),
  63                                          DMA_TO_DEVICE);
  64         } else if (dma_unmap_len(tx_buffer, len)) {
  65                 dma_unmap_page(ring->dev,
  66                                dma_unmap_addr(tx_buffer, dma),
  67                                dma_unmap_len(tx_buffer, len),
  68                                DMA_TO_DEVICE);
  69         }
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 /**
 144  * i40e_get_tx_pending - how many tx descriptors not processed
 145  * @tx_ring: the ring of descriptors
 146  *
 147  * Since there is no access to the ring head register
 148  * in XL710, we need to use our local copies
 149  **/
 150 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
 151 {
 152         u32 head, tail;
 153
 154         head = i40e_get_head(ring);
 155         tail = readl(ring->tail);
 156
 157         if (head != tail)
 158                 return (head < tail) ?
 159                         tail - head : (tail + ring->count - head);
 160
 161         return 0;
 162 }
 163
 164 /**
 165  * i40e_check_tx_hang - Is there a hang in the Tx queue
 166  * @tx_ring: the ring of descriptors
 167  **/
 168 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
 169 {
 170         u32 tx_done = tx_ring->stats.packets;
 171         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 172         u32 tx_pending = i40e_get_tx_pending(tx_ring);
 173         bool ret = false;
 174
 175         clear_check_for_tx_hang(tx_ring);
 176
 177         /* Check for a hung queue, but be thorough. This verifies
 178          * that a transmit has been completed since the previous
 179          * check AND there is at least one packet pending. The
 180          * ARMED bit is set to indicate a potential hang. The
 181          * bit is cleared if a pause frame is received to remove
 182          * false hang detection due to PFC or 802.3x frames. By
 183          * requiring this to fail twice we avoid races with
 184          * PFC clearing the ARMED bit and conditions where we
 185          * run the check_tx_hang logic with a transmit completion
 186          * pending but without time to complete it yet.
 187          */
 188         if ((tx_done_old == tx_done) && tx_pending) {
 189                 /* make sure it is true for two checks in a row */
 190                 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
 191                                        &tx_ring->state);
 192         } else if (tx_done_old == tx_done &&
 193                    (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) {
 194                 /* update completed stats and disarm the hang check */
 195                 tx_ring->tx_stats.tx_done_old = tx_done;
 196                 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
 197         }
 198
 199         return ret;
 200 }
 201
 202 #define WB_STRIDE 0x3
 203
 204 /**
 205  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 206  * @tx_ring:  tx ring to clean
 207  * @budget:   how many cleans we're allowed
 208  *
 209  * Returns true if there's any budget left (e.g. the clean is finished)
 210  **/
 211 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 212 {
 213         u16 i = tx_ring->next_to_clean;
 214         struct i40e_tx_buffer *tx_buf;
 215         struct i40e_tx_desc *tx_head;
 216         struct i40e_tx_desc *tx_desc;
 217         unsigned int total_packets = 0;
 218         unsigned int total_bytes = 0;
 219
 220         tx_buf = &tx_ring->tx_bi[i];
 221         tx_desc = I40E_TX_DESC(tx_ring, i);
 222         i -= tx_ring->count;
 223
 224         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 225
 226         do {
 227                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 228
 229                 /* if next_to_watch is not set then there is no work pending */
 230                 if (!eop_desc)
 231                         break;
 232
 233                 /* prevent any other reads prior to eop_desc */
 234                 read_barrier_depends();
 235
 236                 /* we have caught up to head, no work left to do */
 237                 if (tx_head == tx_desc)
 238                         break;
 239
 240                 /* clear next_to_watch to prevent false hangs */
 241                 tx_buf->next_to_watch = NULL;
 242
 243                 /* update the statistics for this packet */
 244                 total_bytes += tx_buf->bytecount;
 245                 total_packets += tx_buf->gso_segs;
 246
 247                 /* free the skb */
 248                 dev_kfree_skb_any(tx_buf->skb);
 249
 250                 /* unmap skb header data */
 251                 dma_unmap_single(tx_ring->dev,
 252                                  dma_unmap_addr(tx_buf, dma),
 253                                  dma_unmap_len(tx_buf, len),
 254                                  DMA_TO_DEVICE);
 255
 256                 /* clear tx_buffer data */
 257                 tx_buf->skb = NULL;
 258                 dma_unmap_len_set(tx_buf, len, 0);
 259
 260                 /* unmap remaining buffers */
 261                 while (tx_desc != eop_desc) {
 262
 263                         tx_buf++;
 264                         tx_desc++;
 265                         i++;
 266                         if (unlikely(!i)) {
 267                                 i -= tx_ring->count;
 268                                 tx_buf = tx_ring->tx_bi;
 269                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 270                         }
 271
 272                         /* unmap any remaining paged data */
 273                         if (dma_unmap_len(tx_buf, len)) {
 274                                 dma_unmap_page(tx_ring->dev,
 275                                                dma_unmap_addr(tx_buf, dma),
 276                                                dma_unmap_len(tx_buf, len),
 277                                                DMA_TO_DEVICE);
 278                                 dma_unmap_len_set(tx_buf, len, 0);
 279                         }
 280                 }
 281
 282                 /* move us one more past the eop_desc for start of next pkt */
 283                 tx_buf++;
 284                 tx_desc++;
 285                 i++;
 286                 if (unlikely(!i)) {
 287                         i -= tx_ring->count;
 288                         tx_buf = tx_ring->tx_bi;
 289                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 290                 }
 291
 292                 prefetch(tx_desc);
 293
 294                 /* update budget accounting */
 295                 budget--;
 296         } while (likely(budget));
 297
 298         i += tx_ring->count;
 299         tx_ring->next_to_clean = i;
 300         u64_stats_update_begin(&tx_ring->syncp);
 301         tx_ring->stats.bytes += total_bytes;
 302         tx_ring->stats.packets += total_packets;
 303         u64_stats_update_end(&tx_ring->syncp);
 304         tx_ring->q_vector->tx.total_bytes += total_bytes;
 305         tx_ring->q_vector->tx.total_packets += total_packets;
 306
 307         if (budget &&
 308             !((i & WB_STRIDE) == WB_STRIDE) &&
 309             !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 310             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 311                 tx_ring->arm_wb = true;
 312         else
 313                 tx_ring->arm_wb = false;
 314
 315         if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
 316                 /* schedule immediate reset if we believe we hung */
 317                 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
 318                          "  VSI                  <%d>\n"
 319                          "  Tx Queue             <%d>\n"
 320                          "  next_to_use          <%x>\n"
 321                          "  next_to_clean        <%x>\n",
 322                          tx_ring->vsi->seid,
 323                          tx_ring->queue_index,
 324                          tx_ring->next_to_use, i);
 325
 326                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 327
 328                 dev_info(tx_ring->dev,
 329                          "tx hang detected on queue %d, resetting adapter\n",
 330                          tx_ring->queue_index);
 331
 332                 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
 333
 334                 /* the adapter is about to reset, no point in enabling stuff */
 335                 return true;
 336         }
 337
 338         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 339                                                       tx_ring->queue_index),
 340                                   total_packets, total_bytes);
 341
 342 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 343         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 344                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 345                 /* Make sure that anybody stopping the queue after this
 346                  * sees the new next_to_clean.
 347                  */
 348                 smp_mb();
 349                 if (__netif_subqueue_stopped(tx_ring->netdev,
 350                                              tx_ring->queue_index) &&
 351                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 352                         netif_wake_subqueue(tx_ring->netdev,
 353                                             tx_ring->queue_index);
 354                         ++tx_ring->tx_stats.restart_queue;
 355                 }
 356         }
 357
 358         return budget > 0;
 359 }
 360
 361 /**
 362  * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 363  * @vsi: the VSI we care about
 364  * @q_vector: the vector  on which to force writeback
 365  *
 366  **/
 367 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 368 {
 369         u16 flags = q_vector->tx.ring[0].flags;
 370
 371         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 372                 u32 val;
 373
 374                 if (q_vector->arm_wb_state)
 375                         return;
 376
 377                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
 378
 379                 wr32(&vsi->back->hw,
 380                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 381                                           vsi->base_vector - 1),
 382                      val);
 383                 q_vector->arm_wb_state = true;
 384         } else {
 385                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 386                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 387                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 388                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 389                           /* allow 00 to be written to the index */
 390
 391                 wr32(&vsi->back->hw,
 392                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 393                                           vsi->base_vector - 1), val);
 394         }
 395 }
 396
 397 /**
 398  * i40e_set_new_dynamic_itr - Find new ITR level
 399  * @rc: structure containing ring performance data
 400  *
 401  * Stores a new ITR value based on packets and byte counts during
 402  * the last interrupt.  The advantage of per interrupt computation
 403  * is faster updates and more accurate ITR for the current traffic
 404  * pattern.  Constants in this function were computed based on
 405  * theoretical maximum wire speed and thresholds were set based on
 406  * testing data as well as attempting to minimize response time
 407  * while increasing bulk throughput.
 408  **/
 409 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 410 {
 411         enum i40e_latency_range new_latency_range = rc->latency_range;
 412         u32 new_itr = rc->itr;
 413         int bytes_per_int;
 414
 415         if (rc->total_packets == 0 || !rc->itr)
 416                 return;
 417
 418         /* simple throttlerate management
 419          *   0-10MB/s   lowest (100000 ints/s)
 420          *  10-20MB/s   low    (20000 ints/s)
 421          *  20-1249MB/s bulk   (8000 ints/s)
 422          */
 423         bytes_per_int = rc->total_bytes / rc->itr;
 424         switch (new_latency_range) {
 425         case I40E_LOWEST_LATENCY:
 426                 if (bytes_per_int > 10)
 427                         new_latency_range = I40E_LOW_LATENCY;
 428                 break;
 429         case I40E_LOW_LATENCY:
 430                 if (bytes_per_int > 20)
 431                         new_latency_range = I40E_BULK_LATENCY;
 432                 else if (bytes_per_int <= 10)
 433                         new_latency_range = I40E_LOWEST_LATENCY;
 434                 break;
 435         case I40E_BULK_LATENCY:
 436                 if (bytes_per_int <= 20)
 437                         new_latency_range = I40E_LOW_LATENCY;
 438                 break;
 439         default:
 440                 if (bytes_per_int <= 20)
 441                         new_latency_range = I40E_LOW_LATENCY;
 442                 break;
 443         }
 444         rc->latency_range = new_latency_range;
 445
 446         switch (new_latency_range) {
 447         case I40E_LOWEST_LATENCY:
 448                 new_itr = I40E_ITR_100K;
 449                 break;
 450         case I40E_LOW_LATENCY:
 451                 new_itr = I40E_ITR_20K;
 452                 break;
 453         case I40E_BULK_LATENCY:
 454                 new_itr = I40E_ITR_8K;
 455                 break;
 456         default:
 457                 break;
 458         }
 459
 460         if (new_itr != rc->itr)
 461                 rc->itr = new_itr;
 462
 463         rc->total_bytes = 0;
 464         rc->total_packets = 0;
 465 }
 466
 467 /*
 468  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 469  * @tx_ring: the tx ring to set up
 470  *
 471  * Return 0 on success, negative on error
 472  **/
 473 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 474 {
 475         struct device *dev = tx_ring->dev;
 476         int bi_size;
 477
 478         if (!dev)
 479                 return -ENOMEM;
 480
 481         /* warn if we are about to overwrite the pointer */
 482         WARN_ON(tx_ring->tx_bi);
 483         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 484         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 485         if (!tx_ring->tx_bi)
 486                 goto err;
 487
 488         /* round up to nearest 4K */
 489         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 490         /* add u32 for head writeback, align after this takes care of
 491          * guaranteeing this is at least one cache line in size
 492          */
 493         tx_ring->size += sizeof(u32);
 494         tx_ring->size = ALIGN(tx_ring->size, 4096);
 495         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 496                                            &tx_ring->dma, GFP_KERNEL);
 497         if (!tx_ring->desc) {
 498                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 499                          tx_ring->size);
 500                 goto err;
 501         }
 502
 503         tx_ring->next_to_use = 0;
 504         tx_ring->next_to_clean = 0;
 505         return 0;
 506
 507 err:
 508         kfree(tx_ring->tx_bi);
 509         tx_ring->tx_bi = NULL;
 510         return -ENOMEM;
 511 }
 512
 513 /**
 514  * i40evf_clean_rx_ring - Free Rx buffers
 515  * @rx_ring: ring to be cleaned
 516  **/
 517 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 518 {
 519         struct device *dev = rx_ring->dev;
 520         struct i40e_rx_buffer *rx_bi;
 521         unsigned long bi_size;
 522         u16 i;
 523
 524         /* ring already cleared, nothing to do */
 525         if (!rx_ring->rx_bi)
 526                 return;
 527
 528         if (ring_is_ps_enabled(rx_ring)) {
 529                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 530
 531                 rx_bi = &rx_ring->rx_bi[0];
 532                 if (rx_bi->hdr_buf) {
 533                         dma_free_coherent(dev,
 534                                           bufsz,
 535                                           rx_bi->hdr_buf,
 536                                           rx_bi->dma);
 537                         for (i = 0; i < rx_ring->count; i++) {
 538                                 rx_bi = &rx_ring->rx_bi[i];
 539                                 rx_bi->dma = 0;
 540                                 rx_bi->hdr_buf = NULL;
 541                         }
 542                 }
 543         }
 544         /* Free all the Rx ring sk_buffs */
 545         for (i = 0; i < rx_ring->count; i++) {
 546                 rx_bi = &rx_ring->rx_bi[i];
 547                 if (rx_bi->dma) {
 548                         dma_unmap_single(dev,
 549                                          rx_bi->dma,
 550                                          rx_ring->rx_buf_len,
 551                                          DMA_FROM_DEVICE);
 552                         rx_bi->dma = 0;
 553                 }
 554                 if (rx_bi->skb) {
 555                         dev_kfree_skb(rx_bi->skb);
 556                         rx_bi->skb = NULL;
 557                 }
 558                 if (rx_bi->page) {
 559                         if (rx_bi->page_dma) {
 560                                 dma_unmap_page(dev,
 561                                                rx_bi->page_dma,
 562                                                PAGE_SIZE / 2,
 563                                                DMA_FROM_DEVICE);
 564                                 rx_bi->page_dma = 0;
 565                         }
 566                         __free_page(rx_bi->page);
 567                         rx_bi->page = NULL;
 568                         rx_bi->page_offset = 0;
 569                 }
 570         }
 571
 572         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 573         memset(rx_ring->rx_bi, 0, bi_size);
 574
 575         /* Zero out the descriptor ring */
 576         memset(rx_ring->desc, 0, rx_ring->size);
 577
 578         rx_ring->next_to_clean = 0;
 579         rx_ring->next_to_use = 0;
 580 }
 581
 582 /**
 583  * i40evf_free_rx_resources - Free Rx resources
 584  * @rx_ring: ring to clean the resources from
 585  *
 586  * Free all receive software resources
 587  **/
 588 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 589 {
 590         i40evf_clean_rx_ring(rx_ring);
 591         kfree(rx_ring->rx_bi);
 592         rx_ring->rx_bi = NULL;
 593
 594         if (rx_ring->desc) {
 595                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 596                                   rx_ring->desc, rx_ring->dma);
 597                 rx_ring->desc = NULL;
 598         }
 599 }
 600
 601 /**
 602  * i40evf_alloc_rx_headers - allocate rx header buffers
 603  * @rx_ring: ring to alloc buffers
 604  *
 605  * Allocate rx header buffers for the entire ring. As these are static,
 606  * this is only called when setting up a new ring.
 607  **/
 608 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 609 {
 610         struct device *dev = rx_ring->dev;
 611         struct i40e_rx_buffer *rx_bi;
 612         dma_addr_t dma;
 613         void *buffer;
 614         int buf_size;
 615         int i;
 616
 617         if (rx_ring->rx_bi[0].hdr_buf)
 618                 return;
 619         /* Make sure the buffers don't cross cache line boundaries. */
 620         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 621         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 622                                     &dma, GFP_KERNEL);
 623         if (!buffer)
 624                 return;
 625         for (i = 0; i < rx_ring->count; i++) {
 626                 rx_bi = &rx_ring->rx_bi[i];
 627                 rx_bi->dma = dma + (i * buf_size);
 628                 rx_bi->hdr_buf = buffer + (i * buf_size);
 629         }
 630 }
 631
 632 /**
 633  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 634  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 635  *
 636  * Returns 0 on success, negative on failure
 637  **/
 638 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 639 {
 640         struct device *dev = rx_ring->dev;
 641         int bi_size;
 642
 643         /* warn if we are about to overwrite the pointer */
 644         WARN_ON(rx_ring->rx_bi);
 645         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 646         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 647         if (!rx_ring->rx_bi)
 648                 goto err;
 649
 650         u64_stats_init(&rx_ring->syncp);
 651
 652         /* Round up to nearest 4K */
 653         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 654                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 655                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 656         rx_ring->size = ALIGN(rx_ring->size, 4096);
 657         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 658                                            &rx_ring->dma, GFP_KERNEL);
 659
 660         if (!rx_ring->desc) {
 661                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 662                          rx_ring->size);
 663                 goto err;
 664         }
 665
 666         rx_ring->next_to_clean = 0;
 667         rx_ring->next_to_use = 0;
 668
 669         return 0;
 670 err:
 671         kfree(rx_ring->rx_bi);
 672         rx_ring->rx_bi = NULL;
 673         return -ENOMEM;
 674 }
 675
 676 /**
 677  * i40e_release_rx_desc - Store the new tail and head values
 678  * @rx_ring: ring to bump
 679  * @val: new head index
 680  **/
 681 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 682 {
 683         rx_ring->next_to_use = val;
 684         /* Force memory writes to complete before letting h/w
 685          * know there are new descriptors to fetch.  (Only
 686          * applicable for weak-ordered memory model archs,
 687          * such as IA-64).
 688          */
 689         wmb();
 690         writel(val, rx_ring->tail);
 691 }
 692
 693 /**
 694  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 695  * @rx_ring: ring to place buffers on
 696  * @cleaned_count: number of buffers to replace
 697  **/
 698 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 699 {
 700         u16 i = rx_ring->next_to_use;
 701         union i40e_rx_desc *rx_desc;
 702         struct i40e_rx_buffer *bi;
 703
 704         /* do nothing if no valid netdev defined */
 705         if (!rx_ring->netdev || !cleaned_count)
 706                 return;
 707
 708         while (cleaned_count--) {
 709                 rx_desc = I40E_RX_DESC(rx_ring, i);
 710                 bi = &rx_ring->rx_bi[i];
 711
 712                 if (bi->skb) /* desc is in use */
 713                         goto no_buffers;
 714                 if (!bi->page) {
 715                         bi->page = alloc_page(GFP_ATOMIC);
 716                         if (!bi->page) {
 717                                 rx_ring->rx_stats.alloc_page_failed++;
 718                                 goto no_buffers;
 719                         }
 720                 }
 721
 722                 if (!bi->page_dma) {
 723                         /* use a half page if we're re-using */
 724                         bi->page_offset ^= PAGE_SIZE / 2;
 725                         bi->page_dma = dma_map_page(rx_ring->dev,
 726                                                     bi->page,
 727                                                     bi->page_offset,
 728                                                     PAGE_SIZE / 2,
 729                                                     DMA_FROM_DEVICE);
 730                         if (dma_mapping_error(rx_ring->dev,
 731                                               bi->page_dma)) {
 732                                 rx_ring->rx_stats.alloc_page_failed++;
 733                                 bi->page_dma = 0;
 734                                 goto no_buffers;
 735                         }
 736                 }
 737
 738                 dma_sync_single_range_for_device(rx_ring->dev,
 739                                                  bi->dma,
 740                                                  0,
 741                                                  rx_ring->rx_hdr_len,
 742                                                  DMA_FROM_DEVICE);
 743                 /* Refresh the desc even if buffer_addrs didn't change
 744                  * because each write-back erases this info.
 745                  */
 746                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 747                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 748                 i++;
 749                 if (i == rx_ring->count)
 750                         i = 0;
 751         }
 752
 753 no_buffers:
 754         if (rx_ring->next_to_use != i)
 755                 i40e_release_rx_desc(rx_ring, i);
 756 }
 757
 758 /**
 759  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 760  * @rx_ring: ring to place buffers on
 761  * @cleaned_count: number of buffers to replace
 762  **/
 763 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 764 {
 765         u16 i = rx_ring->next_to_use;
 766         union i40e_rx_desc *rx_desc;
 767         struct i40e_rx_buffer *bi;
 768         struct sk_buff *skb;
 769
 770         /* do nothing if no valid netdev defined */
 771         if (!rx_ring->netdev || !cleaned_count)
 772                 return;
 773
 774         while (cleaned_count--) {
 775                 rx_desc = I40E_RX_DESC(rx_ring, i);
 776                 bi = &rx_ring->rx_bi[i];
 777                 skb = bi->skb;
 778
 779                 if (!skb) {
 780                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 781                                                         rx_ring->rx_buf_len);
 782                         if (!skb) {
 783                                 rx_ring->rx_stats.alloc_buff_failed++;
 784                                 goto no_buffers;
 785                         }
 786                         /* initialize queue mapping */
 787                         skb_record_rx_queue(skb, rx_ring->queue_index);
 788                         bi->skb = skb;
 789                 }
 790
 791                 if (!bi->dma) {
 792                         bi->dma = dma_map_single(rx_ring->dev,
 793                                                  skb->data,
 794                                                  rx_ring->rx_buf_len,
 795                                                  DMA_FROM_DEVICE);
 796                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 797                                 rx_ring->rx_stats.alloc_buff_failed++;
 798                                 bi->dma = 0;
 799                                 goto no_buffers;
 800                         }
 801                 }
 802
 803                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 804                 rx_desc->read.hdr_addr = 0;
 805                 i++;
 806                 if (i == rx_ring->count)
 807                         i = 0;
 808         }
 809
 810 no_buffers:
 811         if (rx_ring->next_to_use != i)
 812                 i40e_release_rx_desc(rx_ring, i);
 813 }
 814
 815 /**
 816  * i40e_receive_skb - Send a completed packet up the stack
 817  * @rx_ring:  rx ring in play
 818  * @skb: packet to send up
 819  * @vlan_tag: vlan tag for packet
 820  **/
 821 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 822                              struct sk_buff *skb, u16 vlan_tag)
 823 {
 824         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 825         struct i40e_vsi *vsi = rx_ring->vsi;
 826         u64 flags = vsi->back->flags;
 827
 828         if (vlan_tag & VLAN_VID_MASK)
 829                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 830
 831         if (flags & I40E_FLAG_IN_NETPOLL)
 832                 netif_rx(skb);
 833         else
 834                 napi_gro_receive(&q_vector->napi, skb);
 835 }
 836
 837 /**
 838  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 839  * @vsi: the VSI we care about
 840  * @skb: skb currently being received and modified
 841  * @rx_status: status value of last descriptor in packet
 842  * @rx_error: error value of last descriptor in packet
 843  * @rx_ptype: ptype value of last descriptor in packet
 844  **/
 845 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 846                                     struct sk_buff *skb,
 847                                     u32 rx_status,
 848                                     u32 rx_error,
 849                                     u16 rx_ptype)
 850 {
 851         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 852         bool ipv4 = false, ipv6 = false;
 853         bool ipv4_tunnel, ipv6_tunnel;
 854         __wsum rx_udp_csum;
 855         struct iphdr *iph;
 856         __sum16 csum;
 857
 858         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 859                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 860         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 861                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 862
 863         skb->ip_summed = CHECKSUM_NONE;
 864
 865         /* Rx csum enabled and ip headers found? */
 866         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 867                 return;
 868
 869         /* did the hardware decode the packet and checksum? */
 870         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 871                 return;
 872
 873         /* both known and outer_ip must be set for the below code to work */
 874         if (!(decoded.known && decoded.outer_ip))
 875                 return;
 876
 877         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 878             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 879                 ipv4 = true;
 880         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 881                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 882                 ipv6 = true;
 883
 884         if (ipv4 &&
 885             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 886                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 887                 goto checksum_fail;
 888
 889         /* likely incorrect csum if alternate IP extension headers found */
 890         if (ipv6 &&
 891             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 892                 /* don't increment checksum err here, non-fatal err */
 893                 return;
 894
 895         /* there was some L4 error, count error and punt packet to the stack */
 896         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 897                 goto checksum_fail;
 898
 899         /* handle packets that were not able to be checksummed due
 900          * to arrival speed, in this case the stack can compute
 901          * the csum.
 902          */
 903         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 904                 return;
 905
 906         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 907          * it in the driver, hardware does not do it for us.
 908          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 909          * so the total length of IPv4 header is IHL*4 bytes
 910          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 911          */
 912         if (ipv4_tunnel) {
 913                 skb->transport_header = skb->mac_header +
 914                                         sizeof(struct ethhdr) +
 915                                         (ip_hdr(skb)->ihl * 4);
 916
 917                 /* Add 4 bytes for VLAN tagged packets */
 918                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 919                                           skb->protocol == htons(ETH_P_8021AD))
 920                                           ? VLAN_HLEN : 0;
 921
 922                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 923                     (udp_hdr(skb)->check != 0)) {
 924                         rx_udp_csum = udp_csum(skb);
 925                         iph = ip_hdr(skb);
 926                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 927                                                  (skb->len -
 928                                                   skb_transport_offset(skb)),
 929                                                  IPPROTO_UDP, rx_udp_csum);
 930
 931                         if (udp_hdr(skb)->check != csum)
 932                                 goto checksum_fail;
 933
 934                 } /* else its GRE and so no outer UDP header */
 935         }
 936
 937         skb->ip_summed = CHECKSUM_UNNECESSARY;
 938         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 939
 940         return;
 941
 942 checksum_fail:
 943         vsi->back->hw_csum_rx_error++;
 944 }
 945
 946 /**
 947  * i40e_rx_hash - returns the hash value from the Rx descriptor
 948  * @ring: descriptor ring
 949  * @rx_desc: specific descriptor
 950  **/
 951 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 952                                union i40e_rx_desc *rx_desc)
 953 {
 954         const __le64 rss_mask =
 955                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 956                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 957
 958         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 959             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 960                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 961         else
 962                 return 0;
 963 }
 964
 965 /**
 966  * i40e_ptype_to_hash - get a hash type
 967  * @ptype: the ptype value from the descriptor
 968  *
 969  * Returns a hash type to be used by skb_set_hash
 970  **/
 971 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 972 {
 973         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 974
 975         if (!decoded.known)
 976                 return PKT_HASH_TYPE_NONE;
 977
 978         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 979             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 980                 return PKT_HASH_TYPE_L4;
 981         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 982                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 983                 return PKT_HASH_TYPE_L3;
 984         else
 985                 return PKT_HASH_TYPE_L2;
 986 }
 987
 988 /**
 989  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 990  * @rx_ring:  rx ring to clean
 991  * @budget:   how many cleans we're allowed
 992  *
 993  * Returns true if there's any budget left (e.g. the clean is finished)
 994  **/
 995 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 996 {
 997         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 998         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 999         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1000         const int current_node = numa_node_id();
1001         struct i40e_vsi *vsi = rx_ring->vsi;
1002         u16 i = rx_ring->next_to_clean;
1003         union i40e_rx_desc *rx_desc;
1004         u32 rx_error, rx_status;
1005         u8 rx_ptype;
1006         u64 qword;
1007
1008         do {
1009                 struct i40e_rx_buffer *rx_bi;
1010                 struct sk_buff *skb;
1011                 u16 vlan_tag;
1012                 /* return some buffers to hardware, one at a time is too slow */
1013                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1014                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1015                         cleaned_count = 0;
1016                 }
1017
1018                 i = rx_ring->next_to_clean;
1019                 rx_desc = I40E_RX_DESC(rx_ring, i);
1020                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1021                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1022                         I40E_RXD_QW1_STATUS_SHIFT;
1023
1024                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1025                         break;
1026
1027                 /* This memory barrier is needed to keep us from reading
1028                  * any other fields out of the rx_desc until we know the
1029                  * DD bit is set.
1030                  */
1031                 dma_rmb();
1032                 rx_bi = &rx_ring->rx_bi[i];
1033                 skb = rx_bi->skb;
1034                 if (likely(!skb)) {
1035                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1036                                                         rx_ring->rx_hdr_len);
1037                         if (!skb) {
1038                                 rx_ring->rx_stats.alloc_buff_failed++;
1039                                 break;
1040                         }
1041
1042                         /* initialize queue mapping */
1043                         skb_record_rx_queue(skb, rx_ring->queue_index);
1044                         /* we are reusing so sync this buffer for CPU use */
1045                         dma_sync_single_range_for_cpu(rx_ring->dev,
1046                                                       rx_bi->dma,
1047                                                       0,
1048                                                       rx_ring->rx_hdr_len,
1049                                                       DMA_FROM_DEVICE);
1050                 }
1051                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1052                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1053                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1054                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1055                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1056                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1057
1058                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1059                            I40E_RXD_QW1_ERROR_SHIFT;
1060                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1061                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1062
1063                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1064                            I40E_RXD_QW1_PTYPE_SHIFT;
1065                 prefetch(rx_bi->page);
1066                 rx_bi->skb = NULL;
1067                 cleaned_count++;
1068                 if (rx_hbo || rx_sph) {
1069                         int len;
1070                         if (rx_hbo)
1071                                 len = I40E_RX_HDR_SIZE;
1072                         else
1073                                 len = rx_header_len;
1074                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1075                 } else if (skb->len == 0) {
1076                         int len;
1077
1078                         len = (rx_packet_len > skb_headlen(skb) ?
1079                                 skb_headlen(skb) : rx_packet_len);
1080                         memcpy(__skb_put(skb, len),
1081                                rx_bi->page + rx_bi->page_offset,
1082                                len);
1083                         rx_bi->page_offset += len;
1084                         rx_packet_len -= len;
1085                 }
1086
1087                 /* Get the rest of the data if this was a header split */
1088                 if (rx_packet_len) {
1089                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1090                                            rx_bi->page,
1091                                            rx_bi->page_offset,
1092                                            rx_packet_len);
1093
1094                         skb->len += rx_packet_len;
1095                         skb->data_len += rx_packet_len;
1096                         skb->truesize += rx_packet_len;
1097
1098                         if ((page_count(rx_bi->page) == 1) &&
1099                             (page_to_nid(rx_bi->page) == current_node))
1100                                 get_page(rx_bi->page);
1101                         else
1102                                 rx_bi->page = NULL;
1103
1104                         dma_unmap_page(rx_ring->dev,
1105                                        rx_bi->page_dma,
1106                                        PAGE_SIZE / 2,
1107                                        DMA_FROM_DEVICE);
1108                         rx_bi->page_dma = 0;
1109                 }
1110                 I40E_RX_INCREMENT(rx_ring, i);
1111
1112                 if (unlikely(
1113                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1114                         struct i40e_rx_buffer *next_buffer;
1115
1116                         next_buffer = &rx_ring->rx_bi[i];
1117                         next_buffer->skb = skb;
1118                         rx_ring->rx_stats.non_eop_descs++;
1119                         continue;
1120                 }
1121
1122                 /* ERR_MASK will only have valid bits if EOP set */
1123                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1124                         dev_kfree_skb_any(skb);
1125                         continue;
1126                 }
1127
1128                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1129                              i40e_ptype_to_hash(rx_ptype));
1130                 /* probably a little skewed due to removing CRC */
1131                 total_rx_bytes += skb->len;
1132                 total_rx_packets++;
1133
1134                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1135
1136                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1137
1138                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1139                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1140                          : 0;
1141 #ifdef I40E_FCOE
1142                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1143                         dev_kfree_skb_any(skb);
1144                         continue;
1145                 }
1146 #endif
1147                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1148                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1149
1150                 rx_desc->wb.qword1.status_error_len = 0;
1151
1152         } while (likely(total_rx_packets < budget));
1153
1154         u64_stats_update_begin(&rx_ring->syncp);
1155         rx_ring->stats.packets += total_rx_packets;
1156         rx_ring->stats.bytes += total_rx_bytes;
1157         u64_stats_update_end(&rx_ring->syncp);
1158         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1159         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1160
1161         return total_rx_packets;
1162 }
1163
1164 /**
1165  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1166  * @rx_ring:  rx ring to clean
1167  * @budget:   how many cleans we're allowed
1168  *
1169  * Returns number of packets cleaned
1170  **/
1171 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1172 {
1173         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1174         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1175         struct i40e_vsi *vsi = rx_ring->vsi;
1176         union i40e_rx_desc *rx_desc;
1177         u32 rx_error, rx_status;
1178         u16 rx_packet_len;
1179         u8 rx_ptype;
1180         u64 qword;
1181         u16 i;
1182
1183         do {
1184                 struct i40e_rx_buffer *rx_bi;
1185                 struct sk_buff *skb;
1186                 u16 vlan_tag;
1187                 /* return some buffers to hardware, one at a time is too slow */
1188                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1189                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1190                         cleaned_count = 0;
1191                 }
1192
1193                 i = rx_ring->next_to_clean;
1194                 rx_desc = I40E_RX_DESC(rx_ring, i);
1195                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1196                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1197                         I40E_RXD_QW1_STATUS_SHIFT;
1198
1199                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1200                         break;
1201
1202                 /* This memory barrier is needed to keep us from reading
1203                  * any other fields out of the rx_desc until we know the
1204                  * DD bit is set.
1205                  */
1206                 dma_rmb();
1207
1208                 rx_bi = &rx_ring->rx_bi[i];
1209                 skb = rx_bi->skb;
1210                 prefetch(skb->data);
1211
1212                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1213                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1214
1215                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1216                            I40E_RXD_QW1_ERROR_SHIFT;
1217                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1218
1219                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1220                            I40E_RXD_QW1_PTYPE_SHIFT;
1221                 rx_bi->skb = NULL;
1222                 cleaned_count++;
1223
1224                 /* Get the header and possibly the whole packet
1225                  * If this is an skb from previous receive dma will be 0
1226                  */
1227                 skb_put(skb, rx_packet_len);
1228                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1229                                  DMA_FROM_DEVICE);
1230                 rx_bi->dma = 0;
1231
1232                 I40E_RX_INCREMENT(rx_ring, i);
1233
1234                 if (unlikely(
1235                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1236                         rx_ring->rx_stats.non_eop_descs++;
1237                         continue;
1238                 }
1239
1240                 /* ERR_MASK will only have valid bits if EOP set */
1241                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1242                         dev_kfree_skb_any(skb);
1243                         /* TODO: shouldn't we increment a counter indicating the
1244                          * drop?
1245                          */
1246                         continue;
1247                 }
1248
1249                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1250                              i40e_ptype_to_hash(rx_ptype));
1251                 /* probably a little skewed due to removing CRC */
1252                 total_rx_bytes += skb->len;
1253                 total_rx_packets++;
1254
1255                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1256
1257                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1258
1259                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1260                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1261                          : 0;
1262                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1263
1264                 rx_desc->wb.qword1.status_error_len = 0;
1265         } while (likely(total_rx_packets < budget));
1266
1267         u64_stats_update_begin(&rx_ring->syncp);
1268         rx_ring->stats.packets += total_rx_packets;
1269         rx_ring->stats.bytes += total_rx_bytes;
1270         u64_stats_update_end(&rx_ring->syncp);
1271         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1272         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1273
1274         return total_rx_packets;
1275 }
1276
1277 /**
1278  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1279  * @vsi: the VSI we care about
1280  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1281  *
1282  **/
1283 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1284                                           struct i40e_q_vector *q_vector)
1285 {
1286         struct i40e_hw *hw = &vsi->back->hw;
1287         u16 old_itr;
1288         int vector;
1289         u32 val;
1290
1291         vector = (q_vector->v_idx + vsi->base_vector);
1292         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1293                 old_itr = q_vector->rx.itr;
1294                 i40e_set_new_dynamic_itr(&q_vector->rx);
1295                 if (old_itr != q_vector->rx.itr) {
1296                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1297                         I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1298                         (I40E_RX_ITR <<
1299                                 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1300                         (q_vector->rx.itr <<
1301                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1302                 } else {
1303                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1304                         I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1305                         (I40E_ITR_NONE <<
1306                                 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
1307                 }
1308                 if (!test_bit(__I40E_DOWN, &vsi->state))
1309                         wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1310         } else {
1311                 i40evf_irq_enable_queues(vsi->back, 1
1312                         << q_vector->v_idx);
1313         }
1314         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1315                 old_itr = q_vector->tx.itr;
1316                 i40e_set_new_dynamic_itr(&q_vector->tx);
1317                 if (old_itr != q_vector->tx.itr) {
1318                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1319                                 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1320                                 (I40E_TX_ITR <<
1321                                    I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1322                                 (q_vector->tx.itr <<
1323                                    I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1324
1325                 } else {
1326                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1327                                 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1328                                 (I40E_ITR_NONE <<
1329                                    I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
1330                 }
1331                 if (!test_bit(__I40E_DOWN, &vsi->state))
1332                         wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1333         } else {
1334                 i40evf_irq_enable_queues(vsi->back, BIT(q_vector->v_idx));
1335         }
1336 }
1337
1338 /**
1339  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1340  * @napi: napi struct with our devices info in it
1341  * @budget: amount of work driver is allowed to do this pass, in packets
1342  *
1343  * This function will clean all queues associated with a q_vector.
1344  *
1345  * Returns the amount of work done
1346  **/
1347 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1348 {
1349         struct i40e_q_vector *q_vector =
1350                                container_of(napi, struct i40e_q_vector, napi);
1351         struct i40e_vsi *vsi = q_vector->vsi;
1352         struct i40e_ring *ring;
1353         bool clean_complete = true;
1354         bool arm_wb = false;
1355         int budget_per_ring;
1356         int cleaned;
1357
1358         if (test_bit(__I40E_DOWN, &vsi->state)) {
1359                 napi_complete(napi);
1360                 return 0;
1361         }
1362
1363         /* Since the actual Tx work is minimal, we can give the Tx a larger
1364          * budget and be more aggressive about cleaning up the Tx descriptors.
1365          */
1366         i40e_for_each_ring(ring, q_vector->tx) {
1367                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1368                 arm_wb |= ring->arm_wb;
1369         }
1370
1371         /* We attempt to distribute budget to each Rx queue fairly, but don't
1372          * allow the budget to go below 1 because that would exit polling early.
1373          */
1374         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1375
1376         i40e_for_each_ring(ring, q_vector->rx) {
1377                 if (ring_is_ps_enabled(ring))
1378                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1379                 else
1380                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1381                 /* if we didn't clean as many as budgeted, we must be done */
1382                 clean_complete &= (budget_per_ring != cleaned);
1383         }
1384
1385         /* If work not completed, return budget and polling will return */
1386         if (!clean_complete) {
1387                 if (arm_wb)
1388                         i40e_force_wb(vsi, q_vector);
1389                 return budget;
1390         }
1391
1392         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1393                 q_vector->arm_wb_state = false;
1394
1395         /* Work is done so exit the polling mode and re-enable the interrupt */
1396         napi_complete(napi);
1397         i40e_update_enable_itr(vsi, q_vector);
1398         return 0;
1399 }
1400
1401 /**
1402  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1403  * @skb:     send buffer
1404  * @tx_ring: ring to send buffer on
1405  * @flags:   the tx flags to be set
1406  *
1407  * Checks the skb and set up correspondingly several generic transmit flags
1408  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1409  *
1410  * Returns error code indicate the frame should be dropped upon error and the
1411  * otherwise  returns 0 to indicate the flags has been set properly.
1412  **/
1413 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1414                                                struct i40e_ring *tx_ring,
1415                                                u32 *flags)
1416 {
1417         __be16 protocol = skb->protocol;
1418         u32  tx_flags = 0;
1419
1420         if (protocol == htons(ETH_P_8021Q) &&
1421             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1422                 /* When HW VLAN acceleration is turned off by the user the
1423                  * stack sets the protocol to 8021q so that the driver
1424                  * can take any steps required to support the SW only
1425                  * VLAN handling.  In our case the driver doesn't need
1426                  * to take any further steps so just set the protocol
1427                  * to the encapsulated ethertype.
1428                  */
1429                 skb->protocol = vlan_get_protocol(skb);
1430                 goto out;
1431         }
1432
1433         /* if we have a HW VLAN tag being added, default to the HW one */
1434         if (skb_vlan_tag_present(skb)) {
1435                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1436                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1437         /* else if it is a SW VLAN, check the next protocol and store the tag */
1438         } else if (protocol == htons(ETH_P_8021Q)) {
1439                 struct vlan_hdr *vhdr, _vhdr;
1440                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1441                 if (!vhdr)
1442                         return -EINVAL;
1443
1444                 protocol = vhdr->h_vlan_encapsulated_proto;
1445                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1446                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1447         }
1448
1449 out:
1450         *flags = tx_flags;
1451         return 0;
1452 }
1453
1454 /**
1455  * i40e_tso - set up the tso context descriptor
1456  * @tx_ring:  ptr to the ring to send
1457  * @skb:      ptr to the skb we're sending
1458  * @hdr_len:  ptr to the size of the packet header
1459  * @cd_tunneling: ptr to context descriptor bits
1460  *
1461  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1462  **/
1463 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1464                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1465                     u32 *cd_tunneling)
1466 {
1467         u32 cd_cmd, cd_tso_len, cd_mss;
1468         struct ipv6hdr *ipv6h;
1469         struct tcphdr *tcph;
1470         struct iphdr *iph;
1471         u32 l4len;
1472         int err;
1473
1474         if (!skb_is_gso(skb))
1475                 return 0;
1476
1477         err = skb_cow_head(skb, 0);
1478         if (err < 0)
1479                 return err;
1480
1481         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1482         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1483
1484         if (iph->version == 4) {
1485                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1486                 iph->tot_len = 0;
1487                 iph->check = 0;
1488                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1489                                                  0, IPPROTO_TCP, 0);
1490         } else if (ipv6h->version == 6) {
1491                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1492                 ipv6h->payload_len = 0;
1493                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1494                                                0, IPPROTO_TCP, 0);
1495         }
1496
1497         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1498         *hdr_len = (skb->encapsulation
1499                     ? (skb_inner_transport_header(skb) - skb->data)
1500                     : skb_transport_offset(skb)) + l4len;
1501
1502         /* find the field values */
1503         cd_cmd = I40E_TX_CTX_DESC_TSO;
1504         cd_tso_len = skb->len - *hdr_len;
1505         cd_mss = skb_shinfo(skb)->gso_size;
1506         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1507                                 ((u64)cd_tso_len <<
1508                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1509                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1510         return 1;
1511 }
1512
1513 /**
1514  * i40e_tx_enable_csum - Enable Tx checksum offloads
1515  * @skb: send buffer
1516  * @tx_flags: pointer to Tx flags currently set
1517  * @td_cmd: Tx descriptor command bits to set
1518  * @td_offset: Tx descriptor header offsets to set
1519  * @cd_tunneling: ptr to context desc bits
1520  **/
1521 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1522                                 u32 *td_cmd, u32 *td_offset,
1523                                 struct i40e_ring *tx_ring,
1524                                 u32 *cd_tunneling)
1525 {
1526         struct ipv6hdr *this_ipv6_hdr;
1527         unsigned int this_tcp_hdrlen;
1528         struct iphdr *this_ip_hdr;
1529         u32 network_hdr_len;
1530         u8 l4_hdr = 0;
1531         struct udphdr *oudph;
1532         struct iphdr *oiph;
1533         u32 l4_tunnel = 0;
1534
1535         if (skb->encapsulation) {
1536                 switch (ip_hdr(skb)->protocol) {
1537                 case IPPROTO_UDP:
1538                         oudph = udp_hdr(skb);
1539                         oiph = ip_hdr(skb);
1540                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1541                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1542                         break;
1543                 default:
1544                         return;
1545                 }
1546                 network_hdr_len = skb_inner_network_header_len(skb);
1547                 this_ip_hdr = inner_ip_hdr(skb);
1548                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1549                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1550
1551                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1552                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1553                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1554                                 ip_hdr(skb)->check = 0;
1555                         } else {
1556                                 *cd_tunneling |=
1557                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1558                         }
1559                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1560                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1561                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1562                                 ip_hdr(skb)->check = 0;
1563                 }
1564
1565                 /* Now set the ctx descriptor fields */
1566                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1567                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1568                                    l4_tunnel                             |
1569                                    ((skb_inner_network_offset(skb) -
1570                                         skb_transport_offset(skb)) >> 1) <<
1571                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1572                 if (this_ip_hdr->version == 6) {
1573                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1574                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1575                 }
1576
1577
1578                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1579                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1580                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1581                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1582                                         oiph->daddr,
1583                                         (skb->len - skb_transport_offset(skb)),
1584                                         IPPROTO_UDP, 0);
1585                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1586                 }
1587         } else {
1588                 network_hdr_len = skb_network_header_len(skb);
1589                 this_ip_hdr = ip_hdr(skb);
1590                 this_ipv6_hdr = ipv6_hdr(skb);
1591                 this_tcp_hdrlen = tcp_hdrlen(skb);
1592         }
1593
1594         /* Enable IP checksum offloads */
1595         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1596                 l4_hdr = this_ip_hdr->protocol;
1597                 /* the stack computes the IP header already, the only time we
1598                  * need the hardware to recompute it is in the case of TSO.
1599                  */
1600                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1601                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1602                         this_ip_hdr->check = 0;
1603                 } else {
1604                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1605                 }
1606                 /* Now set the td_offset for IP header length */
1607                 *td_offset = (network_hdr_len >> 2) <<
1608                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1609         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1610                 l4_hdr = this_ipv6_hdr->nexthdr;
1611                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1612                 /* Now set the td_offset for IP header length */
1613                 *td_offset = (network_hdr_len >> 2) <<
1614                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1615         }
1616         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1617         *td_offset |= (skb_network_offset(skb) >> 1) <<
1618                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1619
1620         /* Enable L4 checksum offloads */
1621         switch (l4_hdr) {
1622         case IPPROTO_TCP:
1623                 /* enable checksum offloads */
1624                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1625                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1626                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1627                 break;
1628         case IPPROTO_SCTP:
1629                 /* enable SCTP checksum offload */
1630                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1631                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1632                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1633                 break;
1634         case IPPROTO_UDP:
1635                 /* enable UDP checksum offload */
1636                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1637                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1638                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1639                 break;
1640         default:
1641                 break;
1642         }
1643 }
1644
1645 /**
1646  * i40e_create_tx_ctx Build the Tx context descriptor
1647  * @tx_ring:  ring to create the descriptor on
1648  * @cd_type_cmd_tso_mss: Quad Word 1
1649  * @cd_tunneling: Quad Word 0 - bits 0-31
1650  * @cd_l2tag2: Quad Word 0 - bits 32-63
1651  **/
1652 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1653                                const u64 cd_type_cmd_tso_mss,
1654                                const u32 cd_tunneling, const u32 cd_l2tag2)
1655 {
1656         struct i40e_tx_context_desc *context_desc;
1657         int i = tx_ring->next_to_use;
1658
1659         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1660             !cd_tunneling && !cd_l2tag2)
1661                 return;
1662
1663         /* grab the next descriptor */
1664         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1665
1666         i++;
1667         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1668
1669         /* cpu_to_le32 and assign to struct fields */
1670         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1671         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1672         context_desc->rsvd = cpu_to_le16(0);
1673         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1674 }
1675
1676  /**
1677  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1678  * @skb:      send buffer
1679  * @tx_flags: collected send information
1680  *
1681  * Note: Our HW can't scatter-gather more than 8 fragments to build
1682  * a packet on the wire and so we need to figure out the cases where we
1683  * need to linearize the skb.
1684  **/
1685 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1686 {
1687         struct skb_frag_struct *frag;
1688         bool linearize = false;
1689         unsigned int size = 0;
1690         u16 num_frags;
1691         u16 gso_segs;
1692
1693         num_frags = skb_shinfo(skb)->nr_frags;
1694         gso_segs = skb_shinfo(skb)->gso_segs;
1695
1696         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1697                 u16 j = 0;
1698
1699                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1700                         goto linearize_chk_done;
1701                 /* try the simple math, if we have too many frags per segment */
1702                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1703                     I40E_MAX_BUFFER_TXD) {
1704                         linearize = true;
1705                         goto linearize_chk_done;
1706                 }
1707                 frag = &skb_shinfo(skb)->frags[0];
1708                 /* we might still have more fragments per segment */
1709                 do {
1710                         size += skb_frag_size(frag);
1711                         frag++; j++;
1712                         if ((size >= skb_shinfo(skb)->gso_size) &&
1713                             (j < I40E_MAX_BUFFER_TXD)) {
1714                                 size = (size % skb_shinfo(skb)->gso_size);
1715                                 j = (size) ? 1 : 0;
1716                         }
1717                         if (j == I40E_MAX_BUFFER_TXD) {
1718                                 linearize = true;
1719                                 break;
1720                         }
1721                         num_frags--;
1722                 } while (num_frags);
1723         } else {
1724                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1725                         linearize = true;
1726         }
1727
1728 linearize_chk_done:
1729         return linearize;
1730 }
1731
1732 /**
1733  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1734  * @tx_ring: the ring to be checked
1735  * @size:    the size buffer we want to assure is available
1736  *
1737  * Returns -EBUSY if a stop is needed, else 0
1738  **/
1739 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1740 {
1741         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1742         /* Memory barrier before checking head and tail */
1743         smp_mb();
1744
1745         /* Check again in a case another CPU has just made room available. */
1746         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1747                 return -EBUSY;
1748
1749         /* A reprieve! - use start_queue because it doesn't call schedule */
1750         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1751         ++tx_ring->tx_stats.restart_queue;
1752         return 0;
1753 }
1754
1755 /**
1756  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1757  * @tx_ring: the ring to be checked
1758  * @size:    the size buffer we want to assure is available
1759  *
1760  * Returns 0 if stop is not needed
1761  **/
1762 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1763 {
1764         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1765                 return 0;
1766         return __i40evf_maybe_stop_tx(tx_ring, size);
1767 }
1768
1769 /**
1770  * i40evf_tx_map - Build the Tx descriptor
1771  * @tx_ring:  ring to send buffer on
1772  * @skb:      send buffer
1773  * @first:    first buffer info buffer to use
1774  * @tx_flags: collected send information
1775  * @hdr_len:  size of the packet header
1776  * @td_cmd:   the command field in the descriptor
1777  * @td_offset: offset for checksum or crc
1778  **/
1779 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1780                                  struct i40e_tx_buffer *first, u32 tx_flags,
1781                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1782 {
1783         unsigned int data_len = skb->data_len;
1784         unsigned int size = skb_headlen(skb);
1785         struct skb_frag_struct *frag;
1786         struct i40e_tx_buffer *tx_bi;
1787         struct i40e_tx_desc *tx_desc;
1788         u16 i = tx_ring->next_to_use;
1789         u32 td_tag = 0;
1790         dma_addr_t dma;
1791         u16 gso_segs;
1792
1793         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1794                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1795                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1796                          I40E_TX_FLAGS_VLAN_SHIFT;
1797         }
1798
1799         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1800                 gso_segs = skb_shinfo(skb)->gso_segs;
1801         else
1802                 gso_segs = 1;
1803
1804         /* multiply data chunks by size of headers */
1805         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1806         first->gso_segs = gso_segs;
1807         first->skb = skb;
1808         first->tx_flags = tx_flags;
1809
1810         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1811
1812         tx_desc = I40E_TX_DESC(tx_ring, i);
1813         tx_bi = first;
1814
1815         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1816                 if (dma_mapping_error(tx_ring->dev, dma))
1817                         goto dma_error;
1818
1819                 /* record length, and DMA address */
1820                 dma_unmap_len_set(tx_bi, len, size);
1821                 dma_unmap_addr_set(tx_bi, dma, dma);
1822
1823                 tx_desc->buffer_addr = cpu_to_le64(dma);
1824
1825                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1826                         tx_desc->cmd_type_offset_bsz =
1827                                 build_ctob(td_cmd, td_offset,
1828                                            I40E_MAX_DATA_PER_TXD, td_tag);
1829
1830                         tx_desc++;
1831                         i++;
1832                         if (i == tx_ring->count) {
1833                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1834                                 i = 0;
1835                         }
1836
1837                         dma += I40E_MAX_DATA_PER_TXD;
1838                         size -= I40E_MAX_DATA_PER_TXD;
1839
1840                         tx_desc->buffer_addr = cpu_to_le64(dma);
1841                 }
1842
1843                 if (likely(!data_len))
1844                         break;
1845
1846                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1847                                                           size, td_tag);
1848
1849                 tx_desc++;
1850                 i++;
1851                 if (i == tx_ring->count) {
1852                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1853                         i = 0;
1854                 }
1855
1856                 size = skb_frag_size(frag);
1857                 data_len -= size;
1858
1859                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1860                                        DMA_TO_DEVICE);
1861
1862                 tx_bi = &tx_ring->tx_bi[i];
1863         }
1864
1865         /* Place RS bit on last descriptor of any packet that spans across the
1866          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1867          */
1868 #define WB_STRIDE 0x3
1869         if (((i & WB_STRIDE) != WB_STRIDE) &&
1870             (first <= &tx_ring->tx_bi[i]) &&
1871             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1872                 tx_desc->cmd_type_offset_bsz =
1873                         build_ctob(td_cmd, td_offset, size, td_tag) |
1874                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1875                                          I40E_TXD_QW1_CMD_SHIFT);
1876         } else {
1877                 tx_desc->cmd_type_offset_bsz =
1878                         build_ctob(td_cmd, td_offset, size, td_tag) |
1879                         cpu_to_le64((u64)I40E_TXD_CMD <<
1880                                          I40E_TXD_QW1_CMD_SHIFT);
1881         }
1882
1883         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1884                                                  tx_ring->queue_index),
1885                              first->bytecount);
1886
1887         /* Force memory writes to complete before letting h/w
1888          * know there are new descriptors to fetch.  (Only
1889          * applicable for weak-ordered memory model archs,
1890          * such as IA-64).
1891          */
1892         wmb();
1893
1894         /* set next_to_watch value indicating a packet is present */
1895         first->next_to_watch = tx_desc;
1896
1897         i++;
1898         if (i == tx_ring->count)
1899                 i = 0;
1900
1901         tx_ring->next_to_use = i;
1902
1903         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1904         /* notify HW of packet */
1905         if (!skb->xmit_more ||
1906             netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1907                                                    tx_ring->queue_index)))
1908                 writel(i, tx_ring->tail);
1909         else
1910                 prefetchw(tx_desc + 1);
1911
1912         return;
1913
1914 dma_error:
1915         dev_info(tx_ring->dev, "TX DMA map failed\n");
1916
1917         /* clear dma mappings for failed tx_bi map */
1918         for (;;) {
1919                 tx_bi = &tx_ring->tx_bi[i];
1920                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1921                 if (tx_bi == first)
1922                         break;
1923                 if (i == 0)
1924                         i = tx_ring->count;
1925                 i--;
1926         }
1927
1928         tx_ring->next_to_use = i;
1929 }
1930
1931 /**
1932  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1933  * @skb:     send buffer
1934  * @tx_ring: ring to send buffer on
1935  *
1936  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1937  * there is not enough descriptors available in this ring since we need at least
1938  * one descriptor.
1939  **/
1940 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1941                                                struct i40e_ring *tx_ring)
1942 {
1943         unsigned int f;
1944         int count = 0;
1945
1946         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1947          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1948          *       + 4 desc gap to avoid the cache line where head is,
1949          *       + 1 desc for context descriptor,
1950          * otherwise try next time
1951          */
1952         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1953                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1954
1955         count += TXD_USE_COUNT(skb_headlen(skb));
1956         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1957                 tx_ring->tx_stats.tx_busy++;
1958                 return 0;
1959         }
1960         return count;
1961 }
1962
1963 /**
1964  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1965  * @skb:     send buffer
1966  * @tx_ring: ring to send buffer on
1967  *
1968  * Returns NETDEV_TX_OK if sent, else an error code
1969  **/
1970 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1971                                         struct i40e_ring *tx_ring)
1972 {
1973         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1974         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1975         struct i40e_tx_buffer *first;
1976         u32 td_offset = 0;
1977         u32 tx_flags = 0;
1978         __be16 protocol;
1979         u32 td_cmd = 0;
1980         u8 hdr_len = 0;
1981         int tso;
1982         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
1983                 return NETDEV_TX_BUSY;
1984
1985         /* prepare the xmit flags */
1986         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1987                 goto out_drop;
1988
1989         /* obtain protocol of skb */
1990         protocol = vlan_get_protocol(skb);
1991
1992         /* record the location of the first descriptor for this packet */
1993         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1994
1995         /* setup IPv4/IPv6 offloads */
1996         if (protocol == htons(ETH_P_IP))
1997                 tx_flags |= I40E_TX_FLAGS_IPV4;
1998         else if (protocol == htons(ETH_P_IPV6))
1999                 tx_flags |= I40E_TX_FLAGS_IPV6;
2000
2001         tso = i40e_tso(tx_ring, skb, &hdr_len,
2002                        &cd_type_cmd_tso_mss, &cd_tunneling);
2003
2004         if (tso < 0)
2005                 goto out_drop;
2006         else if (tso)
2007                 tx_flags |= I40E_TX_FLAGS_TSO;
2008
2009         if (i40e_chk_linearize(skb, tx_flags))
2010                 if (skb_linearize(skb))
2011                         goto out_drop;
2012
2013         skb_tx_timestamp(skb);
2014
2015         /* always enable CRC insertion offload */
2016         td_cmd |= I40E_TX_DESC_CMD_ICRC;
2017
2018         /* Always offload the checksum, since it's in the data descriptor */
2019         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2020                 tx_flags |= I40E_TX_FLAGS_CSUM;
2021
2022                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2023                                     tx_ring, &cd_tunneling);
2024         }
2025
2026         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2027                            cd_tunneling, cd_l2tag2);
2028
2029         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2030                       td_cmd, td_offset);
2031
2032         return NETDEV_TX_OK;
2033
2034 out_drop:
2035         dev_kfree_skb_any(skb);
2036         return NETDEV_TX_OK;
2037 }
2038
2039 /**
2040  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2041  * @skb:    send buffer
2042  * @netdev: network interface device structure
2043  *
2044  * Returns NETDEV_TX_OK if sent, else an error code
2045  **/
2046 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2047 {
2048         struct i40evf_adapter *adapter = netdev_priv(netdev);
2049         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
2050
2051         /* hardware can't handle really short frames, hardware padding works
2052          * beyond this point
2053          */
2054         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2055                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2056                         return NETDEV_TX_OK;
2057                 skb->len = I40E_MIN_TX_LEN;
2058                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2059         }
2060
2061         return i40e_xmit_frame_ring(skb, tx_ring);
2062 }