drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  55                         kfree(tx_buffer->raw_buf);
  56                 else
  57                         dev_kfree_skb_any(tx_buffer->skb);
  58
  59                 if (dma_unmap_len(tx_buffer, len))
  60                         dma_unmap_single(ring->dev,
  61                                          dma_unmap_addr(tx_buffer, dma),
  62                                          dma_unmap_len(tx_buffer, len),
  63                                          DMA_TO_DEVICE);
  64         } else if (dma_unmap_len(tx_buffer, len)) {
  65                 dma_unmap_page(ring->dev,
  66                                dma_unmap_addr(tx_buffer, dma),
  67                                dma_unmap_len(tx_buffer, len),
  68                                DMA_TO_DEVICE);
  69         }
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 #define WB_STRIDE 0x3
 144
 145 /**
 146  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 147  * @tx_ring:  tx ring to clean
 148  * @budget:   how many cleans we're allowed
 149  *
 150  * Returns true if there's any budget left (e.g. the clean is finished)
 151  **/
 152 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 153 {
 154         u16 i = tx_ring->next_to_clean;
 155         struct i40e_tx_buffer *tx_buf;
 156         struct i40e_tx_desc *tx_head;
 157         struct i40e_tx_desc *tx_desc;
 158         unsigned int total_packets = 0;
 159         unsigned int total_bytes = 0;
 160
 161         tx_buf = &tx_ring->tx_bi[i];
 162         tx_desc = I40E_TX_DESC(tx_ring, i);
 163         i -= tx_ring->count;
 164
 165         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 166
 167         do {
 168                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 169
 170                 /* if next_to_watch is not set then there is no work pending */
 171                 if (!eop_desc)
 172                         break;
 173
 174                 /* prevent any other reads prior to eop_desc */
 175                 read_barrier_depends();
 176
 177                 /* we have caught up to head, no work left to do */
 178                 if (tx_head == tx_desc)
 179                         break;
 180
 181                 /* clear next_to_watch to prevent false hangs */
 182                 tx_buf->next_to_watch = NULL;
 183
 184                 /* update the statistics for this packet */
 185                 total_bytes += tx_buf->bytecount;
 186                 total_packets += tx_buf->gso_segs;
 187
 188                 /* free the skb */
 189                 dev_kfree_skb_any(tx_buf->skb);
 190
 191                 /* unmap skb header data */
 192                 dma_unmap_single(tx_ring->dev,
 193                                  dma_unmap_addr(tx_buf, dma),
 194                                  dma_unmap_len(tx_buf, len),
 195                                  DMA_TO_DEVICE);
 196
 197                 /* clear tx_buffer data */
 198                 tx_buf->skb = NULL;
 199                 dma_unmap_len_set(tx_buf, len, 0);
 200
 201                 /* unmap remaining buffers */
 202                 while (tx_desc != eop_desc) {
 203
 204                         tx_buf++;
 205                         tx_desc++;
 206                         i++;
 207                         if (unlikely(!i)) {
 208                                 i -= tx_ring->count;
 209                                 tx_buf = tx_ring->tx_bi;
 210                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 211                         }
 212
 213                         /* unmap any remaining paged data */
 214                         if (dma_unmap_len(tx_buf, len)) {
 215                                 dma_unmap_page(tx_ring->dev,
 216                                                dma_unmap_addr(tx_buf, dma),
 217                                                dma_unmap_len(tx_buf, len),
 218                                                DMA_TO_DEVICE);
 219                                 dma_unmap_len_set(tx_buf, len, 0);
 220                         }
 221                 }
 222
 223                 /* move us one more past the eop_desc for start of next pkt */
 224                 tx_buf++;
 225                 tx_desc++;
 226                 i++;
 227                 if (unlikely(!i)) {
 228                         i -= tx_ring->count;
 229                         tx_buf = tx_ring->tx_bi;
 230                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 231                 }
 232
 233                 prefetch(tx_desc);
 234
 235                 /* update budget accounting */
 236                 budget--;
 237         } while (likely(budget));
 238
 239         i += tx_ring->count;
 240         tx_ring->next_to_clean = i;
 241         u64_stats_update_begin(&tx_ring->syncp);
 242         tx_ring->stats.bytes += total_bytes;
 243         tx_ring->stats.packets += total_packets;
 244         u64_stats_update_end(&tx_ring->syncp);
 245         tx_ring->q_vector->tx.total_bytes += total_bytes;
 246         tx_ring->q_vector->tx.total_packets += total_packets;
 247
 248         /* check to see if there are any non-cache aligned descriptors
 249          * waiting to be written back, and kick the hardware to force
 250          * them to be written back in case of napi polling
 251          */
 252         if (budget &&
 253             !((i & WB_STRIDE) == WB_STRIDE) &&
 254             !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 255             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 256                 tx_ring->arm_wb = true;
 257         else
 258                 tx_ring->arm_wb = false;
 259
 260         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 261                                                       tx_ring->queue_index),
 262                                   total_packets, total_bytes);
 263
 264 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 265         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 266                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 267                 /* Make sure that anybody stopping the queue after this
 268                  * sees the new next_to_clean.
 269                  */
 270                 smp_mb();
 271                 if (__netif_subqueue_stopped(tx_ring->netdev,
 272                                              tx_ring->queue_index) &&
 273                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 274                         netif_wake_subqueue(tx_ring->netdev,
 275                                             tx_ring->queue_index);
 276                         ++tx_ring->tx_stats.restart_queue;
 277                 }
 278         }
 279
 280         return !!budget;
 281 }
 282
 283 /**
 284  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 285  * @vsi: the VSI we care about
 286  * @q_vector: the vector  on which to force writeback
 287  *
 288  **/
 289 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 290 {
 291         u16 flags = q_vector->tx.ring[0].flags;
 292
 293         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 294                 u32 val;
 295
 296                 if (q_vector->arm_wb_state)
 297                         return;
 298
 299                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
 300
 301                 wr32(&vsi->back->hw,
 302                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 303                                           vsi->base_vector - 1),
 304                      val);
 305                 q_vector->arm_wb_state = true;
 306         } else {
 307                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 308                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 309                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 310                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 311                           /* allow 00 to be written to the index */
 312
 313                 wr32(&vsi->back->hw,
 314                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 315                                           vsi->base_vector - 1), val);
 316         }
 317 }
 318
 319 /**
 320  * i40e_set_new_dynamic_itr - Find new ITR level
 321  * @rc: structure containing ring performance data
 322  *
 323  * Stores a new ITR value based on packets and byte counts during
 324  * the last interrupt.  The advantage of per interrupt computation
 325  * is faster updates and more accurate ITR for the current traffic
 326  * pattern.  Constants in this function were computed based on
 327  * theoretical maximum wire speed and thresholds were set based on
 328  * testing data as well as attempting to minimize response time
 329  * while increasing bulk throughput.
 330  **/
 331 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 332 {
 333         enum i40e_latency_range new_latency_range = rc->latency_range;
 334         u32 new_itr = rc->itr;
 335         int bytes_per_int;
 336
 337         if (rc->total_packets == 0 || !rc->itr)
 338                 return;
 339
 340         /* simple throttlerate management
 341          *   0-10MB/s   lowest (100000 ints/s)
 342          *  10-20MB/s   low    (20000 ints/s)
 343          *  20-1249MB/s bulk   (8000 ints/s)
 344          */
 345         bytes_per_int = rc->total_bytes / rc->itr;
 346         switch (new_latency_range) {
 347         case I40E_LOWEST_LATENCY:
 348                 if (bytes_per_int > 10)
 349                         new_latency_range = I40E_LOW_LATENCY;
 350                 break;
 351         case I40E_LOW_LATENCY:
 352                 if (bytes_per_int > 20)
 353                         new_latency_range = I40E_BULK_LATENCY;
 354                 else if (bytes_per_int <= 10)
 355                         new_latency_range = I40E_LOWEST_LATENCY;
 356                 break;
 357         case I40E_BULK_LATENCY:
 358                 if (bytes_per_int <= 20)
 359                         new_latency_range = I40E_LOW_LATENCY;
 360                 break;
 361         default:
 362                 if (bytes_per_int <= 20)
 363                         new_latency_range = I40E_LOW_LATENCY;
 364                 break;
 365         }
 366         rc->latency_range = new_latency_range;
 367
 368         switch (new_latency_range) {
 369         case I40E_LOWEST_LATENCY:
 370                 new_itr = I40E_ITR_100K;
 371                 break;
 372         case I40E_LOW_LATENCY:
 373                 new_itr = I40E_ITR_20K;
 374                 break;
 375         case I40E_BULK_LATENCY:
 376                 new_itr = I40E_ITR_8K;
 377                 break;
 378         default:
 379                 break;
 380         }
 381
 382         if (new_itr != rc->itr)
 383                 rc->itr = new_itr;
 384
 385         rc->total_bytes = 0;
 386         rc->total_packets = 0;
 387 }
 388
 389 /*
 390  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 391  * @tx_ring: the tx ring to set up
 392  *
 393  * Return 0 on success, negative on error
 394  **/
 395 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 396 {
 397         struct device *dev = tx_ring->dev;
 398         int bi_size;
 399
 400         if (!dev)
 401                 return -ENOMEM;
 402
 403         /* warn if we are about to overwrite the pointer */
 404         WARN_ON(tx_ring->tx_bi);
 405         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 406         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 407         if (!tx_ring->tx_bi)
 408                 goto err;
 409
 410         /* round up to nearest 4K */
 411         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 412         /* add u32 for head writeback, align after this takes care of
 413          * guaranteeing this is at least one cache line in size
 414          */
 415         tx_ring->size += sizeof(u32);
 416         tx_ring->size = ALIGN(tx_ring->size, 4096);
 417         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 418                                            &tx_ring->dma, GFP_KERNEL);
 419         if (!tx_ring->desc) {
 420                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 421                          tx_ring->size);
 422                 goto err;
 423         }
 424
 425         tx_ring->next_to_use = 0;
 426         tx_ring->next_to_clean = 0;
 427         return 0;
 428
 429 err:
 430         kfree(tx_ring->tx_bi);
 431         tx_ring->tx_bi = NULL;
 432         return -ENOMEM;
 433 }
 434
 435 /**
 436  * i40evf_clean_rx_ring - Free Rx buffers
 437  * @rx_ring: ring to be cleaned
 438  **/
 439 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 440 {
 441         struct device *dev = rx_ring->dev;
 442         struct i40e_rx_buffer *rx_bi;
 443         unsigned long bi_size;
 444         u16 i;
 445
 446         /* ring already cleared, nothing to do */
 447         if (!rx_ring->rx_bi)
 448                 return;
 449
 450         if (ring_is_ps_enabled(rx_ring)) {
 451                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 452
 453                 rx_bi = &rx_ring->rx_bi[0];
 454                 if (rx_bi->hdr_buf) {
 455                         dma_free_coherent(dev,
 456                                           bufsz,
 457                                           rx_bi->hdr_buf,
 458                                           rx_bi->dma);
 459                         for (i = 0; i < rx_ring->count; i++) {
 460                                 rx_bi = &rx_ring->rx_bi[i];
 461                                 rx_bi->dma = 0;
 462                                 rx_bi->hdr_buf = NULL;
 463                         }
 464                 }
 465         }
 466         /* Free all the Rx ring sk_buffs */
 467         for (i = 0; i < rx_ring->count; i++) {
 468                 rx_bi = &rx_ring->rx_bi[i];
 469                 if (rx_bi->dma) {
 470                         dma_unmap_single(dev,
 471                                          rx_bi->dma,
 472                                          rx_ring->rx_buf_len,
 473                                          DMA_FROM_DEVICE);
 474                         rx_bi->dma = 0;
 475                 }
 476                 if (rx_bi->skb) {
 477                         dev_kfree_skb(rx_bi->skb);
 478                         rx_bi->skb = NULL;
 479                 }
 480                 if (rx_bi->page) {
 481                         if (rx_bi->page_dma) {
 482                                 dma_unmap_page(dev,
 483                                                rx_bi->page_dma,
 484                                                PAGE_SIZE / 2,
 485                                                DMA_FROM_DEVICE);
 486                                 rx_bi->page_dma = 0;
 487                         }
 488                         __free_page(rx_bi->page);
 489                         rx_bi->page = NULL;
 490                         rx_bi->page_offset = 0;
 491                 }
 492         }
 493
 494         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 495         memset(rx_ring->rx_bi, 0, bi_size);
 496
 497         /* Zero out the descriptor ring */
 498         memset(rx_ring->desc, 0, rx_ring->size);
 499
 500         rx_ring->next_to_clean = 0;
 501         rx_ring->next_to_use = 0;
 502 }
 503
 504 /**
 505  * i40evf_free_rx_resources - Free Rx resources
 506  * @rx_ring: ring to clean the resources from
 507  *
 508  * Free all receive software resources
 509  **/
 510 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 511 {
 512         i40evf_clean_rx_ring(rx_ring);
 513         kfree(rx_ring->rx_bi);
 514         rx_ring->rx_bi = NULL;
 515
 516         if (rx_ring->desc) {
 517                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 518                                   rx_ring->desc, rx_ring->dma);
 519                 rx_ring->desc = NULL;
 520         }
 521 }
 522
 523 /**
 524  * i40evf_alloc_rx_headers - allocate rx header buffers
 525  * @rx_ring: ring to alloc buffers
 526  *
 527  * Allocate rx header buffers for the entire ring. As these are static,
 528  * this is only called when setting up a new ring.
 529  **/
 530 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 531 {
 532         struct device *dev = rx_ring->dev;
 533         struct i40e_rx_buffer *rx_bi;
 534         dma_addr_t dma;
 535         void *buffer;
 536         int buf_size;
 537         int i;
 538
 539         if (rx_ring->rx_bi[0].hdr_buf)
 540                 return;
 541         /* Make sure the buffers don't cross cache line boundaries. */
 542         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 543         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 544                                     &dma, GFP_KERNEL);
 545         if (!buffer)
 546                 return;
 547         for (i = 0; i < rx_ring->count; i++) {
 548                 rx_bi = &rx_ring->rx_bi[i];
 549                 rx_bi->dma = dma + (i * buf_size);
 550                 rx_bi->hdr_buf = buffer + (i * buf_size);
 551         }
 552 }
 553
 554 /**
 555  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 556  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 557  *
 558  * Returns 0 on success, negative on failure
 559  **/
 560 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 561 {
 562         struct device *dev = rx_ring->dev;
 563         int bi_size;
 564
 565         /* warn if we are about to overwrite the pointer */
 566         WARN_ON(rx_ring->rx_bi);
 567         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 568         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 569         if (!rx_ring->rx_bi)
 570                 goto err;
 571
 572         u64_stats_init(&rx_ring->syncp);
 573
 574         /* Round up to nearest 4K */
 575         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 576                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 577                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 578         rx_ring->size = ALIGN(rx_ring->size, 4096);
 579         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 580                                            &rx_ring->dma, GFP_KERNEL);
 581
 582         if (!rx_ring->desc) {
 583                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 584                          rx_ring->size);
 585                 goto err;
 586         }
 587
 588         rx_ring->next_to_clean = 0;
 589         rx_ring->next_to_use = 0;
 590
 591         return 0;
 592 err:
 593         kfree(rx_ring->rx_bi);
 594         rx_ring->rx_bi = NULL;
 595         return -ENOMEM;
 596 }
 597
 598 /**
 599  * i40e_release_rx_desc - Store the new tail and head values
 600  * @rx_ring: ring to bump
 601  * @val: new head index
 602  **/
 603 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 604 {
 605         rx_ring->next_to_use = val;
 606         /* Force memory writes to complete before letting h/w
 607          * know there are new descriptors to fetch.  (Only
 608          * applicable for weak-ordered memory model archs,
 609          * such as IA-64).
 610          */
 611         wmb();
 612         writel(val, rx_ring->tail);
 613 }
 614
 615 /**
 616  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 617  * @rx_ring: ring to place buffers on
 618  * @cleaned_count: number of buffers to replace
 619  **/
 620 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 621 {
 622         u16 i = rx_ring->next_to_use;
 623         union i40e_rx_desc *rx_desc;
 624         struct i40e_rx_buffer *bi;
 625
 626         /* do nothing if no valid netdev defined */
 627         if (!rx_ring->netdev || !cleaned_count)
 628                 return;
 629
 630         while (cleaned_count--) {
 631                 rx_desc = I40E_RX_DESC(rx_ring, i);
 632                 bi = &rx_ring->rx_bi[i];
 633
 634                 if (bi->skb) /* desc is in use */
 635                         goto no_buffers;
 636                 if (!bi->page) {
 637                         bi->page = alloc_page(GFP_ATOMIC);
 638                         if (!bi->page) {
 639                                 rx_ring->rx_stats.alloc_page_failed++;
 640                                 goto no_buffers;
 641                         }
 642                 }
 643
 644                 if (!bi->page_dma) {
 645                         /* use a half page if we're re-using */
 646                         bi->page_offset ^= PAGE_SIZE / 2;
 647                         bi->page_dma = dma_map_page(rx_ring->dev,
 648                                                     bi->page,
 649                                                     bi->page_offset,
 650                                                     PAGE_SIZE / 2,
 651                                                     DMA_FROM_DEVICE);
 652                         if (dma_mapping_error(rx_ring->dev,
 653                                               bi->page_dma)) {
 654                                 rx_ring->rx_stats.alloc_page_failed++;
 655                                 bi->page_dma = 0;
 656                                 goto no_buffers;
 657                         }
 658                 }
 659
 660                 dma_sync_single_range_for_device(rx_ring->dev,
 661                                                  bi->dma,
 662                                                  0,
 663                                                  rx_ring->rx_hdr_len,
 664                                                  DMA_FROM_DEVICE);
 665                 /* Refresh the desc even if buffer_addrs didn't change
 666                  * because each write-back erases this info.
 667                  */
 668                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 669                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 670                 i++;
 671                 if (i == rx_ring->count)
 672                         i = 0;
 673         }
 674
 675 no_buffers:
 676         if (rx_ring->next_to_use != i)
 677                 i40e_release_rx_desc(rx_ring, i);
 678 }
 679
 680 /**
 681  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 682  * @rx_ring: ring to place buffers on
 683  * @cleaned_count: number of buffers to replace
 684  **/
 685 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 686 {
 687         u16 i = rx_ring->next_to_use;
 688         union i40e_rx_desc *rx_desc;
 689         struct i40e_rx_buffer *bi;
 690         struct sk_buff *skb;
 691
 692         /* do nothing if no valid netdev defined */
 693         if (!rx_ring->netdev || !cleaned_count)
 694                 return;
 695
 696         while (cleaned_count--) {
 697                 rx_desc = I40E_RX_DESC(rx_ring, i);
 698                 bi = &rx_ring->rx_bi[i];
 699                 skb = bi->skb;
 700
 701                 if (!skb) {
 702                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 703                                                         rx_ring->rx_buf_len);
 704                         if (!skb) {
 705                                 rx_ring->rx_stats.alloc_buff_failed++;
 706                                 goto no_buffers;
 707                         }
 708                         /* initialize queue mapping */
 709                         skb_record_rx_queue(skb, rx_ring->queue_index);
 710                         bi->skb = skb;
 711                 }
 712
 713                 if (!bi->dma) {
 714                         bi->dma = dma_map_single(rx_ring->dev,
 715                                                  skb->data,
 716                                                  rx_ring->rx_buf_len,
 717                                                  DMA_FROM_DEVICE);
 718                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 719                                 rx_ring->rx_stats.alloc_buff_failed++;
 720                                 bi->dma = 0;
 721                                 goto no_buffers;
 722                         }
 723                 }
 724
 725                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 726                 rx_desc->read.hdr_addr = 0;
 727                 i++;
 728                 if (i == rx_ring->count)
 729                         i = 0;
 730         }
 731
 732 no_buffers:
 733         if (rx_ring->next_to_use != i)
 734                 i40e_release_rx_desc(rx_ring, i);
 735 }
 736
 737 /**
 738  * i40e_receive_skb - Send a completed packet up the stack
 739  * @rx_ring:  rx ring in play
 740  * @skb: packet to send up
 741  * @vlan_tag: vlan tag for packet
 742  **/
 743 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 744                              struct sk_buff *skb, u16 vlan_tag)
 745 {
 746         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 747         struct i40e_vsi *vsi = rx_ring->vsi;
 748         u64 flags = vsi->back->flags;
 749
 750         if (vlan_tag & VLAN_VID_MASK)
 751                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 752
 753         if (flags & I40E_FLAG_IN_NETPOLL)
 754                 netif_rx(skb);
 755         else
 756                 napi_gro_receive(&q_vector->napi, skb);
 757 }
 758
 759 /**
 760  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 761  * @vsi: the VSI we care about
 762  * @skb: skb currently being received and modified
 763  * @rx_status: status value of last descriptor in packet
 764  * @rx_error: error value of last descriptor in packet
 765  * @rx_ptype: ptype value of last descriptor in packet
 766  **/
 767 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 768                                     struct sk_buff *skb,
 769                                     u32 rx_status,
 770                                     u32 rx_error,
 771                                     u16 rx_ptype)
 772 {
 773         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 774         bool ipv4 = false, ipv6 = false;
 775         bool ipv4_tunnel, ipv6_tunnel;
 776         __wsum rx_udp_csum;
 777         struct iphdr *iph;
 778         __sum16 csum;
 779
 780         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 781                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 782         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 783                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 784
 785         skb->ip_summed = CHECKSUM_NONE;
 786
 787         /* Rx csum enabled and ip headers found? */
 788         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 789                 return;
 790
 791         /* did the hardware decode the packet and checksum? */
 792         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 793                 return;
 794
 795         /* both known and outer_ip must be set for the below code to work */
 796         if (!(decoded.known && decoded.outer_ip))
 797                 return;
 798
 799         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 800             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 801                 ipv4 = true;
 802         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 803                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 804                 ipv6 = true;
 805
 806         if (ipv4 &&
 807             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 808                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 809                 goto checksum_fail;
 810
 811         /* likely incorrect csum if alternate IP extension headers found */
 812         if (ipv6 &&
 813             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 814                 /* don't increment checksum err here, non-fatal err */
 815                 return;
 816
 817         /* there was some L4 error, count error and punt packet to the stack */
 818         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 819                 goto checksum_fail;
 820
 821         /* handle packets that were not able to be checksummed due
 822          * to arrival speed, in this case the stack can compute
 823          * the csum.
 824          */
 825         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 826                 return;
 827
 828         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 829          * it in the driver, hardware does not do it for us.
 830          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 831          * so the total length of IPv4 header is IHL*4 bytes
 832          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 833          */
 834         if (ipv4_tunnel) {
 835                 skb->transport_header = skb->mac_header +
 836                                         sizeof(struct ethhdr) +
 837                                         (ip_hdr(skb)->ihl * 4);
 838
 839                 /* Add 4 bytes for VLAN tagged packets */
 840                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 841                                           skb->protocol == htons(ETH_P_8021AD))
 842                                           ? VLAN_HLEN : 0;
 843
 844                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 845                     (udp_hdr(skb)->check != 0)) {
 846                         rx_udp_csum = udp_csum(skb);
 847                         iph = ip_hdr(skb);
 848                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 849                                                  (skb->len -
 850                                                   skb_transport_offset(skb)),
 851                                                  IPPROTO_UDP, rx_udp_csum);
 852
 853                         if (udp_hdr(skb)->check != csum)
 854                                 goto checksum_fail;
 855
 856                 } /* else its GRE and so no outer UDP header */
 857         }
 858
 859         skb->ip_summed = CHECKSUM_UNNECESSARY;
 860         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 861
 862         return;
 863
 864 checksum_fail:
 865         vsi->back->hw_csum_rx_error++;
 866 }
 867
 868 /**
 869  * i40e_rx_hash - returns the hash value from the Rx descriptor
 870  * @ring: descriptor ring
 871  * @rx_desc: specific descriptor
 872  **/
 873 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 874                                union i40e_rx_desc *rx_desc)
 875 {
 876         const __le64 rss_mask =
 877                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 878                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 879
 880         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 881             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 882                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 883         else
 884                 return 0;
 885 }
 886
 887 /**
 888  * i40e_ptype_to_hash - get a hash type
 889  * @ptype: the ptype value from the descriptor
 890  *
 891  * Returns a hash type to be used by skb_set_hash
 892  **/
 893 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 894 {
 895         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 896
 897         if (!decoded.known)
 898                 return PKT_HASH_TYPE_NONE;
 899
 900         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 901             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 902                 return PKT_HASH_TYPE_L4;
 903         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 904                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 905                 return PKT_HASH_TYPE_L3;
 906         else
 907                 return PKT_HASH_TYPE_L2;
 908 }
 909
 910 /**
 911  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 912  * @rx_ring:  rx ring to clean
 913  * @budget:   how many cleans we're allowed
 914  *
 915  * Returns true if there's any budget left (e.g. the clean is finished)
 916  **/
 917 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 918 {
 919         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 920         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 921         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 922         const int current_node = numa_node_id();
 923         struct i40e_vsi *vsi = rx_ring->vsi;
 924         u16 i = rx_ring->next_to_clean;
 925         union i40e_rx_desc *rx_desc;
 926         u32 rx_error, rx_status;
 927         u8 rx_ptype;
 928         u64 qword;
 929
 930         do {
 931                 struct i40e_rx_buffer *rx_bi;
 932                 struct sk_buff *skb;
 933                 u16 vlan_tag;
 934                 /* return some buffers to hardware, one at a time is too slow */
 935                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 936                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
 937                         cleaned_count = 0;
 938                 }
 939
 940                 i = rx_ring->next_to_clean;
 941                 rx_desc = I40E_RX_DESC(rx_ring, i);
 942                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 943                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 944                         I40E_RXD_QW1_STATUS_SHIFT;
 945
 946                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
 947                         break;
 948
 949                 /* This memory barrier is needed to keep us from reading
 950                  * any other fields out of the rx_desc until we know the
 951                  * DD bit is set.
 952                  */
 953                 dma_rmb();
 954                 rx_bi = &rx_ring->rx_bi[i];
 955                 skb = rx_bi->skb;
 956                 if (likely(!skb)) {
 957                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 958                                                         rx_ring->rx_hdr_len);
 959                         if (!skb) {
 960                                 rx_ring->rx_stats.alloc_buff_failed++;
 961                                 break;
 962                         }
 963
 964                         /* initialize queue mapping */
 965                         skb_record_rx_queue(skb, rx_ring->queue_index);
 966                         /* we are reusing so sync this buffer for CPU use */
 967                         dma_sync_single_range_for_cpu(rx_ring->dev,
 968                                                       rx_bi->dma,
 969                                                       0,
 970                                                       rx_ring->rx_hdr_len,
 971                                                       DMA_FROM_DEVICE);
 972                 }
 973                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 974                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 975                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 976                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 977                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 978                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 979
 980                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 981                            I40E_RXD_QW1_ERROR_SHIFT;
 982                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 983                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 984
 985                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
 986                            I40E_RXD_QW1_PTYPE_SHIFT;
 987                 prefetch(rx_bi->page);
 988                 rx_bi->skb = NULL;
 989                 cleaned_count++;
 990                 if (rx_hbo || rx_sph) {
 991                         int len;
 992                         if (rx_hbo)
 993                                 len = I40E_RX_HDR_SIZE;
 994                         else
 995                                 len = rx_header_len;
 996                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
 997                 } else if (skb->len == 0) {
 998                         int len;
 999
1000                         len = (rx_packet_len > skb_headlen(skb) ?
1001                                 skb_headlen(skb) : rx_packet_len);
1002                         memcpy(__skb_put(skb, len),
1003                                rx_bi->page + rx_bi->page_offset,
1004                                len);
1005                         rx_bi->page_offset += len;
1006                         rx_packet_len -= len;
1007                 }
1008
1009                 /* Get the rest of the data if this was a header split */
1010                 if (rx_packet_len) {
1011                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1012                                            rx_bi->page,
1013                                            rx_bi->page_offset,
1014                                            rx_packet_len);
1015
1016                         skb->len += rx_packet_len;
1017                         skb->data_len += rx_packet_len;
1018                         skb->truesize += rx_packet_len;
1019
1020                         if ((page_count(rx_bi->page) == 1) &&
1021                             (page_to_nid(rx_bi->page) == current_node))
1022                                 get_page(rx_bi->page);
1023                         else
1024                                 rx_bi->page = NULL;
1025
1026                         dma_unmap_page(rx_ring->dev,
1027                                        rx_bi->page_dma,
1028                                        PAGE_SIZE / 2,
1029                                        DMA_FROM_DEVICE);
1030                         rx_bi->page_dma = 0;
1031                 }
1032                 I40E_RX_INCREMENT(rx_ring, i);
1033
1034                 if (unlikely(
1035                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1036                         struct i40e_rx_buffer *next_buffer;
1037
1038                         next_buffer = &rx_ring->rx_bi[i];
1039                         next_buffer->skb = skb;
1040                         rx_ring->rx_stats.non_eop_descs++;
1041                         continue;
1042                 }
1043
1044                 /* ERR_MASK will only have valid bits if EOP set */
1045                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1046                         dev_kfree_skb_any(skb);
1047                         continue;
1048                 }
1049
1050                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1051                              i40e_ptype_to_hash(rx_ptype));
1052                 /* probably a little skewed due to removing CRC */
1053                 total_rx_bytes += skb->len;
1054                 total_rx_packets++;
1055
1056                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1057
1058                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1059
1060                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1061                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1062                          : 0;
1063 #ifdef I40E_FCOE
1064                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1065                         dev_kfree_skb_any(skb);
1066                         continue;
1067                 }
1068 #endif
1069                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1070                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1071
1072                 rx_desc->wb.qword1.status_error_len = 0;
1073
1074         } while (likely(total_rx_packets < budget));
1075
1076         u64_stats_update_begin(&rx_ring->syncp);
1077         rx_ring->stats.packets += total_rx_packets;
1078         rx_ring->stats.bytes += total_rx_bytes;
1079         u64_stats_update_end(&rx_ring->syncp);
1080         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1081         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1082
1083         return total_rx_packets;
1084 }
1085
1086 /**
1087  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1088  * @rx_ring:  rx ring to clean
1089  * @budget:   how many cleans we're allowed
1090  *
1091  * Returns number of packets cleaned
1092  **/
1093 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1094 {
1095         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1096         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1097         struct i40e_vsi *vsi = rx_ring->vsi;
1098         union i40e_rx_desc *rx_desc;
1099         u32 rx_error, rx_status;
1100         u16 rx_packet_len;
1101         u8 rx_ptype;
1102         u64 qword;
1103         u16 i;
1104
1105         do {
1106                 struct i40e_rx_buffer *rx_bi;
1107                 struct sk_buff *skb;
1108                 u16 vlan_tag;
1109                 /* return some buffers to hardware, one at a time is too slow */
1110                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1111                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1112                         cleaned_count = 0;
1113                 }
1114
1115                 i = rx_ring->next_to_clean;
1116                 rx_desc = I40E_RX_DESC(rx_ring, i);
1117                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1118                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1119                         I40E_RXD_QW1_STATUS_SHIFT;
1120
1121                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1122                         break;
1123
1124                 /* This memory barrier is needed to keep us from reading
1125                  * any other fields out of the rx_desc until we know the
1126                  * DD bit is set.
1127                  */
1128                 dma_rmb();
1129
1130                 rx_bi = &rx_ring->rx_bi[i];
1131                 skb = rx_bi->skb;
1132                 prefetch(skb->data);
1133
1134                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1135                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1136
1137                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1138                            I40E_RXD_QW1_ERROR_SHIFT;
1139                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1140
1141                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1142                            I40E_RXD_QW1_PTYPE_SHIFT;
1143                 rx_bi->skb = NULL;
1144                 cleaned_count++;
1145
1146                 /* Get the header and possibly the whole packet
1147                  * If this is an skb from previous receive dma will be 0
1148                  */
1149                 skb_put(skb, rx_packet_len);
1150                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1151                                  DMA_FROM_DEVICE);
1152                 rx_bi->dma = 0;
1153
1154                 I40E_RX_INCREMENT(rx_ring, i);
1155
1156                 if (unlikely(
1157                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1158                         rx_ring->rx_stats.non_eop_descs++;
1159                         continue;
1160                 }
1161
1162                 /* ERR_MASK will only have valid bits if EOP set */
1163                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1164                         dev_kfree_skb_any(skb);
1165                         /* TODO: shouldn't we increment a counter indicating the
1166                          * drop?
1167                          */
1168                         continue;
1169                 }
1170
1171                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1172                              i40e_ptype_to_hash(rx_ptype));
1173                 /* probably a little skewed due to removing CRC */
1174                 total_rx_bytes += skb->len;
1175                 total_rx_packets++;
1176
1177                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1178
1179                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1180
1181                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1182                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1183                          : 0;
1184                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1185
1186                 rx_desc->wb.qword1.status_error_len = 0;
1187         } while (likely(total_rx_packets < budget));
1188
1189         u64_stats_update_begin(&rx_ring->syncp);
1190         rx_ring->stats.packets += total_rx_packets;
1191         rx_ring->stats.bytes += total_rx_bytes;
1192         u64_stats_update_end(&rx_ring->syncp);
1193         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1194         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1195
1196         return total_rx_packets;
1197 }
1198
1199 /**
1200  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1201  * @vsi: the VSI we care about
1202  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1203  *
1204  **/
1205 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1206                                           struct i40e_q_vector *q_vector)
1207 {
1208         struct i40e_hw *hw = &vsi->back->hw;
1209         u16 old_itr;
1210         int vector;
1211         u32 val;
1212
1213         vector = (q_vector->v_idx + vsi->base_vector);
1214         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1215                 old_itr = q_vector->rx.itr;
1216                 i40e_set_new_dynamic_itr(&q_vector->rx);
1217                 if (old_itr != q_vector->rx.itr) {
1218                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1219                         I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1220                         (I40E_RX_ITR <<
1221                                 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1222                         (q_vector->rx.itr <<
1223                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1224                 } else {
1225                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1226                         I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1227                         (I40E_ITR_NONE <<
1228                                 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
1229                 }
1230                 if (!test_bit(__I40E_DOWN, &vsi->state))
1231                         wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1232         } else {
1233                 i40evf_irq_enable_queues(vsi->back, 1
1234                         << q_vector->v_idx);
1235         }
1236         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1237                 old_itr = q_vector->tx.itr;
1238                 i40e_set_new_dynamic_itr(&q_vector->tx);
1239                 if (old_itr != q_vector->tx.itr) {
1240                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1241                                 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1242                                 (I40E_TX_ITR <<
1243                                    I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1244                                 (q_vector->tx.itr <<
1245                                    I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1246
1247                 } else {
1248                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1249                                 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1250                                 (I40E_ITR_NONE <<
1251                                    I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
1252                 }
1253                 if (!test_bit(__I40E_DOWN, &vsi->state))
1254                         wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1255         } else {
1256                 i40evf_irq_enable_queues(vsi->back, BIT(q_vector->v_idx));
1257         }
1258 }
1259
1260 /**
1261  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1262  * @napi: napi struct with our devices info in it
1263  * @budget: amount of work driver is allowed to do this pass, in packets
1264  *
1265  * This function will clean all queues associated with a q_vector.
1266  *
1267  * Returns the amount of work done
1268  **/
1269 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1270 {
1271         struct i40e_q_vector *q_vector =
1272                                container_of(napi, struct i40e_q_vector, napi);
1273         struct i40e_vsi *vsi = q_vector->vsi;
1274         struct i40e_ring *ring;
1275         bool clean_complete = true;
1276         bool arm_wb = false;
1277         int budget_per_ring;
1278         int cleaned;
1279
1280         if (test_bit(__I40E_DOWN, &vsi->state)) {
1281                 napi_complete(napi);
1282                 return 0;
1283         }
1284
1285         /* Since the actual Tx work is minimal, we can give the Tx a larger
1286          * budget and be more aggressive about cleaning up the Tx descriptors.
1287          */
1288         i40e_for_each_ring(ring, q_vector->tx) {
1289                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1290                 arm_wb |= ring->arm_wb;
1291         }
1292
1293         /* We attempt to distribute budget to each Rx queue fairly, but don't
1294          * allow the budget to go below 1 because that would exit polling early.
1295          */
1296         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1297
1298         i40e_for_each_ring(ring, q_vector->rx) {
1299                 if (ring_is_ps_enabled(ring))
1300                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1301                 else
1302                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1303                 /* if we didn't clean as many as budgeted, we must be done */
1304                 clean_complete &= (budget_per_ring != cleaned);
1305         }
1306
1307         /* If work not completed, return budget and polling will return */
1308         if (!clean_complete) {
1309                 if (arm_wb)
1310                         i40evf_force_wb(vsi, q_vector);
1311                 return budget;
1312         }
1313
1314         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1315                 q_vector->arm_wb_state = false;
1316
1317         /* Work is done so exit the polling mode and re-enable the interrupt */
1318         napi_complete(napi);
1319         i40e_update_enable_itr(vsi, q_vector);
1320         return 0;
1321 }
1322
1323 /**
1324  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1325  * @skb:     send buffer
1326  * @tx_ring: ring to send buffer on
1327  * @flags:   the tx flags to be set
1328  *
1329  * Checks the skb and set up correspondingly several generic transmit flags
1330  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1331  *
1332  * Returns error code indicate the frame should be dropped upon error and the
1333  * otherwise  returns 0 to indicate the flags has been set properly.
1334  **/
1335 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1336                                                struct i40e_ring *tx_ring,
1337                                                u32 *flags)
1338 {
1339         __be16 protocol = skb->protocol;
1340         u32  tx_flags = 0;
1341
1342         if (protocol == htons(ETH_P_8021Q) &&
1343             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1344                 /* When HW VLAN acceleration is turned off by the user the
1345                  * stack sets the protocol to 8021q so that the driver
1346                  * can take any steps required to support the SW only
1347                  * VLAN handling.  In our case the driver doesn't need
1348                  * to take any further steps so just set the protocol
1349                  * to the encapsulated ethertype.
1350                  */
1351                 skb->protocol = vlan_get_protocol(skb);
1352                 goto out;
1353         }
1354
1355         /* if we have a HW VLAN tag being added, default to the HW one */
1356         if (skb_vlan_tag_present(skb)) {
1357                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1358                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1359         /* else if it is a SW VLAN, check the next protocol and store the tag */
1360         } else if (protocol == htons(ETH_P_8021Q)) {
1361                 struct vlan_hdr *vhdr, _vhdr;
1362                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1363                 if (!vhdr)
1364                         return -EINVAL;
1365
1366                 protocol = vhdr->h_vlan_encapsulated_proto;
1367                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1368                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1369         }
1370
1371 out:
1372         *flags = tx_flags;
1373         return 0;
1374 }
1375
1376 /**
1377  * i40e_tso - set up the tso context descriptor
1378  * @tx_ring:  ptr to the ring to send
1379  * @skb:      ptr to the skb we're sending
1380  * @hdr_len:  ptr to the size of the packet header
1381  * @cd_tunneling: ptr to context descriptor bits
1382  *
1383  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1384  **/
1385 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1386                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1387                     u32 *cd_tunneling)
1388 {
1389         u32 cd_cmd, cd_tso_len, cd_mss;
1390         struct ipv6hdr *ipv6h;
1391         struct tcphdr *tcph;
1392         struct iphdr *iph;
1393         u32 l4len;
1394         int err;
1395
1396         if (!skb_is_gso(skb))
1397                 return 0;
1398
1399         err = skb_cow_head(skb, 0);
1400         if (err < 0)
1401                 return err;
1402
1403         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1404         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1405
1406         if (iph->version == 4) {
1407                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1408                 iph->tot_len = 0;
1409                 iph->check = 0;
1410                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1411                                                  0, IPPROTO_TCP, 0);
1412         } else if (ipv6h->version == 6) {
1413                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1414                 ipv6h->payload_len = 0;
1415                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1416                                                0, IPPROTO_TCP, 0);
1417         }
1418
1419         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1420         *hdr_len = (skb->encapsulation
1421                     ? (skb_inner_transport_header(skb) - skb->data)
1422                     : skb_transport_offset(skb)) + l4len;
1423
1424         /* find the field values */
1425         cd_cmd = I40E_TX_CTX_DESC_TSO;
1426         cd_tso_len = skb->len - *hdr_len;
1427         cd_mss = skb_shinfo(skb)->gso_size;
1428         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1429                                 ((u64)cd_tso_len <<
1430                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1431                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1432         return 1;
1433 }
1434
1435 /**
1436  * i40e_tx_enable_csum - Enable Tx checksum offloads
1437  * @skb: send buffer
1438  * @tx_flags: pointer to Tx flags currently set
1439  * @td_cmd: Tx descriptor command bits to set
1440  * @td_offset: Tx descriptor header offsets to set
1441  * @cd_tunneling: ptr to context desc bits
1442  **/
1443 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1444                                 u32 *td_cmd, u32 *td_offset,
1445                                 struct i40e_ring *tx_ring,
1446                                 u32 *cd_tunneling)
1447 {
1448         struct ipv6hdr *this_ipv6_hdr;
1449         unsigned int this_tcp_hdrlen;
1450         struct iphdr *this_ip_hdr;
1451         u32 network_hdr_len;
1452         u8 l4_hdr = 0;
1453         struct udphdr *oudph;
1454         struct iphdr *oiph;
1455         u32 l4_tunnel = 0;
1456
1457         if (skb->encapsulation) {
1458                 switch (ip_hdr(skb)->protocol) {
1459                 case IPPROTO_UDP:
1460                         oudph = udp_hdr(skb);
1461                         oiph = ip_hdr(skb);
1462                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1463                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1464                         break;
1465                 default:
1466                         return;
1467                 }
1468                 network_hdr_len = skb_inner_network_header_len(skb);
1469                 this_ip_hdr = inner_ip_hdr(skb);
1470                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1471                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1472
1473                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1474                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1475                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1476                                 ip_hdr(skb)->check = 0;
1477                         } else {
1478                                 *cd_tunneling |=
1479                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1480                         }
1481                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1482                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1483                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1484                                 ip_hdr(skb)->check = 0;
1485                 }
1486
1487                 /* Now set the ctx descriptor fields */
1488                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1489                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1490                                    l4_tunnel                             |
1491                                    ((skb_inner_network_offset(skb) -
1492                                         skb_transport_offset(skb)) >> 1) <<
1493                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1494                 if (this_ip_hdr->version == 6) {
1495                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1496                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1497                 }
1498
1499
1500                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1501                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1502                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1503                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1504                                         oiph->daddr,
1505                                         (skb->len - skb_transport_offset(skb)),
1506                                         IPPROTO_UDP, 0);
1507                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1508                 }
1509         } else {
1510                 network_hdr_len = skb_network_header_len(skb);
1511                 this_ip_hdr = ip_hdr(skb);
1512                 this_ipv6_hdr = ipv6_hdr(skb);
1513                 this_tcp_hdrlen = tcp_hdrlen(skb);
1514         }
1515
1516         /* Enable IP checksum offloads */
1517         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1518                 l4_hdr = this_ip_hdr->protocol;
1519                 /* the stack computes the IP header already, the only time we
1520                  * need the hardware to recompute it is in the case of TSO.
1521                  */
1522                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1523                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1524                         this_ip_hdr->check = 0;
1525                 } else {
1526                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1527                 }
1528                 /* Now set the td_offset for IP header length */
1529                 *td_offset = (network_hdr_len >> 2) <<
1530                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1531         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1532                 l4_hdr = this_ipv6_hdr->nexthdr;
1533                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1534                 /* Now set the td_offset for IP header length */
1535                 *td_offset = (network_hdr_len >> 2) <<
1536                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1537         }
1538         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1539         *td_offset |= (skb_network_offset(skb) >> 1) <<
1540                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1541
1542         /* Enable L4 checksum offloads */
1543         switch (l4_hdr) {
1544         case IPPROTO_TCP:
1545                 /* enable checksum offloads */
1546                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1547                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1548                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1549                 break;
1550         case IPPROTO_SCTP:
1551                 /* enable SCTP checksum offload */
1552                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1553                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1554                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1555                 break;
1556         case IPPROTO_UDP:
1557                 /* enable UDP checksum offload */
1558                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1559                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1560                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1561                 break;
1562         default:
1563                 break;
1564         }
1565 }
1566
1567 /**
1568  * i40e_create_tx_ctx Build the Tx context descriptor
1569  * @tx_ring:  ring to create the descriptor on
1570  * @cd_type_cmd_tso_mss: Quad Word 1
1571  * @cd_tunneling: Quad Word 0 - bits 0-31
1572  * @cd_l2tag2: Quad Word 0 - bits 32-63
1573  **/
1574 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1575                                const u64 cd_type_cmd_tso_mss,
1576                                const u32 cd_tunneling, const u32 cd_l2tag2)
1577 {
1578         struct i40e_tx_context_desc *context_desc;
1579         int i = tx_ring->next_to_use;
1580
1581         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1582             !cd_tunneling && !cd_l2tag2)
1583                 return;
1584
1585         /* grab the next descriptor */
1586         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1587
1588         i++;
1589         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1590
1591         /* cpu_to_le32 and assign to struct fields */
1592         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1593         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1594         context_desc->rsvd = cpu_to_le16(0);
1595         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1596 }
1597
1598  /**
1599  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1600  * @skb:      send buffer
1601  * @tx_flags: collected send information
1602  *
1603  * Note: Our HW can't scatter-gather more than 8 fragments to build
1604  * a packet on the wire and so we need to figure out the cases where we
1605  * need to linearize the skb.
1606  **/
1607 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1608 {
1609         struct skb_frag_struct *frag;
1610         bool linearize = false;
1611         unsigned int size = 0;
1612         u16 num_frags;
1613         u16 gso_segs;
1614
1615         num_frags = skb_shinfo(skb)->nr_frags;
1616         gso_segs = skb_shinfo(skb)->gso_segs;
1617
1618         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1619                 u16 j = 0;
1620
1621                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1622                         goto linearize_chk_done;
1623                 /* try the simple math, if we have too many frags per segment */
1624                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1625                     I40E_MAX_BUFFER_TXD) {
1626                         linearize = true;
1627                         goto linearize_chk_done;
1628                 }
1629                 frag = &skb_shinfo(skb)->frags[0];
1630                 /* we might still have more fragments per segment */
1631                 do {
1632                         size += skb_frag_size(frag);
1633                         frag++; j++;
1634                         if ((size >= skb_shinfo(skb)->gso_size) &&
1635                             (j < I40E_MAX_BUFFER_TXD)) {
1636                                 size = (size % skb_shinfo(skb)->gso_size);
1637                                 j = (size) ? 1 : 0;
1638                         }
1639                         if (j == I40E_MAX_BUFFER_TXD) {
1640                                 linearize = true;
1641                                 break;
1642                         }
1643                         num_frags--;
1644                 } while (num_frags);
1645         } else {
1646                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1647                         linearize = true;
1648         }
1649
1650 linearize_chk_done:
1651         return linearize;
1652 }
1653
1654 /**
1655  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1656  * @tx_ring: the ring to be checked
1657  * @size:    the size buffer we want to assure is available
1658  *
1659  * Returns -EBUSY if a stop is needed, else 0
1660  **/
1661 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1662 {
1663         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1664         /* Memory barrier before checking head and tail */
1665         smp_mb();
1666
1667         /* Check again in a case another CPU has just made room available. */
1668         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1669                 return -EBUSY;
1670
1671         /* A reprieve! - use start_queue because it doesn't call schedule */
1672         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1673         ++tx_ring->tx_stats.restart_queue;
1674         return 0;
1675 }
1676
1677 /**
1678  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1679  * @tx_ring: the ring to be checked
1680  * @size:    the size buffer we want to assure is available
1681  *
1682  * Returns 0 if stop is not needed
1683  **/
1684 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1685 {
1686         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1687                 return 0;
1688         return __i40evf_maybe_stop_tx(tx_ring, size);
1689 }
1690
1691 /**
1692  * i40evf_tx_map - Build the Tx descriptor
1693  * @tx_ring:  ring to send buffer on
1694  * @skb:      send buffer
1695  * @first:    first buffer info buffer to use
1696  * @tx_flags: collected send information
1697  * @hdr_len:  size of the packet header
1698  * @td_cmd:   the command field in the descriptor
1699  * @td_offset: offset for checksum or crc
1700  **/
1701 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1702                                  struct i40e_tx_buffer *first, u32 tx_flags,
1703                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1704 {
1705         unsigned int data_len = skb->data_len;
1706         unsigned int size = skb_headlen(skb);
1707         struct skb_frag_struct *frag;
1708         struct i40e_tx_buffer *tx_bi;
1709         struct i40e_tx_desc *tx_desc;
1710         u16 i = tx_ring->next_to_use;
1711         u32 td_tag = 0;
1712         dma_addr_t dma;
1713         u16 gso_segs;
1714
1715         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1716                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1717                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1718                          I40E_TX_FLAGS_VLAN_SHIFT;
1719         }
1720
1721         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1722                 gso_segs = skb_shinfo(skb)->gso_segs;
1723         else
1724                 gso_segs = 1;
1725
1726         /* multiply data chunks by size of headers */
1727         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1728         first->gso_segs = gso_segs;
1729         first->skb = skb;
1730         first->tx_flags = tx_flags;
1731
1732         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1733
1734         tx_desc = I40E_TX_DESC(tx_ring, i);
1735         tx_bi = first;
1736
1737         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1738                 if (dma_mapping_error(tx_ring->dev, dma))
1739                         goto dma_error;
1740
1741                 /* record length, and DMA address */
1742                 dma_unmap_len_set(tx_bi, len, size);
1743                 dma_unmap_addr_set(tx_bi, dma, dma);
1744
1745                 tx_desc->buffer_addr = cpu_to_le64(dma);
1746
1747                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1748                         tx_desc->cmd_type_offset_bsz =
1749                                 build_ctob(td_cmd, td_offset,
1750                                            I40E_MAX_DATA_PER_TXD, td_tag);
1751
1752                         tx_desc++;
1753                         i++;
1754                         if (i == tx_ring->count) {
1755                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1756                                 i = 0;
1757                         }
1758
1759                         dma += I40E_MAX_DATA_PER_TXD;
1760                         size -= I40E_MAX_DATA_PER_TXD;
1761
1762                         tx_desc->buffer_addr = cpu_to_le64(dma);
1763                 }
1764
1765                 if (likely(!data_len))
1766                         break;
1767
1768                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1769                                                           size, td_tag);
1770
1771                 tx_desc++;
1772                 i++;
1773                 if (i == tx_ring->count) {
1774                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1775                         i = 0;
1776                 }
1777
1778                 size = skb_frag_size(frag);
1779                 data_len -= size;
1780
1781                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1782                                        DMA_TO_DEVICE);
1783
1784                 tx_bi = &tx_ring->tx_bi[i];
1785         }
1786
1787         /* Place RS bit on last descriptor of any packet that spans across the
1788          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1789          */
1790 #define WB_STRIDE 0x3
1791         if (((i & WB_STRIDE) != WB_STRIDE) &&
1792             (first <= &tx_ring->tx_bi[i]) &&
1793             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1794                 tx_desc->cmd_type_offset_bsz =
1795                         build_ctob(td_cmd, td_offset, size, td_tag) |
1796                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1797                                          I40E_TXD_QW1_CMD_SHIFT);
1798         } else {
1799                 tx_desc->cmd_type_offset_bsz =
1800                         build_ctob(td_cmd, td_offset, size, td_tag) |
1801                         cpu_to_le64((u64)I40E_TXD_CMD <<
1802                                          I40E_TXD_QW1_CMD_SHIFT);
1803         }
1804
1805         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1806                                                  tx_ring->queue_index),
1807                              first->bytecount);
1808
1809         /* Force memory writes to complete before letting h/w
1810          * know there are new descriptors to fetch.  (Only
1811          * applicable for weak-ordered memory model archs,
1812          * such as IA-64).
1813          */
1814         wmb();
1815
1816         /* set next_to_watch value indicating a packet is present */
1817         first->next_to_watch = tx_desc;
1818
1819         i++;
1820         if (i == tx_ring->count)
1821                 i = 0;
1822
1823         tx_ring->next_to_use = i;
1824
1825         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1826         /* notify HW of packet */
1827         if (!skb->xmit_more ||
1828             netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1829                                                    tx_ring->queue_index)))
1830                 writel(i, tx_ring->tail);
1831         else
1832                 prefetchw(tx_desc + 1);
1833
1834         return;
1835
1836 dma_error:
1837         dev_info(tx_ring->dev, "TX DMA map failed\n");
1838
1839         /* clear dma mappings for failed tx_bi map */
1840         for (;;) {
1841                 tx_bi = &tx_ring->tx_bi[i];
1842                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1843                 if (tx_bi == first)
1844                         break;
1845                 if (i == 0)
1846                         i = tx_ring->count;
1847                 i--;
1848         }
1849
1850         tx_ring->next_to_use = i;
1851 }
1852
1853 /**
1854  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1855  * @skb:     send buffer
1856  * @tx_ring: ring to send buffer on
1857  *
1858  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1859  * there is not enough descriptors available in this ring since we need at least
1860  * one descriptor.
1861  **/
1862 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1863                                                struct i40e_ring *tx_ring)
1864 {
1865         unsigned int f;
1866         int count = 0;
1867
1868         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1869          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1870          *       + 4 desc gap to avoid the cache line where head is,
1871          *       + 1 desc for context descriptor,
1872          * otherwise try next time
1873          */
1874         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1875                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1876
1877         count += TXD_USE_COUNT(skb_headlen(skb));
1878         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1879                 tx_ring->tx_stats.tx_busy++;
1880                 return 0;
1881         }
1882         return count;
1883 }
1884
1885 /**
1886  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1887  * @skb:     send buffer
1888  * @tx_ring: ring to send buffer on
1889  *
1890  * Returns NETDEV_TX_OK if sent, else an error code
1891  **/
1892 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1893                                         struct i40e_ring *tx_ring)
1894 {
1895         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1896         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1897         struct i40e_tx_buffer *first;
1898         u32 td_offset = 0;
1899         u32 tx_flags = 0;
1900         __be16 protocol;
1901         u32 td_cmd = 0;
1902         u8 hdr_len = 0;
1903         int tso;
1904         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
1905                 return NETDEV_TX_BUSY;
1906
1907         /* prepare the xmit flags */
1908         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1909                 goto out_drop;
1910
1911         /* obtain protocol of skb */
1912         protocol = vlan_get_protocol(skb);
1913
1914         /* record the location of the first descriptor for this packet */
1915         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1916
1917         /* setup IPv4/IPv6 offloads */
1918         if (protocol == htons(ETH_P_IP))
1919                 tx_flags |= I40E_TX_FLAGS_IPV4;
1920         else if (protocol == htons(ETH_P_IPV6))
1921                 tx_flags |= I40E_TX_FLAGS_IPV6;
1922
1923         tso = i40e_tso(tx_ring, skb, &hdr_len,
1924                        &cd_type_cmd_tso_mss, &cd_tunneling);
1925
1926         if (tso < 0)
1927                 goto out_drop;
1928         else if (tso)
1929                 tx_flags |= I40E_TX_FLAGS_TSO;
1930
1931         if (i40e_chk_linearize(skb, tx_flags))
1932                 if (skb_linearize(skb))
1933                         goto out_drop;
1934
1935         skb_tx_timestamp(skb);
1936
1937         /* always enable CRC insertion offload */
1938         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1939
1940         /* Always offload the checksum, since it's in the data descriptor */
1941         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1942                 tx_flags |= I40E_TX_FLAGS_CSUM;
1943
1944                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
1945                                     tx_ring, &cd_tunneling);
1946         }
1947
1948         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1949                            cd_tunneling, cd_l2tag2);
1950
1951         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1952                       td_cmd, td_offset);
1953
1954         return NETDEV_TX_OK;
1955
1956 out_drop:
1957         dev_kfree_skb_any(skb);
1958         return NETDEV_TX_OK;
1959 }
1960
1961 /**
1962  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1963  * @skb:    send buffer
1964  * @netdev: network interface device structure
1965  *
1966  * Returns NETDEV_TX_OK if sent, else an error code
1967  **/
1968 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1969 {
1970         struct i40evf_adapter *adapter = netdev_priv(netdev);
1971         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1972
1973         /* hardware can't handle really short frames, hardware padding works
1974          * beyond this point
1975          */
1976         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1977                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1978                         return NETDEV_TX_OK;
1979                 skb->len = I40E_MIN_TX_LEN;
1980                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1981         }
1982
1983         return i40e_xmit_frame_ring(skb, tx_ring);
1984 }