drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  55                         kfree(tx_buffer->raw_buf);
  56                 else
  57                         dev_kfree_skb_any(tx_buffer->skb);
  58
  59                 if (dma_unmap_len(tx_buffer, len))
  60                         dma_unmap_single(ring->dev,
  61                                          dma_unmap_addr(tx_buffer, dma),
  62                                          dma_unmap_len(tx_buffer, len),
  63                                          DMA_TO_DEVICE);
  64         } else if (dma_unmap_len(tx_buffer, len)) {
  65                 dma_unmap_page(ring->dev,
  66                                dma_unmap_addr(tx_buffer, dma),
  67                                dma_unmap_len(tx_buffer, len),
  68                                DMA_TO_DEVICE);
  69         }
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 #define WB_STRIDE 0x3
 144
 145 /**
 146  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 147  * @tx_ring:  tx ring to clean
 148  * @budget:   how many cleans we're allowed
 149  *
 150  * Returns true if there's any budget left (e.g. the clean is finished)
 151  **/
 152 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 153 {
 154         u16 i = tx_ring->next_to_clean;
 155         struct i40e_tx_buffer *tx_buf;
 156         struct i40e_tx_desc *tx_head;
 157         struct i40e_tx_desc *tx_desc;
 158         unsigned int total_packets = 0;
 159         unsigned int total_bytes = 0;
 160
 161         tx_buf = &tx_ring->tx_bi[i];
 162         tx_desc = I40E_TX_DESC(tx_ring, i);
 163         i -= tx_ring->count;
 164
 165         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 166
 167         do {
 168                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 169
 170                 /* if next_to_watch is not set then there is no work pending */
 171                 if (!eop_desc)
 172                         break;
 173
 174                 /* prevent any other reads prior to eop_desc */
 175                 read_barrier_depends();
 176
 177                 /* we have caught up to head, no work left to do */
 178                 if (tx_head == tx_desc)
 179                         break;
 180
 181                 /* clear next_to_watch to prevent false hangs */
 182                 tx_buf->next_to_watch = NULL;
 183
 184                 /* update the statistics for this packet */
 185                 total_bytes += tx_buf->bytecount;
 186                 total_packets += tx_buf->gso_segs;
 187
 188                 /* free the skb */
 189                 dev_kfree_skb_any(tx_buf->skb);
 190
 191                 /* unmap skb header data */
 192                 dma_unmap_single(tx_ring->dev,
 193                                  dma_unmap_addr(tx_buf, dma),
 194                                  dma_unmap_len(tx_buf, len),
 195                                  DMA_TO_DEVICE);
 196
 197                 /* clear tx_buffer data */
 198                 tx_buf->skb = NULL;
 199                 dma_unmap_len_set(tx_buf, len, 0);
 200
 201                 /* unmap remaining buffers */
 202                 while (tx_desc != eop_desc) {
 203
 204                         tx_buf++;
 205                         tx_desc++;
 206                         i++;
 207                         if (unlikely(!i)) {
 208                                 i -= tx_ring->count;
 209                                 tx_buf = tx_ring->tx_bi;
 210                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 211                         }
 212
 213                         /* unmap any remaining paged data */
 214                         if (dma_unmap_len(tx_buf, len)) {
 215                                 dma_unmap_page(tx_ring->dev,
 216                                                dma_unmap_addr(tx_buf, dma),
 217                                                dma_unmap_len(tx_buf, len),
 218                                                DMA_TO_DEVICE);
 219                                 dma_unmap_len_set(tx_buf, len, 0);
 220                         }
 221                 }
 222
 223                 /* move us one more past the eop_desc for start of next pkt */
 224                 tx_buf++;
 225                 tx_desc++;
 226                 i++;
 227                 if (unlikely(!i)) {
 228                         i -= tx_ring->count;
 229                         tx_buf = tx_ring->tx_bi;
 230                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 231                 }
 232
 233                 prefetch(tx_desc);
 234
 235                 /* update budget accounting */
 236                 budget--;
 237         } while (likely(budget));
 238
 239         i += tx_ring->count;
 240         tx_ring->next_to_clean = i;
 241         u64_stats_update_begin(&tx_ring->syncp);
 242         tx_ring->stats.bytes += total_bytes;
 243         tx_ring->stats.packets += total_packets;
 244         u64_stats_update_end(&tx_ring->syncp);
 245         tx_ring->q_vector->tx.total_bytes += total_bytes;
 246         tx_ring->q_vector->tx.total_packets += total_packets;
 247
 248         /* check to see if there are any non-cache aligned descriptors
 249          * waiting to be written back, and kick the hardware to force
 250          * them to be written back in case of napi polling
 251          */
 252         if (budget &&
 253             !((i & WB_STRIDE) == WB_STRIDE) &&
 254             !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 255             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 256                 tx_ring->arm_wb = true;
 257
 258         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 259                                                       tx_ring->queue_index),
 260                                   total_packets, total_bytes);
 261
 262 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 263         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 264                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 265                 /* Make sure that anybody stopping the queue after this
 266                  * sees the new next_to_clean.
 267                  */
 268                 smp_mb();
 269                 if (__netif_subqueue_stopped(tx_ring->netdev,
 270                                              tx_ring->queue_index) &&
 271                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 272                         netif_wake_subqueue(tx_ring->netdev,
 273                                             tx_ring->queue_index);
 274                         ++tx_ring->tx_stats.restart_queue;
 275                 }
 276         }
 277
 278         return !!budget;
 279 }
 280
 281 /**
 282  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 283  * @vsi: the VSI we care about
 284  * @q_vector: the vector  on which to force writeback
 285  *
 286  **/
 287 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 288 {
 289         u16 flags = q_vector->tx.ring[0].flags;
 290
 291         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 292                 u32 val;
 293
 294                 if (q_vector->arm_wb_state)
 295                         return;
 296
 297                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
 298
 299                 wr32(&vsi->back->hw,
 300                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 301                                           vsi->base_vector - 1),
 302                      val);
 303                 q_vector->arm_wb_state = true;
 304         } else {
 305                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 306                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 307                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 308                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 309                           /* allow 00 to be written to the index */
 310
 311                 wr32(&vsi->back->hw,
 312                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 313                                           vsi->base_vector - 1), val);
 314         }
 315 }
 316
 317 /**
 318  * i40e_set_new_dynamic_itr - Find new ITR level
 319  * @rc: structure containing ring performance data
 320  *
 321  * Returns true if ITR changed, false if not
 322  *
 323  * Stores a new ITR value based on packets and byte counts during
 324  * the last interrupt.  The advantage of per interrupt computation
 325  * is faster updates and more accurate ITR for the current traffic
 326  * pattern.  Constants in this function were computed based on
 327  * theoretical maximum wire speed and thresholds were set based on
 328  * testing data as well as attempting to minimize response time
 329  * while increasing bulk throughput.
 330  **/
 331 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 332 {
 333         enum i40e_latency_range new_latency_range = rc->latency_range;
 334         struct i40e_q_vector *qv = rc->ring->q_vector;
 335         u32 new_itr = rc->itr;
 336         int bytes_per_int;
 337         int usecs;
 338
 339         if (rc->total_packets == 0 || !rc->itr)
 340                 return false;
 341
 342         /* simple throttlerate management
 343          *   0-10MB/s   lowest (50000 ints/s)
 344          *  10-20MB/s   low    (20000 ints/s)
 345          *  20-1249MB/s bulk   (18000 ints/s)
 346          *  > 40000 Rx packets per second (8000 ints/s)
 347          *
 348          * The math works out because the divisor is in 10^(-6) which
 349          * turns the bytes/us input value into MB/s values, but
 350          * make sure to use usecs, as the register values written
 351          * are in 2 usec increments in the ITR registers.
 352          */
 353         usecs = (rc->itr << 1);
 354         bytes_per_int = rc->total_bytes / usecs;
 355         switch (new_latency_range) {
 356         case I40E_LOWEST_LATENCY:
 357                 if (bytes_per_int > 10)
 358                         new_latency_range = I40E_LOW_LATENCY;
 359                 break;
 360         case I40E_LOW_LATENCY:
 361                 if (bytes_per_int > 20)
 362                         new_latency_range = I40E_BULK_LATENCY;
 363                 else if (bytes_per_int <= 10)
 364                         new_latency_range = I40E_LOWEST_LATENCY;
 365                 break;
 366         case I40E_BULK_LATENCY:
 367         case I40E_ULTRA_LATENCY:
 368         default:
 369                 if (bytes_per_int <= 20)
 370                         new_latency_range = I40E_LOW_LATENCY;
 371                 break;
 372         }
 373
 374         /* this is to adjust RX more aggressively when streaming small
 375          * packets.  The value of 40000 was picked as it is just beyond
 376          * what the hardware can receive per second if in low latency
 377          * mode.
 378          */
 379 #define RX_ULTRA_PACKET_RATE 40000
 380
 381         if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
 382             (&qv->rx == rc))
 383                 new_latency_range = I40E_ULTRA_LATENCY;
 384
 385         rc->latency_range = new_latency_range;
 386
 387         switch (new_latency_range) {
 388         case I40E_LOWEST_LATENCY:
 389                 new_itr = I40E_ITR_50K;
 390                 break;
 391         case I40E_LOW_LATENCY:
 392                 new_itr = I40E_ITR_20K;
 393                 break;
 394         case I40E_BULK_LATENCY:
 395                 new_itr = I40E_ITR_18K;
 396                 break;
 397         case I40E_ULTRA_LATENCY:
 398                 new_itr = I40E_ITR_8K;
 399                 break;
 400         default:
 401                 break;
 402         }
 403
 404         rc->total_bytes = 0;
 405         rc->total_packets = 0;
 406
 407         if (new_itr != rc->itr) {
 408                 rc->itr = new_itr;
 409                 return true;
 410         }
 411
 412         return false;
 413 }
 414
 415 /*
 416  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 417  * @tx_ring: the tx ring to set up
 418  *
 419  * Return 0 on success, negative on error
 420  **/
 421 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 422 {
 423         struct device *dev = tx_ring->dev;
 424         int bi_size;
 425
 426         if (!dev)
 427                 return -ENOMEM;
 428
 429         /* warn if we are about to overwrite the pointer */
 430         WARN_ON(tx_ring->tx_bi);
 431         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 432         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 433         if (!tx_ring->tx_bi)
 434                 goto err;
 435
 436         /* round up to nearest 4K */
 437         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 438         /* add u32 for head writeback, align after this takes care of
 439          * guaranteeing this is at least one cache line in size
 440          */
 441         tx_ring->size += sizeof(u32);
 442         tx_ring->size = ALIGN(tx_ring->size, 4096);
 443         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 444                                            &tx_ring->dma, GFP_KERNEL);
 445         if (!tx_ring->desc) {
 446                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 447                          tx_ring->size);
 448                 goto err;
 449         }
 450
 451         tx_ring->next_to_use = 0;
 452         tx_ring->next_to_clean = 0;
 453         return 0;
 454
 455 err:
 456         kfree(tx_ring->tx_bi);
 457         tx_ring->tx_bi = NULL;
 458         return -ENOMEM;
 459 }
 460
 461 /**
 462  * i40evf_clean_rx_ring - Free Rx buffers
 463  * @rx_ring: ring to be cleaned
 464  **/
 465 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 466 {
 467         struct device *dev = rx_ring->dev;
 468         struct i40e_rx_buffer *rx_bi;
 469         unsigned long bi_size;
 470         u16 i;
 471
 472         /* ring already cleared, nothing to do */
 473         if (!rx_ring->rx_bi)
 474                 return;
 475
 476         if (ring_is_ps_enabled(rx_ring)) {
 477                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 478
 479                 rx_bi = &rx_ring->rx_bi[0];
 480                 if (rx_bi->hdr_buf) {
 481                         dma_free_coherent(dev,
 482                                           bufsz,
 483                                           rx_bi->hdr_buf,
 484                                           rx_bi->dma);
 485                         for (i = 0; i < rx_ring->count; i++) {
 486                                 rx_bi = &rx_ring->rx_bi[i];
 487                                 rx_bi->dma = 0;
 488                                 rx_bi->hdr_buf = NULL;
 489                         }
 490                 }
 491         }
 492         /* Free all the Rx ring sk_buffs */
 493         for (i = 0; i < rx_ring->count; i++) {
 494                 rx_bi = &rx_ring->rx_bi[i];
 495                 if (rx_bi->dma) {
 496                         dma_unmap_single(dev,
 497                                          rx_bi->dma,
 498                                          rx_ring->rx_buf_len,
 499                                          DMA_FROM_DEVICE);
 500                         rx_bi->dma = 0;
 501                 }
 502                 if (rx_bi->skb) {
 503                         dev_kfree_skb(rx_bi->skb);
 504                         rx_bi->skb = NULL;
 505                 }
 506                 if (rx_bi->page) {
 507                         if (rx_bi->page_dma) {
 508                                 dma_unmap_page(dev,
 509                                                rx_bi->page_dma,
 510                                                PAGE_SIZE / 2,
 511                                                DMA_FROM_DEVICE);
 512                                 rx_bi->page_dma = 0;
 513                         }
 514                         __free_page(rx_bi->page);
 515                         rx_bi->page = NULL;
 516                         rx_bi->page_offset = 0;
 517                 }
 518         }
 519
 520         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 521         memset(rx_ring->rx_bi, 0, bi_size);
 522
 523         /* Zero out the descriptor ring */
 524         memset(rx_ring->desc, 0, rx_ring->size);
 525
 526         rx_ring->next_to_clean = 0;
 527         rx_ring->next_to_use = 0;
 528 }
 529
 530 /**
 531  * i40evf_free_rx_resources - Free Rx resources
 532  * @rx_ring: ring to clean the resources from
 533  *
 534  * Free all receive software resources
 535  **/
 536 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 537 {
 538         i40evf_clean_rx_ring(rx_ring);
 539         kfree(rx_ring->rx_bi);
 540         rx_ring->rx_bi = NULL;
 541
 542         if (rx_ring->desc) {
 543                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 544                                   rx_ring->desc, rx_ring->dma);
 545                 rx_ring->desc = NULL;
 546         }
 547 }
 548
 549 /**
 550  * i40evf_alloc_rx_headers - allocate rx header buffers
 551  * @rx_ring: ring to alloc buffers
 552  *
 553  * Allocate rx header buffers for the entire ring. As these are static,
 554  * this is only called when setting up a new ring.
 555  **/
 556 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 557 {
 558         struct device *dev = rx_ring->dev;
 559         struct i40e_rx_buffer *rx_bi;
 560         dma_addr_t dma;
 561         void *buffer;
 562         int buf_size;
 563         int i;
 564
 565         if (rx_ring->rx_bi[0].hdr_buf)
 566                 return;
 567         /* Make sure the buffers don't cross cache line boundaries. */
 568         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 569         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 570                                     &dma, GFP_KERNEL);
 571         if (!buffer)
 572                 return;
 573         for (i = 0; i < rx_ring->count; i++) {
 574                 rx_bi = &rx_ring->rx_bi[i];
 575                 rx_bi->dma = dma + (i * buf_size);
 576                 rx_bi->hdr_buf = buffer + (i * buf_size);
 577         }
 578 }
 579
 580 /**
 581  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 582  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 583  *
 584  * Returns 0 on success, negative on failure
 585  **/
 586 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 587 {
 588         struct device *dev = rx_ring->dev;
 589         int bi_size;
 590
 591         /* warn if we are about to overwrite the pointer */
 592         WARN_ON(rx_ring->rx_bi);
 593         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 594         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 595         if (!rx_ring->rx_bi)
 596                 goto err;
 597
 598         u64_stats_init(&rx_ring->syncp);
 599
 600         /* Round up to nearest 4K */
 601         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 602                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 603                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 604         rx_ring->size = ALIGN(rx_ring->size, 4096);
 605         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 606                                            &rx_ring->dma, GFP_KERNEL);
 607
 608         if (!rx_ring->desc) {
 609                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 610                          rx_ring->size);
 611                 goto err;
 612         }
 613
 614         rx_ring->next_to_clean = 0;
 615         rx_ring->next_to_use = 0;
 616
 617         return 0;
 618 err:
 619         kfree(rx_ring->rx_bi);
 620         rx_ring->rx_bi = NULL;
 621         return -ENOMEM;
 622 }
 623
 624 /**
 625  * i40e_release_rx_desc - Store the new tail and head values
 626  * @rx_ring: ring to bump
 627  * @val: new head index
 628  **/
 629 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 630 {
 631         rx_ring->next_to_use = val;
 632         /* Force memory writes to complete before letting h/w
 633          * know there are new descriptors to fetch.  (Only
 634          * applicable for weak-ordered memory model archs,
 635          * such as IA-64).
 636          */
 637         wmb();
 638         writel(val, rx_ring->tail);
 639 }
 640
 641 /**
 642  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 643  * @rx_ring: ring to place buffers on
 644  * @cleaned_count: number of buffers to replace
 645  **/
 646 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 647 {
 648         u16 i = rx_ring->next_to_use;
 649         union i40e_rx_desc *rx_desc;
 650         struct i40e_rx_buffer *bi;
 651
 652         /* do nothing if no valid netdev defined */
 653         if (!rx_ring->netdev || !cleaned_count)
 654                 return;
 655
 656         while (cleaned_count--) {
 657                 rx_desc = I40E_RX_DESC(rx_ring, i);
 658                 bi = &rx_ring->rx_bi[i];
 659
 660                 if (bi->skb) /* desc is in use */
 661                         goto no_buffers;
 662                 if (!bi->page) {
 663                         bi->page = alloc_page(GFP_ATOMIC);
 664                         if (!bi->page) {
 665                                 rx_ring->rx_stats.alloc_page_failed++;
 666                                 goto no_buffers;
 667                         }
 668                 }
 669
 670                 if (!bi->page_dma) {
 671                         /* use a half page if we're re-using */
 672                         bi->page_offset ^= PAGE_SIZE / 2;
 673                         bi->page_dma = dma_map_page(rx_ring->dev,
 674                                                     bi->page,
 675                                                     bi->page_offset,
 676                                                     PAGE_SIZE / 2,
 677                                                     DMA_FROM_DEVICE);
 678                         if (dma_mapping_error(rx_ring->dev,
 679                                               bi->page_dma)) {
 680                                 rx_ring->rx_stats.alloc_page_failed++;
 681                                 bi->page_dma = 0;
 682                                 goto no_buffers;
 683                         }
 684                 }
 685
 686                 dma_sync_single_range_for_device(rx_ring->dev,
 687                                                  bi->dma,
 688                                                  0,
 689                                                  rx_ring->rx_hdr_len,
 690                                                  DMA_FROM_DEVICE);
 691                 /* Refresh the desc even if buffer_addrs didn't change
 692                  * because each write-back erases this info.
 693                  */
 694                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 695                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 696                 i++;
 697                 if (i == rx_ring->count)
 698                         i = 0;
 699         }
 700
 701 no_buffers:
 702         if (rx_ring->next_to_use != i)
 703                 i40e_release_rx_desc(rx_ring, i);
 704 }
 705
 706 /**
 707  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 708  * @rx_ring: ring to place buffers on
 709  * @cleaned_count: number of buffers to replace
 710  **/
 711 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 712 {
 713         u16 i = rx_ring->next_to_use;
 714         union i40e_rx_desc *rx_desc;
 715         struct i40e_rx_buffer *bi;
 716         struct sk_buff *skb;
 717
 718         /* do nothing if no valid netdev defined */
 719         if (!rx_ring->netdev || !cleaned_count)
 720                 return;
 721
 722         while (cleaned_count--) {
 723                 rx_desc = I40E_RX_DESC(rx_ring, i);
 724                 bi = &rx_ring->rx_bi[i];
 725                 skb = bi->skb;
 726
 727                 if (!skb) {
 728                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 729                                                         rx_ring->rx_buf_len);
 730                         if (!skb) {
 731                                 rx_ring->rx_stats.alloc_buff_failed++;
 732                                 goto no_buffers;
 733                         }
 734                         /* initialize queue mapping */
 735                         skb_record_rx_queue(skb, rx_ring->queue_index);
 736                         bi->skb = skb;
 737                 }
 738
 739                 if (!bi->dma) {
 740                         bi->dma = dma_map_single(rx_ring->dev,
 741                                                  skb->data,
 742                                                  rx_ring->rx_buf_len,
 743                                                  DMA_FROM_DEVICE);
 744                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 745                                 rx_ring->rx_stats.alloc_buff_failed++;
 746                                 bi->dma = 0;
 747                                 goto no_buffers;
 748                         }
 749                 }
 750
 751                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 752                 rx_desc->read.hdr_addr = 0;
 753                 i++;
 754                 if (i == rx_ring->count)
 755                         i = 0;
 756         }
 757
 758 no_buffers:
 759         if (rx_ring->next_to_use != i)
 760                 i40e_release_rx_desc(rx_ring, i);
 761 }
 762
 763 /**
 764  * i40e_receive_skb - Send a completed packet up the stack
 765  * @rx_ring:  rx ring in play
 766  * @skb: packet to send up
 767  * @vlan_tag: vlan tag for packet
 768  **/
 769 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 770                              struct sk_buff *skb, u16 vlan_tag)
 771 {
 772         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 773
 774         if (vlan_tag & VLAN_VID_MASK)
 775                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 776
 777         napi_gro_receive(&q_vector->napi, skb);
 778 }
 779
 780 /**
 781  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 782  * @vsi: the VSI we care about
 783  * @skb: skb currently being received and modified
 784  * @rx_status: status value of last descriptor in packet
 785  * @rx_error: error value of last descriptor in packet
 786  * @rx_ptype: ptype value of last descriptor in packet
 787  **/
 788 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 789                                     struct sk_buff *skb,
 790                                     u32 rx_status,
 791                                     u32 rx_error,
 792                                     u16 rx_ptype)
 793 {
 794         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 795         bool ipv4 = false, ipv6 = false;
 796         bool ipv4_tunnel, ipv6_tunnel;
 797         __wsum rx_udp_csum;
 798         struct iphdr *iph;
 799         __sum16 csum;
 800
 801         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 802                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 803         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 804                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 805
 806         skb->ip_summed = CHECKSUM_NONE;
 807
 808         /* Rx csum enabled and ip headers found? */
 809         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 810                 return;
 811
 812         /* did the hardware decode the packet and checksum? */
 813         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 814                 return;
 815
 816         /* both known and outer_ip must be set for the below code to work */
 817         if (!(decoded.known && decoded.outer_ip))
 818                 return;
 819
 820         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 821             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 822                 ipv4 = true;
 823         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 824                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 825                 ipv6 = true;
 826
 827         if (ipv4 &&
 828             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 829                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 830                 goto checksum_fail;
 831
 832         /* likely incorrect csum if alternate IP extension headers found */
 833         if (ipv6 &&
 834             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 835                 /* don't increment checksum err here, non-fatal err */
 836                 return;
 837
 838         /* there was some L4 error, count error and punt packet to the stack */
 839         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 840                 goto checksum_fail;
 841
 842         /* handle packets that were not able to be checksummed due
 843          * to arrival speed, in this case the stack can compute
 844          * the csum.
 845          */
 846         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 847                 return;
 848
 849         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 850          * it in the driver, hardware does not do it for us.
 851          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 852          * so the total length of IPv4 header is IHL*4 bytes
 853          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 854          */
 855         if (ipv4_tunnel) {
 856                 skb->transport_header = skb->mac_header +
 857                                         sizeof(struct ethhdr) +
 858                                         (ip_hdr(skb)->ihl * 4);
 859
 860                 /* Add 4 bytes for VLAN tagged packets */
 861                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 862                                           skb->protocol == htons(ETH_P_8021AD))
 863                                           ? VLAN_HLEN : 0;
 864
 865                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 866                     (udp_hdr(skb)->check != 0)) {
 867                         rx_udp_csum = udp_csum(skb);
 868                         iph = ip_hdr(skb);
 869                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 870                                                  (skb->len -
 871                                                   skb_transport_offset(skb)),
 872                                                  IPPROTO_UDP, rx_udp_csum);
 873
 874                         if (udp_hdr(skb)->check != csum)
 875                                 goto checksum_fail;
 876
 877                 } /* else its GRE and so no outer UDP header */
 878         }
 879
 880         skb->ip_summed = CHECKSUM_UNNECESSARY;
 881         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 882
 883         return;
 884
 885 checksum_fail:
 886         vsi->back->hw_csum_rx_error++;
 887 }
 888
 889 /**
 890  * i40e_rx_hash - returns the hash value from the Rx descriptor
 891  * @ring: descriptor ring
 892  * @rx_desc: specific descriptor
 893  **/
 894 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 895                                union i40e_rx_desc *rx_desc)
 896 {
 897         const __le64 rss_mask =
 898                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 899                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 900
 901         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 902             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 903                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 904         else
 905                 return 0;
 906 }
 907
 908 /**
 909  * i40e_ptype_to_hash - get a hash type
 910  * @ptype: the ptype value from the descriptor
 911  *
 912  * Returns a hash type to be used by skb_set_hash
 913  **/
 914 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 915 {
 916         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 917
 918         if (!decoded.known)
 919                 return PKT_HASH_TYPE_NONE;
 920
 921         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 922             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 923                 return PKT_HASH_TYPE_L4;
 924         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 925                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 926                 return PKT_HASH_TYPE_L3;
 927         else
 928                 return PKT_HASH_TYPE_L2;
 929 }
 930
 931 /**
 932  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 933  * @rx_ring:  rx ring to clean
 934  * @budget:   how many cleans we're allowed
 935  *
 936  * Returns true if there's any budget left (e.g. the clean is finished)
 937  **/
 938 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 939 {
 940         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 941         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 942         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 943         const int current_node = numa_mem_id();
 944         struct i40e_vsi *vsi = rx_ring->vsi;
 945         u16 i = rx_ring->next_to_clean;
 946         union i40e_rx_desc *rx_desc;
 947         u32 rx_error, rx_status;
 948         u8 rx_ptype;
 949         u64 qword;
 950
 951         do {
 952                 struct i40e_rx_buffer *rx_bi;
 953                 struct sk_buff *skb;
 954                 u16 vlan_tag;
 955                 /* return some buffers to hardware, one at a time is too slow */
 956                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 957                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
 958                         cleaned_count = 0;
 959                 }
 960
 961                 i = rx_ring->next_to_clean;
 962                 rx_desc = I40E_RX_DESC(rx_ring, i);
 963                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 964                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 965                         I40E_RXD_QW1_STATUS_SHIFT;
 966
 967                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
 968                         break;
 969
 970                 /* This memory barrier is needed to keep us from reading
 971                  * any other fields out of the rx_desc until we know the
 972                  * DD bit is set.
 973                  */
 974                 dma_rmb();
 975                 rx_bi = &rx_ring->rx_bi[i];
 976                 skb = rx_bi->skb;
 977                 if (likely(!skb)) {
 978                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 979                                                         rx_ring->rx_hdr_len);
 980                         if (!skb) {
 981                                 rx_ring->rx_stats.alloc_buff_failed++;
 982                                 break;
 983                         }
 984
 985                         /* initialize queue mapping */
 986                         skb_record_rx_queue(skb, rx_ring->queue_index);
 987                         /* we are reusing so sync this buffer for CPU use */
 988                         dma_sync_single_range_for_cpu(rx_ring->dev,
 989                                                       rx_bi->dma,
 990                                                       0,
 991                                                       rx_ring->rx_hdr_len,
 992                                                       DMA_FROM_DEVICE);
 993                 }
 994                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 995                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 996                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 997                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 998                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 999                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1000
1001                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1002                            I40E_RXD_QW1_ERROR_SHIFT;
1003                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1004                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1005
1006                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1007                            I40E_RXD_QW1_PTYPE_SHIFT;
1008                 prefetch(rx_bi->page);
1009                 rx_bi->skb = NULL;
1010                 cleaned_count++;
1011                 if (rx_hbo || rx_sph) {
1012                         int len;
1013
1014                         if (rx_hbo)
1015                                 len = I40E_RX_HDR_SIZE;
1016                         else
1017                                 len = rx_header_len;
1018                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1019                 } else if (skb->len == 0) {
1020                         int len;
1021
1022                         len = (rx_packet_len > skb_headlen(skb) ?
1023                                 skb_headlen(skb) : rx_packet_len);
1024                         memcpy(__skb_put(skb, len),
1025                                rx_bi->page + rx_bi->page_offset,
1026                                len);
1027                         rx_bi->page_offset += len;
1028                         rx_packet_len -= len;
1029                 }
1030
1031                 /* Get the rest of the data if this was a header split */
1032                 if (rx_packet_len) {
1033                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1034                                            rx_bi->page,
1035                                            rx_bi->page_offset,
1036                                            rx_packet_len);
1037
1038                         skb->len += rx_packet_len;
1039                         skb->data_len += rx_packet_len;
1040                         skb->truesize += rx_packet_len;
1041
1042                         if ((page_count(rx_bi->page) == 1) &&
1043                             (page_to_nid(rx_bi->page) == current_node))
1044                                 get_page(rx_bi->page);
1045                         else
1046                                 rx_bi->page = NULL;
1047
1048                         dma_unmap_page(rx_ring->dev,
1049                                        rx_bi->page_dma,
1050                                        PAGE_SIZE / 2,
1051                                        DMA_FROM_DEVICE);
1052                         rx_bi->page_dma = 0;
1053                 }
1054                 I40E_RX_INCREMENT(rx_ring, i);
1055
1056                 if (unlikely(
1057                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1058                         struct i40e_rx_buffer *next_buffer;
1059
1060                         next_buffer = &rx_ring->rx_bi[i];
1061                         next_buffer->skb = skb;
1062                         rx_ring->rx_stats.non_eop_descs++;
1063                         continue;
1064                 }
1065
1066                 /* ERR_MASK will only have valid bits if EOP set */
1067                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1068                         dev_kfree_skb_any(skb);
1069                         continue;
1070                 }
1071
1072                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1073                              i40e_ptype_to_hash(rx_ptype));
1074                 /* probably a little skewed due to removing CRC */
1075                 total_rx_bytes += skb->len;
1076                 total_rx_packets++;
1077
1078                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1079
1080                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1081
1082                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1083                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1084                          : 0;
1085 #ifdef I40E_FCOE
1086                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1087                         dev_kfree_skb_any(skb);
1088                         continue;
1089                 }
1090 #endif
1091                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1092                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1093
1094                 rx_desc->wb.qword1.status_error_len = 0;
1095
1096         } while (likely(total_rx_packets < budget));
1097
1098         u64_stats_update_begin(&rx_ring->syncp);
1099         rx_ring->stats.packets += total_rx_packets;
1100         rx_ring->stats.bytes += total_rx_bytes;
1101         u64_stats_update_end(&rx_ring->syncp);
1102         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1103         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1104
1105         return total_rx_packets;
1106 }
1107
1108 /**
1109  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1110  * @rx_ring:  rx ring to clean
1111  * @budget:   how many cleans we're allowed
1112  *
1113  * Returns number of packets cleaned
1114  **/
1115 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1116 {
1117         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1118         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1119         struct i40e_vsi *vsi = rx_ring->vsi;
1120         union i40e_rx_desc *rx_desc;
1121         u32 rx_error, rx_status;
1122         u16 rx_packet_len;
1123         u8 rx_ptype;
1124         u64 qword;
1125         u16 i;
1126
1127         do {
1128                 struct i40e_rx_buffer *rx_bi;
1129                 struct sk_buff *skb;
1130                 u16 vlan_tag;
1131                 /* return some buffers to hardware, one at a time is too slow */
1132                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1133                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1134                         cleaned_count = 0;
1135                 }
1136
1137                 i = rx_ring->next_to_clean;
1138                 rx_desc = I40E_RX_DESC(rx_ring, i);
1139                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1140                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1141                         I40E_RXD_QW1_STATUS_SHIFT;
1142
1143                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1144                         break;
1145
1146                 /* This memory barrier is needed to keep us from reading
1147                  * any other fields out of the rx_desc until we know the
1148                  * DD bit is set.
1149                  */
1150                 dma_rmb();
1151
1152                 rx_bi = &rx_ring->rx_bi[i];
1153                 skb = rx_bi->skb;
1154                 prefetch(skb->data);
1155
1156                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1157                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1158
1159                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1160                            I40E_RXD_QW1_ERROR_SHIFT;
1161                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1162
1163                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1164                            I40E_RXD_QW1_PTYPE_SHIFT;
1165                 rx_bi->skb = NULL;
1166                 cleaned_count++;
1167
1168                 /* Get the header and possibly the whole packet
1169                  * If this is an skb from previous receive dma will be 0
1170                  */
1171                 skb_put(skb, rx_packet_len);
1172                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1173                                  DMA_FROM_DEVICE);
1174                 rx_bi->dma = 0;
1175
1176                 I40E_RX_INCREMENT(rx_ring, i);
1177
1178                 if (unlikely(
1179                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1180                         rx_ring->rx_stats.non_eop_descs++;
1181                         continue;
1182                 }
1183
1184                 /* ERR_MASK will only have valid bits if EOP set */
1185                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1186                         dev_kfree_skb_any(skb);
1187                         continue;
1188                 }
1189
1190                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1191                              i40e_ptype_to_hash(rx_ptype));
1192                 /* probably a little skewed due to removing CRC */
1193                 total_rx_bytes += skb->len;
1194                 total_rx_packets++;
1195
1196                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1197
1198                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1199
1200                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1201                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1202                          : 0;
1203                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1204
1205                 rx_desc->wb.qword1.status_error_len = 0;
1206         } while (likely(total_rx_packets < budget));
1207
1208         u64_stats_update_begin(&rx_ring->syncp);
1209         rx_ring->stats.packets += total_rx_packets;
1210         rx_ring->stats.bytes += total_rx_bytes;
1211         u64_stats_update_end(&rx_ring->syncp);
1212         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1213         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1214
1215         return total_rx_packets;
1216 }
1217
1218 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1219 {
1220         u32 val;
1221
1222         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1223               I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1224               (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1225               (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1226
1227         return val;
1228 }
1229
1230 /* a small macro to shorten up some long lines */
1231 #define INTREG I40E_VFINT_DYN_CTLN1
1232
1233 /**
1234  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1235  * @vsi: the VSI we care about
1236  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1237  *
1238  **/
1239 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1240                                           struct i40e_q_vector *q_vector)
1241 {
1242         struct i40e_hw *hw = &vsi->back->hw;
1243         bool rx = false, tx = false;
1244         u32 rxval, txval;
1245         int vector;
1246
1247         vector = (q_vector->v_idx + vsi->base_vector);
1248         rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1249
1250         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1251                 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1252                 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1253         }
1254         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1255                 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1256                 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1257         }
1258         if (rx || tx) {
1259                 /* get the higher of the two ITR adjustments and
1260                  * use the same value for both ITR registers
1261                  * when in adaptive mode (Rx and/or Tx)
1262                  */
1263                 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1264
1265                 q_vector->tx.itr = q_vector->rx.itr = itr;
1266                 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1267                 tx = true;
1268                 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1269                 rx = true;
1270         }
1271
1272         /* only need to enable the interrupt once, but need
1273          * to possibly update both ITR values
1274          */
1275         if (rx) {
1276                 /* set the INTENA_MSK_MASK so that this first write
1277                  * won't actually enable the interrupt, instead just
1278                  * updating the ITR (it's bit 31 PF and VF)
1279                  */
1280                 rxval |= BIT(31);
1281                 /* don't check _DOWN because interrupt isn't being enabled */
1282                 wr32(hw, INTREG(vector - 1), rxval);
1283         }
1284
1285         if (!test_bit(__I40E_DOWN, &vsi->state))
1286                 wr32(hw, INTREG(vector - 1), txval);
1287 }
1288
1289 /**
1290  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1291  * @napi: napi struct with our devices info in it
1292  * @budget: amount of work driver is allowed to do this pass, in packets
1293  *
1294  * This function will clean all queues associated with a q_vector.
1295  *
1296  * Returns the amount of work done
1297  **/
1298 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1299 {
1300         struct i40e_q_vector *q_vector =
1301                                container_of(napi, struct i40e_q_vector, napi);
1302         struct i40e_vsi *vsi = q_vector->vsi;
1303         struct i40e_ring *ring;
1304         bool clean_complete = true;
1305         bool arm_wb = false;
1306         int budget_per_ring;
1307         int work_done = 0;
1308
1309         if (test_bit(__I40E_DOWN, &vsi->state)) {
1310                 napi_complete(napi);
1311                 return 0;
1312         }
1313
1314         /* Since the actual Tx work is minimal, we can give the Tx a larger
1315          * budget and be more aggressive about cleaning up the Tx descriptors.
1316          */
1317         i40e_for_each_ring(ring, q_vector->tx) {
1318                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1319                 arm_wb |= ring->arm_wb;
1320                 ring->arm_wb = false;
1321         }
1322
1323         /* Handle case where we are called by netpoll with a budget of 0 */
1324         if (budget <= 0)
1325                 goto tx_only;
1326
1327         /* We attempt to distribute budget to each Rx queue fairly, but don't
1328          * allow the budget to go below 1 because that would exit polling early.
1329          */
1330         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1331
1332         i40e_for_each_ring(ring, q_vector->rx) {
1333                 int cleaned;
1334
1335                 if (ring_is_ps_enabled(ring))
1336                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1337                 else
1338                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1339
1340                 work_done += cleaned;
1341                 /* if we didn't clean as many as budgeted, we must be done */
1342                 clean_complete &= (budget_per_ring != cleaned);
1343         }
1344
1345         /* If work not completed, return budget and polling will return */
1346         if (!clean_complete) {
1347 tx_only:
1348                 if (arm_wb)
1349                         i40evf_force_wb(vsi, q_vector);
1350                 return budget;
1351         }
1352
1353         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1354                 q_vector->arm_wb_state = false;
1355
1356         /* Work is done so exit the polling mode and re-enable the interrupt */
1357         napi_complete_done(napi, work_done);
1358         i40e_update_enable_itr(vsi, q_vector);
1359         return 0;
1360 }
1361
1362 /**
1363  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1364  * @skb:     send buffer
1365  * @tx_ring: ring to send buffer on
1366  * @flags:   the tx flags to be set
1367  *
1368  * Checks the skb and set up correspondingly several generic transmit flags
1369  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1370  *
1371  * Returns error code indicate the frame should be dropped upon error and the
1372  * otherwise  returns 0 to indicate the flags has been set properly.
1373  **/
1374 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1375                                                struct i40e_ring *tx_ring,
1376                                                u32 *flags)
1377 {
1378         __be16 protocol = skb->protocol;
1379         u32  tx_flags = 0;
1380
1381         if (protocol == htons(ETH_P_8021Q) &&
1382             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1383                 /* When HW VLAN acceleration is turned off by the user the
1384                  * stack sets the protocol to 8021q so that the driver
1385                  * can take any steps required to support the SW only
1386                  * VLAN handling.  In our case the driver doesn't need
1387                  * to take any further steps so just set the protocol
1388                  * to the encapsulated ethertype.
1389                  */
1390                 skb->protocol = vlan_get_protocol(skb);
1391                 goto out;
1392         }
1393
1394         /* if we have a HW VLAN tag being added, default to the HW one */
1395         if (skb_vlan_tag_present(skb)) {
1396                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1397                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1398         /* else if it is a SW VLAN, check the next protocol and store the tag */
1399         } else if (protocol == htons(ETH_P_8021Q)) {
1400                 struct vlan_hdr *vhdr, _vhdr;
1401
1402                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1403                 if (!vhdr)
1404                         return -EINVAL;
1405
1406                 protocol = vhdr->h_vlan_encapsulated_proto;
1407                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1408                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1409         }
1410
1411 out:
1412         *flags = tx_flags;
1413         return 0;
1414 }
1415
1416 /**
1417  * i40e_tso - set up the tso context descriptor
1418  * @tx_ring:  ptr to the ring to send
1419  * @skb:      ptr to the skb we're sending
1420  * @hdr_len:  ptr to the size of the packet header
1421  * @cd_tunneling: ptr to context descriptor bits
1422  *
1423  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1424  **/
1425 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1426                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1427                     u32 *cd_tunneling)
1428 {
1429         u32 cd_cmd, cd_tso_len, cd_mss;
1430         struct ipv6hdr *ipv6h;
1431         struct tcphdr *tcph;
1432         struct iphdr *iph;
1433         u32 l4len;
1434         int err;
1435
1436         if (!skb_is_gso(skb))
1437                 return 0;
1438
1439         err = skb_cow_head(skb, 0);
1440         if (err < 0)
1441                 return err;
1442
1443         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1444         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1445
1446         if (iph->version == 4) {
1447                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1448                 iph->tot_len = 0;
1449                 iph->check = 0;
1450                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1451                                                  0, IPPROTO_TCP, 0);
1452         } else if (ipv6h->version == 6) {
1453                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1454                 ipv6h->payload_len = 0;
1455                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1456                                                0, IPPROTO_TCP, 0);
1457         }
1458
1459         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1460         *hdr_len = (skb->encapsulation
1461                     ? (skb_inner_transport_header(skb) - skb->data)
1462                     : skb_transport_offset(skb)) + l4len;
1463
1464         /* find the field values */
1465         cd_cmd = I40E_TX_CTX_DESC_TSO;
1466         cd_tso_len = skb->len - *hdr_len;
1467         cd_mss = skb_shinfo(skb)->gso_size;
1468         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1469                                 ((u64)cd_tso_len <<
1470                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1471                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1472         return 1;
1473 }
1474
1475 /**
1476  * i40e_tx_enable_csum - Enable Tx checksum offloads
1477  * @skb: send buffer
1478  * @tx_flags: pointer to Tx flags currently set
1479  * @td_cmd: Tx descriptor command bits to set
1480  * @td_offset: Tx descriptor header offsets to set
1481  * @cd_tunneling: ptr to context desc bits
1482  **/
1483 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1484                                 u32 *td_cmd, u32 *td_offset,
1485                                 struct i40e_ring *tx_ring,
1486                                 u32 *cd_tunneling)
1487 {
1488         struct ipv6hdr *this_ipv6_hdr;
1489         unsigned int this_tcp_hdrlen;
1490         struct iphdr *this_ip_hdr;
1491         u32 network_hdr_len;
1492         u8 l4_hdr = 0;
1493         struct udphdr *oudph;
1494         struct iphdr *oiph;
1495         u32 l4_tunnel = 0;
1496
1497         if (skb->encapsulation) {
1498                 switch (ip_hdr(skb)->protocol) {
1499                 case IPPROTO_UDP:
1500                         oudph = udp_hdr(skb);
1501                         oiph = ip_hdr(skb);
1502                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1503                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1504                         break;
1505                 default:
1506                         return;
1507                 }
1508                 network_hdr_len = skb_inner_network_header_len(skb);
1509                 this_ip_hdr = inner_ip_hdr(skb);
1510                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1511                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1512
1513                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1514                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1515                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1516                                 ip_hdr(skb)->check = 0;
1517                         } else {
1518                                 *cd_tunneling |=
1519                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1520                         }
1521                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1522                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1523                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1524                                 ip_hdr(skb)->check = 0;
1525                 }
1526
1527                 /* Now set the ctx descriptor fields */
1528                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1529                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1530                                    l4_tunnel                             |
1531                                    ((skb_inner_network_offset(skb) -
1532                                         skb_transport_offset(skb)) >> 1) <<
1533                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1534                 if (this_ip_hdr->version == 6) {
1535                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1536                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1537                 }
1538
1539
1540                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1541                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1542                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1543                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1544                                         oiph->daddr,
1545                                         (skb->len - skb_transport_offset(skb)),
1546                                         IPPROTO_UDP, 0);
1547                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1548                 }
1549         } else {
1550                 network_hdr_len = skb_network_header_len(skb);
1551                 this_ip_hdr = ip_hdr(skb);
1552                 this_ipv6_hdr = ipv6_hdr(skb);
1553                 this_tcp_hdrlen = tcp_hdrlen(skb);
1554         }
1555
1556         /* Enable IP checksum offloads */
1557         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1558                 l4_hdr = this_ip_hdr->protocol;
1559                 /* the stack computes the IP header already, the only time we
1560                  * need the hardware to recompute it is in the case of TSO.
1561                  */
1562                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1563                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1564                         this_ip_hdr->check = 0;
1565                 } else {
1566                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1567                 }
1568                 /* Now set the td_offset for IP header length */
1569                 *td_offset = (network_hdr_len >> 2) <<
1570                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1571         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1572                 l4_hdr = this_ipv6_hdr->nexthdr;
1573                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1574                 /* Now set the td_offset for IP header length */
1575                 *td_offset = (network_hdr_len >> 2) <<
1576                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1577         }
1578         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1579         *td_offset |= (skb_network_offset(skb) >> 1) <<
1580                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1581
1582         /* Enable L4 checksum offloads */
1583         switch (l4_hdr) {
1584         case IPPROTO_TCP:
1585                 /* enable checksum offloads */
1586                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1587                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1588                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1589                 break;
1590         case IPPROTO_SCTP:
1591                 /* enable SCTP checksum offload */
1592                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1593                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1594                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1595                 break;
1596         case IPPROTO_UDP:
1597                 /* enable UDP checksum offload */
1598                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1599                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1600                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1601                 break;
1602         default:
1603                 break;
1604         }
1605 }
1606
1607 /**
1608  * i40e_create_tx_ctx Build the Tx context descriptor
1609  * @tx_ring:  ring to create the descriptor on
1610  * @cd_type_cmd_tso_mss: Quad Word 1
1611  * @cd_tunneling: Quad Word 0 - bits 0-31
1612  * @cd_l2tag2: Quad Word 0 - bits 32-63
1613  **/
1614 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1615                                const u64 cd_type_cmd_tso_mss,
1616                                const u32 cd_tunneling, const u32 cd_l2tag2)
1617 {
1618         struct i40e_tx_context_desc *context_desc;
1619         int i = tx_ring->next_to_use;
1620
1621         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1622             !cd_tunneling && !cd_l2tag2)
1623                 return;
1624
1625         /* grab the next descriptor */
1626         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1627
1628         i++;
1629         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1630
1631         /* cpu_to_le32 and assign to struct fields */
1632         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1633         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1634         context_desc->rsvd = cpu_to_le16(0);
1635         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1636 }
1637
1638  /**
1639  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1640  * @skb:      send buffer
1641  * @tx_flags: collected send information
1642  *
1643  * Note: Our HW can't scatter-gather more than 8 fragments to build
1644  * a packet on the wire and so we need to figure out the cases where we
1645  * need to linearize the skb.
1646  **/
1647 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1648 {
1649         struct skb_frag_struct *frag;
1650         bool linearize = false;
1651         unsigned int size = 0;
1652         u16 num_frags;
1653         u16 gso_segs;
1654
1655         num_frags = skb_shinfo(skb)->nr_frags;
1656         gso_segs = skb_shinfo(skb)->gso_segs;
1657
1658         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1659                 u16 j = 0;
1660
1661                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1662                         goto linearize_chk_done;
1663                 /* try the simple math, if we have too many frags per segment */
1664                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1665                     I40E_MAX_BUFFER_TXD) {
1666                         linearize = true;
1667                         goto linearize_chk_done;
1668                 }
1669                 frag = &skb_shinfo(skb)->frags[0];
1670                 /* we might still have more fragments per segment */
1671                 do {
1672                         size += skb_frag_size(frag);
1673                         frag++; j++;
1674                         if ((size >= skb_shinfo(skb)->gso_size) &&
1675                             (j < I40E_MAX_BUFFER_TXD)) {
1676                                 size = (size % skb_shinfo(skb)->gso_size);
1677                                 j = (size) ? 1 : 0;
1678                         }
1679                         if (j == I40E_MAX_BUFFER_TXD) {
1680                                 linearize = true;
1681                                 break;
1682                         }
1683                         num_frags--;
1684                 } while (num_frags);
1685         } else {
1686                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1687                         linearize = true;
1688         }
1689
1690 linearize_chk_done:
1691         return linearize;
1692 }
1693
1694 /**
1695  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1696  * @tx_ring: the ring to be checked
1697  * @size:    the size buffer we want to assure is available
1698  *
1699  * Returns -EBUSY if a stop is needed, else 0
1700  **/
1701 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1702 {
1703         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1704         /* Memory barrier before checking head and tail */
1705         smp_mb();
1706
1707         /* Check again in a case another CPU has just made room available. */
1708         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1709                 return -EBUSY;
1710
1711         /* A reprieve! - use start_queue because it doesn't call schedule */
1712         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1713         ++tx_ring->tx_stats.restart_queue;
1714         return 0;
1715 }
1716
1717 /**
1718  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1719  * @tx_ring: the ring to be checked
1720  * @size:    the size buffer we want to assure is available
1721  *
1722  * Returns 0 if stop is not needed
1723  **/
1724 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1725 {
1726         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1727                 return 0;
1728         return __i40evf_maybe_stop_tx(tx_ring, size);
1729 }
1730
1731 /**
1732  * i40evf_tx_map - Build the Tx descriptor
1733  * @tx_ring:  ring to send buffer on
1734  * @skb:      send buffer
1735  * @first:    first buffer info buffer to use
1736  * @tx_flags: collected send information
1737  * @hdr_len:  size of the packet header
1738  * @td_cmd:   the command field in the descriptor
1739  * @td_offset: offset for checksum or crc
1740  **/
1741 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1742                                  struct i40e_tx_buffer *first, u32 tx_flags,
1743                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1744 {
1745         unsigned int data_len = skb->data_len;
1746         unsigned int size = skb_headlen(skb);
1747         struct skb_frag_struct *frag;
1748         struct i40e_tx_buffer *tx_bi;
1749         struct i40e_tx_desc *tx_desc;
1750         u16 i = tx_ring->next_to_use;
1751         u32 td_tag = 0;
1752         dma_addr_t dma;
1753         u16 gso_segs;
1754
1755         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1756                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1757                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1758                          I40E_TX_FLAGS_VLAN_SHIFT;
1759         }
1760
1761         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1762                 gso_segs = skb_shinfo(skb)->gso_segs;
1763         else
1764                 gso_segs = 1;
1765
1766         /* multiply data chunks by size of headers */
1767         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1768         first->gso_segs = gso_segs;
1769         first->skb = skb;
1770         first->tx_flags = tx_flags;
1771
1772         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1773
1774         tx_desc = I40E_TX_DESC(tx_ring, i);
1775         tx_bi = first;
1776
1777         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1778                 if (dma_mapping_error(tx_ring->dev, dma))
1779                         goto dma_error;
1780
1781                 /* record length, and DMA address */
1782                 dma_unmap_len_set(tx_bi, len, size);
1783                 dma_unmap_addr_set(tx_bi, dma, dma);
1784
1785                 tx_desc->buffer_addr = cpu_to_le64(dma);
1786
1787                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1788                         tx_desc->cmd_type_offset_bsz =
1789                                 build_ctob(td_cmd, td_offset,
1790                                            I40E_MAX_DATA_PER_TXD, td_tag);
1791
1792                         tx_desc++;
1793                         i++;
1794                         if (i == tx_ring->count) {
1795                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1796                                 i = 0;
1797                         }
1798
1799                         dma += I40E_MAX_DATA_PER_TXD;
1800                         size -= I40E_MAX_DATA_PER_TXD;
1801
1802                         tx_desc->buffer_addr = cpu_to_le64(dma);
1803                 }
1804
1805                 if (likely(!data_len))
1806                         break;
1807
1808                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1809                                                           size, td_tag);
1810
1811                 tx_desc++;
1812                 i++;
1813                 if (i == tx_ring->count) {
1814                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1815                         i = 0;
1816                 }
1817
1818                 size = skb_frag_size(frag);
1819                 data_len -= size;
1820
1821                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1822                                        DMA_TO_DEVICE);
1823
1824                 tx_bi = &tx_ring->tx_bi[i];
1825         }
1826
1827         /* Place RS bit on last descriptor of any packet that spans across the
1828          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1829          */
1830 #define WB_STRIDE 0x3
1831         if (((i & WB_STRIDE) != WB_STRIDE) &&
1832             (first <= &tx_ring->tx_bi[i]) &&
1833             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1834                 tx_desc->cmd_type_offset_bsz =
1835                         build_ctob(td_cmd, td_offset, size, td_tag) |
1836                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1837                                          I40E_TXD_QW1_CMD_SHIFT);
1838         } else {
1839                 tx_desc->cmd_type_offset_bsz =
1840                         build_ctob(td_cmd, td_offset, size, td_tag) |
1841                         cpu_to_le64((u64)I40E_TXD_CMD <<
1842                                          I40E_TXD_QW1_CMD_SHIFT);
1843         }
1844
1845         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1846                                                  tx_ring->queue_index),
1847                              first->bytecount);
1848
1849         /* Force memory writes to complete before letting h/w
1850          * know there are new descriptors to fetch.  (Only
1851          * applicable for weak-ordered memory model archs,
1852          * such as IA-64).
1853          */
1854         wmb();
1855
1856         /* set next_to_watch value indicating a packet is present */
1857         first->next_to_watch = tx_desc;
1858
1859         i++;
1860         if (i == tx_ring->count)
1861                 i = 0;
1862
1863         tx_ring->next_to_use = i;
1864
1865         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1866         /* notify HW of packet */
1867         if (!skb->xmit_more ||
1868             netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1869                                                    tx_ring->queue_index)))
1870                 writel(i, tx_ring->tail);
1871         else
1872                 prefetchw(tx_desc + 1);
1873
1874         return;
1875
1876 dma_error:
1877         dev_info(tx_ring->dev, "TX DMA map failed\n");
1878
1879         /* clear dma mappings for failed tx_bi map */
1880         for (;;) {
1881                 tx_bi = &tx_ring->tx_bi[i];
1882                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1883                 if (tx_bi == first)
1884                         break;
1885                 if (i == 0)
1886                         i = tx_ring->count;
1887                 i--;
1888         }
1889
1890         tx_ring->next_to_use = i;
1891 }
1892
1893 /**
1894  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1895  * @skb:     send buffer
1896  * @tx_ring: ring to send buffer on
1897  *
1898  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1899  * there is not enough descriptors available in this ring since we need at least
1900  * one descriptor.
1901  **/
1902 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1903                                                struct i40e_ring *tx_ring)
1904 {
1905         unsigned int f;
1906         int count = 0;
1907
1908         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1909          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1910          *       + 4 desc gap to avoid the cache line where head is,
1911          *       + 1 desc for context descriptor,
1912          * otherwise try next time
1913          */
1914         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1915                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1916
1917         count += TXD_USE_COUNT(skb_headlen(skb));
1918         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1919                 tx_ring->tx_stats.tx_busy++;
1920                 return 0;
1921         }
1922         return count;
1923 }
1924
1925 /**
1926  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1927  * @skb:     send buffer
1928  * @tx_ring: ring to send buffer on
1929  *
1930  * Returns NETDEV_TX_OK if sent, else an error code
1931  **/
1932 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1933                                         struct i40e_ring *tx_ring)
1934 {
1935         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1936         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1937         struct i40e_tx_buffer *first;
1938         u32 td_offset = 0;
1939         u32 tx_flags = 0;
1940         __be16 protocol;
1941         u32 td_cmd = 0;
1942         u8 hdr_len = 0;
1943         int tso;
1944
1945         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
1946                 return NETDEV_TX_BUSY;
1947
1948         /* prepare the xmit flags */
1949         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1950                 goto out_drop;
1951
1952         /* obtain protocol of skb */
1953         protocol = vlan_get_protocol(skb);
1954
1955         /* record the location of the first descriptor for this packet */
1956         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1957
1958         /* setup IPv4/IPv6 offloads */
1959         if (protocol == htons(ETH_P_IP))
1960                 tx_flags |= I40E_TX_FLAGS_IPV4;
1961         else if (protocol == htons(ETH_P_IPV6))
1962                 tx_flags |= I40E_TX_FLAGS_IPV6;
1963
1964         tso = i40e_tso(tx_ring, skb, &hdr_len,
1965                        &cd_type_cmd_tso_mss, &cd_tunneling);
1966
1967         if (tso < 0)
1968                 goto out_drop;
1969         else if (tso)
1970                 tx_flags |= I40E_TX_FLAGS_TSO;
1971
1972         if (i40e_chk_linearize(skb, tx_flags)) {
1973                 if (skb_linearize(skb))
1974                         goto out_drop;
1975                 tx_ring->tx_stats.tx_linearize++;
1976         }
1977         skb_tx_timestamp(skb);
1978
1979         /* always enable CRC insertion offload */
1980         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1981
1982         /* Always offload the checksum, since it's in the data descriptor */
1983         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1984                 tx_flags |= I40E_TX_FLAGS_CSUM;
1985
1986                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
1987                                     tx_ring, &cd_tunneling);
1988         }
1989
1990         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1991                            cd_tunneling, cd_l2tag2);
1992
1993         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1994                       td_cmd, td_offset);
1995
1996         return NETDEV_TX_OK;
1997
1998 out_drop:
1999         dev_kfree_skb_any(skb);
2000         return NETDEV_TX_OK;
2001 }
2002
2003 /**
2004  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2005  * @skb:    send buffer
2006  * @netdev: network interface device structure
2007  *
2008  * Returns NETDEV_TX_OK if sent, else an error code
2009  **/
2010 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2011 {
2012         struct i40evf_adapter *adapter = netdev_priv(netdev);
2013         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
2014
2015         /* hardware can't handle really short frames, hardware padding works
2016          * beyond this point
2017          */
2018         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2019                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2020                         return NETDEV_TX_OK;
2021                 skb->len = I40E_MIN_TX_LEN;
2022                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2023         }
2024
2025         return i40e_xmit_frame_ring(skb, tx_ring);
2026 }