drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  55                         kfree(tx_buffer->raw_buf);
  56                 else
  57                         dev_kfree_skb_any(tx_buffer->skb);
  58
  59                 if (dma_unmap_len(tx_buffer, len))
  60                         dma_unmap_single(ring->dev,
  61                                          dma_unmap_addr(tx_buffer, dma),
  62                                          dma_unmap_len(tx_buffer, len),
  63                                          DMA_TO_DEVICE);
  64         } else if (dma_unmap_len(tx_buffer, len)) {
  65                 dma_unmap_page(ring->dev,
  66                                dma_unmap_addr(tx_buffer, dma),
  67                                dma_unmap_len(tx_buffer, len),
  68                                DMA_TO_DEVICE);
  69         }
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 #define WB_STRIDE 0x3
 144
 145 /**
 146  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 147  * @tx_ring:  tx ring to clean
 148  * @budget:   how many cleans we're allowed
 149  *
 150  * Returns true if there's any budget left (e.g. the clean is finished)
 151  **/
 152 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 153 {
 154         u16 i = tx_ring->next_to_clean;
 155         struct i40e_tx_buffer *tx_buf;
 156         struct i40e_tx_desc *tx_head;
 157         struct i40e_tx_desc *tx_desc;
 158         unsigned int total_packets = 0;
 159         unsigned int total_bytes = 0;
 160
 161         tx_buf = &tx_ring->tx_bi[i];
 162         tx_desc = I40E_TX_DESC(tx_ring, i);
 163         i -= tx_ring->count;
 164
 165         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 166
 167         do {
 168                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 169
 170                 /* if next_to_watch is not set then there is no work pending */
 171                 if (!eop_desc)
 172                         break;
 173
 174                 /* prevent any other reads prior to eop_desc */
 175                 read_barrier_depends();
 176
 177                 /* we have caught up to head, no work left to do */
 178                 if (tx_head == tx_desc)
 179                         break;
 180
 181                 /* clear next_to_watch to prevent false hangs */
 182                 tx_buf->next_to_watch = NULL;
 183
 184                 /* update the statistics for this packet */
 185                 total_bytes += tx_buf->bytecount;
 186                 total_packets += tx_buf->gso_segs;
 187
 188                 /* free the skb */
 189                 dev_kfree_skb_any(tx_buf->skb);
 190
 191                 /* unmap skb header data */
 192                 dma_unmap_single(tx_ring->dev,
 193                                  dma_unmap_addr(tx_buf, dma),
 194                                  dma_unmap_len(tx_buf, len),
 195                                  DMA_TO_DEVICE);
 196
 197                 /* clear tx_buffer data */
 198                 tx_buf->skb = NULL;
 199                 dma_unmap_len_set(tx_buf, len, 0);
 200
 201                 /* unmap remaining buffers */
 202                 while (tx_desc != eop_desc) {
 203
 204                         tx_buf++;
 205                         tx_desc++;
 206                         i++;
 207                         if (unlikely(!i)) {
 208                                 i -= tx_ring->count;
 209                                 tx_buf = tx_ring->tx_bi;
 210                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 211                         }
 212
 213                         /* unmap any remaining paged data */
 214                         if (dma_unmap_len(tx_buf, len)) {
 215                                 dma_unmap_page(tx_ring->dev,
 216                                                dma_unmap_addr(tx_buf, dma),
 217                                                dma_unmap_len(tx_buf, len),
 218                                                DMA_TO_DEVICE);
 219                                 dma_unmap_len_set(tx_buf, len, 0);
 220                         }
 221                 }
 222
 223                 /* move us one more past the eop_desc for start of next pkt */
 224                 tx_buf++;
 225                 tx_desc++;
 226                 i++;
 227                 if (unlikely(!i)) {
 228                         i -= tx_ring->count;
 229                         tx_buf = tx_ring->tx_bi;
 230                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 231                 }
 232
 233                 prefetch(tx_desc);
 234
 235                 /* update budget accounting */
 236                 budget--;
 237         } while (likely(budget));
 238
 239         i += tx_ring->count;
 240         tx_ring->next_to_clean = i;
 241         u64_stats_update_begin(&tx_ring->syncp);
 242         tx_ring->stats.bytes += total_bytes;
 243         tx_ring->stats.packets += total_packets;
 244         u64_stats_update_end(&tx_ring->syncp);
 245         tx_ring->q_vector->tx.total_bytes += total_bytes;
 246         tx_ring->q_vector->tx.total_packets += total_packets;
 247
 248         /* check to see if there are any non-cache aligned descriptors
 249          * waiting to be written back, and kick the hardware to force
 250          * them to be written back in case of napi polling
 251          */
 252         if (budget &&
 253             !((i & WB_STRIDE) == WB_STRIDE) &&
 254             !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 255             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 256                 tx_ring->arm_wb = true;
 257
 258         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 259                                                       tx_ring->queue_index),
 260                                   total_packets, total_bytes);
 261
 262 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 263         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 264                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 265                 /* Make sure that anybody stopping the queue after this
 266                  * sees the new next_to_clean.
 267                  */
 268                 smp_mb();
 269                 if (__netif_subqueue_stopped(tx_ring->netdev,
 270                                              tx_ring->queue_index) &&
 271                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 272                         netif_wake_subqueue(tx_ring->netdev,
 273                                             tx_ring->queue_index);
 274                         ++tx_ring->tx_stats.restart_queue;
 275                 }
 276         }
 277
 278         return !!budget;
 279 }
 280
 281 /**
 282  * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 283  * @vsi: the VSI we care about
 284  * @q_vector: the vector  on which to force writeback
 285  *
 286  **/
 287 static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 288 {
 289         u16 flags = q_vector->tx.ring[0].flags;
 290
 291         if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
 292                 u32 val;
 293
 294                 if (q_vector->arm_wb_state)
 295                         return;
 296
 297                 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
 298
 299                 wr32(&vsi->back->hw,
 300                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 301                                           vsi->base_vector - 1),
 302                      val);
 303                 q_vector->arm_wb_state = true;
 304         } else {
 305                 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 306                           I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 307                           I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 308                           I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
 309                           /* allow 00 to be written to the index */
 310
 311                 wr32(&vsi->back->hw,
 312                      I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
 313                                           vsi->base_vector - 1), val);
 314         }
 315 }
 316
 317 /**
 318  * i40e_set_new_dynamic_itr - Find new ITR level
 319  * @rc: structure containing ring performance data
 320  *
 321  * Stores a new ITR value based on packets and byte counts during
 322  * the last interrupt.  The advantage of per interrupt computation
 323  * is faster updates and more accurate ITR for the current traffic
 324  * pattern.  Constants in this function were computed based on
 325  * theoretical maximum wire speed and thresholds were set based on
 326  * testing data as well as attempting to minimize response time
 327  * while increasing bulk throughput.
 328  **/
 329 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 330 {
 331         enum i40e_latency_range new_latency_range = rc->latency_range;
 332         u32 new_itr = rc->itr;
 333         int bytes_per_int;
 334
 335         if (rc->total_packets == 0 || !rc->itr)
 336                 return;
 337
 338         /* simple throttlerate management
 339          *   0-10MB/s   lowest (100000 ints/s)
 340          *  10-20MB/s   low    (20000 ints/s)
 341          *  20-1249MB/s bulk   (8000 ints/s)
 342          */
 343         bytes_per_int = rc->total_bytes / rc->itr;
 344         switch (new_latency_range) {
 345         case I40E_LOWEST_LATENCY:
 346                 if (bytes_per_int > 10)
 347                         new_latency_range = I40E_LOW_LATENCY;
 348                 break;
 349         case I40E_LOW_LATENCY:
 350                 if (bytes_per_int > 20)
 351                         new_latency_range = I40E_BULK_LATENCY;
 352                 else if (bytes_per_int <= 10)
 353                         new_latency_range = I40E_LOWEST_LATENCY;
 354                 break;
 355         case I40E_BULK_LATENCY:
 356                 if (bytes_per_int <= 20)
 357                         new_latency_range = I40E_LOW_LATENCY;
 358                 break;
 359         default:
 360                 if (bytes_per_int <= 20)
 361                         new_latency_range = I40E_LOW_LATENCY;
 362                 break;
 363         }
 364         rc->latency_range = new_latency_range;
 365
 366         switch (new_latency_range) {
 367         case I40E_LOWEST_LATENCY:
 368                 new_itr = I40E_ITR_100K;
 369                 break;
 370         case I40E_LOW_LATENCY:
 371                 new_itr = I40E_ITR_20K;
 372                 break;
 373         case I40E_BULK_LATENCY:
 374                 new_itr = I40E_ITR_8K;
 375                 break;
 376         default:
 377                 break;
 378         }
 379
 380         if (new_itr != rc->itr)
 381                 rc->itr = new_itr;
 382
 383         rc->total_bytes = 0;
 384         rc->total_packets = 0;
 385 }
 386
 387 /*
 388  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 389  * @tx_ring: the tx ring to set up
 390  *
 391  * Return 0 on success, negative on error
 392  **/
 393 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 394 {
 395         struct device *dev = tx_ring->dev;
 396         int bi_size;
 397
 398         if (!dev)
 399                 return -ENOMEM;
 400
 401         /* warn if we are about to overwrite the pointer */
 402         WARN_ON(tx_ring->tx_bi);
 403         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 404         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 405         if (!tx_ring->tx_bi)
 406                 goto err;
 407
 408         /* round up to nearest 4K */
 409         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 410         /* add u32 for head writeback, align after this takes care of
 411          * guaranteeing this is at least one cache line in size
 412          */
 413         tx_ring->size += sizeof(u32);
 414         tx_ring->size = ALIGN(tx_ring->size, 4096);
 415         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 416                                            &tx_ring->dma, GFP_KERNEL);
 417         if (!tx_ring->desc) {
 418                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 419                          tx_ring->size);
 420                 goto err;
 421         }
 422
 423         tx_ring->next_to_use = 0;
 424         tx_ring->next_to_clean = 0;
 425         return 0;
 426
 427 err:
 428         kfree(tx_ring->tx_bi);
 429         tx_ring->tx_bi = NULL;
 430         return -ENOMEM;
 431 }
 432
 433 /**
 434  * i40evf_clean_rx_ring - Free Rx buffers
 435  * @rx_ring: ring to be cleaned
 436  **/
 437 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 438 {
 439         struct device *dev = rx_ring->dev;
 440         struct i40e_rx_buffer *rx_bi;
 441         unsigned long bi_size;
 442         u16 i;
 443
 444         /* ring already cleared, nothing to do */
 445         if (!rx_ring->rx_bi)
 446                 return;
 447
 448         if (ring_is_ps_enabled(rx_ring)) {
 449                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 450
 451                 rx_bi = &rx_ring->rx_bi[0];
 452                 if (rx_bi->hdr_buf) {
 453                         dma_free_coherent(dev,
 454                                           bufsz,
 455                                           rx_bi->hdr_buf,
 456                                           rx_bi->dma);
 457                         for (i = 0; i < rx_ring->count; i++) {
 458                                 rx_bi = &rx_ring->rx_bi[i];
 459                                 rx_bi->dma = 0;
 460                                 rx_bi->hdr_buf = NULL;
 461                         }
 462                 }
 463         }
 464         /* Free all the Rx ring sk_buffs */
 465         for (i = 0; i < rx_ring->count; i++) {
 466                 rx_bi = &rx_ring->rx_bi[i];
 467                 if (rx_bi->dma) {
 468                         dma_unmap_single(dev,
 469                                          rx_bi->dma,
 470                                          rx_ring->rx_buf_len,
 471                                          DMA_FROM_DEVICE);
 472                         rx_bi->dma = 0;
 473                 }
 474                 if (rx_bi->skb) {
 475                         dev_kfree_skb(rx_bi->skb);
 476                         rx_bi->skb = NULL;
 477                 }
 478                 if (rx_bi->page) {
 479                         if (rx_bi->page_dma) {
 480                                 dma_unmap_page(dev,
 481                                                rx_bi->page_dma,
 482                                                PAGE_SIZE / 2,
 483                                                DMA_FROM_DEVICE);
 484                                 rx_bi->page_dma = 0;
 485                         }
 486                         __free_page(rx_bi->page);
 487                         rx_bi->page = NULL;
 488                         rx_bi->page_offset = 0;
 489                 }
 490         }
 491
 492         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 493         memset(rx_ring->rx_bi, 0, bi_size);
 494
 495         /* Zero out the descriptor ring */
 496         memset(rx_ring->desc, 0, rx_ring->size);
 497
 498         rx_ring->next_to_clean = 0;
 499         rx_ring->next_to_use = 0;
 500 }
 501
 502 /**
 503  * i40evf_free_rx_resources - Free Rx resources
 504  * @rx_ring: ring to clean the resources from
 505  *
 506  * Free all receive software resources
 507  **/
 508 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 509 {
 510         i40evf_clean_rx_ring(rx_ring);
 511         kfree(rx_ring->rx_bi);
 512         rx_ring->rx_bi = NULL;
 513
 514         if (rx_ring->desc) {
 515                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 516                                   rx_ring->desc, rx_ring->dma);
 517                 rx_ring->desc = NULL;
 518         }
 519 }
 520
 521 /**
 522  * i40evf_alloc_rx_headers - allocate rx header buffers
 523  * @rx_ring: ring to alloc buffers
 524  *
 525  * Allocate rx header buffers for the entire ring. As these are static,
 526  * this is only called when setting up a new ring.
 527  **/
 528 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 529 {
 530         struct device *dev = rx_ring->dev;
 531         struct i40e_rx_buffer *rx_bi;
 532         dma_addr_t dma;
 533         void *buffer;
 534         int buf_size;
 535         int i;
 536
 537         if (rx_ring->rx_bi[0].hdr_buf)
 538                 return;
 539         /* Make sure the buffers don't cross cache line boundaries. */
 540         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 541         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 542                                     &dma, GFP_KERNEL);
 543         if (!buffer)
 544                 return;
 545         for (i = 0; i < rx_ring->count; i++) {
 546                 rx_bi = &rx_ring->rx_bi[i];
 547                 rx_bi->dma = dma + (i * buf_size);
 548                 rx_bi->hdr_buf = buffer + (i * buf_size);
 549         }
 550 }
 551
 552 /**
 553  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 554  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 555  *
 556  * Returns 0 on success, negative on failure
 557  **/
 558 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 559 {
 560         struct device *dev = rx_ring->dev;
 561         int bi_size;
 562
 563         /* warn if we are about to overwrite the pointer */
 564         WARN_ON(rx_ring->rx_bi);
 565         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 566         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 567         if (!rx_ring->rx_bi)
 568                 goto err;
 569
 570         u64_stats_init(&rx_ring->syncp);
 571
 572         /* Round up to nearest 4K */
 573         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 574                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 575                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 576         rx_ring->size = ALIGN(rx_ring->size, 4096);
 577         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 578                                            &rx_ring->dma, GFP_KERNEL);
 579
 580         if (!rx_ring->desc) {
 581                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 582                          rx_ring->size);
 583                 goto err;
 584         }
 585
 586         rx_ring->next_to_clean = 0;
 587         rx_ring->next_to_use = 0;
 588
 589         return 0;
 590 err:
 591         kfree(rx_ring->rx_bi);
 592         rx_ring->rx_bi = NULL;
 593         return -ENOMEM;
 594 }
 595
 596 /**
 597  * i40e_release_rx_desc - Store the new tail and head values
 598  * @rx_ring: ring to bump
 599  * @val: new head index
 600  **/
 601 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 602 {
 603         rx_ring->next_to_use = val;
 604         /* Force memory writes to complete before letting h/w
 605          * know there are new descriptors to fetch.  (Only
 606          * applicable for weak-ordered memory model archs,
 607          * such as IA-64).
 608          */
 609         wmb();
 610         writel(val, rx_ring->tail);
 611 }
 612
 613 /**
 614  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 615  * @rx_ring: ring to place buffers on
 616  * @cleaned_count: number of buffers to replace
 617  **/
 618 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 619 {
 620         u16 i = rx_ring->next_to_use;
 621         union i40e_rx_desc *rx_desc;
 622         struct i40e_rx_buffer *bi;
 623
 624         /* do nothing if no valid netdev defined */
 625         if (!rx_ring->netdev || !cleaned_count)
 626                 return;
 627
 628         while (cleaned_count--) {
 629                 rx_desc = I40E_RX_DESC(rx_ring, i);
 630                 bi = &rx_ring->rx_bi[i];
 631
 632                 if (bi->skb) /* desc is in use */
 633                         goto no_buffers;
 634                 if (!bi->page) {
 635                         bi->page = alloc_page(GFP_ATOMIC);
 636                         if (!bi->page) {
 637                                 rx_ring->rx_stats.alloc_page_failed++;
 638                                 goto no_buffers;
 639                         }
 640                 }
 641
 642                 if (!bi->page_dma) {
 643                         /* use a half page if we're re-using */
 644                         bi->page_offset ^= PAGE_SIZE / 2;
 645                         bi->page_dma = dma_map_page(rx_ring->dev,
 646                                                     bi->page,
 647                                                     bi->page_offset,
 648                                                     PAGE_SIZE / 2,
 649                                                     DMA_FROM_DEVICE);
 650                         if (dma_mapping_error(rx_ring->dev,
 651                                               bi->page_dma)) {
 652                                 rx_ring->rx_stats.alloc_page_failed++;
 653                                 bi->page_dma = 0;
 654                                 goto no_buffers;
 655                         }
 656                 }
 657
 658                 dma_sync_single_range_for_device(rx_ring->dev,
 659                                                  bi->dma,
 660                                                  0,
 661                                                  rx_ring->rx_hdr_len,
 662                                                  DMA_FROM_DEVICE);
 663                 /* Refresh the desc even if buffer_addrs didn't change
 664                  * because each write-back erases this info.
 665                  */
 666                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 667                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 668                 i++;
 669                 if (i == rx_ring->count)
 670                         i = 0;
 671         }
 672
 673 no_buffers:
 674         if (rx_ring->next_to_use != i)
 675                 i40e_release_rx_desc(rx_ring, i);
 676 }
 677
 678 /**
 679  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 680  * @rx_ring: ring to place buffers on
 681  * @cleaned_count: number of buffers to replace
 682  **/
 683 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 684 {
 685         u16 i = rx_ring->next_to_use;
 686         union i40e_rx_desc *rx_desc;
 687         struct i40e_rx_buffer *bi;
 688         struct sk_buff *skb;
 689
 690         /* do nothing if no valid netdev defined */
 691         if (!rx_ring->netdev || !cleaned_count)
 692                 return;
 693
 694         while (cleaned_count--) {
 695                 rx_desc = I40E_RX_DESC(rx_ring, i);
 696                 bi = &rx_ring->rx_bi[i];
 697                 skb = bi->skb;
 698
 699                 if (!skb) {
 700                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 701                                                         rx_ring->rx_buf_len);
 702                         if (!skb) {
 703                                 rx_ring->rx_stats.alloc_buff_failed++;
 704                                 goto no_buffers;
 705                         }
 706                         /* initialize queue mapping */
 707                         skb_record_rx_queue(skb, rx_ring->queue_index);
 708                         bi->skb = skb;
 709                 }
 710
 711                 if (!bi->dma) {
 712                         bi->dma = dma_map_single(rx_ring->dev,
 713                                                  skb->data,
 714                                                  rx_ring->rx_buf_len,
 715                                                  DMA_FROM_DEVICE);
 716                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 717                                 rx_ring->rx_stats.alloc_buff_failed++;
 718                                 bi->dma = 0;
 719                                 goto no_buffers;
 720                         }
 721                 }
 722
 723                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 724                 rx_desc->read.hdr_addr = 0;
 725                 i++;
 726                 if (i == rx_ring->count)
 727                         i = 0;
 728         }
 729
 730 no_buffers:
 731         if (rx_ring->next_to_use != i)
 732                 i40e_release_rx_desc(rx_ring, i);
 733 }
 734
 735 /**
 736  * i40e_receive_skb - Send a completed packet up the stack
 737  * @rx_ring:  rx ring in play
 738  * @skb: packet to send up
 739  * @vlan_tag: vlan tag for packet
 740  **/
 741 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 742                              struct sk_buff *skb, u16 vlan_tag)
 743 {
 744         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 745
 746         if (vlan_tag & VLAN_VID_MASK)
 747                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 748
 749         napi_gro_receive(&q_vector->napi, skb);
 750 }
 751
 752 /**
 753  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 754  * @vsi: the VSI we care about
 755  * @skb: skb currently being received and modified
 756  * @rx_status: status value of last descriptor in packet
 757  * @rx_error: error value of last descriptor in packet
 758  * @rx_ptype: ptype value of last descriptor in packet
 759  **/
 760 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 761                                     struct sk_buff *skb,
 762                                     u32 rx_status,
 763                                     u32 rx_error,
 764                                     u16 rx_ptype)
 765 {
 766         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 767         bool ipv4 = false, ipv6 = false;
 768         bool ipv4_tunnel, ipv6_tunnel;
 769         __wsum rx_udp_csum;
 770         struct iphdr *iph;
 771         __sum16 csum;
 772
 773         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 774                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 775         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 776                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 777
 778         skb->ip_summed = CHECKSUM_NONE;
 779
 780         /* Rx csum enabled and ip headers found? */
 781         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 782                 return;
 783
 784         /* did the hardware decode the packet and checksum? */
 785         if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 786                 return;
 787
 788         /* both known and outer_ip must be set for the below code to work */
 789         if (!(decoded.known && decoded.outer_ip))
 790                 return;
 791
 792         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 793             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 794                 ipv4 = true;
 795         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 796                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 797                 ipv6 = true;
 798
 799         if (ipv4 &&
 800             (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
 801                          BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 802                 goto checksum_fail;
 803
 804         /* likely incorrect csum if alternate IP extension headers found */
 805         if (ipv6 &&
 806             rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 807                 /* don't increment checksum err here, non-fatal err */
 808                 return;
 809
 810         /* there was some L4 error, count error and punt packet to the stack */
 811         if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
 812                 goto checksum_fail;
 813
 814         /* handle packets that were not able to be checksummed due
 815          * to arrival speed, in this case the stack can compute
 816          * the csum.
 817          */
 818         if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
 819                 return;
 820
 821         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 822          * it in the driver, hardware does not do it for us.
 823          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 824          * so the total length of IPv4 header is IHL*4 bytes
 825          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 826          */
 827         if (ipv4_tunnel) {
 828                 skb->transport_header = skb->mac_header +
 829                                         sizeof(struct ethhdr) +
 830                                         (ip_hdr(skb)->ihl * 4);
 831
 832                 /* Add 4 bytes for VLAN tagged packets */
 833                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 834                                           skb->protocol == htons(ETH_P_8021AD))
 835                                           ? VLAN_HLEN : 0;
 836
 837                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 838                     (udp_hdr(skb)->check != 0)) {
 839                         rx_udp_csum = udp_csum(skb);
 840                         iph = ip_hdr(skb);
 841                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 842                                                  (skb->len -
 843                                                   skb_transport_offset(skb)),
 844                                                  IPPROTO_UDP, rx_udp_csum);
 845
 846                         if (udp_hdr(skb)->check != csum)
 847                                 goto checksum_fail;
 848
 849                 } /* else its GRE and so no outer UDP header */
 850         }
 851
 852         skb->ip_summed = CHECKSUM_UNNECESSARY;
 853         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 854
 855         return;
 856
 857 checksum_fail:
 858         vsi->back->hw_csum_rx_error++;
 859 }
 860
 861 /**
 862  * i40e_rx_hash - returns the hash value from the Rx descriptor
 863  * @ring: descriptor ring
 864  * @rx_desc: specific descriptor
 865  **/
 866 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 867                                union i40e_rx_desc *rx_desc)
 868 {
 869         const __le64 rss_mask =
 870                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 871                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 872
 873         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 874             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 875                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 876         else
 877                 return 0;
 878 }
 879
 880 /**
 881  * i40e_ptype_to_hash - get a hash type
 882  * @ptype: the ptype value from the descriptor
 883  *
 884  * Returns a hash type to be used by skb_set_hash
 885  **/
 886 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 887 {
 888         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 889
 890         if (!decoded.known)
 891                 return PKT_HASH_TYPE_NONE;
 892
 893         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 894             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 895                 return PKT_HASH_TYPE_L4;
 896         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 897                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 898                 return PKT_HASH_TYPE_L3;
 899         else
 900                 return PKT_HASH_TYPE_L2;
 901 }
 902
 903 /**
 904  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 905  * @rx_ring:  rx ring to clean
 906  * @budget:   how many cleans we're allowed
 907  *
 908  * Returns true if there's any budget left (e.g. the clean is finished)
 909  **/
 910 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 911 {
 912         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 913         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
 914         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
 915         const int current_node = numa_mem_id();
 916         struct i40e_vsi *vsi = rx_ring->vsi;
 917         u16 i = rx_ring->next_to_clean;
 918         union i40e_rx_desc *rx_desc;
 919         u32 rx_error, rx_status;
 920         u8 rx_ptype;
 921         u64 qword;
 922
 923         do {
 924                 struct i40e_rx_buffer *rx_bi;
 925                 struct sk_buff *skb;
 926                 u16 vlan_tag;
 927                 /* return some buffers to hardware, one at a time is too slow */
 928                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
 929                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
 930                         cleaned_count = 0;
 931                 }
 932
 933                 i = rx_ring->next_to_clean;
 934                 rx_desc = I40E_RX_DESC(rx_ring, i);
 935                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
 936                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
 937                         I40E_RXD_QW1_STATUS_SHIFT;
 938
 939                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
 940                         break;
 941
 942                 /* This memory barrier is needed to keep us from reading
 943                  * any other fields out of the rx_desc until we know the
 944                  * DD bit is set.
 945                  */
 946                 dma_rmb();
 947                 rx_bi = &rx_ring->rx_bi[i];
 948                 skb = rx_bi->skb;
 949                 if (likely(!skb)) {
 950                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 951                                                         rx_ring->rx_hdr_len);
 952                         if (!skb) {
 953                                 rx_ring->rx_stats.alloc_buff_failed++;
 954                                 break;
 955                         }
 956
 957                         /* initialize queue mapping */
 958                         skb_record_rx_queue(skb, rx_ring->queue_index);
 959                         /* we are reusing so sync this buffer for CPU use */
 960                         dma_sync_single_range_for_cpu(rx_ring->dev,
 961                                                       rx_bi->dma,
 962                                                       0,
 963                                                       rx_ring->rx_hdr_len,
 964                                                       DMA_FROM_DEVICE);
 965                 }
 966                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 967                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 968                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
 969                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 970                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
 971                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
 972
 973                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
 974                            I40E_RXD_QW1_ERROR_SHIFT;
 975                 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 976                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
 977
 978                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
 979                            I40E_RXD_QW1_PTYPE_SHIFT;
 980                 prefetch(rx_bi->page);
 981                 rx_bi->skb = NULL;
 982                 cleaned_count++;
 983                 if (rx_hbo || rx_sph) {
 984                         int len;
 985
 986                         if (rx_hbo)
 987                                 len = I40E_RX_HDR_SIZE;
 988                         else
 989                                 len = rx_header_len;
 990                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
 991                 } else if (skb->len == 0) {
 992                         int len;
 993
 994                         len = (rx_packet_len > skb_headlen(skb) ?
 995                                 skb_headlen(skb) : rx_packet_len);
 996                         memcpy(__skb_put(skb, len),
 997                                rx_bi->page + rx_bi->page_offset,
 998                                len);
 999                         rx_bi->page_offset += len;
1000                         rx_packet_len -= len;
1001                 }
1002
1003                 /* Get the rest of the data if this was a header split */
1004                 if (rx_packet_len) {
1005                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1006                                            rx_bi->page,
1007                                            rx_bi->page_offset,
1008                                            rx_packet_len);
1009
1010                         skb->len += rx_packet_len;
1011                         skb->data_len += rx_packet_len;
1012                         skb->truesize += rx_packet_len;
1013
1014                         if ((page_count(rx_bi->page) == 1) &&
1015                             (page_to_nid(rx_bi->page) == current_node))
1016                                 get_page(rx_bi->page);
1017                         else
1018                                 rx_bi->page = NULL;
1019
1020                         dma_unmap_page(rx_ring->dev,
1021                                        rx_bi->page_dma,
1022                                        PAGE_SIZE / 2,
1023                                        DMA_FROM_DEVICE);
1024                         rx_bi->page_dma = 0;
1025                 }
1026                 I40E_RX_INCREMENT(rx_ring, i);
1027
1028                 if (unlikely(
1029                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1030                         struct i40e_rx_buffer *next_buffer;
1031
1032                         next_buffer = &rx_ring->rx_bi[i];
1033                         next_buffer->skb = skb;
1034                         rx_ring->rx_stats.non_eop_descs++;
1035                         continue;
1036                 }
1037
1038                 /* ERR_MASK will only have valid bits if EOP set */
1039                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1040                         dev_kfree_skb_any(skb);
1041                         continue;
1042                 }
1043
1044                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1045                              i40e_ptype_to_hash(rx_ptype));
1046                 /* probably a little skewed due to removing CRC */
1047                 total_rx_bytes += skb->len;
1048                 total_rx_packets++;
1049
1050                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1051
1052                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1053
1054                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1055                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1056                          : 0;
1057 #ifdef I40E_FCOE
1058                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1059                         dev_kfree_skb_any(skb);
1060                         continue;
1061                 }
1062 #endif
1063                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1064                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1065
1066                 rx_desc->wb.qword1.status_error_len = 0;
1067
1068         } while (likely(total_rx_packets < budget));
1069
1070         u64_stats_update_begin(&rx_ring->syncp);
1071         rx_ring->stats.packets += total_rx_packets;
1072         rx_ring->stats.bytes += total_rx_bytes;
1073         u64_stats_update_end(&rx_ring->syncp);
1074         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1075         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1076
1077         return total_rx_packets;
1078 }
1079
1080 /**
1081  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1082  * @rx_ring:  rx ring to clean
1083  * @budget:   how many cleans we're allowed
1084  *
1085  * Returns number of packets cleaned
1086  **/
1087 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1088 {
1089         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1090         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1091         struct i40e_vsi *vsi = rx_ring->vsi;
1092         union i40e_rx_desc *rx_desc;
1093         u32 rx_error, rx_status;
1094         u16 rx_packet_len;
1095         u8 rx_ptype;
1096         u64 qword;
1097         u16 i;
1098
1099         do {
1100                 struct i40e_rx_buffer *rx_bi;
1101                 struct sk_buff *skb;
1102                 u16 vlan_tag;
1103                 /* return some buffers to hardware, one at a time is too slow */
1104                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1105                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1106                         cleaned_count = 0;
1107                 }
1108
1109                 i = rx_ring->next_to_clean;
1110                 rx_desc = I40E_RX_DESC(rx_ring, i);
1111                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1112                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1113                         I40E_RXD_QW1_STATUS_SHIFT;
1114
1115                 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1116                         break;
1117
1118                 /* This memory barrier is needed to keep us from reading
1119                  * any other fields out of the rx_desc until we know the
1120                  * DD bit is set.
1121                  */
1122                 dma_rmb();
1123
1124                 rx_bi = &rx_ring->rx_bi[i];
1125                 skb = rx_bi->skb;
1126                 prefetch(skb->data);
1127
1128                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1129                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1130
1131                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1132                            I40E_RXD_QW1_ERROR_SHIFT;
1133                 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1134
1135                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1136                            I40E_RXD_QW1_PTYPE_SHIFT;
1137                 rx_bi->skb = NULL;
1138                 cleaned_count++;
1139
1140                 /* Get the header and possibly the whole packet
1141                  * If this is an skb from previous receive dma will be 0
1142                  */
1143                 skb_put(skb, rx_packet_len);
1144                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1145                                  DMA_FROM_DEVICE);
1146                 rx_bi->dma = 0;
1147
1148                 I40E_RX_INCREMENT(rx_ring, i);
1149
1150                 if (unlikely(
1151                     !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1152                         rx_ring->rx_stats.non_eop_descs++;
1153                         continue;
1154                 }
1155
1156                 /* ERR_MASK will only have valid bits if EOP set */
1157                 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1158                         dev_kfree_skb_any(skb);
1159                         continue;
1160                 }
1161
1162                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1163                              i40e_ptype_to_hash(rx_ptype));
1164                 /* probably a little skewed due to removing CRC */
1165                 total_rx_bytes += skb->len;
1166                 total_rx_packets++;
1167
1168                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1169
1170                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1171
1172                 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1173                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1174                          : 0;
1175                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1176
1177                 rx_desc->wb.qword1.status_error_len = 0;
1178         } while (likely(total_rx_packets < budget));
1179
1180         u64_stats_update_begin(&rx_ring->syncp);
1181         rx_ring->stats.packets += total_rx_packets;
1182         rx_ring->stats.bytes += total_rx_bytes;
1183         u64_stats_update_end(&rx_ring->syncp);
1184         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1185         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1186
1187         return total_rx_packets;
1188 }
1189
1190 /**
1191  * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1192  * @vsi: the VSI we care about
1193  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1194  *
1195  **/
1196 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1197                                           struct i40e_q_vector *q_vector)
1198 {
1199         struct i40e_hw *hw = &vsi->back->hw;
1200         u16 old_itr;
1201         int vector;
1202         u32 val;
1203
1204         vector = (q_vector->v_idx + vsi->base_vector);
1205         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1206                 old_itr = q_vector->rx.itr;
1207                 i40e_set_new_dynamic_itr(&q_vector->rx);
1208                 if (old_itr != q_vector->rx.itr) {
1209                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1210                         I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1211                         (I40E_RX_ITR <<
1212                                 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1213                         (q_vector->rx.itr <<
1214                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1215                 } else {
1216                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1217                         I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1218                         (I40E_ITR_NONE <<
1219                                 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
1220                 }
1221                 if (!test_bit(__I40E_DOWN, &vsi->state))
1222                         wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1223         } else {
1224                 i40evf_irq_enable_queues(vsi->back, 1
1225                         << q_vector->v_idx);
1226         }
1227         if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1228                 old_itr = q_vector->tx.itr;
1229                 i40e_set_new_dynamic_itr(&q_vector->tx);
1230                 if (old_itr != q_vector->tx.itr) {
1231                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1232                                 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1233                                 (I40E_TX_ITR <<
1234                                    I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1235                                 (q_vector->tx.itr <<
1236                                    I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1237
1238                 } else {
1239                         val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1240                                 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1241                                 (I40E_ITR_NONE <<
1242                                    I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
1243                 }
1244                 if (!test_bit(__I40E_DOWN, &vsi->state))
1245                         wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1246         } else {
1247                 i40evf_irq_enable_queues(vsi->back, BIT(q_vector->v_idx));
1248         }
1249 }
1250
1251 /**
1252  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1253  * @napi: napi struct with our devices info in it
1254  * @budget: amount of work driver is allowed to do this pass, in packets
1255  *
1256  * This function will clean all queues associated with a q_vector.
1257  *
1258  * Returns the amount of work done
1259  **/
1260 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1261 {
1262         struct i40e_q_vector *q_vector =
1263                                container_of(napi, struct i40e_q_vector, napi);
1264         struct i40e_vsi *vsi = q_vector->vsi;
1265         struct i40e_ring *ring;
1266         bool clean_complete = true;
1267         bool arm_wb = false;
1268         int budget_per_ring;
1269         int work_done = 0;
1270
1271         if (test_bit(__I40E_DOWN, &vsi->state)) {
1272                 napi_complete(napi);
1273                 return 0;
1274         }
1275
1276         /* Since the actual Tx work is minimal, we can give the Tx a larger
1277          * budget and be more aggressive about cleaning up the Tx descriptors.
1278          */
1279         i40e_for_each_ring(ring, q_vector->tx) {
1280                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1281                 arm_wb |= ring->arm_wb;
1282                 ring->arm_wb = false;
1283         }
1284
1285         /* Handle case where we are called by netpoll with a budget of 0 */
1286         if (budget <= 0)
1287                 goto tx_only;
1288
1289         /* We attempt to distribute budget to each Rx queue fairly, but don't
1290          * allow the budget to go below 1 because that would exit polling early.
1291          */
1292         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1293
1294         i40e_for_each_ring(ring, q_vector->rx) {
1295                 int cleaned;
1296
1297                 if (ring_is_ps_enabled(ring))
1298                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1299                 else
1300                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1301
1302                 work_done += cleaned;
1303                 /* if we didn't clean as many as budgeted, we must be done */
1304                 clean_complete &= (budget_per_ring != cleaned);
1305         }
1306
1307         /* If work not completed, return budget and polling will return */
1308         if (!clean_complete) {
1309 tx_only:
1310                 if (arm_wb)
1311                         i40evf_force_wb(vsi, q_vector);
1312                 return budget;
1313         }
1314
1315         if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1316                 q_vector->arm_wb_state = false;
1317
1318         /* Work is done so exit the polling mode and re-enable the interrupt */
1319         napi_complete_done(napi, work_done);
1320         i40e_update_enable_itr(vsi, q_vector);
1321         return 0;
1322 }
1323
1324 /**
1325  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1326  * @skb:     send buffer
1327  * @tx_ring: ring to send buffer on
1328  * @flags:   the tx flags to be set
1329  *
1330  * Checks the skb and set up correspondingly several generic transmit flags
1331  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1332  *
1333  * Returns error code indicate the frame should be dropped upon error and the
1334  * otherwise  returns 0 to indicate the flags has been set properly.
1335  **/
1336 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1337                                                struct i40e_ring *tx_ring,
1338                                                u32 *flags)
1339 {
1340         __be16 protocol = skb->protocol;
1341         u32  tx_flags = 0;
1342
1343         if (protocol == htons(ETH_P_8021Q) &&
1344             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1345                 /* When HW VLAN acceleration is turned off by the user the
1346                  * stack sets the protocol to 8021q so that the driver
1347                  * can take any steps required to support the SW only
1348                  * VLAN handling.  In our case the driver doesn't need
1349                  * to take any further steps so just set the protocol
1350                  * to the encapsulated ethertype.
1351                  */
1352                 skb->protocol = vlan_get_protocol(skb);
1353                 goto out;
1354         }
1355
1356         /* if we have a HW VLAN tag being added, default to the HW one */
1357         if (skb_vlan_tag_present(skb)) {
1358                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1359                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1360         /* else if it is a SW VLAN, check the next protocol and store the tag */
1361         } else if (protocol == htons(ETH_P_8021Q)) {
1362                 struct vlan_hdr *vhdr, _vhdr;
1363
1364                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1365                 if (!vhdr)
1366                         return -EINVAL;
1367
1368                 protocol = vhdr->h_vlan_encapsulated_proto;
1369                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1370                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1371         }
1372
1373 out:
1374         *flags = tx_flags;
1375         return 0;
1376 }
1377
1378 /**
1379  * i40e_tso - set up the tso context descriptor
1380  * @tx_ring:  ptr to the ring to send
1381  * @skb:      ptr to the skb we're sending
1382  * @hdr_len:  ptr to the size of the packet header
1383  * @cd_tunneling: ptr to context descriptor bits
1384  *
1385  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1386  **/
1387 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1388                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1389                     u32 *cd_tunneling)
1390 {
1391         u32 cd_cmd, cd_tso_len, cd_mss;
1392         struct ipv6hdr *ipv6h;
1393         struct tcphdr *tcph;
1394         struct iphdr *iph;
1395         u32 l4len;
1396         int err;
1397
1398         if (!skb_is_gso(skb))
1399                 return 0;
1400
1401         err = skb_cow_head(skb, 0);
1402         if (err < 0)
1403                 return err;
1404
1405         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1406         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1407
1408         if (iph->version == 4) {
1409                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1410                 iph->tot_len = 0;
1411                 iph->check = 0;
1412                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1413                                                  0, IPPROTO_TCP, 0);
1414         } else if (ipv6h->version == 6) {
1415                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1416                 ipv6h->payload_len = 0;
1417                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1418                                                0, IPPROTO_TCP, 0);
1419         }
1420
1421         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1422         *hdr_len = (skb->encapsulation
1423                     ? (skb_inner_transport_header(skb) - skb->data)
1424                     : skb_transport_offset(skb)) + l4len;
1425
1426         /* find the field values */
1427         cd_cmd = I40E_TX_CTX_DESC_TSO;
1428         cd_tso_len = skb->len - *hdr_len;
1429         cd_mss = skb_shinfo(skb)->gso_size;
1430         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1431                                 ((u64)cd_tso_len <<
1432                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1433                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1434         return 1;
1435 }
1436
1437 /**
1438  * i40e_tx_enable_csum - Enable Tx checksum offloads
1439  * @skb: send buffer
1440  * @tx_flags: pointer to Tx flags currently set
1441  * @td_cmd: Tx descriptor command bits to set
1442  * @td_offset: Tx descriptor header offsets to set
1443  * @cd_tunneling: ptr to context desc bits
1444  **/
1445 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1446                                 u32 *td_cmd, u32 *td_offset,
1447                                 struct i40e_ring *tx_ring,
1448                                 u32 *cd_tunneling)
1449 {
1450         struct ipv6hdr *this_ipv6_hdr;
1451         unsigned int this_tcp_hdrlen;
1452         struct iphdr *this_ip_hdr;
1453         u32 network_hdr_len;
1454         u8 l4_hdr = 0;
1455         struct udphdr *oudph;
1456         struct iphdr *oiph;
1457         u32 l4_tunnel = 0;
1458
1459         if (skb->encapsulation) {
1460                 switch (ip_hdr(skb)->protocol) {
1461                 case IPPROTO_UDP:
1462                         oudph = udp_hdr(skb);
1463                         oiph = ip_hdr(skb);
1464                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1465                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1466                         break;
1467                 default:
1468                         return;
1469                 }
1470                 network_hdr_len = skb_inner_network_header_len(skb);
1471                 this_ip_hdr = inner_ip_hdr(skb);
1472                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1473                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1474
1475                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1476                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1477                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1478                                 ip_hdr(skb)->check = 0;
1479                         } else {
1480                                 *cd_tunneling |=
1481                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1482                         }
1483                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1484                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1485                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1486                                 ip_hdr(skb)->check = 0;
1487                 }
1488
1489                 /* Now set the ctx descriptor fields */
1490                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1491                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1492                                    l4_tunnel                             |
1493                                    ((skb_inner_network_offset(skb) -
1494                                         skb_transport_offset(skb)) >> 1) <<
1495                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1496                 if (this_ip_hdr->version == 6) {
1497                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1498                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1499                 }
1500
1501
1502                 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1503                     (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
1504                     (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1505                         oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1506                                         oiph->daddr,
1507                                         (skb->len - skb_transport_offset(skb)),
1508                                         IPPROTO_UDP, 0);
1509                         *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1510                 }
1511         } else {
1512                 network_hdr_len = skb_network_header_len(skb);
1513                 this_ip_hdr = ip_hdr(skb);
1514                 this_ipv6_hdr = ipv6_hdr(skb);
1515                 this_tcp_hdrlen = tcp_hdrlen(skb);
1516         }
1517
1518         /* Enable IP checksum offloads */
1519         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1520                 l4_hdr = this_ip_hdr->protocol;
1521                 /* the stack computes the IP header already, the only time we
1522                  * need the hardware to recompute it is in the case of TSO.
1523                  */
1524                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1525                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1526                         this_ip_hdr->check = 0;
1527                 } else {
1528                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1529                 }
1530                 /* Now set the td_offset for IP header length */
1531                 *td_offset = (network_hdr_len >> 2) <<
1532                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1533         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1534                 l4_hdr = this_ipv6_hdr->nexthdr;
1535                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1536                 /* Now set the td_offset for IP header length */
1537                 *td_offset = (network_hdr_len >> 2) <<
1538                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1539         }
1540         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1541         *td_offset |= (skb_network_offset(skb) >> 1) <<
1542                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1543
1544         /* Enable L4 checksum offloads */
1545         switch (l4_hdr) {
1546         case IPPROTO_TCP:
1547                 /* enable checksum offloads */
1548                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1549                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1550                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1551                 break;
1552         case IPPROTO_SCTP:
1553                 /* enable SCTP checksum offload */
1554                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1555                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1556                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1557                 break;
1558         case IPPROTO_UDP:
1559                 /* enable UDP checksum offload */
1560                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1561                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1562                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1563                 break;
1564         default:
1565                 break;
1566         }
1567 }
1568
1569 /**
1570  * i40e_create_tx_ctx Build the Tx context descriptor
1571  * @tx_ring:  ring to create the descriptor on
1572  * @cd_type_cmd_tso_mss: Quad Word 1
1573  * @cd_tunneling: Quad Word 0 - bits 0-31
1574  * @cd_l2tag2: Quad Word 0 - bits 32-63
1575  **/
1576 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1577                                const u64 cd_type_cmd_tso_mss,
1578                                const u32 cd_tunneling, const u32 cd_l2tag2)
1579 {
1580         struct i40e_tx_context_desc *context_desc;
1581         int i = tx_ring->next_to_use;
1582
1583         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1584             !cd_tunneling && !cd_l2tag2)
1585                 return;
1586
1587         /* grab the next descriptor */
1588         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1589
1590         i++;
1591         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1592
1593         /* cpu_to_le32 and assign to struct fields */
1594         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1595         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1596         context_desc->rsvd = cpu_to_le16(0);
1597         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1598 }
1599
1600  /**
1601  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1602  * @skb:      send buffer
1603  * @tx_flags: collected send information
1604  *
1605  * Note: Our HW can't scatter-gather more than 8 fragments to build
1606  * a packet on the wire and so we need to figure out the cases where we
1607  * need to linearize the skb.
1608  **/
1609 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1610 {
1611         struct skb_frag_struct *frag;
1612         bool linearize = false;
1613         unsigned int size = 0;
1614         u16 num_frags;
1615         u16 gso_segs;
1616
1617         num_frags = skb_shinfo(skb)->nr_frags;
1618         gso_segs = skb_shinfo(skb)->gso_segs;
1619
1620         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1621                 u16 j = 0;
1622
1623                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1624                         goto linearize_chk_done;
1625                 /* try the simple math, if we have too many frags per segment */
1626                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1627                     I40E_MAX_BUFFER_TXD) {
1628                         linearize = true;
1629                         goto linearize_chk_done;
1630                 }
1631                 frag = &skb_shinfo(skb)->frags[0];
1632                 /* we might still have more fragments per segment */
1633                 do {
1634                         size += skb_frag_size(frag);
1635                         frag++; j++;
1636                         if ((size >= skb_shinfo(skb)->gso_size) &&
1637                             (j < I40E_MAX_BUFFER_TXD)) {
1638                                 size = (size % skb_shinfo(skb)->gso_size);
1639                                 j = (size) ? 1 : 0;
1640                         }
1641                         if (j == I40E_MAX_BUFFER_TXD) {
1642                                 linearize = true;
1643                                 break;
1644                         }
1645                         num_frags--;
1646                 } while (num_frags);
1647         } else {
1648                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1649                         linearize = true;
1650         }
1651
1652 linearize_chk_done:
1653         return linearize;
1654 }
1655
1656 /**
1657  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1658  * @tx_ring: the ring to be checked
1659  * @size:    the size buffer we want to assure is available
1660  *
1661  * Returns -EBUSY if a stop is needed, else 0
1662  **/
1663 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1664 {
1665         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1666         /* Memory barrier before checking head and tail */
1667         smp_mb();
1668
1669         /* Check again in a case another CPU has just made room available. */
1670         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1671                 return -EBUSY;
1672
1673         /* A reprieve! - use start_queue because it doesn't call schedule */
1674         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1675         ++tx_ring->tx_stats.restart_queue;
1676         return 0;
1677 }
1678
1679 /**
1680  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1681  * @tx_ring: the ring to be checked
1682  * @size:    the size buffer we want to assure is available
1683  *
1684  * Returns 0 if stop is not needed
1685  **/
1686 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1687 {
1688         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1689                 return 0;
1690         return __i40evf_maybe_stop_tx(tx_ring, size);
1691 }
1692
1693 /**
1694  * i40evf_tx_map - Build the Tx descriptor
1695  * @tx_ring:  ring to send buffer on
1696  * @skb:      send buffer
1697  * @first:    first buffer info buffer to use
1698  * @tx_flags: collected send information
1699  * @hdr_len:  size of the packet header
1700  * @td_cmd:   the command field in the descriptor
1701  * @td_offset: offset for checksum or crc
1702  **/
1703 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1704                                  struct i40e_tx_buffer *first, u32 tx_flags,
1705                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1706 {
1707         unsigned int data_len = skb->data_len;
1708         unsigned int size = skb_headlen(skb);
1709         struct skb_frag_struct *frag;
1710         struct i40e_tx_buffer *tx_bi;
1711         struct i40e_tx_desc *tx_desc;
1712         u16 i = tx_ring->next_to_use;
1713         u32 td_tag = 0;
1714         dma_addr_t dma;
1715         u16 gso_segs;
1716
1717         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1718                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1719                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1720                          I40E_TX_FLAGS_VLAN_SHIFT;
1721         }
1722
1723         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1724                 gso_segs = skb_shinfo(skb)->gso_segs;
1725         else
1726                 gso_segs = 1;
1727
1728         /* multiply data chunks by size of headers */
1729         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1730         first->gso_segs = gso_segs;
1731         first->skb = skb;
1732         first->tx_flags = tx_flags;
1733
1734         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1735
1736         tx_desc = I40E_TX_DESC(tx_ring, i);
1737         tx_bi = first;
1738
1739         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1740                 if (dma_mapping_error(tx_ring->dev, dma))
1741                         goto dma_error;
1742
1743                 /* record length, and DMA address */
1744                 dma_unmap_len_set(tx_bi, len, size);
1745                 dma_unmap_addr_set(tx_bi, dma, dma);
1746
1747                 tx_desc->buffer_addr = cpu_to_le64(dma);
1748
1749                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1750                         tx_desc->cmd_type_offset_bsz =
1751                                 build_ctob(td_cmd, td_offset,
1752                                            I40E_MAX_DATA_PER_TXD, td_tag);
1753
1754                         tx_desc++;
1755                         i++;
1756                         if (i == tx_ring->count) {
1757                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1758                                 i = 0;
1759                         }
1760
1761                         dma += I40E_MAX_DATA_PER_TXD;
1762                         size -= I40E_MAX_DATA_PER_TXD;
1763
1764                         tx_desc->buffer_addr = cpu_to_le64(dma);
1765                 }
1766
1767                 if (likely(!data_len))
1768                         break;
1769
1770                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1771                                                           size, td_tag);
1772
1773                 tx_desc++;
1774                 i++;
1775                 if (i == tx_ring->count) {
1776                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1777                         i = 0;
1778                 }
1779
1780                 size = skb_frag_size(frag);
1781                 data_len -= size;
1782
1783                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1784                                        DMA_TO_DEVICE);
1785
1786                 tx_bi = &tx_ring->tx_bi[i];
1787         }
1788
1789         /* Place RS bit on last descriptor of any packet that spans across the
1790          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1791          */
1792 #define WB_STRIDE 0x3
1793         if (((i & WB_STRIDE) != WB_STRIDE) &&
1794             (first <= &tx_ring->tx_bi[i]) &&
1795             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1796                 tx_desc->cmd_type_offset_bsz =
1797                         build_ctob(td_cmd, td_offset, size, td_tag) |
1798                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1799                                          I40E_TXD_QW1_CMD_SHIFT);
1800         } else {
1801                 tx_desc->cmd_type_offset_bsz =
1802                         build_ctob(td_cmd, td_offset, size, td_tag) |
1803                         cpu_to_le64((u64)I40E_TXD_CMD <<
1804                                          I40E_TXD_QW1_CMD_SHIFT);
1805         }
1806
1807         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1808                                                  tx_ring->queue_index),
1809                              first->bytecount);
1810
1811         /* Force memory writes to complete before letting h/w
1812          * know there are new descriptors to fetch.  (Only
1813          * applicable for weak-ordered memory model archs,
1814          * such as IA-64).
1815          */
1816         wmb();
1817
1818         /* set next_to_watch value indicating a packet is present */
1819         first->next_to_watch = tx_desc;
1820
1821         i++;
1822         if (i == tx_ring->count)
1823                 i = 0;
1824
1825         tx_ring->next_to_use = i;
1826
1827         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1828         /* notify HW of packet */
1829         if (!skb->xmit_more ||
1830             netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1831                                                    tx_ring->queue_index)))
1832                 writel(i, tx_ring->tail);
1833         else
1834                 prefetchw(tx_desc + 1);
1835
1836         return;
1837
1838 dma_error:
1839         dev_info(tx_ring->dev, "TX DMA map failed\n");
1840
1841         /* clear dma mappings for failed tx_bi map */
1842         for (;;) {
1843                 tx_bi = &tx_ring->tx_bi[i];
1844                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1845                 if (tx_bi == first)
1846                         break;
1847                 if (i == 0)
1848                         i = tx_ring->count;
1849                 i--;
1850         }
1851
1852         tx_ring->next_to_use = i;
1853 }
1854
1855 /**
1856  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1857  * @skb:     send buffer
1858  * @tx_ring: ring to send buffer on
1859  *
1860  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1861  * there is not enough descriptors available in this ring since we need at least
1862  * one descriptor.
1863  **/
1864 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1865                                                struct i40e_ring *tx_ring)
1866 {
1867         unsigned int f;
1868         int count = 0;
1869
1870         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1871          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1872          *       + 4 desc gap to avoid the cache line where head is,
1873          *       + 1 desc for context descriptor,
1874          * otherwise try next time
1875          */
1876         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1877                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1878
1879         count += TXD_USE_COUNT(skb_headlen(skb));
1880         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1881                 tx_ring->tx_stats.tx_busy++;
1882                 return 0;
1883         }
1884         return count;
1885 }
1886
1887 /**
1888  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1889  * @skb:     send buffer
1890  * @tx_ring: ring to send buffer on
1891  *
1892  * Returns NETDEV_TX_OK if sent, else an error code
1893  **/
1894 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1895                                         struct i40e_ring *tx_ring)
1896 {
1897         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1898         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1899         struct i40e_tx_buffer *first;
1900         u32 td_offset = 0;
1901         u32 tx_flags = 0;
1902         __be16 protocol;
1903         u32 td_cmd = 0;
1904         u8 hdr_len = 0;
1905         int tso;
1906
1907         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
1908                 return NETDEV_TX_BUSY;
1909
1910         /* prepare the xmit flags */
1911         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1912                 goto out_drop;
1913
1914         /* obtain protocol of skb */
1915         protocol = vlan_get_protocol(skb);
1916
1917         /* record the location of the first descriptor for this packet */
1918         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1919
1920         /* setup IPv4/IPv6 offloads */
1921         if (protocol == htons(ETH_P_IP))
1922                 tx_flags |= I40E_TX_FLAGS_IPV4;
1923         else if (protocol == htons(ETH_P_IPV6))
1924                 tx_flags |= I40E_TX_FLAGS_IPV6;
1925
1926         tso = i40e_tso(tx_ring, skb, &hdr_len,
1927                        &cd_type_cmd_tso_mss, &cd_tunneling);
1928
1929         if (tso < 0)
1930                 goto out_drop;
1931         else if (tso)
1932                 tx_flags |= I40E_TX_FLAGS_TSO;
1933
1934         if (i40e_chk_linearize(skb, tx_flags)) {
1935                 if (skb_linearize(skb))
1936                         goto out_drop;
1937                 tx_ring->tx_stats.tx_linearize++;
1938         }
1939         skb_tx_timestamp(skb);
1940
1941         /* always enable CRC insertion offload */
1942         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1943
1944         /* Always offload the checksum, since it's in the data descriptor */
1945         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1946                 tx_flags |= I40E_TX_FLAGS_CSUM;
1947
1948                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
1949                                     tx_ring, &cd_tunneling);
1950         }
1951
1952         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1953                            cd_tunneling, cd_l2tag2);
1954
1955         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1956                       td_cmd, td_offset);
1957
1958         return NETDEV_TX_OK;
1959
1960 out_drop:
1961         dev_kfree_skb_any(skb);
1962         return NETDEV_TX_OK;
1963 }
1964
1965 /**
1966  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1967  * @skb:    send buffer
1968  * @netdev: network interface device structure
1969  *
1970  * Returns NETDEV_TX_OK if sent, else an error code
1971  **/
1972 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1973 {
1974         struct i40evf_adapter *adapter = netdev_priv(netdev);
1975         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1976
1977         /* hardware can't handle really short frames, hardware padding works
1978          * beyond this point
1979          */
1980         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1981                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1982                         return NETDEV_TX_OK;
1983                 skb->len = I40E_MIN_TX_LEN;
1984                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1985         }
1986
1987         return i40e_xmit_frame_ring(skb, tx_ring);
1988 }